sys/boot/fdt/dts/db78100.dts

   1 /*
   2  * Copyright (c) 2010 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Semihalf under sponsorship from
   6  * the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * Marvell DB-78100 Device Tree Source.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 /dts-v1/;
  35
  36 / {
  37         model = "mrvl,DB-78100";
  38         compatible = "DB-78100-BP", "DB-78100-BP-A";
  39         #address-cells = <1>;
  40         #size-cells = <1>;
  41
  42         aliases {
  43                 ethernet0 = &enet0;
  44                 serial0 = &serial0;
  45                 serial1 = &serial1;
  46                 mpp = &MPP;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "ARM,88FR571";
  56                         reg = <0x0>;
  57                         d-cache-line-size = <32>;       // 32 bytes
  58                         i-cache-line-size = <32>;       // 32 bytes
  59                         d-cache-size = <0x4000>;        // L1, 16K
  60                         i-cache-size = <0x4000>;        // L1, 16K
  61                         timebase-frequency = <0>;
  62                         bus-frequency = <0>;
  63                         clock-frequency = <0>;
  64                 };
  65         };
  66
  67         memory {
  68                 device_type = "memory";
  69                 reg = <0x0 0x20000000>;         // 512M at 0x0
  70         };
  71
  72         localbus@f1000000 {
  73                 #address-cells = <2>;
  74                 #size-cells = <1>;
  75                 compatible = "mrvl,lbc";
  76                 win-count = <14>;
  77
  78                 /* This reflects CPU decode windows setup. */
  79                 ranges = <0x0 0x0f 0xf9300000 0x00100000
  80                           0x1 0x1e 0xfa000000 0x00100000
  81                           0x2 0x1d 0xfa100000 0x02000000
  82                           0x3 0x1b 0xfc100000 0x00000400>;
  83
  84                 nor@0,0 {
  85                         #address-cells = <1>;
  86                         #size-cells = <1>;
  87                         compatible = "cfi-flash";
  88                         reg = <0x0 0x0 0x00100000>;
  89                         bank-width = <2>;
  90                         device-width = <1>;
  91                 };
  92
  93                 led@1,0 {
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         compatible = "led";
  97                         reg = <0x1 0x0 0x00100000>;
  98                 };
  99
 100                 nor@2,0 {
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         compatible = "cfi-flash";
 104                         reg = <0x2 0x0 0x02000000>;
 105                         bank-width = <2>;
 106                         device-width = <1>;
 107                 };
 108
 109                 nand@3,0 {
 110                         #address-cells = <1>;
 111                         #size-cells = <1>;
 112                         reg = <0x3 0x0 0x00100000>;
 113                         bank-width = <2>;
 114                         device-width = <1>;
 115                 };
 116         };
 117
 118         soc78100@f1000000 {
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 compatible = "simple-bus";
 122                 ranges = <0x0 0xf1000000 0x00100000>;
 123                 bus-frequency = <0>;
 124
 125                 PIC: pic@20200 {
 126                         interrupt-controller;
 127                         #address-cells = <0>;
 128                         #interrupt-cells = <1>;
 129                         reg = <0x20200 0x3c>;
 130                         compatible = "mrvl,pic";
 131                 };
 132
 133                 timer@20300 {
 134                         compatible = "mrvl,timer";
 135                         reg = <0x20300 0x30>;
 136                         interrupts = <8>;
 137                         interrupt-parent = <&PIC>;
 138                         mrvl,has-wdt;
 139                 };
 140
 141                 MPP: mpp@10000 {
 142                         #pin-cells = <2>;
 143                         compatible = "mrvl,mpp";
 144                         reg = <0x10000 0x34>;
 145                         pin-count = <50>;
 146                         pin-map = <
 147                                 0  2            /* MPP[0]:  GE1_TXCLK */
 148                                 1  2            /* MPP[1]:  GE1_TXCTL */
 149                                 2  2            /* MPP[2]:  GE1_RXCTL */
 150                                 3  2            /* MPP[3]:  GE1_RXCLK */
 151                                 4  2            /* MPP[4]:  GE1_TXD[0] */
 152                                 5  2            /* MPP[5]:  GE1_TXD[1] */
 153                                 6  2            /* MPP[6]:  GE1_TXD[2] */
 154                                 7  2            /* MPP[7]:  GE1_TXD[3] */
 155                                 8  2            /* MPP[8]:  GE1_RXD[0] */
 156                                 9  2            /* MPP[9]:  GE1_RXD[1] */
 157                                 10 2            /* MPP[10]: GE1_RXD[2] */
 158                                 11 2            /* MPP[11]: GE1_RXD[3] */
 159                                 13 3            /* MPP[13]: SYSRST_OUTn */
 160                                 14 3            /* MPP[14]: SATA1_ACTn */
 161                                 15 3            /* MPP[15]: SATA0_ACTn */
 162                                 16 4            /* MPP[16]: UA2_TXD */
 163                                 17 4            /* MPP[17]: UA2_RXD */
 164                                 18 3            /* MPP[18]: <UNKNOWN> */
 165                                 19 3            /* MPP[19]: <UNKNOWN> */
 166                                 20 3            /* MPP[20]: <UNKNOWN> */
 167                                 21 3            /* MPP[21]: <UNKNOWN> */
 168                                 22 4            /* MPP[22]: UA3_TXD */
 169                                 23 4 >;         /* MPP[21]: UA3_RXD */
 170                 };
 171
 172                 GPIO: gpio@10100 {
 173                         #gpio-cells = <3>;
 174                         compatible = "mrvl,gpio";
 175                         reg = <0x10100 0x20>;
 176                         gpio-controller;
 177                         interrupts = <56 57 58 59>;
 178                         interrupt-parent = <&PIC>;
 179                 };
 180
 181                 rtc@10300 {
 182                         compatible = "mrvl,rtc";
 183                         reg = <0x10300 0x08>;
 184                 };
 185
 186                 twsi@11000 {
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         compatible = "mrvl,twsi";
 190                         reg = <0x11000 0x20>;
 191                         interrupts = <2>;
 192                         interrupt-parent = <&PIC>;
 193                 };
 194
 195                 twsi@11100 {
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198                         compatible = "mrvl,twsi";
 199                         reg = <0x11100 0x20>;
 200                         interrupts = <3>;
 201                         interrupt-parent = <&PIC>;
 202                 };
 203
 204                 enet0: ethernet@72000 {
 205                         #address-cells = <1>;
 206                         #size-cells = <1>;
 207                         model = "V2";
 208                         compatible = "mrvl,ge";
 209                         reg = <0x72000 0x2000>;
 210                         ranges = <0x0 0x72000 0x2000>;
 211                         local-mac-address = [ 00 00 00 00 00 00 ];
 212                         interrupts = <41 42 43 40 70>;
 213                         interrupt-parent = <&PIC>;
 214                         phy-handle = <&phy0>;
 215
 216                         mdio@0 {
 217                                 #address-cells = <1>;
 218                                 #size-cells = <0>;
 219                                 compatible = "mrvl,mdio";
 220
 221                                 phy0: ethernet-phy@0 {
 222                                         reg = <0x8>;
 223                                 };
 224                                 phy1: ethernet-phy@1 {
 225                                         reg = <0x9>;
 226                                 };
 227                         };
 228                 };
 229
 230                 enet1: ethernet@76000 {
 231                         #address-cells = <1>;
 232                         #size-cells = <1>;
 233                         model = "V2";
 234                         compatible = "mrvl,ge";
 235                         reg = <0x76000 0x2000>;
 236                         ranges = <0x0 0x76000 0x2000>;
 237                         local-mac-address = [ 00 00 00 00 00 00 ];
 238                         interrupts = <45 46 47 44 70>;
 239                         interrupt-parent = <&PIC>;
 240                         phy-handle = <&phy1>;
 241                 };
 242
 243                 serial0: serial@12000 {
 244                         compatible = "ns16550";
 245                         reg = <0x12000 0x20>;
 246                         reg-shift = <2>;
 247                         clock-frequency = <0>;
 248                         interrupts = <12>;
 249                         interrupt-parent = <&PIC>;
 250                 };
 251
 252                 serial1: serial@12100 {
 253                         compatible = "ns16550";
 254                         reg = <0x12100 0x20>;
 255                         reg-shift = <2>;
 256                         clock-frequency = <0>;
 257                         interrupts = <13>;
 258                         interrupt-parent = <&PIC>;
 259                 };
 260
 261                 usb@50000 {
 262                         compatible = "mrvl,usb-ehci", "usb-ehci";
 263                         reg = <0x50000 0x1000>;
 264                         interrupts = <72 16>;
 265                         interrupt-parent = <&PIC>;
 266                 };
 267
 268                 usb@51000 {
 269                         compatible = "mrvl,usb-ehci", "usb-ehci";
 270                         reg = <0x51000 0x1000>;
 271                         interrupts = <72 17>;
 272                         interrupt-parent = <&PIC>;
 273                 };
 274
 275                 usb@52000 {
 276                         compatible = "mrvl,usb-ehci", "usb-ehci";
 277                         reg = <0x52000 0x1000>;
 278                         interrupts = <72 18>;
 279                         interrupt-parent = <&PIC>;
 280                 };
 281
 282                 xor@60000 {
 283                         compatible = "mrvl,xor";
 284                         reg = <0x60000 0x1000>;
 285                         interrupts = <22 23>;
 286                         interrupt-parent = <&PIC>;
 287                 };
 288
 289                 crypto@90000 {
 290                         compatible = "mrvl,cesa";
 291                         reg = <0x90000 0x10000>;
 292                         interrupts = <19>;
 293                         interrupt-parent = <&PIC>;
 294                 };
 295
 296                 sata@a0000 {
 297                         compatible = "mrvl,sata";
 298                         reg = <0xa0000 0x6000>;
 299                         interrupts = <26>;
 300                         interrupt-parent = <&PIC>;
 301                 };
 302         };
 303
 304         pci0: pcie@f1040000 {
 305                 compatible = "mrvl,pcie";
 306                 device_type = "pci";
 307                 #interrupt-cells = <1>;
 308                 #size-cells = <2>;
 309                 #address-cells = <3>;
 310                 reg = <0xf1040000 0x2000>;
 311                 bus-range = <0 255>;
 312                 ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
 313                           0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
 314                 clock-frequency = <33333333>;
 315                 interrupt-parent = <&PIC>;
 316                 interrupts = <68>;
 317                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 318                 interrupt-map = <
 319                         /* IDSEL 0x1 */
 320                         0x0800 0x0 0x0 0x1 &PIC 0x20
 321                         0x0800 0x0 0x0 0x2 &PIC 0x21
 322                         0x0800 0x0 0x0 0x3 &PIC 0x22
 323                         0x0800 0x0 0x0 0x4 &PIC 0x23
 324                         >;
 325         };
 326
 327         sram@fd000000 {
 328                 compatible = "mrvl,cesa-sram";
 329                 reg = <0xfd000000 0x00100000>;
 330         };
 331
 332         chosen {
 333                 stdin = "serial0";
 334                 stdout = "serial0";
 335         };
 336 };