sys/boot/fdt/dts/db88f6281.dts

   1 /*
   2  * Copyright (c) 2009-2010 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Semihalf under sponsorship from
   6  * the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * Marvell DB-88F6281 Device Tree Source.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 /dts-v1/;
  35
  36 / {
  37         model = "mrvl,DB-88F6281";
  38         compatible = "DB-88F6281-BP", "DB-88F6281-BP-A";
  39         #address-cells = <1>;
  40         #size-cells = <1>;
  41
  42         aliases {
  43                 ethernet0 = &enet0;
  44                 mpp = &MPP;
  45                 pci0 = &pci0;
  46                 serial0 = &serial0;
  47                 serial1 = &serial1;
  48                 soc = &SOC;
  49                 sram = &SRAM;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "ARM,88FR131";
  59                         reg = <0x0>;
  60                         d-cache-line-size = <32>;       // 32 bytes
  61                         i-cache-line-size = <32>;       // 32 bytes
  62                         d-cache-size = <0x4000>;        // L1, 16K
  63                         i-cache-size = <0x4000>;        // L1, 16K
  64                         timebase-frequency = <0>;
  65                         bus-frequency = <0>;
  66                         clock-frequency = <0>;
  67                 };
  68         };
  69
  70         memory {
  71                 device_type = "memory";
  72                 reg = <0x0 0x20000000>;         // 512M at 0x0
  73         };
  74
  75         localbus@f1000000 {
  76                 #address-cells = <2>;
  77                 #size-cells = <1>;
  78                 compatible = "mrvl,lbc";
  79
  80                 /* This reflects CPU decode windows setup. */
  81                 ranges = <0x0 0x0f 0xf9300000 0x00100000
  82                           0x1 0x1e 0xfa000000 0x00100000
  83                           0x2 0x1d 0xfa100000 0x02000000
  84                           0x3 0x1b 0xfc100000 0x00000400>;
  85
  86                 nor@0,0 {
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         compatible = "cfi-flash";
  90                         reg = <0x0 0x0 0x00100000>;
  91                         bank-width = <2>;
  92                         device-width = <1>;
  93                 };
  94
  95                 led@1,0 {
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         compatible = "led";
  99                         reg = <0x1 0x0 0x00100000>;
 100                 };
 101
 102                 nor@2,0 {
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         compatible = "cfi-flash";
 106                         reg = <0x2 0x0 0x02000000>;
 107                         bank-width = <2>;
 108                         device-width = <1>;
 109                 };
 110
 111                 nand@3,0 {
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         reg = <0x3 0x0 0x00100000>;
 115                         bank-width = <2>;
 116                         device-width = <1>;
 117                 };
 118         };
 119
 120         SOC: soc88f6281@f1000000 {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 compatible = "simple-bus";
 124                 ranges = <0x0 0xf1000000 0x00100000>;
 125                 bus-frequency = <0>;
 126
 127                 PIC: pic@20200 {
 128                         interrupt-controller;
 129                         #address-cells = <0>;
 130                         #interrupt-cells = <1>;
 131                         reg = <0x20200 0x3c>;
 132                         compatible = "mrvl,pic";
 133                 };
 134
 135                 timer@20300 {
 136                         compatible = "mrvl,timer";
 137                         reg = <0x20300 0x30>;
 138                         interrupts = <1>;
 139                         interrupt-parent = <&PIC>;
 140                         mrvl,has-wdt;
 141                 };
 142
 143                 MPP: mpp@10000 {
 144                         #pin-cells = <2>;
 145                         compatible = "mrvl,mpp";
 146                         reg = <0x10000 0x34>;
 147                         pin-count = <50>;
 148                         pin-map = <
 149                                 0  1            /* MPP[0]:  NF_IO[2] */
 150                                 1  1            /* MPP[1]:  NF_IO[3] */
 151                                 2  1            /* MPP[2]:  NF_IO[4] */
 152                                 3  1            /* MPP[3]:  NF_IO[5] */
 153                                 4  1            /* MPP[4]:  NF_IO[6] */
 154                                 5  1            /* MPP[5]:  NF_IO[7] */
 155                                 6  1            /* MPP[6]:  SYSRST_OUTn */
 156                                 7  2            /* MPP[7]:  SPI_SCn */
 157                                 8  1            /* MPP[8]:  TW_SDA */
 158                                 9  1            /* MPP[9]:  TW_SCK */
 159                                 10 3            /* MPP[10]: UA0_TXD */
 160                                 11 3            /* MPP[11]: UA0_RXD */
 161                                 12 1            /* MPP[12]: SD_CLK */
 162                                 13 1            /* MPP[13]: SD_CMD */
 163                                 14 1            /* MPP[14]: SD_D[0] */
 164                                 15 1            /* MPP[15]: SD_D[1] */
 165                                 16 1            /* MPP[16]: SD_D[2] */
 166                                 17 1            /* MPP[17]: SD_D[3] */
 167                                 18 1            /* MPP[18]: NF_IO[0] */
 168                                 19 1            /* MPP[19]: NF_IO[1] */
 169                                 20 5            /* MPP[20]: SATA1_AC */
 170                                 21 5 >;         /* MPP[21]: SATA0_AC */
 171                 };
 172
 173                 GPIO: gpio@10100 {
 174                         #gpio-cells = <3>;
 175                         compatible = "mrvl,gpio";
 176                         reg = <0x10100 0x20>;
 177                         gpio-controller;
 178                         interrupts = <35 36 37 38 39 40 41>;
 179                         interrupt-parent = <&PIC>;
 180                 };
 181
 182                 rtc@10300 {
 183                         compatible = "mrvl,rtc";
 184                         reg = <0x10300 0x08>;
 185                 };
 186
 187                 twsi@11000 {
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         compatible = "mrvl,twsi";
 191                         reg = <0x11000 0x20>;
 192                         interrupts = <43>;
 193                         interrupt-parent = <&PIC>;
 194                 };
 195
 196                 enet0: ethernet@72000 {
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         model = "V2";
 200                         compatible = "mrvl,ge";
 201                         reg = <0x72000 0x2000>;
 202                         ranges = <0x0 0x72000 0x2000>;
 203                         local-mac-address = [ 00 00 00 00 00 00 ];
 204                         interrupts = <12 13 14 11 46>;
 205                         interrupt-parent = <&PIC>;
 206                         phy-handle = <&phy0>;
 207
 208                         mdio@0 {
 209                                 #address-cells = <1>;
 210                                 #size-cells = <0>;
 211                                 compatible = "mrvl,mdio";
 212
 213                                 phy0: ethernet-phy@0 {
 214                                         reg = <0x8>;
 215                                 };
 216                         };
 217                 };
 218
 219                 serial0: serial@12000 {
 220                         compatible = "ns16550";
 221                         reg = <0x12000 0x20>;
 222                         reg-shift = <2>;
 223                         clock-frequency = <0>;
 224                         interrupts = <33>;
 225                         interrupt-parent = <&PIC>;
 226                 };
 227
 228                 serial1: serial@12100 {
 229                         compatible = "ns16550";
 230                         reg = <0x12100 0x20>;
 231                         reg-shift = <2>;
 232                         clock-frequency = <0>;
 233                         interrupts = <34>;
 234                         interrupt-parent = <&PIC>;
 235                 };
 236
 237                 crypto@30000 {
 238                         compatible = "mrvl,cesa";
 239                         reg = <0x30000 0x10000>;
 240                         interrupts = <22>;
 241                         interrupt-parent = <&PIC>;
 242
 243                         sram-handle = <&SRAM>;
 244                 };
 245
 246                 usb@50000 {
 247                         compatible = "mrvl,usb-ehci", "usb-ehci";
 248                         reg = <0x50000 0x1000>;
 249                         interrupts = <48 19>;
 250                         interrupt-parent = <&PIC>;
 251                 };
 252
 253                 xor@60000 {
 254                         compatible = "mrvl,xor";
 255                         reg = <0x60000 0x1000>;
 256                         interrupts = <5 6 7 8>;
 257                         interrupt-parent = <&PIC>;
 258                 };
 259
 260                 sata@80000 {
 261                         compatible = "mrvl,sata";
 262                         reg = <0x80000 0x6000>;
 263                         interrupts = <21>;
 264                         interrupt-parent = <&PIC>;
 265                 };
 266         };
 267
 268         SRAM: sram@fd000000 {
 269                 compatible = "mrvl,cesa-sram";
 270                 reg = <0xfd000000 0x00100000>;
 271         };
 272
 273         pci0: pcie@f1040000 {
 274                 compatible = "mrvl,pcie";
 275                 device_type = "pci";
 276                 #interrupt-cells = <1>;
 277                 #size-cells = <2>;
 278                 #address-cells = <3>;
 279                 reg = <0xf1040000 0x2000>;
 280                 bus-range = <0 255>;
 281                 ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000
 282                           0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
 283                 clock-frequency = <33333333>;
 284                 interrupt-parent = <&PIC>;
 285                 interrupts = <44>;
 286                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 287                 interrupt-map = <
 288                         /* IDSEL 0x1 */
 289                         0x0800 0x0 0x0 0x1 &PIC 0x9
 290                         0x0800 0x0 0x0 0x2 &PIC 0x9
 291                         0x0800 0x0 0x0 0x3 &PIC 0x9
 292                         0x0800 0x0 0x0 0x4 &PIC 0x9
 293                         >;
 294                 pcie@0 {
 295                         reg = <0x0 0x0 0x0 0x0 0x0>;
 296                         #size-cells = <2>;
 297                         #address-cells = <3>;
 298                         device_type = "pci";
 299                         ranges = <0x02000000 0x0 0xf1300000
 300                                   0x02000000 0x0 0xf1300000
 301                                   0x0 0x04000000
 302
 303                                   0x01000000 0x0 0x0
 304                                   0x01000000 0x0 0x0
 305                                   0x0 0x00100000>;
 306                 };
 307         };
 308 };