sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c

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  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn30xx.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN30XX</h2>
  51  * @dot
  52  * digraph cn30xx
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
  59  *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  60  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
  61  *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  62  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
  63  *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  64  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
  65  *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  66  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
  67  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  68  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
  69  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  70  *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"];
  71  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
  72  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
  73  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
  74  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
  75  *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<i0_rtout>i0_rtout|<i0_overf>i0_overf|<p0_rtout>p0_rtout|<p0_perr>p0_perr|<g0_rtout>g0_rtout|<p0_pperr>p0_pperr|<p0_ptout>p0_ptout|<i0_pperr>i0_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
  76  *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
  77  *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
  78  *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
  79  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
  80  *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
  81  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
  82  *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
  83  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
  84  *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
  85  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
  86  *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
  87  *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
  88  *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
  89  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
  90  *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
  91  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
  92  *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
  93  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
  94  *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
  95  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  96  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
  97  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  98  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
  99  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
 100  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
 101  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
 102  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
 103  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
 104  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
 105  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
 106  *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
 107  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
 108  *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
 109  *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
 110  *     cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
 111  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 112  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 113  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 114  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 115  *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
 116  * }
 117  * @enddot
 118  */
 119 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 120 #include <asm/octeon/cvmx.h>
 121 #include <asm/octeon/cvmx-error.h>
 122 #include <asm/octeon/cvmx-error-custom.h>
 123 #include <asm/octeon/cvmx-csr-typedefs.h>
 124 #else
 125 #include "cvmx.h"
 126 #include "cvmx-error.h"
 127 #include "cvmx-error-custom.h"
 128 #endif
 129
 130 int cvmx_error_initialize_cn30xx(void);
 131
 132 int cvmx_error_initialize_cn30xx(void)
 133 {
 134     cvmx_error_info_t info;
 135     int fail = 0;
 136
 137     /* CVMX_CIU_INTX_SUM0(0) */
 138     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 139     info.status_addr        = CVMX_CIU_INTX_SUM0(0);
 140     info.status_mask        = 0;
 141     info.enable_addr        = 0;
 142     info.enable_mask        = 0;
 143     info.flags              = 0;
 144     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 145     info.group_index        = 0;
 146     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 147     info.parent.status_addr = 0;
 148     info.parent.status_mask = 0;
 149     info.func               = __cvmx_error_decode;
 150     info.user_info          = 0;
 151     fail |= cvmx_error_add(&info);
 152
 153     /* CVMX_PCMX_INT_SUM(0) */
 154     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 155     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 156     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 157     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 158     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 159     info.flags              = 0;
 160     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 161     info.group_index        = 0;
 162     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 163     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 164     info.parent.status_mask = 1ull<<57 /* pcm */;
 165     info.func               = __cvmx_error_display;
 166     info.user_info          = (long)
 167         "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 168     fail |= cvmx_error_add(&info);
 169
 170     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 171     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 172     info.status_mask        = 1ull<<1 /* fsyncextra */;
 173     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 174     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 175     info.flags              = 0;
 176     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 177     info.group_index        = 0;
 178     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 179     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 180     info.parent.status_mask = 1ull<<57 /* pcm */;
 181     info.func               = __cvmx_error_display;
 182     info.user_info          = (long)
 183         "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 184     fail |= cvmx_error_add(&info);
 185
 186     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 187     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 188     info.status_mask        = 1ull<<6 /* txempty */;
 189     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 190     info.enable_mask        = 1ull<<6 /* txempty */;
 191     info.flags              = 0;
 192     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 193     info.group_index        = 0;
 194     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 195     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 196     info.parent.status_mask = 1ull<<57 /* pcm */;
 197     info.func               = __cvmx_error_display;
 198     info.user_info          = (long)
 199         "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
 200     fail |= cvmx_error_add(&info);
 201
 202     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 203     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 204     info.status_mask        = 1ull<<7 /* rxovf */;
 205     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 206     info.enable_mask        = 1ull<<7 /* rxovf */;
 207     info.flags              = 0;
 208     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 209     info.group_index        = 0;
 210     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 211     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 212     info.parent.status_mask = 1ull<<57 /* pcm */;
 213     info.func               = __cvmx_error_display;
 214     info.user_info          = (long)
 215         "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
 216     fail |= cvmx_error_add(&info);
 217
 218     /* CVMX_PCMX_INT_SUM(1) */
 219     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 220     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 221     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 222     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 223     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 224     info.flags              = 0;
 225     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 226     info.group_index        = 0;
 227     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 228     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 229     info.parent.status_mask = 1ull<<57 /* pcm */;
 230     info.func               = __cvmx_error_display;
 231     info.user_info          = (long)
 232         "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 233     fail |= cvmx_error_add(&info);
 234
 235     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 236     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 237     info.status_mask        = 1ull<<1 /* fsyncextra */;
 238     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 239     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 240     info.flags              = 0;
 241     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 242     info.group_index        = 0;
 243     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 244     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 245     info.parent.status_mask = 1ull<<57 /* pcm */;
 246     info.func               = __cvmx_error_display;
 247     info.user_info          = (long)
 248         "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 249     fail |= cvmx_error_add(&info);
 250
 251     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 252     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 253     info.status_mask        = 1ull<<6 /* txempty */;
 254     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 255     info.enable_mask        = 1ull<<6 /* txempty */;
 256     info.flags              = 0;
 257     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 258     info.group_index        = 0;
 259     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 260     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 261     info.parent.status_mask = 1ull<<57 /* pcm */;
 262     info.func               = __cvmx_error_display;
 263     info.user_info          = (long)
 264         "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
 265     fail |= cvmx_error_add(&info);
 266
 267     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 268     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 269     info.status_mask        = 1ull<<7 /* rxovf */;
 270     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 271     info.enable_mask        = 1ull<<7 /* rxovf */;
 272     info.flags              = 0;
 273     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 274     info.group_index        = 0;
 275     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 276     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 277     info.parent.status_mask = 1ull<<57 /* pcm */;
 278     info.func               = __cvmx_error_display;
 279     info.user_info          = (long)
 280         "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
 281     fail |= cvmx_error_add(&info);
 282
 283     /* CVMX_PCMX_INT_SUM(2) */
 284     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 285     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 286     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 287     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 288     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 289     info.flags              = 0;
 290     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 291     info.group_index        = 0;
 292     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 293     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 294     info.parent.status_mask = 1ull<<57 /* pcm */;
 295     info.func               = __cvmx_error_display;
 296     info.user_info          = (long)
 297         "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 298     fail |= cvmx_error_add(&info);
 299
 300     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 301     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 302     info.status_mask        = 1ull<<1 /* fsyncextra */;
 303     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 304     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 305     info.flags              = 0;
 306     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 307     info.group_index        = 0;
 308     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 309     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 310     info.parent.status_mask = 1ull<<57 /* pcm */;
 311     info.func               = __cvmx_error_display;
 312     info.user_info          = (long)
 313         "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 314     fail |= cvmx_error_add(&info);
 315
 316     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 317     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 318     info.status_mask        = 1ull<<6 /* txempty */;
 319     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 320     info.enable_mask        = 1ull<<6 /* txempty */;
 321     info.flags              = 0;
 322     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 323     info.group_index        = 0;
 324     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 325     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 326     info.parent.status_mask = 1ull<<57 /* pcm */;
 327     info.func               = __cvmx_error_display;
 328     info.user_info          = (long)
 329         "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
 330     fail |= cvmx_error_add(&info);
 331
 332     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 333     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 334     info.status_mask        = 1ull<<7 /* rxovf */;
 335     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 336     info.enable_mask        = 1ull<<7 /* rxovf */;
 337     info.flags              = 0;
 338     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 339     info.group_index        = 0;
 340     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 341     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 342     info.parent.status_mask = 1ull<<57 /* pcm */;
 343     info.func               = __cvmx_error_display;
 344     info.user_info          = (long)
 345         "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
 346     fail |= cvmx_error_add(&info);
 347
 348     /* CVMX_PCMX_INT_SUM(3) */
 349     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 350     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 351     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 352     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 353     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 354     info.flags              = 0;
 355     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 356     info.group_index        = 0;
 357     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 358     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 359     info.parent.status_mask = 1ull<<57 /* pcm */;
 360     info.func               = __cvmx_error_display;
 361     info.user_info          = (long)
 362         "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 363     fail |= cvmx_error_add(&info);
 364
 365     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 366     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 367     info.status_mask        = 1ull<<1 /* fsyncextra */;
 368     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 369     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 370     info.flags              = 0;
 371     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 372     info.group_index        = 0;
 373     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 374     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 375     info.parent.status_mask = 1ull<<57 /* pcm */;
 376     info.func               = __cvmx_error_display;
 377     info.user_info          = (long)
 378         "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 379     fail |= cvmx_error_add(&info);
 380
 381     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 382     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 383     info.status_mask        = 1ull<<6 /* txempty */;
 384     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 385     info.enable_mask        = 1ull<<6 /* txempty */;
 386     info.flags              = 0;
 387     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 388     info.group_index        = 0;
 389     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 390     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 391     info.parent.status_mask = 1ull<<57 /* pcm */;
 392     info.func               = __cvmx_error_display;
 393     info.user_info          = (long)
 394         "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
 395     fail |= cvmx_error_add(&info);
 396
 397     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 398     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 399     info.status_mask        = 1ull<<7 /* rxovf */;
 400     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 401     info.enable_mask        = 1ull<<7 /* rxovf */;
 402     info.flags              = 0;
 403     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 404     info.group_index        = 0;
 405     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 406     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 407     info.parent.status_mask = 1ull<<57 /* pcm */;
 408     info.func               = __cvmx_error_display;
 409     info.user_info          = (long)
 410         "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
 411     fail |= cvmx_error_add(&info);
 412
 413     /* CVMX_CIU_INT_SUM1 */
 414     /* CVMX_NPI_RSL_INT_BLOCKS */
 415     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 416     info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
 417     info.status_mask        = 0;
 418     info.enable_addr        = 0;
 419     info.enable_mask        = 0;
 420     info.flags              = 0;
 421     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 422     info.group_index        = 0;
 423     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 424     info.parent.status_addr = 0;
 425     info.parent.status_mask = 0;
 426     info.func               = __cvmx_error_decode;
 427     info.user_info          = 0;
 428     fail |= cvmx_error_add(&info);
 429
 430     /* CVMX_L2D_ERR */
 431     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 432     info.status_addr        = CVMX_L2D_ERR;
 433     info.status_mask        = 1ull<<3 /* sec_err */;
 434     info.enable_addr        = CVMX_L2D_ERR;
 435     info.enable_mask        = 1ull<<1 /* sec_intena */;
 436     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 437     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 438     info.group_index        = 0;
 439     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 440     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 441     info.parent.status_mask = 1ull<<16 /* l2c */;
 442     info.func               = __cvmx_error_handle_l2d_err_sec_err;
 443     info.user_info          = (long)
 444         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
 445     fail |= cvmx_error_add(&info);
 446
 447     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 448     info.status_addr        = CVMX_L2D_ERR;
 449     info.status_mask        = 1ull<<4 /* ded_err */;
 450     info.enable_addr        = CVMX_L2D_ERR;
 451     info.enable_mask        = 1ull<<2 /* ded_intena */;
 452     info.flags              = 0;
 453     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 454     info.group_index        = 0;
 455     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 456     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 457     info.parent.status_mask = 1ull<<16 /* l2c */;
 458     info.func               = __cvmx_error_handle_l2d_err_ded_err;
 459     info.user_info          = (long)
 460         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
 461     fail |= cvmx_error_add(&info);
 462
 463     /* CVMX_L2T_ERR */
 464     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 465     info.status_addr        = CVMX_L2T_ERR;
 466     info.status_mask        = 1ull<<3 /* sec_err */;
 467     info.enable_addr        = CVMX_L2T_ERR;
 468     info.enable_mask        = 1ull<<1 /* sec_intena */;
 469     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 470     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 471     info.group_index        = 0;
 472     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 473     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 474     info.parent.status_mask = 1ull<<16 /* l2c */;
 475     info.func               = __cvmx_error_handle_l2t_err_sec_err;
 476     info.user_info          = (long)
 477         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
 478         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 479         "    given index) are checked for single bit errors(SBEs).\n"
 480         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 481         "    SBEs are auto corrected in HW and generate an\n"
 482         "    interrupt(if enabled).\n";
 483     fail |= cvmx_error_add(&info);
 484
 485     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 486     info.status_addr        = CVMX_L2T_ERR;
 487     info.status_mask        = 1ull<<4 /* ded_err */;
 488     info.enable_addr        = CVMX_L2T_ERR;
 489     info.enable_mask        = 1ull<<2 /* ded_intena */;
 490     info.flags              = 0;
 491     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 492     info.group_index        = 0;
 493     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 494     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 495     info.parent.status_mask = 1ull<<16 /* l2c */;
 496     info.func               = __cvmx_error_handle_l2t_err_ded_err;
 497     info.user_info          = (long)
 498         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
 499         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 500         "    given index) are checked for double bit errors(DBEs).\n"
 501         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 502         "    DBEs also generated an interrupt(if enabled).\n";
 503     fail |= cvmx_error_add(&info);
 504
 505     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 506     info.status_addr        = CVMX_L2T_ERR;
 507     info.status_mask        = 1ull<<24 /* lckerr */;
 508     info.enable_addr        = CVMX_L2T_ERR;
 509     info.enable_mask        = 1ull<<25 /* lck_intena */;
 510     info.flags              = 0;
 511     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 512     info.group_index        = 0;
 513     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 514     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 515     info.parent.status_mask = 1ull<<16 /* l2c */;
 516     info.func               = __cvmx_error_handle_l2t_err_lckerr;
 517     info.user_info          = (long)
 518         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
 519         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 520         "    The LDD(L1 load-miss) for the LOCK operation is\n"
 521         "    completed successfully, however the address is NOT\n"
 522         "    locked.\n"
 523         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 524         "    into account. For example, if diagnostic PPx has\n"
 525         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 526         "    been previously LOCKED, then an attempt to LOCK the\n"
 527         "    last available SET0 would result in a LCKERR. (This\n"
 528         "    is to ensure that at least 1 SET at each INDEX is\n"
 529         "    not LOCKED for general use by other PPs).\n";
 530     fail |= cvmx_error_add(&info);
 531
 532     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 533     info.status_addr        = CVMX_L2T_ERR;
 534     info.status_mask        = 1ull<<26 /* lckerr2 */;
 535     info.enable_addr        = CVMX_L2T_ERR;
 536     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
 537     info.flags              = 0;
 538     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 539     info.group_index        = 0;
 540     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 541     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 542     info.parent.status_mask = 1ull<<16 /* l2c */;
 543     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
 544     info.user_info          = (long)
 545         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 546         "    could not find an available/unlocked set (for\n"
 547         "    replacement).\n"
 548         "    Most likely, this is a result of SW mixing SET\n"
 549         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 550         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 551         "    then a Rd/Wr Miss from PP#n will be unable\n"
 552         "    to determine a 'valid' replacement set (since LOCKED\n"
 553         "    addresses should NEVER be replaced).\n"
 554         "    If such an event occurs, the HW will select the smallest\n"
 555         "    available SET(specified by UMSK'x)' as the replacement\n"
 556         "    set, and the address is unlocked.\n";
 557     fail |= cvmx_error_add(&info);
 558
 559     /* CVMX_NPI_INT_SUM */
 560     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 561     info.status_addr        = CVMX_NPI_INT_SUM;
 562     info.status_mask        = 1ull<<0 /* rml_rto */;
 563     info.enable_addr        = CVMX_NPI_INT_ENB;
 564     info.enable_mask        = 1ull<<0 /* rml_rto */;
 565     info.flags              = 0;
 566     info.group              = CVMX_ERROR_GROUP_PCI;
 567     info.group_index        = 0;
 568     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 569     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 570     info.parent.status_mask = 1ull<<3 /* npi */;
 571     info.func               = __cvmx_error_display;
 572     info.user_info          = (long)
 573         "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
 574         "    back from a RSL after sending a read command to\n"
 575         "    a RSL.\n";
 576     fail |= cvmx_error_add(&info);
 577
 578     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 579     info.status_addr        = CVMX_NPI_INT_SUM;
 580     info.status_mask        = 1ull<<1 /* rml_wto */;
 581     info.enable_addr        = CVMX_NPI_INT_ENB;
 582     info.enable_mask        = 1ull<<1 /* rml_wto */;
 583     info.flags              = 0;
 584     info.group              = CVMX_ERROR_GROUP_PCI;
 585     info.group_index        = 0;
 586     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 587     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 588     info.parent.status_mask = 1ull<<3 /* npi */;
 589     info.func               = __cvmx_error_display;
 590     info.user_info          = (long)
 591         "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
 592         "    back from a RSL after sending a write command to\n"
 593         "    a RSL.\n";
 594     fail |= cvmx_error_add(&info);
 595
 596     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 597     info.status_addr        = CVMX_NPI_INT_SUM;
 598     info.status_mask        = 1ull<<3 /* po0_2sml */;
 599     info.enable_addr        = CVMX_NPI_INT_ENB;
 600     info.enable_mask        = 1ull<<3 /* po0_2sml */;
 601     info.flags              = 0;
 602     info.group              = CVMX_ERROR_GROUP_PCI;
 603     info.group_index        = 0;
 604     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 605     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 606     info.parent.status_mask = 1ull<<3 /* npi */;
 607     info.func               = __cvmx_error_display;
 608     info.user_info          = (long)
 609         "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
 610         "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
 611     fail |= cvmx_error_add(&info);
 612
 613     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 614     info.status_addr        = CVMX_NPI_INT_SUM;
 615     info.status_mask        = 1ull<<7 /* i0_rtout */;
 616     info.enable_addr        = CVMX_NPI_INT_ENB;
 617     info.enable_mask        = 1ull<<7 /* i0_rtout */;
 618     info.flags              = 0;
 619     info.group              = CVMX_ERROR_GROUP_PCI;
 620     info.group_index        = 0;
 621     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 622     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 623     info.parent.status_mask = 1ull<<3 /* npi */;
 624     info.func               = __cvmx_error_display;
 625     info.user_info          = (long)
 626         "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 627         "    read instructions.\n";
 628     fail |= cvmx_error_add(&info);
 629
 630     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 631     info.status_addr        = CVMX_NPI_INT_SUM;
 632     info.status_mask        = 1ull<<11 /* i0_overf */;
 633     info.enable_addr        = CVMX_NPI_INT_ENB;
 634     info.enable_mask        = 1ull<<11 /* i0_overf */;
 635     info.flags              = 0;
 636     info.group              = CVMX_ERROR_GROUP_PCI;
 637     info.group_index        = 0;
 638     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 639     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 640     info.parent.status_mask = 1ull<<3 /* npi */;
 641     info.func               = __cvmx_error_display;
 642     info.user_info          = (long)
 643         "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
 644         "    doorbell count was set.\n";
 645     fail |= cvmx_error_add(&info);
 646
 647     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 648     info.status_addr        = CVMX_NPI_INT_SUM;
 649     info.status_mask        = 1ull<<15 /* p0_rtout */;
 650     info.enable_addr        = CVMX_NPI_INT_ENB;
 651     info.enable_mask        = 1ull<<15 /* p0_rtout */;
 652     info.flags              = 0;
 653     info.group              = CVMX_ERROR_GROUP_PCI;
 654     info.group_index        = 0;
 655     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 656     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 657     info.parent.status_mask = 1ull<<3 /* npi */;
 658     info.func               = __cvmx_error_display;
 659     info.user_info          = (long)
 660         "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 661         "    read packet data.\n";
 662     fail |= cvmx_error_add(&info);
 663
 664     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 665     info.status_addr        = CVMX_NPI_INT_SUM;
 666     info.status_mask        = 1ull<<19 /* p0_perr */;
 667     info.enable_addr        = CVMX_NPI_INT_ENB;
 668     info.enable_mask        = 1ull<<19 /* p0_perr */;
 669     info.flags              = 0;
 670     info.group              = CVMX_ERROR_GROUP_PCI;
 671     info.group_index        = 0;
 672     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 673     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 674     info.parent.status_mask = 1ull<<3 /* npi */;
 675     info.func               = __cvmx_error_display;
 676     info.user_info          = (long)
 677         "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
 678         "    data this bit may be set.\n";
 679     fail |= cvmx_error_add(&info);
 680
 681     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 682     info.status_addr        = CVMX_NPI_INT_SUM;
 683     info.status_mask        = 1ull<<23 /* g0_rtout */;
 684     info.enable_addr        = CVMX_NPI_INT_ENB;
 685     info.enable_mask        = 1ull<<23 /* g0_rtout */;
 686     info.flags              = 0;
 687     info.group              = CVMX_ERROR_GROUP_PCI;
 688     info.group_index        = 0;
 689     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 690     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 691     info.parent.status_mask = 1ull<<3 /* npi */;
 692     info.func               = __cvmx_error_display;
 693     info.user_info          = (long)
 694         "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 695         "    read a gather list.\n";
 696     fail |= cvmx_error_add(&info);
 697
 698     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 699     info.status_addr        = CVMX_NPI_INT_SUM;
 700     info.status_mask        = 1ull<<27 /* p0_pperr */;
 701     info.enable_addr        = CVMX_NPI_INT_ENB;
 702     info.enable_mask        = 1ull<<27 /* p0_pperr */;
 703     info.flags              = 0;
 704     info.group              = CVMX_ERROR_GROUP_PCI;
 705     info.group_index        = 0;
 706     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 707     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 708     info.parent.status_mask = 1ull<<3 /* npi */;
 709     info.func               = __cvmx_error_display;
 710     info.user_info          = (long)
 711         "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
 712         "    pointer-pair, this bit may be set.\n";
 713     fail |= cvmx_error_add(&info);
 714
 715     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 716     info.status_addr        = CVMX_NPI_INT_SUM;
 717     info.status_mask        = 1ull<<31 /* p0_ptout */;
 718     info.enable_addr        = CVMX_NPI_INT_ENB;
 719     info.enable_mask        = 1ull<<31 /* p0_ptout */;
 720     info.flags              = 0;
 721     info.group              = CVMX_ERROR_GROUP_PCI;
 722     info.group_index        = 0;
 723     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 724     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 725     info.parent.status_mask = 1ull<<3 /* npi */;
 726     info.func               = __cvmx_error_display;
 727     info.user_info          = (long)
 728         "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
 729         "    pair.\n";
 730     fail |= cvmx_error_add(&info);
 731
 732     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 733     info.status_addr        = CVMX_NPI_INT_SUM;
 734     info.status_mask        = 1ull<<35 /* i0_pperr */;
 735     info.enable_addr        = CVMX_NPI_INT_ENB;
 736     info.enable_mask        = 1ull<<35 /* i0_pperr */;
 737     info.flags              = 0;
 738     info.group              = CVMX_ERROR_GROUP_PCI;
 739     info.group_index        = 0;
 740     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 741     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 742     info.parent.status_mask = 1ull<<3 /* npi */;
 743     info.func               = __cvmx_error_display;
 744     info.user_info          = (long)
 745         "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
 746         "    this bit may be set.\n";
 747     fail |= cvmx_error_add(&info);
 748
 749     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 750     info.status_addr        = CVMX_NPI_INT_SUM;
 751     info.status_mask        = 1ull<<39 /* win_rto */;
 752     info.enable_addr        = CVMX_NPI_INT_ENB;
 753     info.enable_mask        = 1ull<<39 /* win_rto */;
 754     info.flags              = 0;
 755     info.group              = CVMX_ERROR_GROUP_PCI;
 756     info.group_index        = 0;
 757     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 758     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 759     info.parent.status_mask = 1ull<<3 /* npi */;
 760     info.func               = __cvmx_error_display;
 761     info.user_info          = (long)
 762         "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
 763     fail |= cvmx_error_add(&info);
 764
 765     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 766     info.status_addr        = CVMX_NPI_INT_SUM;
 767     info.status_mask        = 1ull<<40 /* p_dperr */;
 768     info.enable_addr        = CVMX_NPI_INT_ENB;
 769     info.enable_mask        = 1ull<<40 /* p_dperr */;
 770     info.flags              = 0;
 771     info.group              = CVMX_ERROR_GROUP_PCI;
 772     info.group_index        = 0;
 773     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 774     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 775     info.parent.status_mask = 1ull<<3 /* npi */;
 776     info.func               = __cvmx_error_display;
 777     info.user_info          = (long)
 778         "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
 779         "    from the PCI this bit may be set.\n";
 780     fail |= cvmx_error_add(&info);
 781
 782     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 783     info.status_addr        = CVMX_NPI_INT_SUM;
 784     info.status_mask        = 1ull<<41 /* iobdma */;
 785     info.enable_addr        = CVMX_NPI_INT_ENB;
 786     info.enable_mask        = 1ull<<41 /* iobdma */;
 787     info.flags              = 0;
 788     info.group              = CVMX_ERROR_GROUP_PCI;
 789     info.group_index        = 0;
 790     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 791     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 792     info.parent.status_mask = 1ull<<3 /* npi */;
 793     info.func               = __cvmx_error_display;
 794     info.user_info          = (long)
 795         "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
 796     fail |= cvmx_error_add(&info);
 797
 798     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 799     info.status_addr        = CVMX_NPI_INT_SUM;
 800     info.status_mask        = 1ull<<42 /* fcr_s_e */;
 801     info.enable_addr        = CVMX_NPI_INT_ENB;
 802     info.enable_mask        = 1ull<<42 /* fcr_s_e */;
 803     info.flags              = 0;
 804     info.group              = CVMX_ERROR_GROUP_PCI;
 805     info.group_index        = 0;
 806     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 807     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 808     info.parent.status_mask = 1ull<<3 /* npi */;
 809     info.func               = __cvmx_error_display;
 810     info.user_info          = (long)
 811         "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
 812     fail |= cvmx_error_add(&info);
 813
 814     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 815     info.status_addr        = CVMX_NPI_INT_SUM;
 816     info.status_mask        = 1ull<<43 /* fcr_a_f */;
 817     info.enable_addr        = CVMX_NPI_INT_ENB;
 818     info.enable_mask        = 1ull<<43 /* fcr_a_f */;
 819     info.flags              = 0;
 820     info.group              = CVMX_ERROR_GROUP_PCI;
 821     info.group_index        = 0;
 822     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 823     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 824     info.parent.status_mask = 1ull<<3 /* npi */;
 825     info.func               = __cvmx_error_display;
 826     info.user_info          = (long)
 827         "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
 828     fail |= cvmx_error_add(&info);
 829
 830     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 831     info.status_addr        = CVMX_NPI_INT_SUM;
 832     info.status_mask        = 1ull<<44 /* pcr_s_e */;
 833     info.enable_addr        = CVMX_NPI_INT_ENB;
 834     info.enable_mask        = 1ull<<44 /* pcr_s_e */;
 835     info.flags              = 0;
 836     info.group              = CVMX_ERROR_GROUP_PCI;
 837     info.group_index        = 0;
 838     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 839     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 840     info.parent.status_mask = 1ull<<3 /* npi */;
 841     info.func               = __cvmx_error_display;
 842     info.user_info          = (long)
 843         "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
 844     fail |= cvmx_error_add(&info);
 845
 846     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 847     info.status_addr        = CVMX_NPI_INT_SUM;
 848     info.status_mask        = 1ull<<45 /* pcr_a_f */;
 849     info.enable_addr        = CVMX_NPI_INT_ENB;
 850     info.enable_mask        = 1ull<<45 /* pcr_a_f */;
 851     info.flags              = 0;
 852     info.group              = CVMX_ERROR_GROUP_PCI;
 853     info.group_index        = 0;
 854     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 855     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 856     info.parent.status_mask = 1ull<<3 /* npi */;
 857     info.func               = __cvmx_error_display;
 858     info.user_info          = (long)
 859         "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
 860     fail |= cvmx_error_add(&info);
 861
 862     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 863     info.status_addr        = CVMX_NPI_INT_SUM;
 864     info.status_mask        = 1ull<<46 /* q2_s_e */;
 865     info.enable_addr        = CVMX_NPI_INT_ENB;
 866     info.enable_mask        = 1ull<<46 /* q2_s_e */;
 867     info.flags              = 0;
 868     info.group              = CVMX_ERROR_GROUP_PCI;
 869     info.group_index        = 0;
 870     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 871     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 872     info.parent.status_mask = 1ull<<3 /* npi */;
 873     info.func               = __cvmx_error_display;
 874     info.user_info          = (long)
 875         "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
 876     fail |= cvmx_error_add(&info);
 877
 878     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 879     info.status_addr        = CVMX_NPI_INT_SUM;
 880     info.status_mask        = 1ull<<47 /* q2_a_f */;
 881     info.enable_addr        = CVMX_NPI_INT_ENB;
 882     info.enable_mask        = 1ull<<47 /* q2_a_f */;
 883     info.flags              = 0;
 884     info.group              = CVMX_ERROR_GROUP_PCI;
 885     info.group_index        = 0;
 886     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 887     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 888     info.parent.status_mask = 1ull<<3 /* npi */;
 889     info.func               = __cvmx_error_display;
 890     info.user_info          = (long)
 891         "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
 892     fail |= cvmx_error_add(&info);
 893
 894     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 895     info.status_addr        = CVMX_NPI_INT_SUM;
 896     info.status_mask        = 1ull<<48 /* q3_s_e */;
 897     info.enable_addr        = CVMX_NPI_INT_ENB;
 898     info.enable_mask        = 1ull<<48 /* q3_s_e */;
 899     info.flags              = 0;
 900     info.group              = CVMX_ERROR_GROUP_PCI;
 901     info.group_index        = 0;
 902     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 903     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 904     info.parent.status_mask = 1ull<<3 /* npi */;
 905     info.func               = __cvmx_error_display;
 906     info.user_info          = (long)
 907         "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
 908     fail |= cvmx_error_add(&info);
 909
 910     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 911     info.status_addr        = CVMX_NPI_INT_SUM;
 912     info.status_mask        = 1ull<<49 /* q3_a_f */;
 913     info.enable_addr        = CVMX_NPI_INT_ENB;
 914     info.enable_mask        = 1ull<<49 /* q3_a_f */;
 915     info.flags              = 0;
 916     info.group              = CVMX_ERROR_GROUP_PCI;
 917     info.group_index        = 0;
 918     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 919     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 920     info.parent.status_mask = 1ull<<3 /* npi */;
 921     info.func               = __cvmx_error_display;
 922     info.user_info          = (long)
 923         "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
 924     fail |= cvmx_error_add(&info);
 925
 926     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 927     info.status_addr        = CVMX_NPI_INT_SUM;
 928     info.status_mask        = 1ull<<50 /* com_s_e */;
 929     info.enable_addr        = CVMX_NPI_INT_ENB;
 930     info.enable_mask        = 1ull<<50 /* com_s_e */;
 931     info.flags              = 0;
 932     info.group              = CVMX_ERROR_GROUP_PCI;
 933     info.group_index        = 0;
 934     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 935     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 936     info.parent.status_mask = 1ull<<3 /* npi */;
 937     info.func               = __cvmx_error_display;
 938     info.user_info          = (long)
 939         "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
 940     fail |= cvmx_error_add(&info);
 941
 942     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 943     info.status_addr        = CVMX_NPI_INT_SUM;
 944     info.status_mask        = 1ull<<51 /* com_a_f */;
 945     info.enable_addr        = CVMX_NPI_INT_ENB;
 946     info.enable_mask        = 1ull<<51 /* com_a_f */;
 947     info.flags              = 0;
 948     info.group              = CVMX_ERROR_GROUP_PCI;
 949     info.group_index        = 0;
 950     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 951     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 952     info.parent.status_mask = 1ull<<3 /* npi */;
 953     info.func               = __cvmx_error_display;
 954     info.user_info          = (long)
 955         "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
 956     fail |= cvmx_error_add(&info);
 957
 958     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 959     info.status_addr        = CVMX_NPI_INT_SUM;
 960     info.status_mask        = 1ull<<52 /* pnc_s_e */;
 961     info.enable_addr        = CVMX_NPI_INT_ENB;
 962     info.enable_mask        = 1ull<<52 /* pnc_s_e */;
 963     info.flags              = 0;
 964     info.group              = CVMX_ERROR_GROUP_PCI;
 965     info.group_index        = 0;
 966     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 967     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 968     info.parent.status_mask = 1ull<<3 /* npi */;
 969     info.func               = __cvmx_error_display;
 970     info.user_info          = (long)
 971         "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
 972     fail |= cvmx_error_add(&info);
 973
 974     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 975     info.status_addr        = CVMX_NPI_INT_SUM;
 976     info.status_mask        = 1ull<<53 /* pnc_a_f */;
 977     info.enable_addr        = CVMX_NPI_INT_ENB;
 978     info.enable_mask        = 1ull<<53 /* pnc_a_f */;
 979     info.flags              = 0;
 980     info.group              = CVMX_ERROR_GROUP_PCI;
 981     info.group_index        = 0;
 982     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 983     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 984     info.parent.status_mask = 1ull<<3 /* npi */;
 985     info.func               = __cvmx_error_display;
 986     info.user_info          = (long)
 987         "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
 988     fail |= cvmx_error_add(&info);
 989
 990     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 991     info.status_addr        = CVMX_NPI_INT_SUM;
 992     info.status_mask        = 1ull<<54 /* rwx_s_e */;
 993     info.enable_addr        = CVMX_NPI_INT_ENB;
 994     info.enable_mask        = 1ull<<54 /* rwx_s_e */;
 995     info.flags              = 0;
 996     info.group              = CVMX_ERROR_GROUP_PCI;
 997     info.group_index        = 0;
 998     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 999     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1000     info.parent.status_mask = 1ull<<3 /* npi */;
1001     info.func               = __cvmx_error_display;
1002     info.user_info          = (long)
1003         "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
1004     fail |= cvmx_error_add(&info);
1005
1006     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1007     info.status_addr        = CVMX_NPI_INT_SUM;
1008     info.status_mask        = 1ull<<55 /* rdx_s_e */;
1009     info.enable_addr        = CVMX_NPI_INT_ENB;
1010     info.enable_mask        = 1ull<<55 /* rdx_s_e */;
1011     info.flags              = 0;
1012     info.group              = CVMX_ERROR_GROUP_PCI;
1013     info.group_index        = 0;
1014     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1015     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1016     info.parent.status_mask = 1ull<<3 /* npi */;
1017     info.func               = __cvmx_error_display;
1018     info.user_info          = (long)
1019         "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
1020     fail |= cvmx_error_add(&info);
1021
1022     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1023     info.status_addr        = CVMX_NPI_INT_SUM;
1024     info.status_mask        = 1ull<<56 /* pcf_p_e */;
1025     info.enable_addr        = CVMX_NPI_INT_ENB;
1026     info.enable_mask        = 1ull<<56 /* pcf_p_e */;
1027     info.flags              = 0;
1028     info.group              = CVMX_ERROR_GROUP_PCI;
1029     info.group_index        = 0;
1030     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1031     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1032     info.parent.status_mask = 1ull<<3 /* npi */;
1033     info.func               = __cvmx_error_display;
1034     info.user_info          = (long)
1035         "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
1036     fail |= cvmx_error_add(&info);
1037
1038     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1039     info.status_addr        = CVMX_NPI_INT_SUM;
1040     info.status_mask        = 1ull<<57 /* pcf_p_f */;
1041     info.enable_addr        = CVMX_NPI_INT_ENB;
1042     info.enable_mask        = 1ull<<57 /* pcf_p_f */;
1043     info.flags              = 0;
1044     info.group              = CVMX_ERROR_GROUP_PCI;
1045     info.group_index        = 0;
1046     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1047     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1048     info.parent.status_mask = 1ull<<3 /* npi */;
1049     info.func               = __cvmx_error_display;
1050     info.user_info          = (long)
1051         "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
1052     fail |= cvmx_error_add(&info);
1053
1054     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1055     info.status_addr        = CVMX_NPI_INT_SUM;
1056     info.status_mask        = 1ull<<58 /* pdf_p_e */;
1057     info.enable_addr        = CVMX_NPI_INT_ENB;
1058     info.enable_mask        = 1ull<<58 /* pdf_p_e */;
1059     info.flags              = 0;
1060     info.group              = CVMX_ERROR_GROUP_PCI;
1061     info.group_index        = 0;
1062     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1063     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1064     info.parent.status_mask = 1ull<<3 /* npi */;
1065     info.func               = __cvmx_error_display;
1066     info.user_info          = (long)
1067         "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
1068     fail |= cvmx_error_add(&info);
1069
1070     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1071     info.status_addr        = CVMX_NPI_INT_SUM;
1072     info.status_mask        = 1ull<<59 /* pdf_p_f */;
1073     info.enable_addr        = CVMX_NPI_INT_ENB;
1074     info.enable_mask        = 1ull<<59 /* pdf_p_f */;
1075     info.flags              = 0;
1076     info.group              = CVMX_ERROR_GROUP_PCI;
1077     info.group_index        = 0;
1078     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1079     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1080     info.parent.status_mask = 1ull<<3 /* npi */;
1081     info.func               = __cvmx_error_display;
1082     info.user_info          = (long)
1083         "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
1084     fail |= cvmx_error_add(&info);
1085
1086     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1087     info.status_addr        = CVMX_NPI_INT_SUM;
1088     info.status_mask        = 1ull<<60 /* q1_s_e */;
1089     info.enable_addr        = CVMX_NPI_INT_ENB;
1090     info.enable_mask        = 1ull<<60 /* q1_s_e */;
1091     info.flags              = 0;
1092     info.group              = CVMX_ERROR_GROUP_PCI;
1093     info.group_index        = 0;
1094     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1095     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1096     info.parent.status_mask = 1ull<<3 /* npi */;
1097     info.func               = __cvmx_error_display;
1098     info.user_info          = (long)
1099         "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
1100     fail |= cvmx_error_add(&info);
1101
1102     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1103     info.status_addr        = CVMX_NPI_INT_SUM;
1104     info.status_mask        = 1ull<<61 /* q1_a_f */;
1105     info.enable_addr        = CVMX_NPI_INT_ENB;
1106     info.enable_mask        = 1ull<<61 /* q1_a_f */;
1107     info.flags              = 0;
1108     info.group              = CVMX_ERROR_GROUP_PCI;
1109     info.group_index        = 0;
1110     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1111     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1112     info.parent.status_mask = 1ull<<3 /* npi */;
1113     info.func               = __cvmx_error_display;
1114     info.user_info          = (long)
1115         "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
1116     fail |= cvmx_error_add(&info);
1117
1118     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1119     info.status_addr        = CVMX_NPI_INT_SUM;
1120     info.status_mask        = 0;
1121     info.enable_addr        = 0;
1122     info.enable_mask        = 0;
1123     info.flags              = 0;
1124     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1125     info.group_index        = 0;
1126     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1127     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1128     info.parent.status_mask = 1ull<<3 /* npi */;
1129     info.func               = __cvmx_error_decode;
1130     info.user_info          = 0;
1131     fail |= cvmx_error_add(&info);
1132
1133     /* CVMX_NPI_PCI_INT_SUM2 */
1134     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1135     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1136     info.status_mask        = 1ull<<0 /* tr_wabt */;
1137     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1138     info.enable_mask        = 1ull<<0 /* rtr_wabt */;
1139     info.flags              = 0;
1140     info.group              = CVMX_ERROR_GROUP_PCI;
1141     info.group_index        = 0;
1142     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1143     info.parent.status_addr = CVMX_NPI_INT_SUM;
1144     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1145     info.func               = __cvmx_error_display;
1146     info.user_info          = (long)
1147         "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
1148     fail |= cvmx_error_add(&info);
1149
1150     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1151     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1152     info.status_mask        = 1ull<<1 /* mr_wabt */;
1153     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1154     info.enable_mask        = 1ull<<1 /* rmr_wabt */;
1155     info.flags              = 0;
1156     info.group              = CVMX_ERROR_GROUP_PCI;
1157     info.group_index        = 0;
1158     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1159     info.parent.status_addr = CVMX_NPI_INT_SUM;
1160     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1161     info.func               = __cvmx_error_display;
1162     info.user_info          = (long)
1163         "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
1164     fail |= cvmx_error_add(&info);
1165
1166     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1167     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1168     info.status_mask        = 1ull<<2 /* mr_wtto */;
1169     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1170     info.enable_mask        = 1ull<<2 /* rmr_wtto */;
1171     info.flags              = 0;
1172     info.group              = CVMX_ERROR_GROUP_PCI;
1173     info.group_index        = 0;
1174     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1175     info.parent.status_addr = CVMX_NPI_INT_SUM;
1176     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1177     info.func               = __cvmx_error_display;
1178     info.user_info          = (long)
1179         "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
1180     fail |= cvmx_error_add(&info);
1181
1182     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1183     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1184     info.status_mask        = 1ull<<3 /* tr_abt */;
1185     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1186     info.enable_mask        = 1ull<<3 /* rtr_abt */;
1187     info.flags              = 0;
1188     info.group              = CVMX_ERROR_GROUP_PCI;
1189     info.group_index        = 0;
1190     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1191     info.parent.status_addr = CVMX_NPI_INT_SUM;
1192     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1193     info.func               = __cvmx_error_display;
1194     info.user_info          = (long)
1195         "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
1196     fail |= cvmx_error_add(&info);
1197
1198     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1199     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1200     info.status_mask        = 1ull<<4 /* mr_abt */;
1201     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1202     info.enable_mask        = 1ull<<4 /* rmr_abt */;
1203     info.flags              = 0;
1204     info.group              = CVMX_ERROR_GROUP_PCI;
1205     info.group_index        = 0;
1206     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1207     info.parent.status_addr = CVMX_NPI_INT_SUM;
1208     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1209     info.func               = __cvmx_error_display;
1210     info.user_info          = (long)
1211         "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
1212     fail |= cvmx_error_add(&info);
1213
1214     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1215     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1216     info.status_mask        = 1ull<<5 /* mr_tto */;
1217     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1218     info.enable_mask        = 1ull<<5 /* rmr_tto */;
1219     info.flags              = 0;
1220     info.group              = CVMX_ERROR_GROUP_PCI;
1221     info.group_index        = 0;
1222     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1223     info.parent.status_addr = CVMX_NPI_INT_SUM;
1224     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1225     info.func               = __cvmx_error_display;
1226     info.user_info          = (long)
1227         "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
1228     fail |= cvmx_error_add(&info);
1229
1230     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1231     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1232     info.status_mask        = 1ull<<6 /* msi_per */;
1233     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1234     info.enable_mask        = 1ull<<6 /* rmsi_per */;
1235     info.flags              = 0;
1236     info.group              = CVMX_ERROR_GROUP_PCI;
1237     info.group_index        = 0;
1238     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1239     info.parent.status_addr = CVMX_NPI_INT_SUM;
1240     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1241     info.func               = __cvmx_error_display;
1242     info.user_info          = (long)
1243         "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
1244     fail |= cvmx_error_add(&info);
1245
1246     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1247     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1248     info.status_mask        = 1ull<<7 /* msi_tabt */;
1249     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1250     info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
1251     info.flags              = 0;
1252     info.group              = CVMX_ERROR_GROUP_PCI;
1253     info.group_index        = 0;
1254     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1255     info.parent.status_addr = CVMX_NPI_INT_SUM;
1256     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1257     info.func               = __cvmx_error_display;
1258     info.user_info          = (long)
1259         "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
1260     fail |= cvmx_error_add(&info);
1261
1262     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1263     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1264     info.status_mask        = 1ull<<8 /* msi_mabt */;
1265     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1266     info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
1267     info.flags              = 0;
1268     info.group              = CVMX_ERROR_GROUP_PCI;
1269     info.group_index        = 0;
1270     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1271     info.parent.status_addr = CVMX_NPI_INT_SUM;
1272     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1273     info.func               = __cvmx_error_display;
1274     info.user_info          = (long)
1275         "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
1276     fail |= cvmx_error_add(&info);
1277
1278     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1279     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1280     info.status_mask        = 1ull<<9 /* msc_msg */;
1281     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1282     info.enable_mask        = 1ull<<9 /* rmsc_msg */;
1283     info.flags              = 0;
1284     info.group              = CVMX_ERROR_GROUP_PCI;
1285     info.group_index        = 0;
1286     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1287     info.parent.status_addr = CVMX_NPI_INT_SUM;
1288     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1289     info.func               = __cvmx_error_display;
1290     info.user_info          = (long)
1291         "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
1292     fail |= cvmx_error_add(&info);
1293
1294     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1295     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1296     info.status_mask        = 1ull<<10 /* tsr_abt */;
1297     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1298     info.enable_mask        = 1ull<<10 /* rtsr_abt */;
1299     info.flags              = 0;
1300     info.group              = CVMX_ERROR_GROUP_PCI;
1301     info.group_index        = 0;
1302     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1303     info.parent.status_addr = CVMX_NPI_INT_SUM;
1304     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1305     info.func               = __cvmx_error_display;
1306     info.user_info          = (long)
1307         "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
1308     fail |= cvmx_error_add(&info);
1309
1310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1311     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1312     info.status_mask        = 1ull<<11 /* serr */;
1313     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1314     info.enable_mask        = 1ull<<11 /* rserr */;
1315     info.flags              = 0;
1316     info.group              = CVMX_ERROR_GROUP_PCI;
1317     info.group_index        = 0;
1318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1319     info.parent.status_addr = CVMX_NPI_INT_SUM;
1320     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1321     info.func               = __cvmx_error_display;
1322     info.user_info          = (long)
1323         "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
1324     fail |= cvmx_error_add(&info);
1325
1326     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1327     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1328     info.status_mask        = 1ull<<12 /* aperr */;
1329     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1330     info.enable_mask        = 1ull<<12 /* raperr */;
1331     info.flags              = 0;
1332     info.group              = CVMX_ERROR_GROUP_PCI;
1333     info.group_index        = 0;
1334     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1335     info.parent.status_addr = CVMX_NPI_INT_SUM;
1336     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1337     info.func               = __cvmx_error_display;
1338     info.user_info          = (long)
1339         "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
1340     fail |= cvmx_error_add(&info);
1341
1342     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1343     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1344     info.status_mask        = 1ull<<13 /* dperr */;
1345     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1346     info.enable_mask        = 1ull<<13 /* rdperr */;
1347     info.flags              = 0;
1348     info.group              = CVMX_ERROR_GROUP_PCI;
1349     info.group_index        = 0;
1350     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1351     info.parent.status_addr = CVMX_NPI_INT_SUM;
1352     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1353     info.func               = __cvmx_error_display;
1354     info.user_info          = (long)
1355         "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
1356     fail |= cvmx_error_add(&info);
1357
1358     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1359     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1360     info.status_mask        = 1ull<<14 /* ill_rwr */;
1361     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1362     info.enable_mask        = 1ull<<14 /* ill_rwr */;
1363     info.flags              = 0;
1364     info.group              = CVMX_ERROR_GROUP_PCI;
1365     info.group_index        = 0;
1366     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1367     info.parent.status_addr = CVMX_NPI_INT_SUM;
1368     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1369     info.func               = __cvmx_error_display;
1370     info.user_info          = (long)
1371         "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
1372     fail |= cvmx_error_add(&info);
1373
1374     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1375     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1376     info.status_mask        = 1ull<<15 /* ill_rrd */;
1377     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1378     info.enable_mask        = 1ull<<15 /* ill_rrd */;
1379     info.flags              = 0;
1380     info.group              = CVMX_ERROR_GROUP_PCI;
1381     info.group_index        = 0;
1382     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1383     info.parent.status_addr = CVMX_NPI_INT_SUM;
1384     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1385     info.func               = __cvmx_error_display;
1386     info.user_info          = (long)
1387         "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
1388     fail |= cvmx_error_add(&info);
1389
1390     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1391     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1392     info.status_mask        = 1ull<<31 /* win_wr */;
1393     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1394     info.enable_mask        = 1ull<<31 /* win_wr */;
1395     info.flags              = 0;
1396     info.group              = CVMX_ERROR_GROUP_PCI;
1397     info.group_index        = 0;
1398     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1399     info.parent.status_addr = CVMX_NPI_INT_SUM;
1400     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1401     info.func               = __cvmx_error_display;
1402     info.user_info          = (long)
1403         "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
1404         "    Read-Address Register took place.\n";
1405     fail |= cvmx_error_add(&info);
1406
1407     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1408     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1409     info.status_mask        = 1ull<<32 /* ill_wr */;
1410     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1411     info.enable_mask        = 1ull<<32 /* ill_wr */;
1412     info.flags              = 0;
1413     info.group              = CVMX_ERROR_GROUP_PCI;
1414     info.group_index        = 0;
1415     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1416     info.parent.status_addr = CVMX_NPI_INT_SUM;
1417     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1418     info.func               = __cvmx_error_display;
1419     info.user_info          = (long)
1420         "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
1421         "    when the mem area is disabled.\n";
1422     fail |= cvmx_error_add(&info);
1423
1424     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1425     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1426     info.status_mask        = 1ull<<33 /* ill_rd */;
1427     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1428     info.enable_mask        = 1ull<<33 /* ill_rd */;
1429     info.flags              = 0;
1430     info.group              = CVMX_ERROR_GROUP_PCI;
1431     info.group_index        = 0;
1432     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1433     info.parent.status_addr = CVMX_NPI_INT_SUM;
1434     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1435     info.func               = __cvmx_error_display;
1436     info.user_info          = (long)
1437         "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
1438         "    when the mem area is disabled.\n";
1439     fail |= cvmx_error_add(&info);
1440
1441     /* CVMX_FPA_INT_SUM */
1442     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1443     info.status_addr        = CVMX_FPA_INT_SUM;
1444     info.status_mask        = 1ull<<0 /* fed0_sbe */;
1445     info.enable_addr        = CVMX_FPA_INT_ENB;
1446     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
1447     info.flags              = 0;
1448     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1449     info.group_index        = 0;
1450     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1451     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1452     info.parent.status_mask = 1ull<<5 /* fpa */;
1453     info.func               = __cvmx_error_display;
1454     info.user_info          = (long)
1455         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
1456     fail |= cvmx_error_add(&info);
1457
1458     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1459     info.status_addr        = CVMX_FPA_INT_SUM;
1460     info.status_mask        = 1ull<<1 /* fed0_dbe */;
1461     info.enable_addr        = CVMX_FPA_INT_ENB;
1462     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
1463     info.flags              = 0;
1464     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1465     info.group_index        = 0;
1466     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1467     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1468     info.parent.status_mask = 1ull<<5 /* fpa */;
1469     info.func               = __cvmx_error_display;
1470     info.user_info          = (long)
1471         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
1472     fail |= cvmx_error_add(&info);
1473
1474     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1475     info.status_addr        = CVMX_FPA_INT_SUM;
1476     info.status_mask        = 1ull<<2 /* fed1_sbe */;
1477     info.enable_addr        = CVMX_FPA_INT_ENB;
1478     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
1479     info.flags              = 0;
1480     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1481     info.group_index        = 0;
1482     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1483     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1484     info.parent.status_mask = 1ull<<5 /* fpa */;
1485     info.func               = __cvmx_error_display;
1486     info.user_info          = (long)
1487         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
1488     fail |= cvmx_error_add(&info);
1489
1490     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1491     info.status_addr        = CVMX_FPA_INT_SUM;
1492     info.status_mask        = 1ull<<3 /* fed1_dbe */;
1493     info.enable_addr        = CVMX_FPA_INT_ENB;
1494     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
1495     info.flags              = 0;
1496     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1497     info.group_index        = 0;
1498     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1499     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1500     info.parent.status_mask = 1ull<<5 /* fpa */;
1501     info.func               = __cvmx_error_display;
1502     info.user_info          = (long)
1503         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
1504     fail |= cvmx_error_add(&info);
1505
1506     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1507     info.status_addr        = CVMX_FPA_INT_SUM;
1508     info.status_mask        = 1ull<<4 /* q0_und */;
1509     info.enable_addr        = CVMX_FPA_INT_ENB;
1510     info.enable_mask        = 1ull<<4 /* q0_und */;
1511     info.flags              = 0;
1512     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1513     info.group_index        = 0;
1514     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1515     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1516     info.parent.status_mask = 1ull<<5 /* fpa */;
1517     info.func               = __cvmx_error_display;
1518     info.user_info          = (long)
1519         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
1520         "    negative.\n";
1521     fail |= cvmx_error_add(&info);
1522
1523     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1524     info.status_addr        = CVMX_FPA_INT_SUM;
1525     info.status_mask        = 1ull<<5 /* q0_coff */;
1526     info.enable_addr        = CVMX_FPA_INT_ENB;
1527     info.enable_mask        = 1ull<<5 /* q0_coff */;
1528     info.flags              = 0;
1529     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1530     info.group_index        = 0;
1531     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1532     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1533     info.parent.status_mask = 1ull<<5 /* fpa */;
1534     info.func               = __cvmx_error_display;
1535     info.user_info          = (long)
1536         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
1537         "    the count available is greater than pointers\n"
1538         "    present in the FPA.\n";
1539     fail |= cvmx_error_add(&info);
1540
1541     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1542     info.status_addr        = CVMX_FPA_INT_SUM;
1543     info.status_mask        = 1ull<<6 /* q0_perr */;
1544     info.enable_addr        = CVMX_FPA_INT_ENB;
1545     info.enable_mask        = 1ull<<6 /* q0_perr */;
1546     info.flags              = 0;
1547     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1548     info.group_index        = 0;
1549     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1550     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1551     info.parent.status_mask = 1ull<<5 /* fpa */;
1552     info.func               = __cvmx_error_display;
1553     info.user_info          = (long)
1554         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
1555         "    the L2C does not have the FPA owner ship bit set.\n";
1556     fail |= cvmx_error_add(&info);
1557
1558     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1559     info.status_addr        = CVMX_FPA_INT_SUM;
1560     info.status_mask        = 1ull<<7 /* q1_und */;
1561     info.enable_addr        = CVMX_FPA_INT_ENB;
1562     info.enable_mask        = 1ull<<7 /* q1_und */;
1563     info.flags              = 0;
1564     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1565     info.group_index        = 0;
1566     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1567     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1568     info.parent.status_mask = 1ull<<5 /* fpa */;
1569     info.func               = __cvmx_error_display;
1570     info.user_info          = (long)
1571         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
1572         "    negative.\n";
1573     fail |= cvmx_error_add(&info);
1574
1575     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1576     info.status_addr        = CVMX_FPA_INT_SUM;
1577     info.status_mask        = 1ull<<8 /* q1_coff */;
1578     info.enable_addr        = CVMX_FPA_INT_ENB;
1579     info.enable_mask        = 1ull<<8 /* q1_coff */;
1580     info.flags              = 0;
1581     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1582     info.group_index        = 0;
1583     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1584     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1585     info.parent.status_mask = 1ull<<5 /* fpa */;
1586     info.func               = __cvmx_error_display;
1587     info.user_info          = (long)
1588         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
1589         "    the count available is greater than pointers\n"
1590         "    present in the FPA.\n";
1591     fail |= cvmx_error_add(&info);
1592
1593     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1594     info.status_addr        = CVMX_FPA_INT_SUM;
1595     info.status_mask        = 1ull<<9 /* q1_perr */;
1596     info.enable_addr        = CVMX_FPA_INT_ENB;
1597     info.enable_mask        = 1ull<<9 /* q1_perr */;
1598     info.flags              = 0;
1599     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1600     info.group_index        = 0;
1601     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1602     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1603     info.parent.status_mask = 1ull<<5 /* fpa */;
1604     info.func               = __cvmx_error_display;
1605     info.user_info          = (long)
1606         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
1607         "    the L2C does not have the FPA owner ship bit set.\n";
1608     fail |= cvmx_error_add(&info);
1609
1610     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1611     info.status_addr        = CVMX_FPA_INT_SUM;
1612     info.status_mask        = 1ull<<10 /* q2_und */;
1613     info.enable_addr        = CVMX_FPA_INT_ENB;
1614     info.enable_mask        = 1ull<<10 /* q2_und */;
1615     info.flags              = 0;
1616     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1617     info.group_index        = 0;
1618     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1619     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1620     info.parent.status_mask = 1ull<<5 /* fpa */;
1621     info.func               = __cvmx_error_display;
1622     info.user_info          = (long)
1623         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
1624         "    negative.\n";
1625     fail |= cvmx_error_add(&info);
1626
1627     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1628     info.status_addr        = CVMX_FPA_INT_SUM;
1629     info.status_mask        = 1ull<<11 /* q2_coff */;
1630     info.enable_addr        = CVMX_FPA_INT_ENB;
1631     info.enable_mask        = 1ull<<11 /* q2_coff */;
1632     info.flags              = 0;
1633     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1634     info.group_index        = 0;
1635     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1636     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1637     info.parent.status_mask = 1ull<<5 /* fpa */;
1638     info.func               = __cvmx_error_display;
1639     info.user_info          = (long)
1640         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
1641         "    the count available is greater than than pointers\n"
1642         "    present in the FPA.\n";
1643     fail |= cvmx_error_add(&info);
1644
1645     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1646     info.status_addr        = CVMX_FPA_INT_SUM;
1647     info.status_mask        = 1ull<<12 /* q2_perr */;
1648     info.enable_addr        = CVMX_FPA_INT_ENB;
1649     info.enable_mask        = 1ull<<12 /* q2_perr */;
1650     info.flags              = 0;
1651     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1652     info.group_index        = 0;
1653     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1654     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1655     info.parent.status_mask = 1ull<<5 /* fpa */;
1656     info.func               = __cvmx_error_display;
1657     info.user_info          = (long)
1658         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
1659         "    the L2C does not have the FPA owner ship bit set.\n";
1660     fail |= cvmx_error_add(&info);
1661
1662     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1663     info.status_addr        = CVMX_FPA_INT_SUM;
1664     info.status_mask        = 1ull<<13 /* q3_und */;
1665     info.enable_addr        = CVMX_FPA_INT_ENB;
1666     info.enable_mask        = 1ull<<13 /* q3_und */;
1667     info.flags              = 0;
1668     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1669     info.group_index        = 0;
1670     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1671     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1672     info.parent.status_mask = 1ull<<5 /* fpa */;
1673     info.func               = __cvmx_error_display;
1674     info.user_info          = (long)
1675         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
1676         "    negative.\n";
1677     fail |= cvmx_error_add(&info);
1678
1679     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1680     info.status_addr        = CVMX_FPA_INT_SUM;
1681     info.status_mask        = 1ull<<14 /* q3_coff */;
1682     info.enable_addr        = CVMX_FPA_INT_ENB;
1683     info.enable_mask        = 1ull<<14 /* q3_coff */;
1684     info.flags              = 0;
1685     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1686     info.group_index        = 0;
1687     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1688     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1689     info.parent.status_mask = 1ull<<5 /* fpa */;
1690     info.func               = __cvmx_error_display;
1691     info.user_info          = (long)
1692         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
1693         "    the count available is greater than than pointers\n"
1694         "    present in the FPA.\n";
1695     fail |= cvmx_error_add(&info);
1696
1697     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1698     info.status_addr        = CVMX_FPA_INT_SUM;
1699     info.status_mask        = 1ull<<15 /* q3_perr */;
1700     info.enable_addr        = CVMX_FPA_INT_ENB;
1701     info.enable_mask        = 1ull<<15 /* q3_perr */;
1702     info.flags              = 0;
1703     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1704     info.group_index        = 0;
1705     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1706     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1707     info.parent.status_mask = 1ull<<5 /* fpa */;
1708     info.func               = __cvmx_error_display;
1709     info.user_info          = (long)
1710         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
1711         "    the L2C does not have the FPA owner ship bit set.\n";
1712     fail |= cvmx_error_add(&info);
1713
1714     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1715     info.status_addr        = CVMX_FPA_INT_SUM;
1716     info.status_mask        = 1ull<<16 /* q4_und */;
1717     info.enable_addr        = CVMX_FPA_INT_ENB;
1718     info.enable_mask        = 1ull<<16 /* q4_und */;
1719     info.flags              = 0;
1720     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1721     info.group_index        = 0;
1722     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1723     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1724     info.parent.status_mask = 1ull<<5 /* fpa */;
1725     info.func               = __cvmx_error_display;
1726     info.user_info          = (long)
1727         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
1728         "    negative.\n";
1729     fail |= cvmx_error_add(&info);
1730
1731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1732     info.status_addr        = CVMX_FPA_INT_SUM;
1733     info.status_mask        = 1ull<<17 /* q4_coff */;
1734     info.enable_addr        = CVMX_FPA_INT_ENB;
1735     info.enable_mask        = 1ull<<17 /* q4_coff */;
1736     info.flags              = 0;
1737     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1738     info.group_index        = 0;
1739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1740     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1741     info.parent.status_mask = 1ull<<5 /* fpa */;
1742     info.func               = __cvmx_error_display;
1743     info.user_info          = (long)
1744         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
1745         "    the count available is greater than than pointers\n"
1746         "    present in the FPA.\n";
1747     fail |= cvmx_error_add(&info);
1748
1749     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1750     info.status_addr        = CVMX_FPA_INT_SUM;
1751     info.status_mask        = 1ull<<18 /* q4_perr */;
1752     info.enable_addr        = CVMX_FPA_INT_ENB;
1753     info.enable_mask        = 1ull<<18 /* q4_perr */;
1754     info.flags              = 0;
1755     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1756     info.group_index        = 0;
1757     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1758     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1759     info.parent.status_mask = 1ull<<5 /* fpa */;
1760     info.func               = __cvmx_error_display;
1761     info.user_info          = (long)
1762         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
1763         "    the L2C does not have the FPA owner ship bit set.\n";
1764     fail |= cvmx_error_add(&info);
1765
1766     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1767     info.status_addr        = CVMX_FPA_INT_SUM;
1768     info.status_mask        = 1ull<<19 /* q5_und */;
1769     info.enable_addr        = CVMX_FPA_INT_ENB;
1770     info.enable_mask        = 1ull<<19 /* q5_und */;
1771     info.flags              = 0;
1772     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1773     info.group_index        = 0;
1774     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1775     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1776     info.parent.status_mask = 1ull<<5 /* fpa */;
1777     info.func               = __cvmx_error_display;
1778     info.user_info          = (long)
1779         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
1780         "    negative.\n";
1781     fail |= cvmx_error_add(&info);
1782
1783     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1784     info.status_addr        = CVMX_FPA_INT_SUM;
1785     info.status_mask        = 1ull<<20 /* q5_coff */;
1786     info.enable_addr        = CVMX_FPA_INT_ENB;
1787     info.enable_mask        = 1ull<<20 /* q5_coff */;
1788     info.flags              = 0;
1789     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1790     info.group_index        = 0;
1791     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1792     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1793     info.parent.status_mask = 1ull<<5 /* fpa */;
1794     info.func               = __cvmx_error_display;
1795     info.user_info          = (long)
1796         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
1797         "    the count available is greater than than pointers\n"
1798         "    present in the FPA.\n";
1799     fail |= cvmx_error_add(&info);
1800
1801     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1802     info.status_addr        = CVMX_FPA_INT_SUM;
1803     info.status_mask        = 1ull<<21 /* q5_perr */;
1804     info.enable_addr        = CVMX_FPA_INT_ENB;
1805     info.enable_mask        = 1ull<<21 /* q5_perr */;
1806     info.flags              = 0;
1807     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1808     info.group_index        = 0;
1809     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1810     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1811     info.parent.status_mask = 1ull<<5 /* fpa */;
1812     info.func               = __cvmx_error_display;
1813     info.user_info          = (long)
1814         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
1815         "    the L2C does not have the FPA owner ship bit set.\n";
1816     fail |= cvmx_error_add(&info);
1817
1818     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1819     info.status_addr        = CVMX_FPA_INT_SUM;
1820     info.status_mask        = 1ull<<22 /* q6_und */;
1821     info.enable_addr        = CVMX_FPA_INT_ENB;
1822     info.enable_mask        = 1ull<<22 /* q6_und */;
1823     info.flags              = 0;
1824     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1825     info.group_index        = 0;
1826     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1827     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1828     info.parent.status_mask = 1ull<<5 /* fpa */;
1829     info.func               = __cvmx_error_display;
1830     info.user_info          = (long)
1831         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
1832         "    negative.\n";
1833     fail |= cvmx_error_add(&info);
1834
1835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1836     info.status_addr        = CVMX_FPA_INT_SUM;
1837     info.status_mask        = 1ull<<23 /* q6_coff */;
1838     info.enable_addr        = CVMX_FPA_INT_ENB;
1839     info.enable_mask        = 1ull<<23 /* q6_coff */;
1840     info.flags              = 0;
1841     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1842     info.group_index        = 0;
1843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1844     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1845     info.parent.status_mask = 1ull<<5 /* fpa */;
1846     info.func               = __cvmx_error_display;
1847     info.user_info          = (long)
1848         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
1849         "    the count available is greater than than pointers\n"
1850         "    present in the FPA.\n";
1851     fail |= cvmx_error_add(&info);
1852
1853     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1854     info.status_addr        = CVMX_FPA_INT_SUM;
1855     info.status_mask        = 1ull<<24 /* q6_perr */;
1856     info.enable_addr        = CVMX_FPA_INT_ENB;
1857     info.enable_mask        = 1ull<<24 /* q6_perr */;
1858     info.flags              = 0;
1859     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1860     info.group_index        = 0;
1861     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1862     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1863     info.parent.status_mask = 1ull<<5 /* fpa */;
1864     info.func               = __cvmx_error_display;
1865     info.user_info          = (long)
1866         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
1867         "    the L2C does not have the FPA owner ship bit set.\n";
1868     fail |= cvmx_error_add(&info);
1869
1870     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1871     info.status_addr        = CVMX_FPA_INT_SUM;
1872     info.status_mask        = 1ull<<25 /* q7_und */;
1873     info.enable_addr        = CVMX_FPA_INT_ENB;
1874     info.enable_mask        = 1ull<<25 /* q7_und */;
1875     info.flags              = 0;
1876     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1877     info.group_index        = 0;
1878     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1879     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1880     info.parent.status_mask = 1ull<<5 /* fpa */;
1881     info.func               = __cvmx_error_display;
1882     info.user_info          = (long)
1883         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
1884         "    negative.\n";
1885     fail |= cvmx_error_add(&info);
1886
1887     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1888     info.status_addr        = CVMX_FPA_INT_SUM;
1889     info.status_mask        = 1ull<<26 /* q7_coff */;
1890     info.enable_addr        = CVMX_FPA_INT_ENB;
1891     info.enable_mask        = 1ull<<26 /* q7_coff */;
1892     info.flags              = 0;
1893     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1894     info.group_index        = 0;
1895     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1896     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1897     info.parent.status_mask = 1ull<<5 /* fpa */;
1898     info.func               = __cvmx_error_display;
1899     info.user_info          = (long)
1900         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
1901         "    the count available is greater than than pointers\n"
1902         "    present in the FPA.\n";
1903     fail |= cvmx_error_add(&info);
1904
1905     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1906     info.status_addr        = CVMX_FPA_INT_SUM;
1907     info.status_mask        = 1ull<<27 /* q7_perr */;
1908     info.enable_addr        = CVMX_FPA_INT_ENB;
1909     info.enable_mask        = 1ull<<27 /* q7_perr */;
1910     info.flags              = 0;
1911     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1912     info.group_index        = 0;
1913     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1914     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1915     info.parent.status_mask = 1ull<<5 /* fpa */;
1916     info.func               = __cvmx_error_display;
1917     info.user_info          = (long)
1918         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
1919         "    the L2C does not have the FPA owner ship bit set.\n";
1920     fail |= cvmx_error_add(&info);
1921
1922     /* CVMX_MIO_BOOT_ERR */
1923     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1924     info.status_addr        = CVMX_MIO_BOOT_ERR;
1925     info.status_mask        = 1ull<<0 /* adr_err */;
1926     info.enable_addr        = CVMX_MIO_BOOT_INT;
1927     info.enable_mask        = 1ull<<0 /* adr_int */;
1928     info.flags              = 0;
1929     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1930     info.group_index        = 0;
1931     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1932     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1933     info.parent.status_mask = 1ull<<0 /* mio */;
1934     info.func               = __cvmx_error_display;
1935     info.user_info          = (long)
1936         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
1937     fail |= cvmx_error_add(&info);
1938
1939     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1940     info.status_addr        = CVMX_MIO_BOOT_ERR;
1941     info.status_mask        = 1ull<<1 /* wait_err */;
1942     info.enable_addr        = CVMX_MIO_BOOT_INT;
1943     info.enable_mask        = 1ull<<1 /* wait_int */;
1944     info.flags              = 0;
1945     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1946     info.group_index        = 0;
1947     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1948     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1949     info.parent.status_mask = 1ull<<0 /* mio */;
1950     info.func               = __cvmx_error_display;
1951     info.user_info          = (long)
1952         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
1953     fail |= cvmx_error_add(&info);
1954
1955     /* CVMX_IPD_INT_SUM */
1956     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1957     info.status_addr        = CVMX_IPD_INT_SUM;
1958     info.status_mask        = 1ull<<0 /* prc_par0 */;
1959     info.enable_addr        = CVMX_IPD_INT_ENB;
1960     info.enable_mask        = 1ull<<0 /* prc_par0 */;
1961     info.flags              = 0;
1962     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1963     info.group_index        = 0;
1964     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1965     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1966     info.parent.status_mask = 1ull<<9 /* ipd */;
1967     info.func               = __cvmx_error_display;
1968     info.user_info          = (long)
1969         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
1970         "    [31:0] of the PBM memory.\n";
1971     fail |= cvmx_error_add(&info);
1972
1973     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1974     info.status_addr        = CVMX_IPD_INT_SUM;
1975     info.status_mask        = 1ull<<1 /* prc_par1 */;
1976     info.enable_addr        = CVMX_IPD_INT_ENB;
1977     info.enable_mask        = 1ull<<1 /* prc_par1 */;
1978     info.flags              = 0;
1979     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1980     info.group_index        = 0;
1981     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1982     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1983     info.parent.status_mask = 1ull<<9 /* ipd */;
1984     info.func               = __cvmx_error_display;
1985     info.user_info          = (long)
1986         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
1987         "    [63:32] of the PBM memory.\n";
1988     fail |= cvmx_error_add(&info);
1989
1990     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1991     info.status_addr        = CVMX_IPD_INT_SUM;
1992     info.status_mask        = 1ull<<2 /* prc_par2 */;
1993     info.enable_addr        = CVMX_IPD_INT_ENB;
1994     info.enable_mask        = 1ull<<2 /* prc_par2 */;
1995     info.flags              = 0;
1996     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1997     info.group_index        = 0;
1998     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1999     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2000     info.parent.status_mask = 1ull<<9 /* ipd */;
2001     info.func               = __cvmx_error_display;
2002     info.user_info          = (long)
2003         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2004         "    [95:64] of the PBM memory.\n";
2005     fail |= cvmx_error_add(&info);
2006
2007     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2008     info.status_addr        = CVMX_IPD_INT_SUM;
2009     info.status_mask        = 1ull<<3 /* prc_par3 */;
2010     info.enable_addr        = CVMX_IPD_INT_ENB;
2011     info.enable_mask        = 1ull<<3 /* prc_par3 */;
2012     info.flags              = 0;
2013     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2014     info.group_index        = 0;
2015     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2016     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2017     info.parent.status_mask = 1ull<<9 /* ipd */;
2018     info.func               = __cvmx_error_display;
2019     info.user_info          = (long)
2020         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2021         "    [127:96] of the PBM memory.\n";
2022     fail |= cvmx_error_add(&info);
2023
2024     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2025     info.status_addr        = CVMX_IPD_INT_SUM;
2026     info.status_mask        = 1ull<<4 /* bp_sub */;
2027     info.enable_addr        = CVMX_IPD_INT_ENB;
2028     info.enable_mask        = 1ull<<4 /* bp_sub */;
2029     info.flags              = 0;
2030     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2031     info.group_index        = 0;
2032     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2033     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2034     info.parent.status_mask = 1ull<<9 /* ipd */;
2035     info.func               = __cvmx_error_display;
2036     info.user_info          = (long)
2037         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2038         "    supplied illegal value.\n";
2039     fail |= cvmx_error_add(&info);
2040
2041     /* CVMX_POW_ECC_ERR */
2042     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2043     info.status_addr        = CVMX_POW_ECC_ERR;
2044     info.status_mask        = 1ull<<0 /* sbe */;
2045     info.enable_addr        = CVMX_POW_ECC_ERR;
2046     info.enable_mask        = 1ull<<2 /* sbe_ie */;
2047     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2048     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2049     info.group_index        = 0;
2050     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2051     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2052     info.parent.status_mask = 1ull<<12 /* pow */;
2053     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
2054     info.user_info          = (long)
2055         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2056     fail |= cvmx_error_add(&info);
2057
2058     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2059     info.status_addr        = CVMX_POW_ECC_ERR;
2060     info.status_mask        = 1ull<<1 /* dbe */;
2061     info.enable_addr        = CVMX_POW_ECC_ERR;
2062     info.enable_mask        = 1ull<<3 /* dbe_ie */;
2063     info.flags              = 0;
2064     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2065     info.group_index        = 0;
2066     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2067     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2068     info.parent.status_mask = 1ull<<12 /* pow */;
2069     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
2070     info.user_info          = (long)
2071         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2072     fail |= cvmx_error_add(&info);
2073
2074     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2075     info.status_addr        = CVMX_POW_ECC_ERR;
2076     info.status_mask        = 1ull<<12 /* rpe */;
2077     info.enable_addr        = CVMX_POW_ECC_ERR;
2078     info.enable_mask        = 1ull<<13 /* rpe_ie */;
2079     info.flags              = 0;
2080     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2081     info.group_index        = 0;
2082     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2083     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2084     info.parent.status_mask = 1ull<<12 /* pow */;
2085     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
2086     info.user_info          = (long)
2087         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2088     fail |= cvmx_error_add(&info);
2089
2090     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2091     info.status_addr        = CVMX_POW_ECC_ERR;
2092     info.status_mask        = 0x1fffull<<16 /* iop */;
2093     info.enable_addr        = CVMX_POW_ECC_ERR;
2094     info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
2095     info.flags              = 0;
2096     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2097     info.group_index        = 0;
2098     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2099     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2100     info.parent.status_mask = 1ull<<12 /* pow */;
2101     info.func               = __cvmx_error_handle_pow_ecc_err_iop;
2102     info.user_info          = (long)
2103         "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
2104     fail |= cvmx_error_add(&info);
2105
2106     /* CVMX_ASXX_INT_REG(0) */
2107     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2108     info.status_addr        = CVMX_ASXX_INT_REG(0);
2109     info.status_mask        = 0x7ull<<0 /* ovrflw */;
2110     info.enable_addr        = CVMX_ASXX_INT_EN(0);
2111     info.enable_mask        = 0x7ull<<0 /* ovrflw */;
2112     info.flags              = 0;
2113     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2114     info.group_index        = 0;
2115     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2116     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2117     info.parent.status_mask = 1ull<<22 /* asx0 */;
2118     info.func               = __cvmx_error_display;
2119     info.user_info          = (long)
2120         "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
2121     fail |= cvmx_error_add(&info);
2122
2123     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2124     info.status_addr        = CVMX_ASXX_INT_REG(0);
2125     info.status_mask        = 0x7ull<<4 /* txpop */;
2126     info.enable_addr        = CVMX_ASXX_INT_EN(0);
2127     info.enable_mask        = 0x7ull<<4 /* txpop */;
2128     info.flags              = 0;
2129     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2130     info.group_index        = 0;
2131     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2132     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2133     info.parent.status_mask = 1ull<<22 /* asx0 */;
2134     info.func               = __cvmx_error_display;
2135     info.user_info          = (long)
2136         "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
2137     fail |= cvmx_error_add(&info);
2138
2139     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2140     info.status_addr        = CVMX_ASXX_INT_REG(0);
2141     info.status_mask        = 0x7ull<<8 /* txpsh */;
2142     info.enable_addr        = CVMX_ASXX_INT_EN(0);
2143     info.enable_mask        = 0x7ull<<8 /* txpsh */;
2144     info.flags              = 0;
2145     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2146     info.group_index        = 0;
2147     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2148     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2149     info.parent.status_mask = 1ull<<22 /* asx0 */;
2150     info.func               = __cvmx_error_display;
2151     info.user_info          = (long)
2152         "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
2153     fail |= cvmx_error_add(&info);
2154
2155     /* CVMX_PKO_REG_ERROR */
2156     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2157     info.status_addr        = CVMX_PKO_REG_ERROR;
2158     info.status_mask        = 1ull<<0 /* parity */;
2159     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2160     info.enable_mask        = 1ull<<0 /* parity */;
2161     info.flags              = 0;
2162     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2163     info.group_index        = 0;
2164     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2165     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2166     info.parent.status_mask = 1ull<<10 /* pko */;
2167     info.func               = __cvmx_error_display;
2168     info.user_info          = (long)
2169         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
2170     fail |= cvmx_error_add(&info);
2171
2172     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2173     info.status_addr        = CVMX_PKO_REG_ERROR;
2174     info.status_mask        = 1ull<<1 /* doorbell */;
2175     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2176     info.enable_mask        = 1ull<<1 /* doorbell */;
2177     info.flags              = 0;
2178     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2179     info.group_index        = 0;
2180     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2181     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2182     info.parent.status_mask = 1ull<<10 /* pko */;
2183     info.func               = __cvmx_error_display;
2184     info.user_info          = (long)
2185         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2186     fail |= cvmx_error_add(&info);
2187
2188     /* CVMX_TIM_REG_ERROR */
2189     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2190     info.status_addr        = CVMX_TIM_REG_ERROR;
2191     info.status_mask        = 0xffffull<<0 /* mask */;
2192     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
2193     info.enable_mask        = 0xffffull<<0 /* mask */;
2194     info.flags              = 0;
2195     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2196     info.group_index        = 0;
2197     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2198     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2199     info.parent.status_mask = 1ull<<11 /* tim */;
2200     info.func               = __cvmx_error_display;
2201     info.user_info          = (long)
2202         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2203     fail |= cvmx_error_add(&info);
2204
2205     /* CVMX_PIP_INT_REG */
2206     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2207     info.status_addr        = CVMX_PIP_INT_REG;
2208     info.status_mask        = 1ull<<3 /* prtnxa */;
2209     info.enable_addr        = CVMX_PIP_INT_EN;
2210     info.enable_mask        = 1ull<<3 /* prtnxa */;
2211     info.flags              = 0;
2212     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2213     info.group_index        = 0;
2214     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2215     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2216     info.parent.status_mask = 1ull<<20 /* pip */;
2217     info.func               = __cvmx_error_display;
2218     info.user_info          = (long)
2219         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
2220     fail |= cvmx_error_add(&info);
2221
2222     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2223     info.status_addr        = CVMX_PIP_INT_REG;
2224     info.status_mask        = 1ull<<4 /* badtag */;
2225     info.enable_addr        = CVMX_PIP_INT_EN;
2226     info.enable_mask        = 1ull<<4 /* badtag */;
2227     info.flags              = 0;
2228     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2229     info.group_index        = 0;
2230     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2231     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2232     info.parent.status_mask = 1ull<<20 /* pip */;
2233     info.func               = __cvmx_error_display;
2234     info.user_info          = (long)
2235         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
2236     fail |= cvmx_error_add(&info);
2237
2238     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2239     info.status_addr        = CVMX_PIP_INT_REG;
2240     info.status_mask        = 1ull<<5 /* skprunt */;
2241     info.enable_addr        = CVMX_PIP_INT_EN;
2242     info.enable_mask        = 1ull<<5 /* skprunt */;
2243     info.flags              = 0;
2244     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2245     info.group_index        = 0;
2246     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2247     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2248     info.parent.status_mask = 1ull<<20 /* pip */;
2249     info.func               = __cvmx_error_display;
2250     info.user_info          = (long)
2251         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
2252         "    This interrupt can occur with received PARTIAL\n"
2253         "    packets that are truncated to SKIP bytes or\n"
2254         "    smaller.\n";
2255     fail |= cvmx_error_add(&info);
2256
2257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2258     info.status_addr        = CVMX_PIP_INT_REG;
2259     info.status_mask        = 1ull<<6 /* todoovr */;
2260     info.enable_addr        = CVMX_PIP_INT_EN;
2261     info.enable_mask        = 1ull<<6 /* todoovr */;
2262     info.flags              = 0;
2263     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2264     info.group_index        = 0;
2265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2266     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2267     info.parent.status_mask = 1ull<<20 /* pip */;
2268     info.func               = __cvmx_error_display;
2269     info.user_info          = (long)
2270         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"
2271         "    (not used in O2P)\n";
2272     fail |= cvmx_error_add(&info);
2273
2274     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2275     info.status_addr        = CVMX_PIP_INT_REG;
2276     info.status_mask        = 1ull<<7 /* feperr */;
2277     info.enable_addr        = CVMX_PIP_INT_EN;
2278     info.enable_mask        = 1ull<<7 /* feperr */;
2279     info.flags              = 0;
2280     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2281     info.group_index        = 0;
2282     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2283     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2284     info.parent.status_mask = 1ull<<20 /* pip */;
2285     info.func               = __cvmx_error_display;
2286     info.user_info          = (long)
2287         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
2288     fail |= cvmx_error_add(&info);
2289
2290     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2291     info.status_addr        = CVMX_PIP_INT_REG;
2292     info.status_mask        = 1ull<<8 /* beperr */;
2293     info.enable_addr        = CVMX_PIP_INT_EN;
2294     info.enable_mask        = 1ull<<8 /* beperr */;
2295     info.flags              = 0;
2296     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2297     info.group_index        = 0;
2298     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2299     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2300     info.parent.status_mask = 1ull<<20 /* pip */;
2301     info.func               = __cvmx_error_display;
2302     info.user_info          = (long)
2303         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
2304     fail |= cvmx_error_add(&info);
2305
2306     /* CVMX_GMXX_BAD_REG(0) */
2307     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2308     info.status_addr        = CVMX_GMXX_BAD_REG(0);
2309     info.status_mask        = 0x7ull<<2 /* out_ovr */;
2310     info.enable_addr        = 0;
2311     info.enable_mask        = 0;
2312     info.flags              = 0;
2313     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2314     info.group_index        = 0;
2315     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2316     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2317     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2318     info.func               = __cvmx_error_display;
2319     info.user_info          = (long)
2320         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
2321     fail |= cvmx_error_add(&info);
2322
2323     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2324     info.status_addr        = CVMX_GMXX_BAD_REG(0);
2325     info.status_mask        = 0x7ull<<22 /* loststat */;
2326     info.enable_addr        = 0;
2327     info.enable_mask        = 0;
2328     info.flags              = 0;
2329     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2330     info.group_index        = 0;
2331     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2332     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2333     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2334     info.func               = __cvmx_error_display;
2335     info.user_info          = (long)
2336         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
2337         "    TX Stats are corrupted\n";
2338     fail |= cvmx_error_add(&info);
2339
2340     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2341     info.status_addr        = CVMX_GMXX_BAD_REG(0);
2342     info.status_mask        = 1ull<<26 /* statovr */;
2343     info.enable_addr        = 0;
2344     info.enable_mask        = 0;
2345     info.flags              = 0;
2346     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2347     info.group_index        = 0;
2348     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2349     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2350     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2351     info.func               = __cvmx_error_display;
2352     info.user_info          = (long)
2353         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
2354     fail |= cvmx_error_add(&info);
2355
2356     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2357     info.status_addr        = CVMX_GMXX_BAD_REG(0);
2358     info.status_mask        = 0xfull<<27 /* inb_nxa */;
2359     info.enable_addr        = 0;
2360     info.enable_mask        = 0;
2361     info.flags              = 0;
2362     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2363     info.group_index        = 0;
2364     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2365     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2366     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2367     info.func               = __cvmx_error_display;
2368     info.user_info          = (long)
2369         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
2370     fail |= cvmx_error_add(&info);
2371
2372     /* CVMX_GMXX_RXX_INT_REG(0,0) */
2373     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2374     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2375     info.status_mask        = 1ull<<1 /* carext */;
2376     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2377     info.enable_mask        = 1ull<<1 /* carext */;
2378     info.flags              = 0;
2379     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2380     info.group_index        = 0;
2381     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2382     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2383     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2384     info.func               = __cvmx_error_display;
2385     info.user_info          = (long)
2386         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
2387     fail |= cvmx_error_add(&info);
2388
2389     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2390     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2391     info.status_mask        = 1ull<<2 /* maxerr */;
2392     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2393     info.enable_mask        = 1ull<<2 /* maxerr */;
2394     info.flags              = 0;
2395     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2396     info.group_index        = 0;
2397     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2398     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2399     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2400     info.func               = __cvmx_error_display;
2401     info.user_info          = (long)
2402         "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
2403     fail |= cvmx_error_add(&info);
2404
2405     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2406     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2407     info.status_mask        = 1ull<<5 /* alnerr */;
2408     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2409     info.enable_mask        = 1ull<<5 /* alnerr */;
2410     info.flags              = 0;
2411     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2412     info.group_index        = 0;
2413     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2414     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2415     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2416     info.func               = __cvmx_error_display;
2417     info.user_info          = (long)
2418         "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
2419     fail |= cvmx_error_add(&info);
2420
2421     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2422     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2423     info.status_mask        = 1ull<<6 /* lenerr */;
2424     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2425     info.enable_mask        = 1ull<<6 /* lenerr */;
2426     info.flags              = 0;
2427     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2428     info.group_index        = 0;
2429     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2430     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2431     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2432     info.func               = __cvmx_error_display;
2433     info.user_info          = (long)
2434         "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
2435     fail |= cvmx_error_add(&info);
2436
2437     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2438     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2439     info.status_mask        = 1ull<<8 /* skperr */;
2440     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2441     info.enable_mask        = 1ull<<8 /* skperr */;
2442     info.flags              = 0;
2443     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2444     info.group_index        = 0;
2445     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2446     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2447     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2448     info.func               = __cvmx_error_display;
2449     info.user_info          = (long)
2450         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
2451     fail |= cvmx_error_add(&info);
2452
2453     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2454     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2455     info.status_mask        = 1ull<<9 /* niberr */;
2456     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2457     info.enable_mask        = 1ull<<9 /* niberr */;
2458     info.flags              = 0;
2459     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2460     info.group_index        = 0;
2461     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2462     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2463     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2464     info.func               = __cvmx_error_display;
2465     info.user_info          = (long)
2466         "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2467     fail |= cvmx_error_add(&info);
2468
2469     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2470     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
2471     info.status_mask        = 1ull<<10 /* ovrerr */;
2472     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
2473     info.enable_mask        = 1ull<<10 /* ovrerr */;
2474     info.flags              = 0;
2475     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2476     info.group_index        = 0;
2477     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2478     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2479     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2480     info.func               = __cvmx_error_display;
2481     info.user_info          = (long)
2482         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2483         "    This interrupt should never assert\n";
2484     fail |= cvmx_error_add(&info);
2485
2486     /* CVMX_GMXX_RXX_INT_REG(1,0) */
2487     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2488     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2489     info.status_mask        = 1ull<<1 /* carext */;
2490     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2491     info.enable_mask        = 1ull<<1 /* carext */;
2492     info.flags              = 0;
2493     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2494     info.group_index        = 1;
2495     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2496     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2497     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2498     info.func               = __cvmx_error_display;
2499     info.user_info          = (long)
2500         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
2501     fail |= cvmx_error_add(&info);
2502
2503     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2504     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2505     info.status_mask        = 1ull<<2 /* maxerr */;
2506     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2507     info.enable_mask        = 1ull<<2 /* maxerr */;
2508     info.flags              = 0;
2509     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2510     info.group_index        = 1;
2511     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2512     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2513     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2514     info.func               = __cvmx_error_display;
2515     info.user_info          = (long)
2516         "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
2517     fail |= cvmx_error_add(&info);
2518
2519     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2520     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2521     info.status_mask        = 1ull<<5 /* alnerr */;
2522     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2523     info.enable_mask        = 1ull<<5 /* alnerr */;
2524     info.flags              = 0;
2525     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2526     info.group_index        = 1;
2527     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2528     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2529     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2530     info.func               = __cvmx_error_display;
2531     info.user_info          = (long)
2532         "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
2533     fail |= cvmx_error_add(&info);
2534
2535     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2536     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2537     info.status_mask        = 1ull<<6 /* lenerr */;
2538     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2539     info.enable_mask        = 1ull<<6 /* lenerr */;
2540     info.flags              = 0;
2541     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2542     info.group_index        = 1;
2543     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2544     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2545     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2546     info.func               = __cvmx_error_display;
2547     info.user_info          = (long)
2548         "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
2549     fail |= cvmx_error_add(&info);
2550
2551     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2552     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2553     info.status_mask        = 1ull<<8 /* skperr */;
2554     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2555     info.enable_mask        = 1ull<<8 /* skperr */;
2556     info.flags              = 0;
2557     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2558     info.group_index        = 1;
2559     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2560     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2561     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2562     info.func               = __cvmx_error_display;
2563     info.user_info          = (long)
2564         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
2565     fail |= cvmx_error_add(&info);
2566
2567     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2568     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2569     info.status_mask        = 1ull<<9 /* niberr */;
2570     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2571     info.enable_mask        = 1ull<<9 /* niberr */;
2572     info.flags              = 0;
2573     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2574     info.group_index        = 1;
2575     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2576     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2577     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2578     info.func               = __cvmx_error_display;
2579     info.user_info          = (long)
2580         "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2581     fail |= cvmx_error_add(&info);
2582
2583     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2584     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
2585     info.status_mask        = 1ull<<10 /* ovrerr */;
2586     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
2587     info.enable_mask        = 1ull<<10 /* ovrerr */;
2588     info.flags              = 0;
2589     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2590     info.group_index        = 1;
2591     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2592     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2593     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2594     info.func               = __cvmx_error_display;
2595     info.user_info          = (long)
2596         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2597         "    This interrupt should never assert\n";
2598     fail |= cvmx_error_add(&info);
2599
2600     /* CVMX_GMXX_RXX_INT_REG(2,0) */
2601     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2602     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2603     info.status_mask        = 1ull<<1 /* carext */;
2604     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2605     info.enable_mask        = 1ull<<1 /* carext */;
2606     info.flags              = 0;
2607     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2608     info.group_index        = 2;
2609     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2610     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2611     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2612     info.func               = __cvmx_error_display;
2613     info.user_info          = (long)
2614         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
2615     fail |= cvmx_error_add(&info);
2616
2617     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2618     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2619     info.status_mask        = 1ull<<2 /* maxerr */;
2620     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2621     info.enable_mask        = 1ull<<2 /* maxerr */;
2622     info.flags              = 0;
2623     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2624     info.group_index        = 2;
2625     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2626     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2627     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2628     info.func               = __cvmx_error_display;
2629     info.user_info          = (long)
2630         "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
2631     fail |= cvmx_error_add(&info);
2632
2633     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2634     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2635     info.status_mask        = 1ull<<5 /* alnerr */;
2636     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2637     info.enable_mask        = 1ull<<5 /* alnerr */;
2638     info.flags              = 0;
2639     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2640     info.group_index        = 2;
2641     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2642     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2643     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2644     info.func               = __cvmx_error_display;
2645     info.user_info          = (long)
2646         "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
2647     fail |= cvmx_error_add(&info);
2648
2649     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2650     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2651     info.status_mask        = 1ull<<6 /* lenerr */;
2652     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2653     info.enable_mask        = 1ull<<6 /* lenerr */;
2654     info.flags              = 0;
2655     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2656     info.group_index        = 2;
2657     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2658     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2659     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2660     info.func               = __cvmx_error_display;
2661     info.user_info          = (long)
2662         "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
2663     fail |= cvmx_error_add(&info);
2664
2665     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2666     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2667     info.status_mask        = 1ull<<8 /* skperr */;
2668     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2669     info.enable_mask        = 1ull<<8 /* skperr */;
2670     info.flags              = 0;
2671     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2672     info.group_index        = 2;
2673     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2674     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2675     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2676     info.func               = __cvmx_error_display;
2677     info.user_info          = (long)
2678         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
2679     fail |= cvmx_error_add(&info);
2680
2681     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2682     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2683     info.status_mask        = 1ull<<9 /* niberr */;
2684     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2685     info.enable_mask        = 1ull<<9 /* niberr */;
2686     info.flags              = 0;
2687     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2688     info.group_index        = 2;
2689     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2690     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2691     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2692     info.func               = __cvmx_error_display;
2693     info.user_info          = (long)
2694         "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2695     fail |= cvmx_error_add(&info);
2696
2697     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2698     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2699     info.status_mask        = 1ull<<10 /* ovrerr */;
2700     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2701     info.enable_mask        = 1ull<<10 /* ovrerr */;
2702     info.flags              = 0;
2703     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2704     info.group_index        = 2;
2705     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2706     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2707     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2708     info.func               = __cvmx_error_display;
2709     info.user_info          = (long)
2710         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2711         "    This interrupt should never assert\n";
2712     fail |= cvmx_error_add(&info);
2713
2714     /* CVMX_GMXX_TX_INT_REG(0) */
2715     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2716     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2717     info.status_mask        = 1ull<<0 /* pko_nxa */;
2718     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2719     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2720     info.flags              = 0;
2721     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2722     info.group_index        = 0;
2723     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2724     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2725     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2726     info.func               = __cvmx_error_display;
2727     info.user_info          = (long)
2728         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2729     fail |= cvmx_error_add(&info);
2730
2731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2732     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2733     info.status_mask        = 0x7ull<<2 /* undflw */;
2734     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2735     info.enable_mask        = 0x7ull<<2 /* undflw */;
2736     info.flags              = 0;
2737     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2738     info.group_index        = 0;
2739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2740     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2741     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2742     info.func               = __cvmx_error_display;
2743     info.user_info          = (long)
2744         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
2745     fail |= cvmx_error_add(&info);
2746
2747     /* CVMX_LMCX_MEM_CFG0(0) */
2748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2749     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
2750     info.status_mask        = 0xfull<<21 /* sec_err */;
2751     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
2752     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
2753     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2754     info.group              = CVMX_ERROR_GROUP_LMC;
2755     info.group_index        = 0;
2756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2757     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2758     info.parent.status_mask = 1ull<<17 /* lmc */;
2759     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
2760     info.user_info          = (long)
2761         "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
2762         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
2763         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
2764         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
2765         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
2766         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
2767         "    In 16b mode, ecc is calculated on 8 cycle worth of data\n"
2768         "    [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
2769         "                        DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
2770         "    [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
2771         "                        DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
2772         "    [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
2773         "                        DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
2774         "    [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
2775         "                        DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
2776         "      where _cC_pP denotes cycle C and phase P\n"
2777         "    Write of 1 will clear the corresponding error bit\n";
2778     fail |= cvmx_error_add(&info);
2779
2780     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2781     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
2782     info.status_mask        = 0xfull<<25 /* ded_err */;
2783     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
2784     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
2785     info.flags              = 0;
2786     info.group              = CVMX_ERROR_GROUP_LMC;
2787     info.group_index        = 0;
2788     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2789     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2790     info.parent.status_mask = 1ull<<17 /* lmc */;
2791     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
2792     info.user_info          = (long)
2793         "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
2794         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
2795         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
2796         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
2797         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
2798         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
2799         "    In 16b mode, ecc is calculated on 8 cycle worth of data\n"
2800         "    [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
2801         "                        DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
2802         "    [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
2803         "                        DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
2804         "    [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
2805         "                        DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
2806         "    [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
2807         "                        DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
2808         "      where _cC_pP denotes cycle C and phase P\n"
2809         "    Write of 1 will clear the corresponding error bit\n";
2810     fail |= cvmx_error_add(&info);
2811
2812     /* CVMX_IOB_INT_SUM */
2813     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2814     info.status_addr        = CVMX_IOB_INT_SUM;
2815     info.status_mask        = 1ull<<0 /* np_sop */;
2816     info.enable_addr        = CVMX_IOB_INT_ENB;
2817     info.enable_mask        = 1ull<<0 /* np_sop */;
2818     info.flags              = 0;
2819     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2820     info.group_index        = 0;
2821     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2822     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2823     info.parent.status_mask = 1ull<<30 /* iob */;
2824     info.func               = __cvmx_error_display;
2825     info.user_info          = (long)
2826         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
2827         "    port for a non-passthrough packet.\n"
2828         "    The first detected error associated with bits [3:0]\n"
2829         "    of this register will only be set here. A new bit\n"
2830         "    can be set when the previous reported bit is cleared.\n";
2831     fail |= cvmx_error_add(&info);
2832
2833     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2834     info.status_addr        = CVMX_IOB_INT_SUM;
2835     info.status_mask        = 1ull<<1 /* np_eop */;
2836     info.enable_addr        = CVMX_IOB_INT_ENB;
2837     info.enable_mask        = 1ull<<1 /* np_eop */;
2838     info.flags              = 0;
2839     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2840     info.group_index        = 0;
2841     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2842     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2843     info.parent.status_mask = 1ull<<30 /* iob */;
2844     info.func               = __cvmx_error_display;
2845     info.user_info          = (long)
2846         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
2847         "    port for a non-passthrough packet.\n"
2848         "    The first detected error associated with bits [3:0]\n"
2849         "    of this register will only be set here. A new bit\n"
2850         "    can be set when the previous reported bit is cleared.\n";
2851     fail |= cvmx_error_add(&info);
2852
2853     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2854     info.status_addr        = CVMX_IOB_INT_SUM;
2855     info.status_mask        = 1ull<<2 /* p_sop */;
2856     info.enable_addr        = CVMX_IOB_INT_ENB;
2857     info.enable_mask        = 1ull<<2 /* p_sop */;
2858     info.flags              = 0;
2859     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2860     info.group_index        = 0;
2861     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2862     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2863     info.parent.status_mask = 1ull<<30 /* iob */;
2864     info.func               = __cvmx_error_display;
2865     info.user_info          = (long)
2866         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
2867         "    port for a passthrough packet.\n"
2868         "    The first detected error associated with bits [3:0]\n"
2869         "    of this register will only be set here. A new bit\n"
2870         "    can be set when the previous reported bit is cleared.\n";
2871     fail |= cvmx_error_add(&info);
2872
2873     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2874     info.status_addr        = CVMX_IOB_INT_SUM;
2875     info.status_mask        = 1ull<<3 /* p_eop */;
2876     info.enable_addr        = CVMX_IOB_INT_ENB;
2877     info.enable_mask        = 1ull<<3 /* p_eop */;
2878     info.flags              = 0;
2879     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2880     info.group_index        = 0;
2881     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2882     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2883     info.parent.status_mask = 1ull<<30 /* iob */;
2884     info.func               = __cvmx_error_display;
2885     info.user_info          = (long)
2886         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
2887         "    port for a passthrough packet.\n"
2888         "    The first detected error associated with bits [3:0]\n"
2889         "    of this register will only be set here. A new bit\n"
2890         "    can be set when the previous reported bit is cleared.\n";
2891     fail |= cvmx_error_add(&info);
2892
2893     /* CVMX_USBNX_INT_SUM(0) */
2894     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2895     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2896     info.status_mask        = 1ull<<0 /* pr_po_e */;
2897     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2898     info.enable_mask        = 1ull<<0 /* pr_po_e */;
2899     info.flags              = 0;
2900     info.group              = CVMX_ERROR_GROUP_USB;
2901     info.group_index        = 0;
2902     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2903     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2904     info.parent.status_mask = 1ull<<13 /* usb */;
2905     info.func               = __cvmx_error_display;
2906     info.user_info          = (long)
2907         "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
2908     fail |= cvmx_error_add(&info);
2909
2910     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2911     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2912     info.status_mask        = 1ull<<1 /* pr_pu_f */;
2913     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2914     info.enable_mask        = 1ull<<1 /* pr_pu_f */;
2915     info.flags              = 0;
2916     info.group              = CVMX_ERROR_GROUP_USB;
2917     info.group_index        = 0;
2918     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2919     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2920     info.parent.status_mask = 1ull<<13 /* usb */;
2921     info.func               = __cvmx_error_display;
2922     info.user_info          = (long)
2923         "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
2924     fail |= cvmx_error_add(&info);
2925
2926     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2927     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2928     info.status_mask        = 1ull<<2 /* nr_po_e */;
2929     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2930     info.enable_mask        = 1ull<<2 /* nr_po_e */;
2931     info.flags              = 0;
2932     info.group              = CVMX_ERROR_GROUP_USB;
2933     info.group_index        = 0;
2934     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2935     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2936     info.parent.status_mask = 1ull<<13 /* usb */;
2937     info.func               = __cvmx_error_display;
2938     info.user_info          = (long)
2939         "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
2940     fail |= cvmx_error_add(&info);
2941
2942     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2943     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2944     info.status_mask        = 1ull<<3 /* nr_pu_f */;
2945     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2946     info.enable_mask        = 1ull<<3 /* nr_pu_f */;
2947     info.flags              = 0;
2948     info.group              = CVMX_ERROR_GROUP_USB;
2949     info.group_index        = 0;
2950     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2951     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2952     info.parent.status_mask = 1ull<<13 /* usb */;
2953     info.func               = __cvmx_error_display;
2954     info.user_info          = (long)
2955         "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
2956     fail |= cvmx_error_add(&info);
2957
2958     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2959     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2960     info.status_mask        = 1ull<<4 /* lr_po_e */;
2961     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2962     info.enable_mask        = 1ull<<4 /* lr_po_e */;
2963     info.flags              = 0;
2964     info.group              = CVMX_ERROR_GROUP_USB;
2965     info.group_index        = 0;
2966     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2967     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2968     info.parent.status_mask = 1ull<<13 /* usb */;
2969     info.func               = __cvmx_error_display;
2970     info.user_info          = (long)
2971         "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
2972     fail |= cvmx_error_add(&info);
2973
2974     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2975     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2976     info.status_mask        = 1ull<<5 /* lr_pu_f */;
2977     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2978     info.enable_mask        = 1ull<<5 /* lr_pu_f */;
2979     info.flags              = 0;
2980     info.group              = CVMX_ERROR_GROUP_USB;
2981     info.group_index        = 0;
2982     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2983     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2984     info.parent.status_mask = 1ull<<13 /* usb */;
2985     info.func               = __cvmx_error_display;
2986     info.user_info          = (long)
2987         "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
2988     fail |= cvmx_error_add(&info);
2989
2990     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2991     info.status_addr        = CVMX_USBNX_INT_SUM(0);
2992     info.status_mask        = 1ull<<6 /* pt_po_e */;
2993     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
2994     info.enable_mask        = 1ull<<6 /* pt_po_e */;
2995     info.flags              = 0;
2996     info.group              = CVMX_ERROR_GROUP_USB;
2997     info.group_index        = 0;
2998     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2999     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3000     info.parent.status_mask = 1ull<<13 /* usb */;
3001     info.func               = __cvmx_error_display;
3002     info.user_info          = (long)
3003         "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
3004     fail |= cvmx_error_add(&info);
3005
3006     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3007     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3008     info.status_mask        = 1ull<<7 /* pt_pu_f */;
3009     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3010     info.enable_mask        = 1ull<<7 /* pt_pu_f */;
3011     info.flags              = 0;
3012     info.group              = CVMX_ERROR_GROUP_USB;
3013     info.group_index        = 0;
3014     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3015     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3016     info.parent.status_mask = 1ull<<13 /* usb */;
3017     info.func               = __cvmx_error_display;
3018     info.user_info          = (long)
3019         "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
3020     fail |= cvmx_error_add(&info);
3021
3022     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3023     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3024     info.status_mask        = 1ull<<8 /* nt_po_e */;
3025     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3026     info.enable_mask        = 1ull<<8 /* nt_po_e */;
3027     info.flags              = 0;
3028     info.group              = CVMX_ERROR_GROUP_USB;
3029     info.group_index        = 0;
3030     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3031     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3032     info.parent.status_mask = 1ull<<13 /* usb */;
3033     info.func               = __cvmx_error_display;
3034     info.user_info          = (long)
3035         "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
3036     fail |= cvmx_error_add(&info);
3037
3038     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3039     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3040     info.status_mask        = 1ull<<9 /* nt_pu_f */;
3041     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3042     info.enable_mask        = 1ull<<9 /* nt_pu_f */;
3043     info.flags              = 0;
3044     info.group              = CVMX_ERROR_GROUP_USB;
3045     info.group_index        = 0;
3046     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3047     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3048     info.parent.status_mask = 1ull<<13 /* usb */;
3049     info.func               = __cvmx_error_display;
3050     info.user_info          = (long)
3051         "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
3052     fail |= cvmx_error_add(&info);
3053
3054     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3055     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3056     info.status_mask        = 1ull<<10 /* lt_po_e */;
3057     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3058     info.enable_mask        = 1ull<<10 /* lt_po_e */;
3059     info.flags              = 0;
3060     info.group              = CVMX_ERROR_GROUP_USB;
3061     info.group_index        = 0;
3062     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3063     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3064     info.parent.status_mask = 1ull<<13 /* usb */;
3065     info.func               = __cvmx_error_display;
3066     info.user_info          = (long)
3067         "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
3068     fail |= cvmx_error_add(&info);
3069
3070     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3071     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3072     info.status_mask        = 1ull<<11 /* lt_pu_f */;
3073     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3074     info.enable_mask        = 1ull<<11 /* lt_pu_f */;
3075     info.flags              = 0;
3076     info.group              = CVMX_ERROR_GROUP_USB;
3077     info.group_index        = 0;
3078     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3079     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3080     info.parent.status_mask = 1ull<<13 /* usb */;
3081     info.func               = __cvmx_error_display;
3082     info.user_info          = (long)
3083         "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
3084     fail |= cvmx_error_add(&info);
3085
3086     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3087     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3088     info.status_mask        = 1ull<<12 /* dcred_e */;
3089     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3090     info.enable_mask        = 1ull<<12 /* dcred_e */;
3091     info.flags              = 0;
3092     info.group              = CVMX_ERROR_GROUP_USB;
3093     info.group_index        = 0;
3094     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3095     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3096     info.parent.status_mask = 1ull<<13 /* usb */;
3097     info.func               = __cvmx_error_display;
3098     info.user_info          = (long)
3099         "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
3100     fail |= cvmx_error_add(&info);
3101
3102     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3103     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3104     info.status_mask        = 1ull<<13 /* dcred_f */;
3105     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3106     info.enable_mask        = 1ull<<13 /* dcred_f */;
3107     info.flags              = 0;
3108     info.group              = CVMX_ERROR_GROUP_USB;
3109     info.group_index        = 0;
3110     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3111     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3112     info.parent.status_mask = 1ull<<13 /* usb */;
3113     info.func               = __cvmx_error_display;
3114     info.user_info          = (long)
3115         "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
3116     fail |= cvmx_error_add(&info);
3117
3118     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3119     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3120     info.status_mask        = 1ull<<14 /* l2c_s_e */;
3121     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3122     info.enable_mask        = 1ull<<14 /* l2c_s_e */;
3123     info.flags              = 0;
3124     info.group              = CVMX_ERROR_GROUP_USB;
3125     info.group_index        = 0;
3126     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3127     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3128     info.parent.status_mask = 1ull<<13 /* usb */;
3129     info.func               = __cvmx_error_display;
3130     info.user_info          = (long)
3131         "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
3132     fail |= cvmx_error_add(&info);
3133
3134     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3135     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3136     info.status_mask        = 1ull<<15 /* l2c_a_f */;
3137     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3138     info.enable_mask        = 1ull<<15 /* l2c_a_f */;
3139     info.flags              = 0;
3140     info.group              = CVMX_ERROR_GROUP_USB;
3141     info.group_index        = 0;
3142     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3143     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3144     info.parent.status_mask = 1ull<<13 /* usb */;
3145     info.func               = __cvmx_error_display;
3146     info.user_info          = (long)
3147         "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
3148     fail |= cvmx_error_add(&info);
3149
3150     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3151     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3152     info.status_mask        = 1ull<<16 /* lt_fi_e */;
3153     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3154     info.enable_mask        = 1ull<<16 /* l2_fi_e */;
3155     info.flags              = 0;
3156     info.group              = CVMX_ERROR_GROUP_USB;
3157     info.group_index        = 0;
3158     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3159     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3160     info.parent.status_mask = 1ull<<13 /* usb */;
3161     info.func               = __cvmx_error_display;
3162     info.user_info          = (long)
3163         "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
3164     fail |= cvmx_error_add(&info);
3165
3166     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3167     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3168     info.status_mask        = 1ull<<17 /* lt_fi_f */;
3169     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3170     info.enable_mask        = 1ull<<17 /* l2_fi_f */;
3171     info.flags              = 0;
3172     info.group              = CVMX_ERROR_GROUP_USB;
3173     info.group_index        = 0;
3174     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3175     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3176     info.parent.status_mask = 1ull<<13 /* usb */;
3177     info.func               = __cvmx_error_display;
3178     info.user_info          = (long)
3179         "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
3180     fail |= cvmx_error_add(&info);
3181
3182     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3183     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3184     info.status_mask        = 1ull<<18 /* rg_fi_e */;
3185     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3186     info.enable_mask        = 1ull<<18 /* rg_fi_e */;
3187     info.flags              = 0;
3188     info.group              = CVMX_ERROR_GROUP_USB;
3189     info.group_index        = 0;
3190     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3191     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3192     info.parent.status_mask = 1ull<<13 /* usb */;
3193     info.func               = __cvmx_error_display;
3194     info.user_info          = (long)
3195         "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
3196     fail |= cvmx_error_add(&info);
3197
3198     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3199     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3200     info.status_mask        = 1ull<<19 /* rg_fi_f */;
3201     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3202     info.enable_mask        = 1ull<<19 /* rg_fi_f */;
3203     info.flags              = 0;
3204     info.group              = CVMX_ERROR_GROUP_USB;
3205     info.group_index        = 0;
3206     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3207     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3208     info.parent.status_mask = 1ull<<13 /* usb */;
3209     info.func               = __cvmx_error_display;
3210     info.user_info          = (long)
3211         "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
3212     fail |= cvmx_error_add(&info);
3213
3214     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3215     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3216     info.status_mask        = 1ull<<20 /* rq_q2_f */;
3217     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3218     info.enable_mask        = 1ull<<20 /* rq_q2_f */;
3219     info.flags              = 0;
3220     info.group              = CVMX_ERROR_GROUP_USB;
3221     info.group_index        = 0;
3222     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3223     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3224     info.parent.status_mask = 1ull<<13 /* usb */;
3225     info.func               = __cvmx_error_display;
3226     info.user_info          = (long)
3227         "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
3228     fail |= cvmx_error_add(&info);
3229
3230     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3231     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3232     info.status_mask        = 1ull<<21 /* rq_q2_e */;
3233     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3234     info.enable_mask        = 1ull<<21 /* rq_q2_e */;
3235     info.flags              = 0;
3236     info.group              = CVMX_ERROR_GROUP_USB;
3237     info.group_index        = 0;
3238     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3239     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3240     info.parent.status_mask = 1ull<<13 /* usb */;
3241     info.func               = __cvmx_error_display;
3242     info.user_info          = (long)
3243         "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
3244     fail |= cvmx_error_add(&info);
3245
3246     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3247     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3248     info.status_mask        = 1ull<<22 /* rq_q3_f */;
3249     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3250     info.enable_mask        = 1ull<<22 /* rq_q3_f */;
3251     info.flags              = 0;
3252     info.group              = CVMX_ERROR_GROUP_USB;
3253     info.group_index        = 0;
3254     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3255     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3256     info.parent.status_mask = 1ull<<13 /* usb */;
3257     info.func               = __cvmx_error_display;
3258     info.user_info          = (long)
3259         "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
3260     fail |= cvmx_error_add(&info);
3261
3262     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3263     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3264     info.status_mask        = 1ull<<23 /* rq_q3_e */;
3265     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3266     info.enable_mask        = 1ull<<23 /* rq_q3_e */;
3267     info.flags              = 0;
3268     info.group              = CVMX_ERROR_GROUP_USB;
3269     info.group_index        = 0;
3270     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3271     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3272     info.parent.status_mask = 1ull<<13 /* usb */;
3273     info.func               = __cvmx_error_display;
3274     info.user_info          = (long)
3275         "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
3276     fail |= cvmx_error_add(&info);
3277
3278     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3279     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3280     info.status_mask        = 1ull<<24 /* uod_pe */;
3281     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3282     info.enable_mask        = 1ull<<24 /* uod_pe */;
3283     info.flags              = 0;
3284     info.group              = CVMX_ERROR_GROUP_USB;
3285     info.group_index        = 0;
3286     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3287     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3288     info.parent.status_mask = 1ull<<13 /* usb */;
3289     info.func               = __cvmx_error_display;
3290     info.user_info          = (long)
3291         "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
3292     fail |= cvmx_error_add(&info);
3293
3294     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3295     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3296     info.status_mask        = 1ull<<25 /* uod_pf */;
3297     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3298     info.enable_mask        = 1ull<<25 /* uod_pf */;
3299     info.flags              = 0;
3300     info.group              = CVMX_ERROR_GROUP_USB;
3301     info.group_index        = 0;
3302     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3303     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3304     info.parent.status_mask = 1ull<<13 /* usb */;
3305     info.func               = __cvmx_error_display;
3306     info.user_info          = (long)
3307         "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
3308     fail |= cvmx_error_add(&info);
3309
3310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3311     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3312     info.status_mask        = 1ull<<26 /* n2u_pf */;
3313     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3314     info.enable_mask        = 1ull<<26 /* n2u_pf */;
3315     info.flags              = 0;
3316     info.group              = CVMX_ERROR_GROUP_USB;
3317     info.group_index        = 0;
3318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3319     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3320     info.parent.status_mask = 1ull<<13 /* usb */;
3321     info.func               = __cvmx_error_display;
3322     info.user_info          = (long)
3323         "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n";
3324     fail |= cvmx_error_add(&info);
3325
3326     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3327     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3328     info.status_mask        = 1ull<<27 /* n2u_pe */;
3329     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3330     info.enable_mask        = 1ull<<27 /* n2u_pe */;
3331     info.flags              = 0;
3332     info.group              = CVMX_ERROR_GROUP_USB;
3333     info.group_index        = 0;
3334     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3335     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3336     info.parent.status_mask = 1ull<<13 /* usb */;
3337     info.func               = __cvmx_error_display;
3338     info.user_info          = (long)
3339         "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n";
3340     fail |= cvmx_error_add(&info);
3341
3342     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3343     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3344     info.status_mask        = 1ull<<28 /* u2n_d_pe */;
3345     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3346     info.enable_mask        = 1ull<<28 /* u2n_d_pe */;
3347     info.flags              = 0;
3348     info.group              = CVMX_ERROR_GROUP_USB;
3349     info.group_index        = 0;
3350     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3351     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3352     info.parent.status_mask = 1ull<<13 /* usb */;
3353     info.func               = __cvmx_error_display;
3354     info.user_info          = (long)
3355         "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n";
3356     fail |= cvmx_error_add(&info);
3357
3358     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3359     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3360     info.status_mask        = 1ull<<29 /* u2n_d_pf */;
3361     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3362     info.enable_mask        = 1ull<<29 /* u2n_d_pf */;
3363     info.flags              = 0;
3364     info.group              = CVMX_ERROR_GROUP_USB;
3365     info.group_index        = 0;
3366     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3367     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3368     info.parent.status_mask = 1ull<<13 /* usb */;
3369     info.func               = __cvmx_error_display;
3370     info.user_info          = (long)
3371         "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n";
3372     fail |= cvmx_error_add(&info);
3373
3374     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3375     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3376     info.status_mask        = 1ull<<30 /* u2n_c_pf */;
3377     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3378     info.enable_mask        = 1ull<<30 /* u2n_c_pf */;
3379     info.flags              = 0;
3380     info.group              = CVMX_ERROR_GROUP_USB;
3381     info.group_index        = 0;
3382     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3383     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3384     info.parent.status_mask = 1ull<<13 /* usb */;
3385     info.func               = __cvmx_error_display;
3386     info.user_info          = (long)
3387         "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n";
3388     fail |= cvmx_error_add(&info);
3389
3390     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3391     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3392     info.status_mask        = 1ull<<31 /* u2n_c_pe */;
3393     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3394     info.enable_mask        = 1ull<<31 /* u2n_c_pe */;
3395     info.flags              = 0;
3396     info.group              = CVMX_ERROR_GROUP_USB;
3397     info.group_index        = 0;
3398     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3399     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3400     info.parent.status_mask = 1ull<<13 /* usb */;
3401     info.func               = __cvmx_error_display;
3402     info.user_info          = (long)
3403         "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n";
3404     fail |= cvmx_error_add(&info);
3405
3406     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3407     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3408     info.status_mask        = 1ull<<32 /* ltl_f_pe */;
3409     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3410     info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
3411     info.flags              = 0;
3412     info.group              = CVMX_ERROR_GROUP_USB;
3413     info.group_index        = 0;
3414     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3415     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3416     info.parent.status_mask = 1ull<<13 /* usb */;
3417     info.func               = __cvmx_error_display;
3418     info.user_info          = (long)
3419         "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
3420     fail |= cvmx_error_add(&info);
3421
3422     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3423     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3424     info.status_mask        = 1ull<<33 /* ltl_f_pf */;
3425     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3426     info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
3427     info.flags              = 0;
3428     info.group              = CVMX_ERROR_GROUP_USB;
3429     info.group_index        = 0;
3430     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3431     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3432     info.parent.status_mask = 1ull<<13 /* usb */;
3433     info.func               = __cvmx_error_display;
3434     info.user_info          = (long)
3435         "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
3436     fail |= cvmx_error_add(&info);
3437
3438     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3439     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3440     info.status_mask        = 1ull<<34 /* nd4o_rpe */;
3441     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3442     info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
3443     info.flags              = 0;
3444     info.group              = CVMX_ERROR_GROUP_USB;
3445     info.group_index        = 0;
3446     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3447     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3448     info.parent.status_mask = 1ull<<13 /* usb */;
3449     info.func               = __cvmx_error_display;
3450     info.user_info          = (long)
3451         "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
3452     fail |= cvmx_error_add(&info);
3453
3454     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3455     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3456     info.status_mask        = 1ull<<35 /* nd4o_rpf */;
3457     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3458     info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
3459     info.flags              = 0;
3460     info.group              = CVMX_ERROR_GROUP_USB;
3461     info.group_index        = 0;
3462     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3463     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3464     info.parent.status_mask = 1ull<<13 /* usb */;
3465     info.func               = __cvmx_error_display;
3466     info.user_info          = (long)
3467         "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
3468     fail |= cvmx_error_add(&info);
3469
3470     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3471     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3472     info.status_mask        = 1ull<<36 /* nd4o_dpe */;
3473     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3474     info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
3475     info.flags              = 0;
3476     info.group              = CVMX_ERROR_GROUP_USB;
3477     info.group_index        = 0;
3478     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3479     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3480     info.parent.status_mask = 1ull<<13 /* usb */;
3481     info.func               = __cvmx_error_display;
3482     info.user_info          = (long)
3483         "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
3484     fail |= cvmx_error_add(&info);
3485
3486     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3487     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3488     info.status_mask        = 1ull<<37 /* nd4o_dpf */;
3489     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3490     info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
3491     info.flags              = 0;
3492     info.group              = CVMX_ERROR_GROUP_USB;
3493     info.group_index        = 0;
3494     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3495     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3496     info.parent.status_mask = 1ull<<13 /* usb */;
3497     info.func               = __cvmx_error_display;
3498     info.user_info          = (long)
3499         "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
3500     fail |= cvmx_error_add(&info);
3501
3502     return fail;
3503 }
3504