sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c

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  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn31xx.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN31XX</h2>
  51  * @dot
  52  * digraph cn31xx
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
  59  *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  60  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
  61  *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  62  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
  63  *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  64  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
  65  *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
  66  *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
  67  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  68  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
  69  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  70  *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<zip>zip|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<usb>usb"];
  71  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
  72  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
  73  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
  74  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
  75  *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
  76  *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
  77  *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
  78  *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
  79  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  80  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
  81  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  82  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
  83  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  84  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
  85  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  86  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
  87  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
  88  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
  89  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
  90  *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
  91  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
  92  *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
  93  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"];
  94  *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
  95  *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
  96  *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
  97  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
  98  *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
  99  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
 100  *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
 101  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
 102  *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
 103  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
 104  *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
 105  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
 106  *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
 107  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
 108  *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
 109  *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
 110  *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
 111  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
 112  *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
 113  *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
 114  *     cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
 115  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 116  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 117  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 118  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 119  *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
 120  * }
 121  * @enddot
 122  */
 123 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 124 #include <asm/octeon/cvmx.h>
 125 #include <asm/octeon/cvmx-error.h>
 126 #include <asm/octeon/cvmx-error-custom.h>
 127 #include <asm/octeon/cvmx-csr-typedefs.h>
 128 #else
 129 #include "cvmx.h"
 130 #include "cvmx-error.h"
 131 #include "cvmx-error-custom.h"
 132 #endif
 133
 134 int cvmx_error_initialize_cn31xx(void);
 135
 136 int cvmx_error_initialize_cn31xx(void)
 137 {
 138     cvmx_error_info_t info;
 139     int fail = 0;
 140
 141     /* CVMX_CIU_INTX_SUM0(0) */
 142     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 143     info.status_addr        = CVMX_CIU_INTX_SUM0(0);
 144     info.status_mask        = 0;
 145     info.enable_addr        = 0;
 146     info.enable_mask        = 0;
 147     info.flags              = 0;
 148     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 149     info.group_index        = 0;
 150     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 151     info.parent.status_addr = 0;
 152     info.parent.status_mask = 0;
 153     info.func               = __cvmx_error_decode;
 154     info.user_info          = 0;
 155     fail |= cvmx_error_add(&info);
 156
 157     /* CVMX_PCMX_INT_SUM(0) */
 158     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 159     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 160     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 161     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 162     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 163     info.flags              = 0;
 164     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 165     info.group_index        = 0;
 166     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 167     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 168     info.parent.status_mask = 1ull<<57 /* pcm */;
 169     info.func               = __cvmx_error_display;
 170     info.user_info          = (long)
 171         "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 172     fail |= cvmx_error_add(&info);
 173
 174     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 175     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 176     info.status_mask        = 1ull<<1 /* fsyncextra */;
 177     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 178     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 179     info.flags              = 0;
 180     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 181     info.group_index        = 0;
 182     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 183     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 184     info.parent.status_mask = 1ull<<57 /* pcm */;
 185     info.func               = __cvmx_error_display;
 186     info.user_info          = (long)
 187         "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 188     fail |= cvmx_error_add(&info);
 189
 190     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 191     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 192     info.status_mask        = 1ull<<6 /* txempty */;
 193     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 194     info.enable_mask        = 1ull<<6 /* txempty */;
 195     info.flags              = 0;
 196     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 197     info.group_index        = 0;
 198     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 199     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 200     info.parent.status_mask = 1ull<<57 /* pcm */;
 201     info.func               = __cvmx_error_display;
 202     info.user_info          = (long)
 203         "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
 204     fail |= cvmx_error_add(&info);
 205
 206     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 207     info.status_addr        = CVMX_PCMX_INT_SUM(0);
 208     info.status_mask        = 1ull<<7 /* rxovf */;
 209     info.enable_addr        = CVMX_PCMX_INT_ENA(0);
 210     info.enable_mask        = 1ull<<7 /* rxovf */;
 211     info.flags              = 0;
 212     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 213     info.group_index        = 0;
 214     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 215     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 216     info.parent.status_mask = 1ull<<57 /* pcm */;
 217     info.func               = __cvmx_error_display;
 218     info.user_info          = (long)
 219         "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
 220     fail |= cvmx_error_add(&info);
 221
 222     /* CVMX_PCMX_INT_SUM(1) */
 223     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 224     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 225     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 226     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 227     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 228     info.flags              = 0;
 229     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 230     info.group_index        = 0;
 231     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 232     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 233     info.parent.status_mask = 1ull<<57 /* pcm */;
 234     info.func               = __cvmx_error_display;
 235     info.user_info          = (long)
 236         "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 237     fail |= cvmx_error_add(&info);
 238
 239     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 240     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 241     info.status_mask        = 1ull<<1 /* fsyncextra */;
 242     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 243     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 244     info.flags              = 0;
 245     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 246     info.group_index        = 0;
 247     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 248     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 249     info.parent.status_mask = 1ull<<57 /* pcm */;
 250     info.func               = __cvmx_error_display;
 251     info.user_info          = (long)
 252         "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 253     fail |= cvmx_error_add(&info);
 254
 255     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 256     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 257     info.status_mask        = 1ull<<6 /* txempty */;
 258     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 259     info.enable_mask        = 1ull<<6 /* txempty */;
 260     info.flags              = 0;
 261     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 262     info.group_index        = 0;
 263     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 264     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 265     info.parent.status_mask = 1ull<<57 /* pcm */;
 266     info.func               = __cvmx_error_display;
 267     info.user_info          = (long)
 268         "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
 269     fail |= cvmx_error_add(&info);
 270
 271     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 272     info.status_addr        = CVMX_PCMX_INT_SUM(1);
 273     info.status_mask        = 1ull<<7 /* rxovf */;
 274     info.enable_addr        = CVMX_PCMX_INT_ENA(1);
 275     info.enable_mask        = 1ull<<7 /* rxovf */;
 276     info.flags              = 0;
 277     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 278     info.group_index        = 0;
 279     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 280     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 281     info.parent.status_mask = 1ull<<57 /* pcm */;
 282     info.func               = __cvmx_error_display;
 283     info.user_info          = (long)
 284         "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
 285     fail |= cvmx_error_add(&info);
 286
 287     /* CVMX_PCMX_INT_SUM(2) */
 288     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 289     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 290     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 291     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 292     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 293     info.flags              = 0;
 294     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 295     info.group_index        = 0;
 296     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 297     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 298     info.parent.status_mask = 1ull<<57 /* pcm */;
 299     info.func               = __cvmx_error_display;
 300     info.user_info          = (long)
 301         "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 302     fail |= cvmx_error_add(&info);
 303
 304     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 305     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 306     info.status_mask        = 1ull<<1 /* fsyncextra */;
 307     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 308     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 309     info.flags              = 0;
 310     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 311     info.group_index        = 0;
 312     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 313     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 314     info.parent.status_mask = 1ull<<57 /* pcm */;
 315     info.func               = __cvmx_error_display;
 316     info.user_info          = (long)
 317         "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 318     fail |= cvmx_error_add(&info);
 319
 320     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 321     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 322     info.status_mask        = 1ull<<6 /* txempty */;
 323     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 324     info.enable_mask        = 1ull<<6 /* txempty */;
 325     info.flags              = 0;
 326     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 327     info.group_index        = 0;
 328     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 329     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 330     info.parent.status_mask = 1ull<<57 /* pcm */;
 331     info.func               = __cvmx_error_display;
 332     info.user_info          = (long)
 333         "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
 334     fail |= cvmx_error_add(&info);
 335
 336     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 337     info.status_addr        = CVMX_PCMX_INT_SUM(2);
 338     info.status_mask        = 1ull<<7 /* rxovf */;
 339     info.enable_addr        = CVMX_PCMX_INT_ENA(2);
 340     info.enable_mask        = 1ull<<7 /* rxovf */;
 341     info.flags              = 0;
 342     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 343     info.group_index        = 0;
 344     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 345     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 346     info.parent.status_mask = 1ull<<57 /* pcm */;
 347     info.func               = __cvmx_error_display;
 348     info.user_info          = (long)
 349         "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
 350     fail |= cvmx_error_add(&info);
 351
 352     /* CVMX_PCMX_INT_SUM(3) */
 353     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 354     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 355     info.status_mask        = 1ull<<0 /* fsyncmissed */;
 356     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 357     info.enable_mask        = 1ull<<0 /* fsyncmissed */;
 358     info.flags              = 0;
 359     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 360     info.group_index        = 0;
 361     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 362     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 363     info.parent.status_mask = 1ull<<57 /* pcm */;
 364     info.func               = __cvmx_error_display;
 365     info.user_info          = (long)
 366         "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
 367     fail |= cvmx_error_add(&info);
 368
 369     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 370     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 371     info.status_mask        = 1ull<<1 /* fsyncextra */;
 372     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 373     info.enable_mask        = 1ull<<1 /* fsyncextra */;
 374     info.flags              = 0;
 375     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 376     info.group_index        = 0;
 377     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 378     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 379     info.parent.status_mask = 1ull<<57 /* pcm */;
 380     info.func               = __cvmx_error_display;
 381     info.user_info          = (long)
 382         "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
 383     fail |= cvmx_error_add(&info);
 384
 385     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 386     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 387     info.status_mask        = 1ull<<6 /* txempty */;
 388     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 389     info.enable_mask        = 1ull<<6 /* txempty */;
 390     info.flags              = 0;
 391     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 392     info.group_index        = 0;
 393     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 394     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 395     info.parent.status_mask = 1ull<<57 /* pcm */;
 396     info.func               = __cvmx_error_display;
 397     info.user_info          = (long)
 398         "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
 399     fail |= cvmx_error_add(&info);
 400
 401     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 402     info.status_addr        = CVMX_PCMX_INT_SUM(3);
 403     info.status_mask        = 1ull<<7 /* rxovf */;
 404     info.enable_addr        = CVMX_PCMX_INT_ENA(3);
 405     info.enable_mask        = 1ull<<7 /* rxovf */;
 406     info.flags              = 0;
 407     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 408     info.group_index        = 0;
 409     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 410     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 411     info.parent.status_mask = 1ull<<57 /* pcm */;
 412     info.func               = __cvmx_error_display;
 413     info.user_info          = (long)
 414         "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
 415     fail |= cvmx_error_add(&info);
 416
 417     /* CVMX_CIU_INT_SUM1 */
 418     /* CVMX_NPI_RSL_INT_BLOCKS */
 419     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 420     info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
 421     info.status_mask        = 0;
 422     info.enable_addr        = 0;
 423     info.enable_mask        = 0;
 424     info.flags              = 0;
 425     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 426     info.group_index        = 0;
 427     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 428     info.parent.status_addr = 0;
 429     info.parent.status_mask = 0;
 430     info.func               = __cvmx_error_decode;
 431     info.user_info          = 0;
 432     fail |= cvmx_error_add(&info);
 433
 434     /* CVMX_L2D_ERR */
 435     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 436     info.status_addr        = CVMX_L2D_ERR;
 437     info.status_mask        = 1ull<<3 /* sec_err */;
 438     info.enable_addr        = CVMX_L2D_ERR;
 439     info.enable_mask        = 1ull<<1 /* sec_intena */;
 440     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 441     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 442     info.group_index        = 0;
 443     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 444     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 445     info.parent.status_mask = 1ull<<16 /* l2c */;
 446     info.func               = __cvmx_error_handle_l2d_err_sec_err;
 447     info.user_info          = (long)
 448         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
 449     fail |= cvmx_error_add(&info);
 450
 451     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 452     info.status_addr        = CVMX_L2D_ERR;
 453     info.status_mask        = 1ull<<4 /* ded_err */;
 454     info.enable_addr        = CVMX_L2D_ERR;
 455     info.enable_mask        = 1ull<<2 /* ded_intena */;
 456     info.flags              = 0;
 457     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 458     info.group_index        = 0;
 459     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 460     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 461     info.parent.status_mask = 1ull<<16 /* l2c */;
 462     info.func               = __cvmx_error_handle_l2d_err_ded_err;
 463     info.user_info          = (long)
 464         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
 465     fail |= cvmx_error_add(&info);
 466
 467     /* CVMX_L2T_ERR */
 468     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 469     info.status_addr        = CVMX_L2T_ERR;
 470     info.status_mask        = 1ull<<3 /* sec_err */;
 471     info.enable_addr        = CVMX_L2T_ERR;
 472     info.enable_mask        = 1ull<<1 /* sec_intena */;
 473     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 474     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 475     info.group_index        = 0;
 476     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 477     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 478     info.parent.status_mask = 1ull<<16 /* l2c */;
 479     info.func               = __cvmx_error_handle_l2t_err_sec_err;
 480     info.user_info          = (long)
 481         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
 482         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 483         "    given index) are checked for single bit errors(SBEs).\n"
 484         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 485         "    SBEs are auto corrected in HW and generate an\n"
 486         "    interrupt(if enabled).\n";
 487     fail |= cvmx_error_add(&info);
 488
 489     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 490     info.status_addr        = CVMX_L2T_ERR;
 491     info.status_mask        = 1ull<<4 /* ded_err */;
 492     info.enable_addr        = CVMX_L2T_ERR;
 493     info.enable_mask        = 1ull<<2 /* ded_intena */;
 494     info.flags              = 0;
 495     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 496     info.group_index        = 0;
 497     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 498     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 499     info.parent.status_mask = 1ull<<16 /* l2c */;
 500     info.func               = __cvmx_error_handle_l2t_err_ded_err;
 501     info.user_info          = (long)
 502         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
 503         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 504         "    given index) are checked for double bit errors(DBEs).\n"
 505         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 506         "    DBEs also generated an interrupt(if enabled).\n";
 507     fail |= cvmx_error_add(&info);
 508
 509     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 510     info.status_addr        = CVMX_L2T_ERR;
 511     info.status_mask        = 1ull<<24 /* lckerr */;
 512     info.enable_addr        = CVMX_L2T_ERR;
 513     info.enable_mask        = 1ull<<25 /* lck_intena */;
 514     info.flags              = 0;
 515     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 516     info.group_index        = 0;
 517     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 518     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 519     info.parent.status_mask = 1ull<<16 /* l2c */;
 520     info.func               = __cvmx_error_handle_l2t_err_lckerr;
 521     info.user_info          = (long)
 522         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
 523         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 524         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 525         "    successfully, however the address is NOT locked.\n"
 526         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 527         "    into account. For example, if diagnostic PPx has\n"
 528         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 529         "    been previously LOCKED, then an attempt to LOCK the\n"
 530         "    last available SET0 would result in a LCKERR. (This\n"
 531         "    is to ensure that at least 1 SET at each INDEX is\n"
 532         "    not LOCKED for general use by other PPs).\n";
 533     fail |= cvmx_error_add(&info);
 534
 535     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 536     info.status_addr        = CVMX_L2T_ERR;
 537     info.status_mask        = 1ull<<26 /* lckerr2 */;
 538     info.enable_addr        = CVMX_L2T_ERR;
 539     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
 540     info.flags              = 0;
 541     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 542     info.group_index        = 0;
 543     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 544     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 545     info.parent.status_mask = 1ull<<16 /* l2c */;
 546     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
 547     info.user_info          = (long)
 548         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 549         "    could not find an available/unlocked set (for\n"
 550         "    replacement).\n"
 551         "    Most likely, this is a result of SW mixing SET\n"
 552         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 553         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 554         "    then a Rd/Wr Miss from PP#n will be unable\n"
 555         "    to determine a 'valid' replacement set (since LOCKED\n"
 556         "    addresses should NEVER be replaced).\n"
 557         "    If such an event occurs, the HW will select the smallest\n"
 558         "    available SET(specified by UMSK'x)' as the replacement\n"
 559         "    set, and the address is unlocked.\n";
 560     fail |= cvmx_error_add(&info);
 561
 562     /* CVMX_NPI_INT_SUM */
 563     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 564     info.status_addr        = CVMX_NPI_INT_SUM;
 565     info.status_mask        = 1ull<<0 /* rml_rto */;
 566     info.enable_addr        = CVMX_NPI_INT_ENB;
 567     info.enable_mask        = 1ull<<0 /* rml_rto */;
 568     info.flags              = 0;
 569     info.group              = CVMX_ERROR_GROUP_PCI;
 570     info.group_index        = 0;
 571     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 572     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 573     info.parent.status_mask = 1ull<<3 /* npi */;
 574     info.func               = __cvmx_error_display;
 575     info.user_info          = (long)
 576         "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
 577         "    back from a RSL after sending a read command to\n"
 578         "    a RSL.\n";
 579     fail |= cvmx_error_add(&info);
 580
 581     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 582     info.status_addr        = CVMX_NPI_INT_SUM;
 583     info.status_mask        = 1ull<<1 /* rml_wto */;
 584     info.enable_addr        = CVMX_NPI_INT_ENB;
 585     info.enable_mask        = 1ull<<1 /* rml_wto */;
 586     info.flags              = 0;
 587     info.group              = CVMX_ERROR_GROUP_PCI;
 588     info.group_index        = 0;
 589     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 590     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 591     info.parent.status_mask = 1ull<<3 /* npi */;
 592     info.func               = __cvmx_error_display;
 593     info.user_info          = (long)
 594         "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
 595         "    back from a RSL after sending a write command to\n"
 596         "    a RSL.\n";
 597     fail |= cvmx_error_add(&info);
 598
 599     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 600     info.status_addr        = CVMX_NPI_INT_SUM;
 601     info.status_mask        = 1ull<<3 /* po0_2sml */;
 602     info.enable_addr        = CVMX_NPI_INT_ENB;
 603     info.enable_mask        = 1ull<<3 /* po0_2sml */;
 604     info.flags              = 0;
 605     info.group              = CVMX_ERROR_GROUP_PCI;
 606     info.group_index        = 0;
 607     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 608     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 609     info.parent.status_mask = 1ull<<3 /* npi */;
 610     info.func               = __cvmx_error_display;
 611     info.user_info          = (long)
 612         "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
 613         "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
 614     fail |= cvmx_error_add(&info);
 615
 616     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 617     info.status_addr        = CVMX_NPI_INT_SUM;
 618     info.status_mask        = 1ull<<4 /* po1_2sml */;
 619     info.enable_addr        = CVMX_NPI_INT_ENB;
 620     info.enable_mask        = 1ull<<4 /* po1_2sml */;
 621     info.flags              = 0;
 622     info.group              = CVMX_ERROR_GROUP_PCI;
 623     info.group_index        = 0;
 624     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 625     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 626     info.parent.status_mask = 1ull<<3 /* npi */;
 627     info.func               = __cvmx_error_display;
 628     info.user_info          = (long)
 629         "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
 630         "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
 631     fail |= cvmx_error_add(&info);
 632
 633     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 634     info.status_addr        = CVMX_NPI_INT_SUM;
 635     info.status_mask        = 1ull<<7 /* i0_rtout */;
 636     info.enable_addr        = CVMX_NPI_INT_ENB;
 637     info.enable_mask        = 1ull<<7 /* i0_rtout */;
 638     info.flags              = 0;
 639     info.group              = CVMX_ERROR_GROUP_PCI;
 640     info.group_index        = 0;
 641     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 642     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 643     info.parent.status_mask = 1ull<<3 /* npi */;
 644     info.func               = __cvmx_error_display;
 645     info.user_info          = (long)
 646         "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 647         "    read instructions.\n";
 648     fail |= cvmx_error_add(&info);
 649
 650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 651     info.status_addr        = CVMX_NPI_INT_SUM;
 652     info.status_mask        = 1ull<<8 /* i1_rtout */;
 653     info.enable_addr        = CVMX_NPI_INT_ENB;
 654     info.enable_mask        = 1ull<<8 /* i1_rtout */;
 655     info.flags              = 0;
 656     info.group              = CVMX_ERROR_GROUP_PCI;
 657     info.group_index        = 0;
 658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 659     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 660     info.parent.status_mask = 1ull<<3 /* npi */;
 661     info.func               = __cvmx_error_display;
 662     info.user_info          = (long)
 663         "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 664         "    read instructions.\n";
 665     fail |= cvmx_error_add(&info);
 666
 667     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 668     info.status_addr        = CVMX_NPI_INT_SUM;
 669     info.status_mask        = 1ull<<11 /* i0_overf */;
 670     info.enable_addr        = CVMX_NPI_INT_ENB;
 671     info.enable_mask        = 1ull<<11 /* i0_overf */;
 672     info.flags              = 0;
 673     info.group              = CVMX_ERROR_GROUP_PCI;
 674     info.group_index        = 0;
 675     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 676     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 677     info.parent.status_mask = 1ull<<3 /* npi */;
 678     info.func               = __cvmx_error_display;
 679     info.user_info          = (long)
 680         "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
 681         "    doorbell count was set.\n";
 682     fail |= cvmx_error_add(&info);
 683
 684     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 685     info.status_addr        = CVMX_NPI_INT_SUM;
 686     info.status_mask        = 1ull<<12 /* i1_overf */;
 687     info.enable_addr        = CVMX_NPI_INT_ENB;
 688     info.enable_mask        = 1ull<<12 /* i1_overf */;
 689     info.flags              = 0;
 690     info.group              = CVMX_ERROR_GROUP_PCI;
 691     info.group_index        = 0;
 692     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 693     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 694     info.parent.status_mask = 1ull<<3 /* npi */;
 695     info.func               = __cvmx_error_display;
 696     info.user_info          = (long)
 697         "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
 698         "    doorbell count was set.\n";
 699     fail |= cvmx_error_add(&info);
 700
 701     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 702     info.status_addr        = CVMX_NPI_INT_SUM;
 703     info.status_mask        = 1ull<<15 /* p0_rtout */;
 704     info.enable_addr        = CVMX_NPI_INT_ENB;
 705     info.enable_mask        = 1ull<<15 /* p0_rtout */;
 706     info.flags              = 0;
 707     info.group              = CVMX_ERROR_GROUP_PCI;
 708     info.group_index        = 0;
 709     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 710     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 711     info.parent.status_mask = 1ull<<3 /* npi */;
 712     info.func               = __cvmx_error_display;
 713     info.user_info          = (long)
 714         "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 715         "    read packet data.\n";
 716     fail |= cvmx_error_add(&info);
 717
 718     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 719     info.status_addr        = CVMX_NPI_INT_SUM;
 720     info.status_mask        = 1ull<<16 /* p1_rtout */;
 721     info.enable_addr        = CVMX_NPI_INT_ENB;
 722     info.enable_mask        = 1ull<<16 /* p1_rtout */;
 723     info.flags              = 0;
 724     info.group              = CVMX_ERROR_GROUP_PCI;
 725     info.group_index        = 0;
 726     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 727     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 728     info.parent.status_mask = 1ull<<3 /* npi */;
 729     info.func               = __cvmx_error_display;
 730     info.user_info          = (long)
 731         "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 732         "    read packet data.\n";
 733     fail |= cvmx_error_add(&info);
 734
 735     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 736     info.status_addr        = CVMX_NPI_INT_SUM;
 737     info.status_mask        = 1ull<<19 /* p0_perr */;
 738     info.enable_addr        = CVMX_NPI_INT_ENB;
 739     info.enable_mask        = 1ull<<19 /* p0_perr */;
 740     info.flags              = 0;
 741     info.group              = CVMX_ERROR_GROUP_PCI;
 742     info.group_index        = 0;
 743     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 744     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 745     info.parent.status_mask = 1ull<<3 /* npi */;
 746     info.func               = __cvmx_error_display;
 747     info.user_info          = (long)
 748         "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
 749         "    data this bit may be set.\n";
 750     fail |= cvmx_error_add(&info);
 751
 752     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 753     info.status_addr        = CVMX_NPI_INT_SUM;
 754     info.status_mask        = 1ull<<20 /* p1_perr */;
 755     info.enable_addr        = CVMX_NPI_INT_ENB;
 756     info.enable_mask        = 1ull<<20 /* p1_perr */;
 757     info.flags              = 0;
 758     info.group              = CVMX_ERROR_GROUP_PCI;
 759     info.group_index        = 0;
 760     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 761     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 762     info.parent.status_mask = 1ull<<3 /* npi */;
 763     info.func               = __cvmx_error_display;
 764     info.user_info          = (long)
 765         "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
 766         "    data this bit may be set.\n";
 767     fail |= cvmx_error_add(&info);
 768
 769     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 770     info.status_addr        = CVMX_NPI_INT_SUM;
 771     info.status_mask        = 1ull<<23 /* g0_rtout */;
 772     info.enable_addr        = CVMX_NPI_INT_ENB;
 773     info.enable_mask        = 1ull<<23 /* g0_rtout */;
 774     info.flags              = 0;
 775     info.group              = CVMX_ERROR_GROUP_PCI;
 776     info.group_index        = 0;
 777     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 778     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 779     info.parent.status_mask = 1ull<<3 /* npi */;
 780     info.func               = __cvmx_error_display;
 781     info.user_info          = (long)
 782         "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 783         "    read a gather list.\n";
 784     fail |= cvmx_error_add(&info);
 785
 786     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 787     info.status_addr        = CVMX_NPI_INT_SUM;
 788     info.status_mask        = 1ull<<24 /* g1_rtout */;
 789     info.enable_addr        = CVMX_NPI_INT_ENB;
 790     info.enable_mask        = 1ull<<24 /* g1_rtout */;
 791     info.flags              = 0;
 792     info.group              = CVMX_ERROR_GROUP_PCI;
 793     info.group_index        = 0;
 794     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 795     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 796     info.parent.status_mask = 1ull<<3 /* npi */;
 797     info.func               = __cvmx_error_display;
 798     info.user_info          = (long)
 799         "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 800         "    read a gather list.\n";
 801     fail |= cvmx_error_add(&info);
 802
 803     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 804     info.status_addr        = CVMX_NPI_INT_SUM;
 805     info.status_mask        = 1ull<<27 /* p0_pperr */;
 806     info.enable_addr        = CVMX_NPI_INT_ENB;
 807     info.enable_mask        = 1ull<<27 /* p0_pperr */;
 808     info.flags              = 0;
 809     info.group              = CVMX_ERROR_GROUP_PCI;
 810     info.group_index        = 0;
 811     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 812     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 813     info.parent.status_mask = 1ull<<3 /* npi */;
 814     info.func               = __cvmx_error_display;
 815     info.user_info          = (long)
 816         "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
 817         "    pointer-pair, this bit may be set.\n";
 818     fail |= cvmx_error_add(&info);
 819
 820     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 821     info.status_addr        = CVMX_NPI_INT_SUM;
 822     info.status_mask        = 1ull<<28 /* p1_pperr */;
 823     info.enable_addr        = CVMX_NPI_INT_ENB;
 824     info.enable_mask        = 1ull<<28 /* p1_pperr */;
 825     info.flags              = 0;
 826     info.group              = CVMX_ERROR_GROUP_PCI;
 827     info.group_index        = 0;
 828     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 829     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 830     info.parent.status_mask = 1ull<<3 /* npi */;
 831     info.func               = __cvmx_error_display;
 832     info.user_info          = (long)
 833         "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
 834         "    pointer-pair, this bit may be set.\n";
 835     fail |= cvmx_error_add(&info);
 836
 837     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 838     info.status_addr        = CVMX_NPI_INT_SUM;
 839     info.status_mask        = 1ull<<31 /* p0_ptout */;
 840     info.enable_addr        = CVMX_NPI_INT_ENB;
 841     info.enable_mask        = 1ull<<31 /* p0_ptout */;
 842     info.flags              = 0;
 843     info.group              = CVMX_ERROR_GROUP_PCI;
 844     info.group_index        = 0;
 845     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 846     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 847     info.parent.status_mask = 1ull<<3 /* npi */;
 848     info.func               = __cvmx_error_display;
 849     info.user_info          = (long)
 850         "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
 851         "    pair.\n";
 852     fail |= cvmx_error_add(&info);
 853
 854     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 855     info.status_addr        = CVMX_NPI_INT_SUM;
 856     info.status_mask        = 1ull<<32 /* p1_ptout */;
 857     info.enable_addr        = CVMX_NPI_INT_ENB;
 858     info.enable_mask        = 1ull<<32 /* p1_ptout */;
 859     info.flags              = 0;
 860     info.group              = CVMX_ERROR_GROUP_PCI;
 861     info.group_index        = 0;
 862     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 863     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 864     info.parent.status_mask = 1ull<<3 /* npi */;
 865     info.func               = __cvmx_error_display;
 866     info.user_info          = (long)
 867         "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
 868         "    pair.\n";
 869     fail |= cvmx_error_add(&info);
 870
 871     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 872     info.status_addr        = CVMX_NPI_INT_SUM;
 873     info.status_mask        = 1ull<<35 /* i0_pperr */;
 874     info.enable_addr        = CVMX_NPI_INT_ENB;
 875     info.enable_mask        = 1ull<<35 /* i0_pperr */;
 876     info.flags              = 0;
 877     info.group              = CVMX_ERROR_GROUP_PCI;
 878     info.group_index        = 0;
 879     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 880     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 881     info.parent.status_mask = 1ull<<3 /* npi */;
 882     info.func               = __cvmx_error_display;
 883     info.user_info          = (long)
 884         "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
 885         "    this bit may be set.\n";
 886     fail |= cvmx_error_add(&info);
 887
 888     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 889     info.status_addr        = CVMX_NPI_INT_SUM;
 890     info.status_mask        = 1ull<<36 /* i1_pperr */;
 891     info.enable_addr        = CVMX_NPI_INT_ENB;
 892     info.enable_mask        = 1ull<<36 /* i1_pperr */;
 893     info.flags              = 0;
 894     info.group              = CVMX_ERROR_GROUP_PCI;
 895     info.group_index        = 0;
 896     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 897     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 898     info.parent.status_mask = 1ull<<3 /* npi */;
 899     info.func               = __cvmx_error_display;
 900     info.user_info          = (long)
 901         "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
 902         "    this bit may be set.\n";
 903     fail |= cvmx_error_add(&info);
 904
 905     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 906     info.status_addr        = CVMX_NPI_INT_SUM;
 907     info.status_mask        = 1ull<<39 /* win_rto */;
 908     info.enable_addr        = CVMX_NPI_INT_ENB;
 909     info.enable_mask        = 1ull<<39 /* win_rto */;
 910     info.flags              = 0;
 911     info.group              = CVMX_ERROR_GROUP_PCI;
 912     info.group_index        = 0;
 913     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 914     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 915     info.parent.status_mask = 1ull<<3 /* npi */;
 916     info.func               = __cvmx_error_display;
 917     info.user_info          = (long)
 918         "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
 919     fail |= cvmx_error_add(&info);
 920
 921     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 922     info.status_addr        = CVMX_NPI_INT_SUM;
 923     info.status_mask        = 1ull<<40 /* p_dperr */;
 924     info.enable_addr        = CVMX_NPI_INT_ENB;
 925     info.enable_mask        = 1ull<<40 /* p_dperr */;
 926     info.flags              = 0;
 927     info.group              = CVMX_ERROR_GROUP_PCI;
 928     info.group_index        = 0;
 929     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 930     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 931     info.parent.status_mask = 1ull<<3 /* npi */;
 932     info.func               = __cvmx_error_display;
 933     info.user_info          = (long)
 934         "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
 935         "    from the PCI this bit may be set.\n";
 936     fail |= cvmx_error_add(&info);
 937
 938     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 939     info.status_addr        = CVMX_NPI_INT_SUM;
 940     info.status_mask        = 1ull<<41 /* iobdma */;
 941     info.enable_addr        = CVMX_NPI_INT_ENB;
 942     info.enable_mask        = 1ull<<41 /* iobdma */;
 943     info.flags              = 0;
 944     info.group              = CVMX_ERROR_GROUP_PCI;
 945     info.group_index        = 0;
 946     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 947     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 948     info.parent.status_mask = 1ull<<3 /* npi */;
 949     info.func               = __cvmx_error_display;
 950     info.user_info          = (long)
 951         "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
 952     fail |= cvmx_error_add(&info);
 953
 954     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 955     info.status_addr        = CVMX_NPI_INT_SUM;
 956     info.status_mask        = 1ull<<42 /* fcr_s_e */;
 957     info.enable_addr        = CVMX_NPI_INT_ENB;
 958     info.enable_mask        = 1ull<<42 /* fcr_s_e */;
 959     info.flags              = 0;
 960     info.group              = CVMX_ERROR_GROUP_PCI;
 961     info.group_index        = 0;
 962     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 963     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 964     info.parent.status_mask = 1ull<<3 /* npi */;
 965     info.func               = __cvmx_error_display;
 966     info.user_info          = (long)
 967         "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
 968     fail |= cvmx_error_add(&info);
 969
 970     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 971     info.status_addr        = CVMX_NPI_INT_SUM;
 972     info.status_mask        = 1ull<<43 /* fcr_a_f */;
 973     info.enable_addr        = CVMX_NPI_INT_ENB;
 974     info.enable_mask        = 1ull<<43 /* fcr_a_f */;
 975     info.flags              = 0;
 976     info.group              = CVMX_ERROR_GROUP_PCI;
 977     info.group_index        = 0;
 978     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 979     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 980     info.parent.status_mask = 1ull<<3 /* npi */;
 981     info.func               = __cvmx_error_display;
 982     info.user_info          = (long)
 983         "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
 984     fail |= cvmx_error_add(&info);
 985
 986     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 987     info.status_addr        = CVMX_NPI_INT_SUM;
 988     info.status_mask        = 1ull<<44 /* pcr_s_e */;
 989     info.enable_addr        = CVMX_NPI_INT_ENB;
 990     info.enable_mask        = 1ull<<44 /* pcr_s_e */;
 991     info.flags              = 0;
 992     info.group              = CVMX_ERROR_GROUP_PCI;
 993     info.group_index        = 0;
 994     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 995     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 996     info.parent.status_mask = 1ull<<3 /* npi */;
 997     info.func               = __cvmx_error_display;
 998     info.user_info          = (long)
 999         "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
1000     fail |= cvmx_error_add(&info);
1001
1002     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1003     info.status_addr        = CVMX_NPI_INT_SUM;
1004     info.status_mask        = 1ull<<45 /* pcr_a_f */;
1005     info.enable_addr        = CVMX_NPI_INT_ENB;
1006     info.enable_mask        = 1ull<<45 /* pcr_a_f */;
1007     info.flags              = 0;
1008     info.group              = CVMX_ERROR_GROUP_PCI;
1009     info.group_index        = 0;
1010     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1011     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1012     info.parent.status_mask = 1ull<<3 /* npi */;
1013     info.func               = __cvmx_error_display;
1014     info.user_info          = (long)
1015         "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
1016     fail |= cvmx_error_add(&info);
1017
1018     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1019     info.status_addr        = CVMX_NPI_INT_SUM;
1020     info.status_mask        = 1ull<<46 /* q2_s_e */;
1021     info.enable_addr        = CVMX_NPI_INT_ENB;
1022     info.enable_mask        = 1ull<<46 /* q2_s_e */;
1023     info.flags              = 0;
1024     info.group              = CVMX_ERROR_GROUP_PCI;
1025     info.group_index        = 0;
1026     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1027     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1028     info.parent.status_mask = 1ull<<3 /* npi */;
1029     info.func               = __cvmx_error_display;
1030     info.user_info          = (long)
1031         "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
1032     fail |= cvmx_error_add(&info);
1033
1034     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1035     info.status_addr        = CVMX_NPI_INT_SUM;
1036     info.status_mask        = 1ull<<47 /* q2_a_f */;
1037     info.enable_addr        = CVMX_NPI_INT_ENB;
1038     info.enable_mask        = 1ull<<47 /* q2_a_f */;
1039     info.flags              = 0;
1040     info.group              = CVMX_ERROR_GROUP_PCI;
1041     info.group_index        = 0;
1042     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1043     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1044     info.parent.status_mask = 1ull<<3 /* npi */;
1045     info.func               = __cvmx_error_display;
1046     info.user_info          = (long)
1047         "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
1048     fail |= cvmx_error_add(&info);
1049
1050     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1051     info.status_addr        = CVMX_NPI_INT_SUM;
1052     info.status_mask        = 1ull<<48 /* q3_s_e */;
1053     info.enable_addr        = CVMX_NPI_INT_ENB;
1054     info.enable_mask        = 1ull<<48 /* q3_s_e */;
1055     info.flags              = 0;
1056     info.group              = CVMX_ERROR_GROUP_PCI;
1057     info.group_index        = 0;
1058     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1059     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1060     info.parent.status_mask = 1ull<<3 /* npi */;
1061     info.func               = __cvmx_error_display;
1062     info.user_info          = (long)
1063         "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
1064     fail |= cvmx_error_add(&info);
1065
1066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1067     info.status_addr        = CVMX_NPI_INT_SUM;
1068     info.status_mask        = 1ull<<49 /* q3_a_f */;
1069     info.enable_addr        = CVMX_NPI_INT_ENB;
1070     info.enable_mask        = 1ull<<49 /* q3_a_f */;
1071     info.flags              = 0;
1072     info.group              = CVMX_ERROR_GROUP_PCI;
1073     info.group_index        = 0;
1074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1075     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1076     info.parent.status_mask = 1ull<<3 /* npi */;
1077     info.func               = __cvmx_error_display;
1078     info.user_info          = (long)
1079         "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
1080     fail |= cvmx_error_add(&info);
1081
1082     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1083     info.status_addr        = CVMX_NPI_INT_SUM;
1084     info.status_mask        = 1ull<<50 /* com_s_e */;
1085     info.enable_addr        = CVMX_NPI_INT_ENB;
1086     info.enable_mask        = 1ull<<50 /* com_s_e */;
1087     info.flags              = 0;
1088     info.group              = CVMX_ERROR_GROUP_PCI;
1089     info.group_index        = 0;
1090     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1091     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1092     info.parent.status_mask = 1ull<<3 /* npi */;
1093     info.func               = __cvmx_error_display;
1094     info.user_info          = (long)
1095         "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
1096     fail |= cvmx_error_add(&info);
1097
1098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1099     info.status_addr        = CVMX_NPI_INT_SUM;
1100     info.status_mask        = 1ull<<51 /* com_a_f */;
1101     info.enable_addr        = CVMX_NPI_INT_ENB;
1102     info.enable_mask        = 1ull<<51 /* com_a_f */;
1103     info.flags              = 0;
1104     info.group              = CVMX_ERROR_GROUP_PCI;
1105     info.group_index        = 0;
1106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1107     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1108     info.parent.status_mask = 1ull<<3 /* npi */;
1109     info.func               = __cvmx_error_display;
1110     info.user_info          = (long)
1111         "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
1112     fail |= cvmx_error_add(&info);
1113
1114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1115     info.status_addr        = CVMX_NPI_INT_SUM;
1116     info.status_mask        = 1ull<<52 /* pnc_s_e */;
1117     info.enable_addr        = CVMX_NPI_INT_ENB;
1118     info.enable_mask        = 1ull<<52 /* pnc_s_e */;
1119     info.flags              = 0;
1120     info.group              = CVMX_ERROR_GROUP_PCI;
1121     info.group_index        = 0;
1122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1123     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1124     info.parent.status_mask = 1ull<<3 /* npi */;
1125     info.func               = __cvmx_error_display;
1126     info.user_info          = (long)
1127         "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
1128     fail |= cvmx_error_add(&info);
1129
1130     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1131     info.status_addr        = CVMX_NPI_INT_SUM;
1132     info.status_mask        = 1ull<<53 /* pnc_a_f */;
1133     info.enable_addr        = CVMX_NPI_INT_ENB;
1134     info.enable_mask        = 1ull<<53 /* pnc_a_f */;
1135     info.flags              = 0;
1136     info.group              = CVMX_ERROR_GROUP_PCI;
1137     info.group_index        = 0;
1138     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1139     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1140     info.parent.status_mask = 1ull<<3 /* npi */;
1141     info.func               = __cvmx_error_display;
1142     info.user_info          = (long)
1143         "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
1144     fail |= cvmx_error_add(&info);
1145
1146     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1147     info.status_addr        = CVMX_NPI_INT_SUM;
1148     info.status_mask        = 1ull<<54 /* rwx_s_e */;
1149     info.enable_addr        = CVMX_NPI_INT_ENB;
1150     info.enable_mask        = 1ull<<54 /* rwx_s_e */;
1151     info.flags              = 0;
1152     info.group              = CVMX_ERROR_GROUP_PCI;
1153     info.group_index        = 0;
1154     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1155     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1156     info.parent.status_mask = 1ull<<3 /* npi */;
1157     info.func               = __cvmx_error_display;
1158     info.user_info          = (long)
1159         "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
1160     fail |= cvmx_error_add(&info);
1161
1162     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1163     info.status_addr        = CVMX_NPI_INT_SUM;
1164     info.status_mask        = 1ull<<55 /* rdx_s_e */;
1165     info.enable_addr        = CVMX_NPI_INT_ENB;
1166     info.enable_mask        = 1ull<<55 /* rdx_s_e */;
1167     info.flags              = 0;
1168     info.group              = CVMX_ERROR_GROUP_PCI;
1169     info.group_index        = 0;
1170     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1171     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1172     info.parent.status_mask = 1ull<<3 /* npi */;
1173     info.func               = __cvmx_error_display;
1174     info.user_info          = (long)
1175         "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
1176     fail |= cvmx_error_add(&info);
1177
1178     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1179     info.status_addr        = CVMX_NPI_INT_SUM;
1180     info.status_mask        = 1ull<<56 /* pcf_p_e */;
1181     info.enable_addr        = CVMX_NPI_INT_ENB;
1182     info.enable_mask        = 1ull<<56 /* pcf_p_e */;
1183     info.flags              = 0;
1184     info.group              = CVMX_ERROR_GROUP_PCI;
1185     info.group_index        = 0;
1186     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1187     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1188     info.parent.status_mask = 1ull<<3 /* npi */;
1189     info.func               = __cvmx_error_display;
1190     info.user_info          = (long)
1191         "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
1192     fail |= cvmx_error_add(&info);
1193
1194     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1195     info.status_addr        = CVMX_NPI_INT_SUM;
1196     info.status_mask        = 1ull<<57 /* pcf_p_f */;
1197     info.enable_addr        = CVMX_NPI_INT_ENB;
1198     info.enable_mask        = 1ull<<57 /* pcf_p_f */;
1199     info.flags              = 0;
1200     info.group              = CVMX_ERROR_GROUP_PCI;
1201     info.group_index        = 0;
1202     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1203     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1204     info.parent.status_mask = 1ull<<3 /* npi */;
1205     info.func               = __cvmx_error_display;
1206     info.user_info          = (long)
1207         "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
1208     fail |= cvmx_error_add(&info);
1209
1210     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1211     info.status_addr        = CVMX_NPI_INT_SUM;
1212     info.status_mask        = 1ull<<58 /* pdf_p_e */;
1213     info.enable_addr        = CVMX_NPI_INT_ENB;
1214     info.enable_mask        = 1ull<<58 /* pdf_p_e */;
1215     info.flags              = 0;
1216     info.group              = CVMX_ERROR_GROUP_PCI;
1217     info.group_index        = 0;
1218     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1219     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1220     info.parent.status_mask = 1ull<<3 /* npi */;
1221     info.func               = __cvmx_error_display;
1222     info.user_info          = (long)
1223         "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
1224     fail |= cvmx_error_add(&info);
1225
1226     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1227     info.status_addr        = CVMX_NPI_INT_SUM;
1228     info.status_mask        = 1ull<<59 /* pdf_p_f */;
1229     info.enable_addr        = CVMX_NPI_INT_ENB;
1230     info.enable_mask        = 1ull<<59 /* pdf_p_f */;
1231     info.flags              = 0;
1232     info.group              = CVMX_ERROR_GROUP_PCI;
1233     info.group_index        = 0;
1234     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1235     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1236     info.parent.status_mask = 1ull<<3 /* npi */;
1237     info.func               = __cvmx_error_display;
1238     info.user_info          = (long)
1239         "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
1240     fail |= cvmx_error_add(&info);
1241
1242     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1243     info.status_addr        = CVMX_NPI_INT_SUM;
1244     info.status_mask        = 1ull<<60 /* q1_s_e */;
1245     info.enable_addr        = CVMX_NPI_INT_ENB;
1246     info.enable_mask        = 1ull<<60 /* q1_s_e */;
1247     info.flags              = 0;
1248     info.group              = CVMX_ERROR_GROUP_PCI;
1249     info.group_index        = 0;
1250     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1251     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1252     info.parent.status_mask = 1ull<<3 /* npi */;
1253     info.func               = __cvmx_error_display;
1254     info.user_info          = (long)
1255         "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
1256     fail |= cvmx_error_add(&info);
1257
1258     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1259     info.status_addr        = CVMX_NPI_INT_SUM;
1260     info.status_mask        = 1ull<<61 /* q1_a_f */;
1261     info.enable_addr        = CVMX_NPI_INT_ENB;
1262     info.enable_mask        = 1ull<<61 /* q1_a_f */;
1263     info.flags              = 0;
1264     info.group              = CVMX_ERROR_GROUP_PCI;
1265     info.group_index        = 0;
1266     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1267     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1268     info.parent.status_mask = 1ull<<3 /* npi */;
1269     info.func               = __cvmx_error_display;
1270     info.user_info          = (long)
1271         "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
1272     fail |= cvmx_error_add(&info);
1273
1274     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1275     info.status_addr        = CVMX_NPI_INT_SUM;
1276     info.status_mask        = 0;
1277     info.enable_addr        = 0;
1278     info.enable_mask        = 0;
1279     info.flags              = 0;
1280     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1281     info.group_index        = 0;
1282     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1283     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1284     info.parent.status_mask = 1ull<<3 /* npi */;
1285     info.func               = __cvmx_error_decode;
1286     info.user_info          = 0;
1287     fail |= cvmx_error_add(&info);
1288
1289     /* CVMX_NPI_PCI_INT_SUM2 */
1290     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1291     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1292     info.status_mask        = 1ull<<0 /* tr_wabt */;
1293     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1294     info.enable_mask        = 1ull<<0 /* rtr_wabt */;
1295     info.flags              = 0;
1296     info.group              = CVMX_ERROR_GROUP_PCI;
1297     info.group_index        = 0;
1298     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1299     info.parent.status_addr = CVMX_NPI_INT_SUM;
1300     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1301     info.func               = __cvmx_error_display;
1302     info.user_info          = (long)
1303         "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
1304     fail |= cvmx_error_add(&info);
1305
1306     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1307     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1308     info.status_mask        = 1ull<<1 /* mr_wabt */;
1309     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1310     info.enable_mask        = 1ull<<1 /* rmr_wabt */;
1311     info.flags              = 0;
1312     info.group              = CVMX_ERROR_GROUP_PCI;
1313     info.group_index        = 0;
1314     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1315     info.parent.status_addr = CVMX_NPI_INT_SUM;
1316     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1317     info.func               = __cvmx_error_display;
1318     info.user_info          = (long)
1319         "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
1320     fail |= cvmx_error_add(&info);
1321
1322     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1323     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1324     info.status_mask        = 1ull<<2 /* mr_wtto */;
1325     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1326     info.enable_mask        = 1ull<<2 /* rmr_wtto */;
1327     info.flags              = 0;
1328     info.group              = CVMX_ERROR_GROUP_PCI;
1329     info.group_index        = 0;
1330     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1331     info.parent.status_addr = CVMX_NPI_INT_SUM;
1332     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1333     info.func               = __cvmx_error_display;
1334     info.user_info          = (long)
1335         "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
1336     fail |= cvmx_error_add(&info);
1337
1338     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1339     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1340     info.status_mask        = 1ull<<3 /* tr_abt */;
1341     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1342     info.enable_mask        = 1ull<<3 /* rtr_abt */;
1343     info.flags              = 0;
1344     info.group              = CVMX_ERROR_GROUP_PCI;
1345     info.group_index        = 0;
1346     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1347     info.parent.status_addr = CVMX_NPI_INT_SUM;
1348     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1349     info.func               = __cvmx_error_display;
1350     info.user_info          = (long)
1351         "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
1352     fail |= cvmx_error_add(&info);
1353
1354     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1355     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1356     info.status_mask        = 1ull<<4 /* mr_abt */;
1357     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1358     info.enable_mask        = 1ull<<4 /* rmr_abt */;
1359     info.flags              = 0;
1360     info.group              = CVMX_ERROR_GROUP_PCI;
1361     info.group_index        = 0;
1362     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1363     info.parent.status_addr = CVMX_NPI_INT_SUM;
1364     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1365     info.func               = __cvmx_error_display;
1366     info.user_info          = (long)
1367         "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
1368     fail |= cvmx_error_add(&info);
1369
1370     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1371     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1372     info.status_mask        = 1ull<<5 /* mr_tto */;
1373     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1374     info.enable_mask        = 1ull<<5 /* rmr_tto */;
1375     info.flags              = 0;
1376     info.group              = CVMX_ERROR_GROUP_PCI;
1377     info.group_index        = 0;
1378     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1379     info.parent.status_addr = CVMX_NPI_INT_SUM;
1380     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1381     info.func               = __cvmx_error_display;
1382     info.user_info          = (long)
1383         "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
1384     fail |= cvmx_error_add(&info);
1385
1386     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1387     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1388     info.status_mask        = 1ull<<6 /* msi_per */;
1389     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1390     info.enable_mask        = 1ull<<6 /* rmsi_per */;
1391     info.flags              = 0;
1392     info.group              = CVMX_ERROR_GROUP_PCI;
1393     info.group_index        = 0;
1394     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1395     info.parent.status_addr = CVMX_NPI_INT_SUM;
1396     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1397     info.func               = __cvmx_error_display;
1398     info.user_info          = (long)
1399         "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
1400     fail |= cvmx_error_add(&info);
1401
1402     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1403     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1404     info.status_mask        = 1ull<<7 /* msi_tabt */;
1405     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1406     info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
1407     info.flags              = 0;
1408     info.group              = CVMX_ERROR_GROUP_PCI;
1409     info.group_index        = 0;
1410     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1411     info.parent.status_addr = CVMX_NPI_INT_SUM;
1412     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1413     info.func               = __cvmx_error_display;
1414     info.user_info          = (long)
1415         "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
1416     fail |= cvmx_error_add(&info);
1417
1418     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1419     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1420     info.status_mask        = 1ull<<8 /* msi_mabt */;
1421     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1422     info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
1423     info.flags              = 0;
1424     info.group              = CVMX_ERROR_GROUP_PCI;
1425     info.group_index        = 0;
1426     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1427     info.parent.status_addr = CVMX_NPI_INT_SUM;
1428     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1429     info.func               = __cvmx_error_display;
1430     info.user_info          = (long)
1431         "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
1432     fail |= cvmx_error_add(&info);
1433
1434     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1435     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1436     info.status_mask        = 1ull<<9 /* msc_msg */;
1437     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1438     info.enable_mask        = 1ull<<9 /* rmsc_msg */;
1439     info.flags              = 0;
1440     info.group              = CVMX_ERROR_GROUP_PCI;
1441     info.group_index        = 0;
1442     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1443     info.parent.status_addr = CVMX_NPI_INT_SUM;
1444     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1445     info.func               = __cvmx_error_display;
1446     info.user_info          = (long)
1447         "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
1448     fail |= cvmx_error_add(&info);
1449
1450     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1451     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1452     info.status_mask        = 1ull<<10 /* tsr_abt */;
1453     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1454     info.enable_mask        = 1ull<<10 /* rtsr_abt */;
1455     info.flags              = 0;
1456     info.group              = CVMX_ERROR_GROUP_PCI;
1457     info.group_index        = 0;
1458     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1459     info.parent.status_addr = CVMX_NPI_INT_SUM;
1460     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1461     info.func               = __cvmx_error_display;
1462     info.user_info          = (long)
1463         "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
1464     fail |= cvmx_error_add(&info);
1465
1466     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1467     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1468     info.status_mask        = 1ull<<11 /* serr */;
1469     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1470     info.enable_mask        = 1ull<<11 /* rserr */;
1471     info.flags              = 0;
1472     info.group              = CVMX_ERROR_GROUP_PCI;
1473     info.group_index        = 0;
1474     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1475     info.parent.status_addr = CVMX_NPI_INT_SUM;
1476     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1477     info.func               = __cvmx_error_display;
1478     info.user_info          = (long)
1479         "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
1480     fail |= cvmx_error_add(&info);
1481
1482     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1483     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1484     info.status_mask        = 1ull<<12 /* aperr */;
1485     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1486     info.enable_mask        = 1ull<<12 /* raperr */;
1487     info.flags              = 0;
1488     info.group              = CVMX_ERROR_GROUP_PCI;
1489     info.group_index        = 0;
1490     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1491     info.parent.status_addr = CVMX_NPI_INT_SUM;
1492     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1493     info.func               = __cvmx_error_display;
1494     info.user_info          = (long)
1495         "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
1496     fail |= cvmx_error_add(&info);
1497
1498     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1499     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1500     info.status_mask        = 1ull<<13 /* dperr */;
1501     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1502     info.enable_mask        = 1ull<<13 /* rdperr */;
1503     info.flags              = 0;
1504     info.group              = CVMX_ERROR_GROUP_PCI;
1505     info.group_index        = 0;
1506     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1507     info.parent.status_addr = CVMX_NPI_INT_SUM;
1508     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1509     info.func               = __cvmx_error_display;
1510     info.user_info          = (long)
1511         "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
1512     fail |= cvmx_error_add(&info);
1513
1514     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1515     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1516     info.status_mask        = 1ull<<14 /* ill_rwr */;
1517     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1518     info.enable_mask        = 1ull<<14 /* ill_rwr */;
1519     info.flags              = 0;
1520     info.group              = CVMX_ERROR_GROUP_PCI;
1521     info.group_index        = 0;
1522     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1523     info.parent.status_addr = CVMX_NPI_INT_SUM;
1524     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1525     info.func               = __cvmx_error_display;
1526     info.user_info          = (long)
1527         "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
1528     fail |= cvmx_error_add(&info);
1529
1530     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1531     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1532     info.status_mask        = 1ull<<15 /* ill_rrd */;
1533     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1534     info.enable_mask        = 1ull<<15 /* ill_rrd */;
1535     info.flags              = 0;
1536     info.group              = CVMX_ERROR_GROUP_PCI;
1537     info.group_index        = 0;
1538     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1539     info.parent.status_addr = CVMX_NPI_INT_SUM;
1540     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1541     info.func               = __cvmx_error_display;
1542     info.user_info          = (long)
1543         "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
1544     fail |= cvmx_error_add(&info);
1545
1546     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1547     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1548     info.status_mask        = 1ull<<31 /* win_wr */;
1549     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1550     info.enable_mask        = 1ull<<31 /* win_wr */;
1551     info.flags              = 0;
1552     info.group              = CVMX_ERROR_GROUP_PCI;
1553     info.group_index        = 0;
1554     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1555     info.parent.status_addr = CVMX_NPI_INT_SUM;
1556     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1557     info.func               = __cvmx_error_display;
1558     info.user_info          = (long)
1559         "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
1560         "    Read-Address Register took place.\n";
1561     fail |= cvmx_error_add(&info);
1562
1563     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1564     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1565     info.status_mask        = 1ull<<32 /* ill_wr */;
1566     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1567     info.enable_mask        = 1ull<<32 /* ill_wr */;
1568     info.flags              = 0;
1569     info.group              = CVMX_ERROR_GROUP_PCI;
1570     info.group_index        = 0;
1571     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1572     info.parent.status_addr = CVMX_NPI_INT_SUM;
1573     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1574     info.func               = __cvmx_error_display;
1575     info.user_info          = (long)
1576         "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
1577         "    when the mem area is disabled.\n";
1578     fail |= cvmx_error_add(&info);
1579
1580     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1581     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1582     info.status_mask        = 1ull<<33 /* ill_rd */;
1583     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1584     info.enable_mask        = 1ull<<33 /* ill_rd */;
1585     info.flags              = 0;
1586     info.group              = CVMX_ERROR_GROUP_PCI;
1587     info.group_index        = 0;
1588     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1589     info.parent.status_addr = CVMX_NPI_INT_SUM;
1590     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1591     info.func               = __cvmx_error_display;
1592     info.user_info          = (long)
1593         "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
1594         "    when the mem area is disabled.\n";
1595     fail |= cvmx_error_add(&info);
1596
1597     /* CVMX_GMXX_BAD_REG(0) */
1598     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1599     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1600     info.status_mask        = 0x7ull<<2 /* out_ovr */;
1601     info.enable_addr        = 0;
1602     info.enable_mask        = 0;
1603     info.flags              = 0;
1604     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1605     info.group_index        = 0;
1606     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1607     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1608     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1609     info.func               = __cvmx_error_display;
1610     info.user_info          = (long)
1611         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1612     fail |= cvmx_error_add(&info);
1613
1614     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1615     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1616     info.status_mask        = 0x7ull<<22 /* loststat */;
1617     info.enable_addr        = 0;
1618     info.enable_mask        = 0;
1619     info.flags              = 0;
1620     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1621     info.group_index        = 0;
1622     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1623     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1624     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1625     info.func               = __cvmx_error_display;
1626     info.user_info          = (long)
1627         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
1628         "    TX Stats are corrupted\n";
1629     fail |= cvmx_error_add(&info);
1630
1631     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1632     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1633     info.status_mask        = 1ull<<26 /* statovr */;
1634     info.enable_addr        = 0;
1635     info.enable_mask        = 0;
1636     info.flags              = 0;
1637     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1638     info.group_index        = 0;
1639     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1640     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1641     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1642     info.func               = __cvmx_error_display;
1643     info.user_info          = (long)
1644         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
1645     fail |= cvmx_error_add(&info);
1646
1647     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1648     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1649     info.status_mask        = 0xfull<<27 /* inb_nxa */;
1650     info.enable_addr        = 0;
1651     info.enable_mask        = 0;
1652     info.flags              = 0;
1653     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1654     info.group_index        = 0;
1655     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1656     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1657     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1658     info.func               = __cvmx_error_display;
1659     info.user_info          = (long)
1660         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1661     fail |= cvmx_error_add(&info);
1662
1663     /* CVMX_GMXX_RXX_INT_REG(0,0) */
1664     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1665     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1666     info.status_mask        = 1ull<<1 /* carext */;
1667     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1668     info.enable_mask        = 1ull<<1 /* carext */;
1669     info.flags              = 0;
1670     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1671     info.group_index        = 0;
1672     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1673     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1674     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1675     info.func               = __cvmx_error_display;
1676     info.user_info          = (long)
1677         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
1678     fail |= cvmx_error_add(&info);
1679
1680     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1681     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1682     info.status_mask        = 1ull<<2 /* maxerr */;
1683     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1684     info.enable_mask        = 1ull<<2 /* maxerr */;
1685     info.flags              = 0;
1686     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1687     info.group_index        = 0;
1688     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1689     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1690     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1691     info.func               = __cvmx_error_display;
1692     info.user_info          = (long)
1693         "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
1694     fail |= cvmx_error_add(&info);
1695
1696     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1697     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1698     info.status_mask        = 1ull<<5 /* alnerr */;
1699     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1700     info.enable_mask        = 1ull<<5 /* alnerr */;
1701     info.flags              = 0;
1702     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1703     info.group_index        = 0;
1704     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1705     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1706     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1707     info.func               = __cvmx_error_display;
1708     info.user_info          = (long)
1709         "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
1710     fail |= cvmx_error_add(&info);
1711
1712     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1713     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1714     info.status_mask        = 1ull<<6 /* lenerr */;
1715     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1716     info.enable_mask        = 1ull<<6 /* lenerr */;
1717     info.flags              = 0;
1718     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1719     info.group_index        = 0;
1720     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1721     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1722     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1723     info.func               = __cvmx_error_display;
1724     info.user_info          = (long)
1725         "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
1726     fail |= cvmx_error_add(&info);
1727
1728     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1729     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1730     info.status_mask        = 1ull<<8 /* skperr */;
1731     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1732     info.enable_mask        = 1ull<<8 /* skperr */;
1733     info.flags              = 0;
1734     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1735     info.group_index        = 0;
1736     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1737     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1738     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1739     info.func               = __cvmx_error_display;
1740     info.user_info          = (long)
1741         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
1742     fail |= cvmx_error_add(&info);
1743
1744     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1745     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1746     info.status_mask        = 1ull<<9 /* niberr */;
1747     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1748     info.enable_mask        = 1ull<<9 /* niberr */;
1749     info.flags              = 0;
1750     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1751     info.group_index        = 0;
1752     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1753     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1754     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1755     info.func               = __cvmx_error_display;
1756     info.user_info          = (long)
1757         "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1758     fail |= cvmx_error_add(&info);
1759
1760     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1761     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1762     info.status_mask        = 1ull<<10 /* ovrerr */;
1763     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1764     info.enable_mask        = 1ull<<10 /* ovrerr */;
1765     info.flags              = 0;
1766     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1767     info.group_index        = 0;
1768     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1769     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1770     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1771     info.func               = __cvmx_error_display;
1772     info.user_info          = (long)
1773         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1774         "    This interrupt should never assert\n";
1775     fail |= cvmx_error_add(&info);
1776
1777     /* CVMX_GMXX_RXX_INT_REG(1,0) */
1778     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1779     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1780     info.status_mask        = 1ull<<1 /* carext */;
1781     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1782     info.enable_mask        = 1ull<<1 /* carext */;
1783     info.flags              = 0;
1784     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1785     info.group_index        = 1;
1786     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1787     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1788     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1789     info.func               = __cvmx_error_display;
1790     info.user_info          = (long)
1791         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
1792     fail |= cvmx_error_add(&info);
1793
1794     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1795     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1796     info.status_mask        = 1ull<<2 /* maxerr */;
1797     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1798     info.enable_mask        = 1ull<<2 /* maxerr */;
1799     info.flags              = 0;
1800     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1801     info.group_index        = 1;
1802     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1803     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1804     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1805     info.func               = __cvmx_error_display;
1806     info.user_info          = (long)
1807         "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
1808     fail |= cvmx_error_add(&info);
1809
1810     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1811     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1812     info.status_mask        = 1ull<<5 /* alnerr */;
1813     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1814     info.enable_mask        = 1ull<<5 /* alnerr */;
1815     info.flags              = 0;
1816     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1817     info.group_index        = 1;
1818     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1819     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1820     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1821     info.func               = __cvmx_error_display;
1822     info.user_info          = (long)
1823         "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
1824     fail |= cvmx_error_add(&info);
1825
1826     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1827     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1828     info.status_mask        = 1ull<<6 /* lenerr */;
1829     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1830     info.enable_mask        = 1ull<<6 /* lenerr */;
1831     info.flags              = 0;
1832     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1833     info.group_index        = 1;
1834     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1835     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1836     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1837     info.func               = __cvmx_error_display;
1838     info.user_info          = (long)
1839         "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
1840     fail |= cvmx_error_add(&info);
1841
1842     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1843     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1844     info.status_mask        = 1ull<<8 /* skperr */;
1845     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1846     info.enable_mask        = 1ull<<8 /* skperr */;
1847     info.flags              = 0;
1848     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1849     info.group_index        = 1;
1850     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1851     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1852     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1853     info.func               = __cvmx_error_display;
1854     info.user_info          = (long)
1855         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1856     fail |= cvmx_error_add(&info);
1857
1858     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1859     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1860     info.status_mask        = 1ull<<9 /* niberr */;
1861     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1862     info.enable_mask        = 1ull<<9 /* niberr */;
1863     info.flags              = 0;
1864     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1865     info.group_index        = 1;
1866     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1867     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1868     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1869     info.func               = __cvmx_error_display;
1870     info.user_info          = (long)
1871         "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1872     fail |= cvmx_error_add(&info);
1873
1874     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1875     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1876     info.status_mask        = 1ull<<10 /* ovrerr */;
1877     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1878     info.enable_mask        = 1ull<<10 /* ovrerr */;
1879     info.flags              = 0;
1880     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1881     info.group_index        = 1;
1882     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1883     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1884     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1885     info.func               = __cvmx_error_display;
1886     info.user_info          = (long)
1887         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1888         "    This interrupt should never assert\n";
1889     fail |= cvmx_error_add(&info);
1890
1891     /* CVMX_GMXX_RXX_INT_REG(2,0) */
1892     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1893     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1894     info.status_mask        = 1ull<<1 /* carext */;
1895     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1896     info.enable_mask        = 1ull<<1 /* carext */;
1897     info.flags              = 0;
1898     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1899     info.group_index        = 2;
1900     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1901     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1902     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1903     info.func               = __cvmx_error_display;
1904     info.user_info          = (long)
1905         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
1906     fail |= cvmx_error_add(&info);
1907
1908     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1909     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1910     info.status_mask        = 1ull<<2 /* maxerr */;
1911     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1912     info.enable_mask        = 1ull<<2 /* maxerr */;
1913     info.flags              = 0;
1914     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1915     info.group_index        = 2;
1916     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1917     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1918     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1919     info.func               = __cvmx_error_display;
1920     info.user_info          = (long)
1921         "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
1922     fail |= cvmx_error_add(&info);
1923
1924     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1925     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1926     info.status_mask        = 1ull<<5 /* alnerr */;
1927     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1928     info.enable_mask        = 1ull<<5 /* alnerr */;
1929     info.flags              = 0;
1930     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1931     info.group_index        = 2;
1932     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1933     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1934     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1935     info.func               = __cvmx_error_display;
1936     info.user_info          = (long)
1937         "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
1938     fail |= cvmx_error_add(&info);
1939
1940     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1941     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1942     info.status_mask        = 1ull<<6 /* lenerr */;
1943     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1944     info.enable_mask        = 1ull<<6 /* lenerr */;
1945     info.flags              = 0;
1946     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1947     info.group_index        = 2;
1948     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1949     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1950     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1951     info.func               = __cvmx_error_display;
1952     info.user_info          = (long)
1953         "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
1954     fail |= cvmx_error_add(&info);
1955
1956     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1957     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1958     info.status_mask        = 1ull<<8 /* skperr */;
1959     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1960     info.enable_mask        = 1ull<<8 /* skperr */;
1961     info.flags              = 0;
1962     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1963     info.group_index        = 2;
1964     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1965     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1966     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1967     info.func               = __cvmx_error_display;
1968     info.user_info          = (long)
1969         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
1970     fail |= cvmx_error_add(&info);
1971
1972     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1973     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1974     info.status_mask        = 1ull<<9 /* niberr */;
1975     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1976     info.enable_mask        = 1ull<<9 /* niberr */;
1977     info.flags              = 0;
1978     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1979     info.group_index        = 2;
1980     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1981     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1982     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1983     info.func               = __cvmx_error_display;
1984     info.user_info          = (long)
1985         "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1986     fail |= cvmx_error_add(&info);
1987
1988     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1989     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1990     info.status_mask        = 1ull<<10 /* ovrerr */;
1991     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1992     info.enable_mask        = 1ull<<10 /* ovrerr */;
1993     info.flags              = 0;
1994     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1995     info.group_index        = 2;
1996     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1997     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1998     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1999     info.func               = __cvmx_error_display;
2000     info.user_info          = (long)
2001         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2002         "    This interrupt should never assert\n";
2003     fail |= cvmx_error_add(&info);
2004
2005     /* CVMX_GMXX_TX_INT_REG(0) */
2006     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2007     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2008     info.status_mask        = 1ull<<0 /* pko_nxa */;
2009     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2010     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2011     info.flags              = 0;
2012     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2013     info.group_index        = 0;
2014     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2015     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2016     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2017     info.func               = __cvmx_error_display;
2018     info.user_info          = (long)
2019         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2020     fail |= cvmx_error_add(&info);
2021
2022     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2023     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2024     info.status_mask        = 0x7ull<<2 /* undflw */;
2025     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2026     info.enable_mask        = 0x7ull<<2 /* undflw */;
2027     info.flags              = 0;
2028     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2029     info.group_index        = 0;
2030     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2031     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2032     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2033     info.func               = __cvmx_error_display;
2034     info.user_info          = (long)
2035         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
2036     fail |= cvmx_error_add(&info);
2037
2038     /* CVMX_MIO_BOOT_ERR */
2039     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2040     info.status_addr        = CVMX_MIO_BOOT_ERR;
2041     info.status_mask        = 1ull<<0 /* adr_err */;
2042     info.enable_addr        = CVMX_MIO_BOOT_INT;
2043     info.enable_mask        = 1ull<<0 /* adr_int */;
2044     info.flags              = 0;
2045     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2046     info.group_index        = 0;
2047     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2048     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2049     info.parent.status_mask = 1ull<<0 /* mio */;
2050     info.func               = __cvmx_error_display;
2051     info.user_info          = (long)
2052         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
2053     fail |= cvmx_error_add(&info);
2054
2055     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2056     info.status_addr        = CVMX_MIO_BOOT_ERR;
2057     info.status_mask        = 1ull<<1 /* wait_err */;
2058     info.enable_addr        = CVMX_MIO_BOOT_INT;
2059     info.enable_mask        = 1ull<<1 /* wait_int */;
2060     info.flags              = 0;
2061     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2062     info.group_index        = 0;
2063     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2064     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2065     info.parent.status_mask = 1ull<<0 /* mio */;
2066     info.func               = __cvmx_error_display;
2067     info.user_info          = (long)
2068         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
2069     fail |= cvmx_error_add(&info);
2070
2071     /* CVMX_IPD_INT_SUM */
2072     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2073     info.status_addr        = CVMX_IPD_INT_SUM;
2074     info.status_mask        = 1ull<<0 /* prc_par0 */;
2075     info.enable_addr        = CVMX_IPD_INT_ENB;
2076     info.enable_mask        = 1ull<<0 /* prc_par0 */;
2077     info.flags              = 0;
2078     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2079     info.group_index        = 0;
2080     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2081     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2082     info.parent.status_mask = 1ull<<9 /* ipd */;
2083     info.func               = __cvmx_error_display;
2084     info.user_info          = (long)
2085         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2086         "    [31:0] of the PBM memory.\n";
2087     fail |= cvmx_error_add(&info);
2088
2089     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2090     info.status_addr        = CVMX_IPD_INT_SUM;
2091     info.status_mask        = 1ull<<1 /* prc_par1 */;
2092     info.enable_addr        = CVMX_IPD_INT_ENB;
2093     info.enable_mask        = 1ull<<1 /* prc_par1 */;
2094     info.flags              = 0;
2095     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2096     info.group_index        = 0;
2097     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2098     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2099     info.parent.status_mask = 1ull<<9 /* ipd */;
2100     info.func               = __cvmx_error_display;
2101     info.user_info          = (long)
2102         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2103         "    [63:32] of the PBM memory.\n";
2104     fail |= cvmx_error_add(&info);
2105
2106     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2107     info.status_addr        = CVMX_IPD_INT_SUM;
2108     info.status_mask        = 1ull<<2 /* prc_par2 */;
2109     info.enable_addr        = CVMX_IPD_INT_ENB;
2110     info.enable_mask        = 1ull<<2 /* prc_par2 */;
2111     info.flags              = 0;
2112     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2113     info.group_index        = 0;
2114     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2115     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2116     info.parent.status_mask = 1ull<<9 /* ipd */;
2117     info.func               = __cvmx_error_display;
2118     info.user_info          = (long)
2119         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2120         "    [95:64] of the PBM memory.\n";
2121     fail |= cvmx_error_add(&info);
2122
2123     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2124     info.status_addr        = CVMX_IPD_INT_SUM;
2125     info.status_mask        = 1ull<<3 /* prc_par3 */;
2126     info.enable_addr        = CVMX_IPD_INT_ENB;
2127     info.enable_mask        = 1ull<<3 /* prc_par3 */;
2128     info.flags              = 0;
2129     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2130     info.group_index        = 0;
2131     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2132     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2133     info.parent.status_mask = 1ull<<9 /* ipd */;
2134     info.func               = __cvmx_error_display;
2135     info.user_info          = (long)
2136         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2137         "    [127:96] of the PBM memory.\n";
2138     fail |= cvmx_error_add(&info);
2139
2140     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2141     info.status_addr        = CVMX_IPD_INT_SUM;
2142     info.status_mask        = 1ull<<4 /* bp_sub */;
2143     info.enable_addr        = CVMX_IPD_INT_ENB;
2144     info.enable_mask        = 1ull<<4 /* bp_sub */;
2145     info.flags              = 0;
2146     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2147     info.group_index        = 0;
2148     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2149     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2150     info.parent.status_mask = 1ull<<9 /* ipd */;
2151     info.func               = __cvmx_error_display;
2152     info.user_info          = (long)
2153         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2154         "    supplied illegal value.\n";
2155     fail |= cvmx_error_add(&info);
2156
2157     /* CVMX_POW_ECC_ERR */
2158     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2159     info.status_addr        = CVMX_POW_ECC_ERR;
2160     info.status_mask        = 1ull<<0 /* sbe */;
2161     info.enable_addr        = CVMX_POW_ECC_ERR;
2162     info.enable_mask        = 1ull<<2 /* sbe_ie */;
2163     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2164     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2165     info.group_index        = 0;
2166     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2167     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2168     info.parent.status_mask = 1ull<<12 /* pow */;
2169     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
2170     info.user_info          = (long)
2171         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2172     fail |= cvmx_error_add(&info);
2173
2174     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2175     info.status_addr        = CVMX_POW_ECC_ERR;
2176     info.status_mask        = 1ull<<1 /* dbe */;
2177     info.enable_addr        = CVMX_POW_ECC_ERR;
2178     info.enable_mask        = 1ull<<3 /* dbe_ie */;
2179     info.flags              = 0;
2180     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2181     info.group_index        = 0;
2182     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2183     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2184     info.parent.status_mask = 1ull<<12 /* pow */;
2185     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
2186     info.user_info          = (long)
2187         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2188     fail |= cvmx_error_add(&info);
2189
2190     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2191     info.status_addr        = CVMX_POW_ECC_ERR;
2192     info.status_mask        = 1ull<<12 /* rpe */;
2193     info.enable_addr        = CVMX_POW_ECC_ERR;
2194     info.enable_mask        = 1ull<<13 /* rpe_ie */;
2195     info.flags              = 0;
2196     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2197     info.group_index        = 0;
2198     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2199     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2200     info.parent.status_mask = 1ull<<12 /* pow */;
2201     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
2202     info.user_info          = (long)
2203         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2204     fail |= cvmx_error_add(&info);
2205
2206     /* CVMX_ASXX_INT_REG(0) */
2207     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2208     info.status_addr        = CVMX_ASXX_INT_REG(0);
2209     info.status_mask        = 0x7ull<<0 /* ovrflw */;
2210     info.enable_addr        = CVMX_ASXX_INT_EN(0);
2211     info.enable_mask        = 0x7ull<<0 /* ovrflw */;
2212     info.flags              = 0;
2213     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2214     info.group_index        = 0;
2215     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2216     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2217     info.parent.status_mask = 1ull<<22 /* asx0 */;
2218     info.func               = __cvmx_error_display;
2219     info.user_info          = (long)
2220         "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
2221     fail |= cvmx_error_add(&info);
2222
2223     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2224     info.status_addr        = CVMX_ASXX_INT_REG(0);
2225     info.status_mask        = 0x7ull<<4 /* txpop */;
2226     info.enable_addr        = CVMX_ASXX_INT_EN(0);
2227     info.enable_mask        = 0x7ull<<4 /* txpop */;
2228     info.flags              = 0;
2229     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2230     info.group_index        = 0;
2231     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2232     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2233     info.parent.status_mask = 1ull<<22 /* asx0 */;
2234     info.func               = __cvmx_error_display;
2235     info.user_info          = (long)
2236         "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
2237     fail |= cvmx_error_add(&info);
2238
2239     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2240     info.status_addr        = CVMX_ASXX_INT_REG(0);
2241     info.status_mask        = 0x7ull<<8 /* txpsh */;
2242     info.enable_addr        = CVMX_ASXX_INT_EN(0);
2243     info.enable_mask        = 0x7ull<<8 /* txpsh */;
2244     info.flags              = 0;
2245     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2246     info.group_index        = 0;
2247     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2248     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2249     info.parent.status_mask = 1ull<<22 /* asx0 */;
2250     info.func               = __cvmx_error_display;
2251     info.user_info          = (long)
2252         "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
2253     fail |= cvmx_error_add(&info);
2254
2255     /* CVMX_PKO_REG_ERROR */
2256     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2257     info.status_addr        = CVMX_PKO_REG_ERROR;
2258     info.status_mask        = 1ull<<0 /* parity */;
2259     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2260     info.enable_mask        = 1ull<<0 /* parity */;
2261     info.flags              = 0;
2262     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2263     info.group_index        = 0;
2264     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2265     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2266     info.parent.status_mask = 1ull<<10 /* pko */;
2267     info.func               = __cvmx_error_display;
2268     info.user_info          = (long)
2269         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
2270     fail |= cvmx_error_add(&info);
2271
2272     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2273     info.status_addr        = CVMX_PKO_REG_ERROR;
2274     info.status_mask        = 1ull<<1 /* doorbell */;
2275     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2276     info.enable_mask        = 1ull<<1 /* doorbell */;
2277     info.flags              = 0;
2278     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2279     info.group_index        = 0;
2280     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2281     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2282     info.parent.status_mask = 1ull<<10 /* pko */;
2283     info.func               = __cvmx_error_display;
2284     info.user_info          = (long)
2285         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2286     fail |= cvmx_error_add(&info);
2287
2288     /* CVMX_TIM_REG_ERROR */
2289     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2290     info.status_addr        = CVMX_TIM_REG_ERROR;
2291     info.status_mask        = 0xffffull<<0 /* mask */;
2292     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
2293     info.enable_mask        = 0xffffull<<0 /* mask */;
2294     info.flags              = 0;
2295     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2296     info.group_index        = 0;
2297     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2298     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2299     info.parent.status_mask = 1ull<<11 /* tim */;
2300     info.func               = __cvmx_error_display;
2301     info.user_info          = (long)
2302         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2303     fail |= cvmx_error_add(&info);
2304
2305     /* CVMX_ZIP_ERROR */
2306     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2307     info.status_addr        = CVMX_ZIP_ERROR;
2308     info.status_mask        = 1ull<<0 /* doorbell */;
2309     info.enable_addr        = CVMX_ZIP_INT_MASK;
2310     info.enable_mask        = 1ull<<0 /* doorbell */;
2311     info.flags              = 0;
2312     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2313     info.group_index        = 0;
2314     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2315     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2316     info.parent.status_mask = 1ull<<7 /* zip */;
2317     info.func               = __cvmx_error_display;
2318     info.user_info          = (long)
2319         "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2320     fail |= cvmx_error_add(&info);
2321
2322     /* CVMX_PIP_INT_REG */
2323     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2324     info.status_addr        = CVMX_PIP_INT_REG;
2325     info.status_mask        = 1ull<<3 /* prtnxa */;
2326     info.enable_addr        = CVMX_PIP_INT_EN;
2327     info.enable_mask        = 1ull<<3 /* prtnxa */;
2328     info.flags              = 0;
2329     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2330     info.group_index        = 0;
2331     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2332     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2333     info.parent.status_mask = 1ull<<20 /* pip */;
2334     info.func               = __cvmx_error_display;
2335     info.user_info          = (long)
2336         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
2337     fail |= cvmx_error_add(&info);
2338
2339     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2340     info.status_addr        = CVMX_PIP_INT_REG;
2341     info.status_mask        = 1ull<<4 /* badtag */;
2342     info.enable_addr        = CVMX_PIP_INT_EN;
2343     info.enable_mask        = 1ull<<4 /* badtag */;
2344     info.flags              = 0;
2345     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2346     info.group_index        = 0;
2347     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2348     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2349     info.parent.status_mask = 1ull<<20 /* pip */;
2350     info.func               = __cvmx_error_display;
2351     info.user_info          = (long)
2352         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
2353     fail |= cvmx_error_add(&info);
2354
2355     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2356     info.status_addr        = CVMX_PIP_INT_REG;
2357     info.status_mask        = 1ull<<5 /* skprunt */;
2358     info.enable_addr        = CVMX_PIP_INT_EN;
2359     info.enable_mask        = 1ull<<5 /* skprunt */;
2360     info.flags              = 0;
2361     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2362     info.group_index        = 0;
2363     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2364     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2365     info.parent.status_mask = 1ull<<20 /* pip */;
2366     info.func               = __cvmx_error_display;
2367     info.user_info          = (long)
2368         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
2369         "    This interrupt can occur with received PARTIAL\n"
2370         "    packets that are truncated to SKIP bytes or\n"
2371         "    smaller.\n";
2372     fail |= cvmx_error_add(&info);
2373
2374     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2375     info.status_addr        = CVMX_PIP_INT_REG;
2376     info.status_mask        = 1ull<<6 /* todoovr */;
2377     info.enable_addr        = CVMX_PIP_INT_EN;
2378     info.enable_mask        = 1ull<<6 /* todoovr */;
2379     info.flags              = 0;
2380     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2381     info.group_index        = 0;
2382     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2383     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2384     info.parent.status_mask = 1ull<<20 /* pip */;
2385     info.func               = __cvmx_error_display;
2386     info.user_info          = (long)
2387         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"
2388         "    (not used in O2P)\n";
2389     fail |= cvmx_error_add(&info);
2390
2391     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2392     info.status_addr        = CVMX_PIP_INT_REG;
2393     info.status_mask        = 1ull<<7 /* feperr */;
2394     info.enable_addr        = CVMX_PIP_INT_EN;
2395     info.enable_mask        = 1ull<<7 /* feperr */;
2396     info.flags              = 0;
2397     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2398     info.group_index        = 0;
2399     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2400     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2401     info.parent.status_mask = 1ull<<20 /* pip */;
2402     info.func               = __cvmx_error_display;
2403     info.user_info          = (long)
2404         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
2405     fail |= cvmx_error_add(&info);
2406
2407     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2408     info.status_addr        = CVMX_PIP_INT_REG;
2409     info.status_mask        = 1ull<<8 /* beperr */;
2410     info.enable_addr        = CVMX_PIP_INT_EN;
2411     info.enable_mask        = 1ull<<8 /* beperr */;
2412     info.flags              = 0;
2413     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2414     info.group_index        = 0;
2415     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2416     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2417     info.parent.status_mask = 1ull<<20 /* pip */;
2418     info.func               = __cvmx_error_display;
2419     info.user_info          = (long)
2420         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
2421     fail |= cvmx_error_add(&info);
2422
2423     /* CVMX_FPA_INT_SUM */
2424     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2425     info.status_addr        = CVMX_FPA_INT_SUM;
2426     info.status_mask        = 1ull<<0 /* fed0_sbe */;
2427     info.enable_addr        = CVMX_FPA_INT_ENB;
2428     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
2429     info.flags              = 0;
2430     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2431     info.group_index        = 0;
2432     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2433     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2434     info.parent.status_mask = 1ull<<5 /* fpa */;
2435     info.func               = __cvmx_error_display;
2436     info.user_info          = (long)
2437         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
2438     fail |= cvmx_error_add(&info);
2439
2440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2441     info.status_addr        = CVMX_FPA_INT_SUM;
2442     info.status_mask        = 1ull<<1 /* fed0_dbe */;
2443     info.enable_addr        = CVMX_FPA_INT_ENB;
2444     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
2445     info.flags              = 0;
2446     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2447     info.group_index        = 0;
2448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2449     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2450     info.parent.status_mask = 1ull<<5 /* fpa */;
2451     info.func               = __cvmx_error_display;
2452     info.user_info          = (long)
2453         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
2454     fail |= cvmx_error_add(&info);
2455
2456     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2457     info.status_addr        = CVMX_FPA_INT_SUM;
2458     info.status_mask        = 1ull<<2 /* fed1_sbe */;
2459     info.enable_addr        = CVMX_FPA_INT_ENB;
2460     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
2461     info.flags              = 0;
2462     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2463     info.group_index        = 0;
2464     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2465     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2466     info.parent.status_mask = 1ull<<5 /* fpa */;
2467     info.func               = __cvmx_error_display;
2468     info.user_info          = (long)
2469         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
2470     fail |= cvmx_error_add(&info);
2471
2472     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2473     info.status_addr        = CVMX_FPA_INT_SUM;
2474     info.status_mask        = 1ull<<3 /* fed1_dbe */;
2475     info.enable_addr        = CVMX_FPA_INT_ENB;
2476     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
2477     info.flags              = 0;
2478     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2479     info.group_index        = 0;
2480     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2481     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2482     info.parent.status_mask = 1ull<<5 /* fpa */;
2483     info.func               = __cvmx_error_display;
2484     info.user_info          = (long)
2485         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
2486     fail |= cvmx_error_add(&info);
2487
2488     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2489     info.status_addr        = CVMX_FPA_INT_SUM;
2490     info.status_mask        = 1ull<<4 /* q0_und */;
2491     info.enable_addr        = CVMX_FPA_INT_ENB;
2492     info.enable_mask        = 1ull<<4 /* q0_und */;
2493     info.flags              = 0;
2494     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2495     info.group_index        = 0;
2496     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2497     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2498     info.parent.status_mask = 1ull<<5 /* fpa */;
2499     info.func               = __cvmx_error_display;
2500     info.user_info          = (long)
2501         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
2502         "    negative.\n";
2503     fail |= cvmx_error_add(&info);
2504
2505     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2506     info.status_addr        = CVMX_FPA_INT_SUM;
2507     info.status_mask        = 1ull<<5 /* q0_coff */;
2508     info.enable_addr        = CVMX_FPA_INT_ENB;
2509     info.enable_mask        = 1ull<<5 /* q0_coff */;
2510     info.flags              = 0;
2511     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2512     info.group_index        = 0;
2513     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2514     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2515     info.parent.status_mask = 1ull<<5 /* fpa */;
2516     info.func               = __cvmx_error_display;
2517     info.user_info          = (long)
2518         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
2519         "    the count available is greater than pointers\n"
2520         "    present in the FPA.\n";
2521     fail |= cvmx_error_add(&info);
2522
2523     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2524     info.status_addr        = CVMX_FPA_INT_SUM;
2525     info.status_mask        = 1ull<<6 /* q0_perr */;
2526     info.enable_addr        = CVMX_FPA_INT_ENB;
2527     info.enable_mask        = 1ull<<6 /* q0_perr */;
2528     info.flags              = 0;
2529     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2530     info.group_index        = 0;
2531     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2532     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2533     info.parent.status_mask = 1ull<<5 /* fpa */;
2534     info.func               = __cvmx_error_display;
2535     info.user_info          = (long)
2536         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
2537         "    the L2C does not have the FPA owner ship bit set.\n";
2538     fail |= cvmx_error_add(&info);
2539
2540     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2541     info.status_addr        = CVMX_FPA_INT_SUM;
2542     info.status_mask        = 1ull<<7 /* q1_und */;
2543     info.enable_addr        = CVMX_FPA_INT_ENB;
2544     info.enable_mask        = 1ull<<7 /* q1_und */;
2545     info.flags              = 0;
2546     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2547     info.group_index        = 0;
2548     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2549     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2550     info.parent.status_mask = 1ull<<5 /* fpa */;
2551     info.func               = __cvmx_error_display;
2552     info.user_info          = (long)
2553         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
2554         "    negative.\n";
2555     fail |= cvmx_error_add(&info);
2556
2557     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2558     info.status_addr        = CVMX_FPA_INT_SUM;
2559     info.status_mask        = 1ull<<8 /* q1_coff */;
2560     info.enable_addr        = CVMX_FPA_INT_ENB;
2561     info.enable_mask        = 1ull<<8 /* q1_coff */;
2562     info.flags              = 0;
2563     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2564     info.group_index        = 0;
2565     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2566     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2567     info.parent.status_mask = 1ull<<5 /* fpa */;
2568     info.func               = __cvmx_error_display;
2569     info.user_info          = (long)
2570         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
2571         "    the count available is greater than pointers\n"
2572         "    present in the FPA.\n";
2573     fail |= cvmx_error_add(&info);
2574
2575     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2576     info.status_addr        = CVMX_FPA_INT_SUM;
2577     info.status_mask        = 1ull<<9 /* q1_perr */;
2578     info.enable_addr        = CVMX_FPA_INT_ENB;
2579     info.enable_mask        = 1ull<<9 /* q1_perr */;
2580     info.flags              = 0;
2581     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2582     info.group_index        = 0;
2583     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2584     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2585     info.parent.status_mask = 1ull<<5 /* fpa */;
2586     info.func               = __cvmx_error_display;
2587     info.user_info          = (long)
2588         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
2589         "    the L2C does not have the FPA owner ship bit set.\n";
2590     fail |= cvmx_error_add(&info);
2591
2592     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2593     info.status_addr        = CVMX_FPA_INT_SUM;
2594     info.status_mask        = 1ull<<10 /* q2_und */;
2595     info.enable_addr        = CVMX_FPA_INT_ENB;
2596     info.enable_mask        = 1ull<<10 /* q2_und */;
2597     info.flags              = 0;
2598     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2599     info.group_index        = 0;
2600     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2601     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2602     info.parent.status_mask = 1ull<<5 /* fpa */;
2603     info.func               = __cvmx_error_display;
2604     info.user_info          = (long)
2605         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
2606         "    negative.\n";
2607     fail |= cvmx_error_add(&info);
2608
2609     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2610     info.status_addr        = CVMX_FPA_INT_SUM;
2611     info.status_mask        = 1ull<<11 /* q2_coff */;
2612     info.enable_addr        = CVMX_FPA_INT_ENB;
2613     info.enable_mask        = 1ull<<11 /* q2_coff */;
2614     info.flags              = 0;
2615     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2616     info.group_index        = 0;
2617     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2618     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2619     info.parent.status_mask = 1ull<<5 /* fpa */;
2620     info.func               = __cvmx_error_display;
2621     info.user_info          = (long)
2622         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
2623         "    the count available is greater than than pointers\n"
2624         "    present in the FPA.\n";
2625     fail |= cvmx_error_add(&info);
2626
2627     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2628     info.status_addr        = CVMX_FPA_INT_SUM;
2629     info.status_mask        = 1ull<<12 /* q2_perr */;
2630     info.enable_addr        = CVMX_FPA_INT_ENB;
2631     info.enable_mask        = 1ull<<12 /* q2_perr */;
2632     info.flags              = 0;
2633     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2634     info.group_index        = 0;
2635     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2636     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2637     info.parent.status_mask = 1ull<<5 /* fpa */;
2638     info.func               = __cvmx_error_display;
2639     info.user_info          = (long)
2640         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
2641         "    the L2C does not have the FPA owner ship bit set.\n";
2642     fail |= cvmx_error_add(&info);
2643
2644     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2645     info.status_addr        = CVMX_FPA_INT_SUM;
2646     info.status_mask        = 1ull<<13 /* q3_und */;
2647     info.enable_addr        = CVMX_FPA_INT_ENB;
2648     info.enable_mask        = 1ull<<13 /* q3_und */;
2649     info.flags              = 0;
2650     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2651     info.group_index        = 0;
2652     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2653     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2654     info.parent.status_mask = 1ull<<5 /* fpa */;
2655     info.func               = __cvmx_error_display;
2656     info.user_info          = (long)
2657         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
2658         "    negative.\n";
2659     fail |= cvmx_error_add(&info);
2660
2661     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2662     info.status_addr        = CVMX_FPA_INT_SUM;
2663     info.status_mask        = 1ull<<14 /* q3_coff */;
2664     info.enable_addr        = CVMX_FPA_INT_ENB;
2665     info.enable_mask        = 1ull<<14 /* q3_coff */;
2666     info.flags              = 0;
2667     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2668     info.group_index        = 0;
2669     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2670     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2671     info.parent.status_mask = 1ull<<5 /* fpa */;
2672     info.func               = __cvmx_error_display;
2673     info.user_info          = (long)
2674         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
2675         "    the count available is greater than than pointers\n"
2676         "    present in the FPA.\n";
2677     fail |= cvmx_error_add(&info);
2678
2679     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2680     info.status_addr        = CVMX_FPA_INT_SUM;
2681     info.status_mask        = 1ull<<15 /* q3_perr */;
2682     info.enable_addr        = CVMX_FPA_INT_ENB;
2683     info.enable_mask        = 1ull<<15 /* q3_perr */;
2684     info.flags              = 0;
2685     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2686     info.group_index        = 0;
2687     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2688     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2689     info.parent.status_mask = 1ull<<5 /* fpa */;
2690     info.func               = __cvmx_error_display;
2691     info.user_info          = (long)
2692         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
2693         "    the L2C does not have the FPA owner ship bit set.\n";
2694     fail |= cvmx_error_add(&info);
2695
2696     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2697     info.status_addr        = CVMX_FPA_INT_SUM;
2698     info.status_mask        = 1ull<<16 /* q4_und */;
2699     info.enable_addr        = CVMX_FPA_INT_ENB;
2700     info.enable_mask        = 1ull<<16 /* q4_und */;
2701     info.flags              = 0;
2702     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2703     info.group_index        = 0;
2704     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2705     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2706     info.parent.status_mask = 1ull<<5 /* fpa */;
2707     info.func               = __cvmx_error_display;
2708     info.user_info          = (long)
2709         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
2710         "    negative.\n";
2711     fail |= cvmx_error_add(&info);
2712
2713     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2714     info.status_addr        = CVMX_FPA_INT_SUM;
2715     info.status_mask        = 1ull<<17 /* q4_coff */;
2716     info.enable_addr        = CVMX_FPA_INT_ENB;
2717     info.enable_mask        = 1ull<<17 /* q4_coff */;
2718     info.flags              = 0;
2719     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2720     info.group_index        = 0;
2721     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2722     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2723     info.parent.status_mask = 1ull<<5 /* fpa */;
2724     info.func               = __cvmx_error_display;
2725     info.user_info          = (long)
2726         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
2727         "    the count available is greater than than pointers\n"
2728         "    present in the FPA.\n";
2729     fail |= cvmx_error_add(&info);
2730
2731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2732     info.status_addr        = CVMX_FPA_INT_SUM;
2733     info.status_mask        = 1ull<<18 /* q4_perr */;
2734     info.enable_addr        = CVMX_FPA_INT_ENB;
2735     info.enable_mask        = 1ull<<18 /* q4_perr */;
2736     info.flags              = 0;
2737     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2738     info.group_index        = 0;
2739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2740     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2741     info.parent.status_mask = 1ull<<5 /* fpa */;
2742     info.func               = __cvmx_error_display;
2743     info.user_info          = (long)
2744         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
2745         "    the L2C does not have the FPA owner ship bit set.\n";
2746     fail |= cvmx_error_add(&info);
2747
2748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2749     info.status_addr        = CVMX_FPA_INT_SUM;
2750     info.status_mask        = 1ull<<19 /* q5_und */;
2751     info.enable_addr        = CVMX_FPA_INT_ENB;
2752     info.enable_mask        = 1ull<<19 /* q5_und */;
2753     info.flags              = 0;
2754     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2755     info.group_index        = 0;
2756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2757     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2758     info.parent.status_mask = 1ull<<5 /* fpa */;
2759     info.func               = __cvmx_error_display;
2760     info.user_info          = (long)
2761         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
2762         "    negative.\n";
2763     fail |= cvmx_error_add(&info);
2764
2765     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2766     info.status_addr        = CVMX_FPA_INT_SUM;
2767     info.status_mask        = 1ull<<20 /* q5_coff */;
2768     info.enable_addr        = CVMX_FPA_INT_ENB;
2769     info.enable_mask        = 1ull<<20 /* q5_coff */;
2770     info.flags              = 0;
2771     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2772     info.group_index        = 0;
2773     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2774     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2775     info.parent.status_mask = 1ull<<5 /* fpa */;
2776     info.func               = __cvmx_error_display;
2777     info.user_info          = (long)
2778         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
2779         "    the count available is greater than than pointers\n"
2780         "    present in the FPA.\n";
2781     fail |= cvmx_error_add(&info);
2782
2783     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2784     info.status_addr        = CVMX_FPA_INT_SUM;
2785     info.status_mask        = 1ull<<21 /* q5_perr */;
2786     info.enable_addr        = CVMX_FPA_INT_ENB;
2787     info.enable_mask        = 1ull<<21 /* q5_perr */;
2788     info.flags              = 0;
2789     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2790     info.group_index        = 0;
2791     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2792     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2793     info.parent.status_mask = 1ull<<5 /* fpa */;
2794     info.func               = __cvmx_error_display;
2795     info.user_info          = (long)
2796         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
2797         "    the L2C does not have the FPA owner ship bit set.\n";
2798     fail |= cvmx_error_add(&info);
2799
2800     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2801     info.status_addr        = CVMX_FPA_INT_SUM;
2802     info.status_mask        = 1ull<<22 /* q6_und */;
2803     info.enable_addr        = CVMX_FPA_INT_ENB;
2804     info.enable_mask        = 1ull<<22 /* q6_und */;
2805     info.flags              = 0;
2806     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2807     info.group_index        = 0;
2808     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2809     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2810     info.parent.status_mask = 1ull<<5 /* fpa */;
2811     info.func               = __cvmx_error_display;
2812     info.user_info          = (long)
2813         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
2814         "    negative.\n";
2815     fail |= cvmx_error_add(&info);
2816
2817     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2818     info.status_addr        = CVMX_FPA_INT_SUM;
2819     info.status_mask        = 1ull<<23 /* q6_coff */;
2820     info.enable_addr        = CVMX_FPA_INT_ENB;
2821     info.enable_mask        = 1ull<<23 /* q6_coff */;
2822     info.flags              = 0;
2823     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2824     info.group_index        = 0;
2825     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2826     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2827     info.parent.status_mask = 1ull<<5 /* fpa */;
2828     info.func               = __cvmx_error_display;
2829     info.user_info          = (long)
2830         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
2831         "    the count available is greater than than pointers\n"
2832         "    present in the FPA.\n";
2833     fail |= cvmx_error_add(&info);
2834
2835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2836     info.status_addr        = CVMX_FPA_INT_SUM;
2837     info.status_mask        = 1ull<<24 /* q6_perr */;
2838     info.enable_addr        = CVMX_FPA_INT_ENB;
2839     info.enable_mask        = 1ull<<24 /* q6_perr */;
2840     info.flags              = 0;
2841     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2842     info.group_index        = 0;
2843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2844     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2845     info.parent.status_mask = 1ull<<5 /* fpa */;
2846     info.func               = __cvmx_error_display;
2847     info.user_info          = (long)
2848         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
2849         "    the L2C does not have the FPA owner ship bit set.\n";
2850     fail |= cvmx_error_add(&info);
2851
2852     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2853     info.status_addr        = CVMX_FPA_INT_SUM;
2854     info.status_mask        = 1ull<<25 /* q7_und */;
2855     info.enable_addr        = CVMX_FPA_INT_ENB;
2856     info.enable_mask        = 1ull<<25 /* q7_und */;
2857     info.flags              = 0;
2858     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2859     info.group_index        = 0;
2860     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2861     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2862     info.parent.status_mask = 1ull<<5 /* fpa */;
2863     info.func               = __cvmx_error_display;
2864     info.user_info          = (long)
2865         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
2866         "    negative.\n";
2867     fail |= cvmx_error_add(&info);
2868
2869     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2870     info.status_addr        = CVMX_FPA_INT_SUM;
2871     info.status_mask        = 1ull<<26 /* q7_coff */;
2872     info.enable_addr        = CVMX_FPA_INT_ENB;
2873     info.enable_mask        = 1ull<<26 /* q7_coff */;
2874     info.flags              = 0;
2875     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2876     info.group_index        = 0;
2877     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2878     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2879     info.parent.status_mask = 1ull<<5 /* fpa */;
2880     info.func               = __cvmx_error_display;
2881     info.user_info          = (long)
2882         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
2883         "    the count available is greater than than pointers\n"
2884         "    present in the FPA.\n";
2885     fail |= cvmx_error_add(&info);
2886
2887     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2888     info.status_addr        = CVMX_FPA_INT_SUM;
2889     info.status_mask        = 1ull<<27 /* q7_perr */;
2890     info.enable_addr        = CVMX_FPA_INT_ENB;
2891     info.enable_mask        = 1ull<<27 /* q7_perr */;
2892     info.flags              = 0;
2893     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2894     info.group_index        = 0;
2895     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2896     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2897     info.parent.status_mask = 1ull<<5 /* fpa */;
2898     info.func               = __cvmx_error_display;
2899     info.user_info          = (long)
2900         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
2901         "    the L2C does not have the FPA owner ship bit set.\n";
2902     fail |= cvmx_error_add(&info);
2903
2904     /* CVMX_LMCX_MEM_CFG0(0) */
2905     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2906     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
2907     info.status_mask        = 0xfull<<21 /* sec_err */;
2908     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
2909     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
2910     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2911     info.group              = CVMX_ERROR_GROUP_LMC;
2912     info.group_index        = 0;
2913     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2914     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2915     info.parent.status_mask = 1ull<<17 /* lmc */;
2916     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
2917     info.user_info          = (long)
2918         "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
2919         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
2920         "    [0] corresponds to DQ[63:0]_c0_p0\n"
2921         "    [1] corresponds to DQ[63:0]_c0_p1\n"
2922         "    [2] corresponds to DQ[63:0]_c1_p0\n"
2923         "    [3] corresponds to DQ[63:0]_c1_p1\n"
2924         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
2925         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
2926         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
2927         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
2928         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
2929         "      where _cC_pP denotes cycle C and phase P\n"
2930         "    Write of 1 will clear the corresponding error bit\n";
2931     fail |= cvmx_error_add(&info);
2932
2933     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2934     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
2935     info.status_mask        = 0xfull<<25 /* ded_err */;
2936     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
2937     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
2938     info.flags              = 0;
2939     info.group              = CVMX_ERROR_GROUP_LMC;
2940     info.group_index        = 0;
2941     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2942     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2943     info.parent.status_mask = 1ull<<17 /* lmc */;
2944     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
2945     info.user_info          = (long)
2946         "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
2947         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
2948         "    [0] corresponds to DQ[63:0]_c0_p0\n"
2949         "    [1] corresponds to DQ[63:0]_c0_p1\n"
2950         "    [2] corresponds to DQ[63:0]_c1_p0\n"
2951         "    [3] corresponds to DQ[63:0]_c1_p1\n"
2952         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
2953         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
2954         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
2955         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
2956         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
2957         "      where _cC_pP denotes cycle C and phase P\n"
2958         "    Write of 1 will clear the corresponding error bit\n";
2959     fail |= cvmx_error_add(&info);
2960
2961     /* CVMX_DFA_ERR */
2962     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2963     info.status_addr        = CVMX_DFA_ERR;
2964     info.status_mask        = 1ull<<1 /* cp2sbe */;
2965     info.enable_addr        = 0;
2966     info.enable_mask        = 0;
2967     info.flags              = 0;
2968     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2969     info.group_index        = 0;
2970     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2971     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2972     info.parent.status_mask = 1ull<<6 /* dfa */;
2973     info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
2974     info.user_info          = (long)
2975         "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
2976         "    When set, a single bit error had been detected and\n"
2977         "    corrected for a PP-generated QW Mode read\n"
2978         "    transaction.\n"
2979         "    If the CP2DBE=0, then the CP2SYN contains the\n"
2980         "    failing syndrome (used during correction).\n"
2981         "    Refer to CP2ECCENA.\n"
2982         "    If the CP2SBINA had previously been enabled(set),\n"
2983         "    an interrupt will be posted. Software can clear\n"
2984         "    the interrupt by writing a 1 to this register bit.\n"
2985         "    See also: DFA_MEMFADR CSR which contains more data\n"
2986         "    about the memory address/control to help isolate\n"
2987         "    the failure.\n"
2988         "    NOTE: PP-generated LW Mode Read transactions\n"
2989         "    do not participate in ECC check/correct).\n";
2990     fail |= cvmx_error_add(&info);
2991
2992     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2993     info.status_addr        = CVMX_DFA_ERR;
2994     info.status_mask        = 1ull<<2 /* cp2dbe */;
2995     info.enable_addr        = 0;
2996     info.enable_mask        = 0;
2997     info.flags              = 0;
2998     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2999     info.group_index        = 0;
3000     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3001     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3002     info.parent.status_mask = 1ull<<6 /* dfa */;
3003     info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
3004     info.user_info          = (long)
3005         "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
3006         "    When set, a double bit error had been detected\n"
3007         "    for a PP-generated QW Mode read transaction.\n"
3008         "    The CP2SYN contains the failing syndrome.\n"
3009         "     NOTE: PP-generated LW Mode Read transactions\n"
3010         "    do not participate in ECC check/correct).\n"
3011         "    Refer to CP2ECCENA.\n"
3012         "    If the CP2DBINA had previously been enabled(set),\n"
3013         "    an interrupt will be posted. Software can clear\n"
3014         "    the interrupt by writing a 1 to this register bit.\n"
3015         "    See also: DFA_MEMFADR CSR which contains more data\n"
3016         "    about the memory address/control to help isolate\n"
3017         "    the failure.\n";
3018     fail |= cvmx_error_add(&info);
3019
3020     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3021     info.status_addr        = CVMX_DFA_ERR;
3022     info.status_mask        = 1ull<<14 /* dtesbe */;
3023     info.enable_addr        = 0;
3024     info.enable_mask        = 0;
3025     info.flags              = 0;
3026     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3027     info.group_index        = 0;
3028     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3029     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3030     info.parent.status_mask = 1ull<<6 /* dfa */;
3031     info.func               = __cvmx_error_handle_dfa_err_dtesbe;
3032     info.user_info          = (long)
3033         "ERROR DFA_ERR[DTESBE]: DTE 25b Single Bit Error Corrected - Status bit\n"
3034         "    When set, a single bit error had been detected and\n"
3035         "    corrected for a DTE-generated 32b SIMPLE Mode read\n"
3036         "    transaction.\n"
3037         "    If the DTEDBE=0, then the DTESYN contains the\n"
3038         "    failing syndrome (used during correction).\n"
3039         "    NOTE: DTE-generated 16b SIMPLE Mode Read\n"
3040         "    transactions do not participate in ECC check/correct).\n"
3041         "    If the DTESBINA had previously been enabled(set),\n"
3042         "    an interrupt will be posted. Software can clear\n"
3043         "    the interrupt by writing a 1 to this register bit.\n"
3044         "    See also: DFA_MEMFADR CSR which contains more data\n"
3045         "    about the memory address/control to help isolate\n"
3046         "    the failure.\n";
3047     fail |= cvmx_error_add(&info);
3048
3049     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3050     info.status_addr        = CVMX_DFA_ERR;
3051     info.status_mask        = 1ull<<15 /* dtedbe */;
3052     info.enable_addr        = 0;
3053     info.enable_mask        = 0;
3054     info.flags              = 0;
3055     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3056     info.group_index        = 0;
3057     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3058     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3059     info.parent.status_mask = 1ull<<6 /* dfa */;
3060     info.func               = __cvmx_error_handle_dfa_err_dtedbe;
3061     info.user_info          = (long)
3062         "ERROR DFA_ERR[DTEDBE]: DTE 25b Double Bit Error Detected - Status bit\n"
3063         "    When set, a double bit error had been detected\n"
3064         "    for a DTE-generated 32b SIMPLE Mode read transaction.\n"
3065         "    The DTESYN contains the failing syndrome.\n"
3066         "    If the DTEDBINA had previously been enabled(set),\n"
3067         "    an interrupt will be posted. Software can clear\n"
3068         "    the interrupt by writing a 1 to this register bit.\n"
3069         "    See also: DFA_MEMFADR CSR which contains more data\n"
3070         "    about the memory address/control to help isolate\n"
3071         "    the failure.\n"
3072         "    NOTE: DTE-generated 16b SIMPLE Mode Read transactions\n"
3073         "    do not participate in ECC check/correct).\n";
3074     fail |= cvmx_error_add(&info);
3075
3076     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3077     info.status_addr        = CVMX_DFA_ERR;
3078     info.status_mask        = 1ull<<26 /* dteperr */;
3079     info.enable_addr        = 0;
3080     info.enable_mask        = 0;
3081     info.flags              = 0;
3082     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3083     info.group_index        = 0;
3084     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3085     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3086     info.parent.status_mask = 1ull<<6 /* dfa */;
3087     info.func               = __cvmx_error_handle_dfa_err_dteperr;
3088     info.user_info          = (long)
3089         "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 16b SIMPLE mode ONLY)\n"
3090         "    When set, all DTE-generated 16b SIMPLE Mode read\n"
3091         "    transactions which encounter a parity error (across\n"
3092         "    the 17b of data) are reported.\n";
3093     fail |= cvmx_error_add(&info);
3094
3095     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3096     info.status_addr        = CVMX_DFA_ERR;
3097     info.status_mask        = 1ull<<29 /* cp2perr */;
3098     info.enable_addr        = 0;
3099     info.enable_mask        = 0;
3100     info.flags              = 0;
3101     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3102     info.group_index        = 0;
3103     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3104     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3105     info.parent.status_mask = 1ull<<6 /* dfa */;
3106     info.func               = __cvmx_error_handle_dfa_err_cp2perr;
3107     info.user_info          = (long)
3108         "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
3109         "    When set, a parity error had been detected for a\n"
3110         "    PP-generated LW Mode read transaction.\n"
3111         "    If the CP2PINA had previously been enabled(set),\n"
3112         "    an interrupt will be posted. Software can clear\n"
3113         "    the interrupt by writing a 1 to this register bit.\n"
3114         "    See also: DFA_MEMFADR CSR which contains more data\n"
3115         "    about the memory address/control to help isolate\n"
3116         "    the failure.\n";
3117     fail |= cvmx_error_add(&info);
3118
3119     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3120     info.status_addr        = CVMX_DFA_ERR;
3121     info.status_mask        = 1ull<<31 /* dblovf */;
3122     info.enable_addr        = 0;
3123     info.enable_mask        = 0;
3124     info.flags              = 0;
3125     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3126     info.group_index        = 0;
3127     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3128     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3129     info.parent.status_mask = 1ull<<6 /* dfa */;
3130     info.func               = __cvmx_error_handle_dfa_err_dblovf;
3131     info.user_info          = (long)
3132         "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
3133         "    When set, the 20b accumulated doorbell register\n"
3134         "    had overflowed (SW wrote too many doorbell requests).\n"
3135         "    If the DBLINA had previously been enabled(set),\n"
3136         "    an interrupt will be posted. Software can clear\n"
3137         "    the interrupt by writing a 1 to this register bit.\n"
3138         "    NOTE: Detection of a Doorbell Register overflow\n"
3139         "    is a catastrophic error which may leave the DFA\n"
3140         "    HW in an unrecoverable state.\n";
3141     fail |= cvmx_error_add(&info);
3142
3143     /* CVMX_IOB_INT_SUM */
3144     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3145     info.status_addr        = CVMX_IOB_INT_SUM;
3146     info.status_mask        = 1ull<<0 /* np_sop */;
3147     info.enable_addr        = CVMX_IOB_INT_ENB;
3148     info.enable_mask        = 1ull<<0 /* np_sop */;
3149     info.flags              = 0;
3150     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3151     info.group_index        = 0;
3152     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3153     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3154     info.parent.status_mask = 1ull<<30 /* iob */;
3155     info.func               = __cvmx_error_display;
3156     info.user_info          = (long)
3157         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
3158         "    port for a non-passthrough packet.\n"
3159         "    The first detected error associated with bits [3:0]\n"
3160         "    of this register will only be set here. A new bit\n"
3161         "    can be set when the previous reported bit is cleared.\n";
3162     fail |= cvmx_error_add(&info);
3163
3164     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3165     info.status_addr        = CVMX_IOB_INT_SUM;
3166     info.status_mask        = 1ull<<1 /* np_eop */;
3167     info.enable_addr        = CVMX_IOB_INT_ENB;
3168     info.enable_mask        = 1ull<<1 /* np_eop */;
3169     info.flags              = 0;
3170     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3171     info.group_index        = 0;
3172     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3173     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3174     info.parent.status_mask = 1ull<<30 /* iob */;
3175     info.func               = __cvmx_error_display;
3176     info.user_info          = (long)
3177         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
3178         "    port for a non-passthrough packet.\n"
3179         "    The first detected error associated with bits [3:0]\n"
3180         "    of this register will only be set here. A new bit\n"
3181         "    can be set when the previous reported bit is cleared.\n";
3182     fail |= cvmx_error_add(&info);
3183
3184     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3185     info.status_addr        = CVMX_IOB_INT_SUM;
3186     info.status_mask        = 1ull<<2 /* p_sop */;
3187     info.enable_addr        = CVMX_IOB_INT_ENB;
3188     info.enable_mask        = 1ull<<2 /* p_sop */;
3189     info.flags              = 0;
3190     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3191     info.group_index        = 0;
3192     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3193     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3194     info.parent.status_mask = 1ull<<30 /* iob */;
3195     info.func               = __cvmx_error_display;
3196     info.user_info          = (long)
3197         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
3198         "    port for a passthrough packet.\n"
3199         "    The first detected error associated with bits [3:0]\n"
3200         "    of this register will only be set here. A new bit\n"
3201         "    can be set when the previous reported bit is cleared.\n";
3202     fail |= cvmx_error_add(&info);
3203
3204     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3205     info.status_addr        = CVMX_IOB_INT_SUM;
3206     info.status_mask        = 1ull<<3 /* p_eop */;
3207     info.enable_addr        = CVMX_IOB_INT_ENB;
3208     info.enable_mask        = 1ull<<3 /* p_eop */;
3209     info.flags              = 0;
3210     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3211     info.group_index        = 0;
3212     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3213     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3214     info.parent.status_mask = 1ull<<30 /* iob */;
3215     info.func               = __cvmx_error_display;
3216     info.user_info          = (long)
3217         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
3218         "    port for a passthrough packet.\n"
3219         "    The first detected error associated with bits [3:0]\n"
3220         "    of this register will only be set here. A new bit\n"
3221         "    can be set when the previous reported bit is cleared.\n";
3222     fail |= cvmx_error_add(&info);
3223
3224     /* CVMX_USBNX_INT_SUM(0) */
3225     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3226     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3227     info.status_mask        = 1ull<<0 /* pr_po_e */;
3228     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3229     info.enable_mask        = 1ull<<0 /* pr_po_e */;
3230     info.flags              = 0;
3231     info.group              = CVMX_ERROR_GROUP_USB;
3232     info.group_index        = 0;
3233     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3234     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3235     info.parent.status_mask = 1ull<<13 /* usb */;
3236     info.func               = __cvmx_error_display;
3237     info.user_info          = (long)
3238         "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
3239     fail |= cvmx_error_add(&info);
3240
3241     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3242     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3243     info.status_mask        = 1ull<<1 /* pr_pu_f */;
3244     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3245     info.enable_mask        = 1ull<<1 /* pr_pu_f */;
3246     info.flags              = 0;
3247     info.group              = CVMX_ERROR_GROUP_USB;
3248     info.group_index        = 0;
3249     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3250     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3251     info.parent.status_mask = 1ull<<13 /* usb */;
3252     info.func               = __cvmx_error_display;
3253     info.user_info          = (long)
3254         "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
3255     fail |= cvmx_error_add(&info);
3256
3257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3258     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3259     info.status_mask        = 1ull<<2 /* nr_po_e */;
3260     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3261     info.enable_mask        = 1ull<<2 /* nr_po_e */;
3262     info.flags              = 0;
3263     info.group              = CVMX_ERROR_GROUP_USB;
3264     info.group_index        = 0;
3265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3266     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3267     info.parent.status_mask = 1ull<<13 /* usb */;
3268     info.func               = __cvmx_error_display;
3269     info.user_info          = (long)
3270         "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
3271     fail |= cvmx_error_add(&info);
3272
3273     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3274     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3275     info.status_mask        = 1ull<<3 /* nr_pu_f */;
3276     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3277     info.enable_mask        = 1ull<<3 /* nr_pu_f */;
3278     info.flags              = 0;
3279     info.group              = CVMX_ERROR_GROUP_USB;
3280     info.group_index        = 0;
3281     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3282     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3283     info.parent.status_mask = 1ull<<13 /* usb */;
3284     info.func               = __cvmx_error_display;
3285     info.user_info          = (long)
3286         "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
3287     fail |= cvmx_error_add(&info);
3288
3289     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3290     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3291     info.status_mask        = 1ull<<4 /* lr_po_e */;
3292     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3293     info.enable_mask        = 1ull<<4 /* lr_po_e */;
3294     info.flags              = 0;
3295     info.group              = CVMX_ERROR_GROUP_USB;
3296     info.group_index        = 0;
3297     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3298     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3299     info.parent.status_mask = 1ull<<13 /* usb */;
3300     info.func               = __cvmx_error_display;
3301     info.user_info          = (long)
3302         "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
3303     fail |= cvmx_error_add(&info);
3304
3305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3306     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3307     info.status_mask        = 1ull<<5 /* lr_pu_f */;
3308     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3309     info.enable_mask        = 1ull<<5 /* lr_pu_f */;
3310     info.flags              = 0;
3311     info.group              = CVMX_ERROR_GROUP_USB;
3312     info.group_index        = 0;
3313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3314     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3315     info.parent.status_mask = 1ull<<13 /* usb */;
3316     info.func               = __cvmx_error_display;
3317     info.user_info          = (long)
3318         "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
3319     fail |= cvmx_error_add(&info);
3320
3321     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3322     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3323     info.status_mask        = 1ull<<6 /* pt_po_e */;
3324     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3325     info.enable_mask        = 1ull<<6 /* pt_po_e */;
3326     info.flags              = 0;
3327     info.group              = CVMX_ERROR_GROUP_USB;
3328     info.group_index        = 0;
3329     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3330     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3331     info.parent.status_mask = 1ull<<13 /* usb */;
3332     info.func               = __cvmx_error_display;
3333     info.user_info          = (long)
3334         "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
3335     fail |= cvmx_error_add(&info);
3336
3337     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3338     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3339     info.status_mask        = 1ull<<7 /* pt_pu_f */;
3340     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3341     info.enable_mask        = 1ull<<7 /* pt_pu_f */;
3342     info.flags              = 0;
3343     info.group              = CVMX_ERROR_GROUP_USB;
3344     info.group_index        = 0;
3345     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3346     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3347     info.parent.status_mask = 1ull<<13 /* usb */;
3348     info.func               = __cvmx_error_display;
3349     info.user_info          = (long)
3350         "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
3351     fail |= cvmx_error_add(&info);
3352
3353     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3354     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3355     info.status_mask        = 1ull<<8 /* nt_po_e */;
3356     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3357     info.enable_mask        = 1ull<<8 /* nt_po_e */;
3358     info.flags              = 0;
3359     info.group              = CVMX_ERROR_GROUP_USB;
3360     info.group_index        = 0;
3361     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3362     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3363     info.parent.status_mask = 1ull<<13 /* usb */;
3364     info.func               = __cvmx_error_display;
3365     info.user_info          = (long)
3366         "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
3367     fail |= cvmx_error_add(&info);
3368
3369     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3370     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3371     info.status_mask        = 1ull<<9 /* nt_pu_f */;
3372     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3373     info.enable_mask        = 1ull<<9 /* nt_pu_f */;
3374     info.flags              = 0;
3375     info.group              = CVMX_ERROR_GROUP_USB;
3376     info.group_index        = 0;
3377     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3378     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3379     info.parent.status_mask = 1ull<<13 /* usb */;
3380     info.func               = __cvmx_error_display;
3381     info.user_info          = (long)
3382         "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
3383     fail |= cvmx_error_add(&info);
3384
3385     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3386     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3387     info.status_mask        = 1ull<<10 /* lt_po_e */;
3388     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3389     info.enable_mask        = 1ull<<10 /* lt_po_e */;
3390     info.flags              = 0;
3391     info.group              = CVMX_ERROR_GROUP_USB;
3392     info.group_index        = 0;
3393     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3394     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3395     info.parent.status_mask = 1ull<<13 /* usb */;
3396     info.func               = __cvmx_error_display;
3397     info.user_info          = (long)
3398         "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
3399     fail |= cvmx_error_add(&info);
3400
3401     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3402     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3403     info.status_mask        = 1ull<<11 /* lt_pu_f */;
3404     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3405     info.enable_mask        = 1ull<<11 /* lt_pu_f */;
3406     info.flags              = 0;
3407     info.group              = CVMX_ERROR_GROUP_USB;
3408     info.group_index        = 0;
3409     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3410     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3411     info.parent.status_mask = 1ull<<13 /* usb */;
3412     info.func               = __cvmx_error_display;
3413     info.user_info          = (long)
3414         "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
3415     fail |= cvmx_error_add(&info);
3416
3417     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3418     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3419     info.status_mask        = 1ull<<12 /* dcred_e */;
3420     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3421     info.enable_mask        = 1ull<<12 /* dcred_e */;
3422     info.flags              = 0;
3423     info.group              = CVMX_ERROR_GROUP_USB;
3424     info.group_index        = 0;
3425     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3426     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3427     info.parent.status_mask = 1ull<<13 /* usb */;
3428     info.func               = __cvmx_error_display;
3429     info.user_info          = (long)
3430         "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
3431     fail |= cvmx_error_add(&info);
3432
3433     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3434     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3435     info.status_mask        = 1ull<<13 /* dcred_f */;
3436     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3437     info.enable_mask        = 1ull<<13 /* dcred_f */;
3438     info.flags              = 0;
3439     info.group              = CVMX_ERROR_GROUP_USB;
3440     info.group_index        = 0;
3441     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3442     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3443     info.parent.status_mask = 1ull<<13 /* usb */;
3444     info.func               = __cvmx_error_display;
3445     info.user_info          = (long)
3446         "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
3447     fail |= cvmx_error_add(&info);
3448
3449     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3450     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3451     info.status_mask        = 1ull<<14 /* l2c_s_e */;
3452     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3453     info.enable_mask        = 1ull<<14 /* l2c_s_e */;
3454     info.flags              = 0;
3455     info.group              = CVMX_ERROR_GROUP_USB;
3456     info.group_index        = 0;
3457     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3458     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3459     info.parent.status_mask = 1ull<<13 /* usb */;
3460     info.func               = __cvmx_error_display;
3461     info.user_info          = (long)
3462         "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
3463     fail |= cvmx_error_add(&info);
3464
3465     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3466     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3467     info.status_mask        = 1ull<<15 /* l2c_a_f */;
3468     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3469     info.enable_mask        = 1ull<<15 /* l2c_a_f */;
3470     info.flags              = 0;
3471     info.group              = CVMX_ERROR_GROUP_USB;
3472     info.group_index        = 0;
3473     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3474     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3475     info.parent.status_mask = 1ull<<13 /* usb */;
3476     info.func               = __cvmx_error_display;
3477     info.user_info          = (long)
3478         "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
3479     fail |= cvmx_error_add(&info);
3480
3481     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3482     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3483     info.status_mask        = 1ull<<16 /* lt_fi_e */;
3484     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3485     info.enable_mask        = 1ull<<16 /* l2_fi_e */;
3486     info.flags              = 0;
3487     info.group              = CVMX_ERROR_GROUP_USB;
3488     info.group_index        = 0;
3489     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3490     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3491     info.parent.status_mask = 1ull<<13 /* usb */;
3492     info.func               = __cvmx_error_display;
3493     info.user_info          = (long)
3494         "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
3495     fail |= cvmx_error_add(&info);
3496
3497     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3498     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3499     info.status_mask        = 1ull<<17 /* lt_fi_f */;
3500     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3501     info.enable_mask        = 1ull<<17 /* l2_fi_f */;
3502     info.flags              = 0;
3503     info.group              = CVMX_ERROR_GROUP_USB;
3504     info.group_index        = 0;
3505     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3506     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3507     info.parent.status_mask = 1ull<<13 /* usb */;
3508     info.func               = __cvmx_error_display;
3509     info.user_info          = (long)
3510         "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
3511     fail |= cvmx_error_add(&info);
3512
3513     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3514     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3515     info.status_mask        = 1ull<<18 /* rg_fi_e */;
3516     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3517     info.enable_mask        = 1ull<<18 /* rg_fi_e */;
3518     info.flags              = 0;
3519     info.group              = CVMX_ERROR_GROUP_USB;
3520     info.group_index        = 0;
3521     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3522     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3523     info.parent.status_mask = 1ull<<13 /* usb */;
3524     info.func               = __cvmx_error_display;
3525     info.user_info          = (long)
3526         "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
3527     fail |= cvmx_error_add(&info);
3528
3529     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3530     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3531     info.status_mask        = 1ull<<19 /* rg_fi_f */;
3532     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3533     info.enable_mask        = 1ull<<19 /* rg_fi_f */;
3534     info.flags              = 0;
3535     info.group              = CVMX_ERROR_GROUP_USB;
3536     info.group_index        = 0;
3537     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3538     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3539     info.parent.status_mask = 1ull<<13 /* usb */;
3540     info.func               = __cvmx_error_display;
3541     info.user_info          = (long)
3542         "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
3543     fail |= cvmx_error_add(&info);
3544
3545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3546     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3547     info.status_mask        = 1ull<<20 /* rq_q2_f */;
3548     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3549     info.enable_mask        = 1ull<<20 /* rq_q2_f */;
3550     info.flags              = 0;
3551     info.group              = CVMX_ERROR_GROUP_USB;
3552     info.group_index        = 0;
3553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3554     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3555     info.parent.status_mask = 1ull<<13 /* usb */;
3556     info.func               = __cvmx_error_display;
3557     info.user_info          = (long)
3558         "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
3559     fail |= cvmx_error_add(&info);
3560
3561     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3562     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3563     info.status_mask        = 1ull<<21 /* rq_q2_e */;
3564     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3565     info.enable_mask        = 1ull<<21 /* rq_q2_e */;
3566     info.flags              = 0;
3567     info.group              = CVMX_ERROR_GROUP_USB;
3568     info.group_index        = 0;
3569     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3570     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3571     info.parent.status_mask = 1ull<<13 /* usb */;
3572     info.func               = __cvmx_error_display;
3573     info.user_info          = (long)
3574         "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
3575     fail |= cvmx_error_add(&info);
3576
3577     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3578     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3579     info.status_mask        = 1ull<<22 /* rq_q3_f */;
3580     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3581     info.enable_mask        = 1ull<<22 /* rq_q3_f */;
3582     info.flags              = 0;
3583     info.group              = CVMX_ERROR_GROUP_USB;
3584     info.group_index        = 0;
3585     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3586     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3587     info.parent.status_mask = 1ull<<13 /* usb */;
3588     info.func               = __cvmx_error_display;
3589     info.user_info          = (long)
3590         "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
3591     fail |= cvmx_error_add(&info);
3592
3593     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3594     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3595     info.status_mask        = 1ull<<23 /* rq_q3_e */;
3596     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3597     info.enable_mask        = 1ull<<23 /* rq_q3_e */;
3598     info.flags              = 0;
3599     info.group              = CVMX_ERROR_GROUP_USB;
3600     info.group_index        = 0;
3601     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3602     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3603     info.parent.status_mask = 1ull<<13 /* usb */;
3604     info.func               = __cvmx_error_display;
3605     info.user_info          = (long)
3606         "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
3607     fail |= cvmx_error_add(&info);
3608
3609     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3610     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3611     info.status_mask        = 1ull<<24 /* uod_pe */;
3612     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3613     info.enable_mask        = 1ull<<24 /* uod_pe */;
3614     info.flags              = 0;
3615     info.group              = CVMX_ERROR_GROUP_USB;
3616     info.group_index        = 0;
3617     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3618     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3619     info.parent.status_mask = 1ull<<13 /* usb */;
3620     info.func               = __cvmx_error_display;
3621     info.user_info          = (long)
3622         "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
3623     fail |= cvmx_error_add(&info);
3624
3625     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3626     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3627     info.status_mask        = 1ull<<25 /* uod_pf */;
3628     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3629     info.enable_mask        = 1ull<<25 /* uod_pf */;
3630     info.flags              = 0;
3631     info.group              = CVMX_ERROR_GROUP_USB;
3632     info.group_index        = 0;
3633     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3634     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3635     info.parent.status_mask = 1ull<<13 /* usb */;
3636     info.func               = __cvmx_error_display;
3637     info.user_info          = (long)
3638         "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
3639     fail |= cvmx_error_add(&info);
3640
3641     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3642     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3643     info.status_mask        = 1ull<<26 /* n2u_pf */;
3644     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3645     info.enable_mask        = 1ull<<26 /* n2u_pf */;
3646     info.flags              = 0;
3647     info.group              = CVMX_ERROR_GROUP_USB;
3648     info.group_index        = 0;
3649     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3650     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3651     info.parent.status_mask = 1ull<<13 /* usb */;
3652     info.func               = __cvmx_error_display;
3653     info.user_info          = (long)
3654         "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n";
3655     fail |= cvmx_error_add(&info);
3656
3657     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3658     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3659     info.status_mask        = 1ull<<27 /* n2u_pe */;
3660     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3661     info.enable_mask        = 1ull<<27 /* n2u_pe */;
3662     info.flags              = 0;
3663     info.group              = CVMX_ERROR_GROUP_USB;
3664     info.group_index        = 0;
3665     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3666     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3667     info.parent.status_mask = 1ull<<13 /* usb */;
3668     info.func               = __cvmx_error_display;
3669     info.user_info          = (long)
3670         "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n";
3671     fail |= cvmx_error_add(&info);
3672
3673     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3674     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3675     info.status_mask        = 1ull<<28 /* u2n_d_pe */;
3676     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3677     info.enable_mask        = 1ull<<28 /* u2n_d_pe */;
3678     info.flags              = 0;
3679     info.group              = CVMX_ERROR_GROUP_USB;
3680     info.group_index        = 0;
3681     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3682     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3683     info.parent.status_mask = 1ull<<13 /* usb */;
3684     info.func               = __cvmx_error_display;
3685     info.user_info          = (long)
3686         "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n";
3687     fail |= cvmx_error_add(&info);
3688
3689     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3690     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3691     info.status_mask        = 1ull<<29 /* u2n_d_pf */;
3692     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3693     info.enable_mask        = 1ull<<29 /* u2n_d_pf */;
3694     info.flags              = 0;
3695     info.group              = CVMX_ERROR_GROUP_USB;
3696     info.group_index        = 0;
3697     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3698     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3699     info.parent.status_mask = 1ull<<13 /* usb */;
3700     info.func               = __cvmx_error_display;
3701     info.user_info          = (long)
3702         "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n";
3703     fail |= cvmx_error_add(&info);
3704
3705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3706     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3707     info.status_mask        = 1ull<<30 /* u2n_c_pf */;
3708     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3709     info.enable_mask        = 1ull<<30 /* u2n_c_pf */;
3710     info.flags              = 0;
3711     info.group              = CVMX_ERROR_GROUP_USB;
3712     info.group_index        = 0;
3713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3715     info.parent.status_mask = 1ull<<13 /* usb */;
3716     info.func               = __cvmx_error_display;
3717     info.user_info          = (long)
3718         "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n";
3719     fail |= cvmx_error_add(&info);
3720
3721     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3722     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3723     info.status_mask        = 1ull<<31 /* u2n_c_pe */;
3724     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3725     info.enable_mask        = 1ull<<31 /* u2n_c_pe */;
3726     info.flags              = 0;
3727     info.group              = CVMX_ERROR_GROUP_USB;
3728     info.group_index        = 0;
3729     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3730     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3731     info.parent.status_mask = 1ull<<13 /* usb */;
3732     info.func               = __cvmx_error_display;
3733     info.user_info          = (long)
3734         "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n";
3735     fail |= cvmx_error_add(&info);
3736
3737     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3738     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3739     info.status_mask        = 1ull<<32 /* ltl_f_pe */;
3740     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3741     info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
3742     info.flags              = 0;
3743     info.group              = CVMX_ERROR_GROUP_USB;
3744     info.group_index        = 0;
3745     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3746     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3747     info.parent.status_mask = 1ull<<13 /* usb */;
3748     info.func               = __cvmx_error_display;
3749     info.user_info          = (long)
3750         "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
3751     fail |= cvmx_error_add(&info);
3752
3753     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3754     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3755     info.status_mask        = 1ull<<33 /* ltl_f_pf */;
3756     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3757     info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
3758     info.flags              = 0;
3759     info.group              = CVMX_ERROR_GROUP_USB;
3760     info.group_index        = 0;
3761     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3762     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3763     info.parent.status_mask = 1ull<<13 /* usb */;
3764     info.func               = __cvmx_error_display;
3765     info.user_info          = (long)
3766         "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
3767     fail |= cvmx_error_add(&info);
3768
3769     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3770     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3771     info.status_mask        = 1ull<<34 /* nd4o_rpe */;
3772     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3773     info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
3774     info.flags              = 0;
3775     info.group              = CVMX_ERROR_GROUP_USB;
3776     info.group_index        = 0;
3777     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3778     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3779     info.parent.status_mask = 1ull<<13 /* usb */;
3780     info.func               = __cvmx_error_display;
3781     info.user_info          = (long)
3782         "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
3783     fail |= cvmx_error_add(&info);
3784
3785     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3786     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3787     info.status_mask        = 1ull<<35 /* nd4o_rpf */;
3788     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3789     info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
3790     info.flags              = 0;
3791     info.group              = CVMX_ERROR_GROUP_USB;
3792     info.group_index        = 0;
3793     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3794     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3795     info.parent.status_mask = 1ull<<13 /* usb */;
3796     info.func               = __cvmx_error_display;
3797     info.user_info          = (long)
3798         "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
3799     fail |= cvmx_error_add(&info);
3800
3801     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3802     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3803     info.status_mask        = 1ull<<36 /* nd4o_dpe */;
3804     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3805     info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
3806     info.flags              = 0;
3807     info.group              = CVMX_ERROR_GROUP_USB;
3808     info.group_index        = 0;
3809     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3810     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3811     info.parent.status_mask = 1ull<<13 /* usb */;
3812     info.func               = __cvmx_error_display;
3813     info.user_info          = (long)
3814         "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
3815     fail |= cvmx_error_add(&info);
3816
3817     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3818     info.status_addr        = CVMX_USBNX_INT_SUM(0);
3819     info.status_mask        = 1ull<<37 /* nd4o_dpf */;
3820     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
3821     info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
3822     info.flags              = 0;
3823     info.group              = CVMX_ERROR_GROUP_USB;
3824     info.group_index        = 0;
3825     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3826     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3827     info.parent.status_mask = 1ull<<13 /* usb */;
3828     info.func               = __cvmx_error_display;
3829     info.user_info          = (long)
3830         "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
3831     fail |= cvmx_error_add(&info);
3832
3833     return fail;
3834 }
3835