sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c

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  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn38xxp2.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN38XXP2</h2>
  51  * @dot
  52  * digraph cn38xxp2
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
  59  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  60  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
  61  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  62  *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
  63  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
  64  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
  65  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
  66  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
  67  *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<pci_rsl>pci_rsl"];
  68  *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
  69  *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
  70  *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
  71  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  72  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
  73  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  74  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
  75  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  76  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
  77  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  78  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
  79  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  80  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
  81  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
  82  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
  83  *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  84  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
  85  *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  86  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
  87  *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  88  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
  89  *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  90  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
  91  *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  92  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
  93  *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
  94  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
  95  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
  96  *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
  97  *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
  98  *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
  99  *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
 100  *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
 101  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"];
 102  *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
 103  *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
 104  *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
 105  *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
 106  *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
 107  *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
 108  *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
 109  *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
 110  *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
 111  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
 112  *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
 113  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
 114  *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
 115  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
 116  *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
 117  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
 118  *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
 119  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
 120  *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
 121  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
 122  *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
 123  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
 124  *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
 125  *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
 126  *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
 127  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
 128  *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
 129  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
 130  *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
 131  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 132  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 133  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 134  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
 135  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 136  *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
 137  *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
 138  *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
 139  *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
 140  *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
 141  *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
 142  *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
 143  *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
 144  * }
 145  * @enddot
 146  */
 147 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 148 #include <asm/octeon/cvmx.h>
 149 #include <asm/octeon/cvmx-error.h>
 150 #include <asm/octeon/cvmx-error-custom.h>
 151 #include <asm/octeon/cvmx-csr-typedefs.h>
 152 #else
 153 #include "cvmx.h"
 154 #include "cvmx-error.h"
 155 #include "cvmx-error-custom.h"
 156 #endif
 157
 158 int cvmx_error_initialize_cn38xxp2(void);
 159
 160 int cvmx_error_initialize_cn38xxp2(void)
 161 {
 162     cvmx_error_info_t info;
 163     int fail = 0;
 164
 165     /* CVMX_CIU_INTX_SUM0(0) */
 166     /* CVMX_CIU_INT_SUM1 */
 167     /* CVMX_NPI_RSL_INT_BLOCKS */
 168     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 169     info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
 170     info.status_mask        = 0;
 171     info.enable_addr        = 0;
 172     info.enable_mask        = 0;
 173     info.flags              = 0;
 174     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 175     info.group_index        = 0;
 176     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 177     info.parent.status_addr = 0;
 178     info.parent.status_mask = 0;
 179     info.func               = __cvmx_error_decode;
 180     info.user_info          = 0;
 181     fail |= cvmx_error_add(&info);
 182
 183     /* CVMX_L2D_ERR */
 184     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 185     info.status_addr        = CVMX_L2D_ERR;
 186     info.status_mask        = 1ull<<3 /* sec_err */;
 187     info.enable_addr        = CVMX_L2D_ERR;
 188     info.enable_mask        = 1ull<<1 /* sec_intena */;
 189     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 190     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 191     info.group_index        = 0;
 192     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 193     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 194     info.parent.status_mask = 1ull<<16 /* l2c */;
 195     info.func               = __cvmx_error_handle_l2d_err_sec_err;
 196     info.user_info          = (long)
 197         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
 198     fail |= cvmx_error_add(&info);
 199
 200     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 201     info.status_addr        = CVMX_L2D_ERR;
 202     info.status_mask        = 1ull<<4 /* ded_err */;
 203     info.enable_addr        = CVMX_L2D_ERR;
 204     info.enable_mask        = 1ull<<2 /* ded_intena */;
 205     info.flags              = 0;
 206     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 207     info.group_index        = 0;
 208     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 209     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 210     info.parent.status_mask = 1ull<<16 /* l2c */;
 211     info.func               = __cvmx_error_handle_l2d_err_ded_err;
 212     info.user_info          = (long)
 213         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
 214     fail |= cvmx_error_add(&info);
 215
 216     /* CVMX_L2T_ERR */
 217     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 218     info.status_addr        = CVMX_L2T_ERR;
 219     info.status_mask        = 1ull<<3 /* sec_err */;
 220     info.enable_addr        = CVMX_L2T_ERR;
 221     info.enable_mask        = 1ull<<1 /* sec_intena */;
 222     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 223     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 224     info.group_index        = 0;
 225     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 226     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 227     info.parent.status_mask = 1ull<<16 /* l2c */;
 228     info.func               = __cvmx_error_handle_l2t_err_sec_err;
 229     info.user_info          = (long)
 230         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
 231         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 232         "    given index) are checked for single bit errors(SBEs).\n"
 233         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 234         "    SBEs are auto corrected in HW and generate an\n"
 235         "    interrupt(if enabled).\n";
 236     fail |= cvmx_error_add(&info);
 237
 238     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 239     info.status_addr        = CVMX_L2T_ERR;
 240     info.status_mask        = 1ull<<4 /* ded_err */;
 241     info.enable_addr        = CVMX_L2T_ERR;
 242     info.enable_mask        = 1ull<<2 /* ded_intena */;
 243     info.flags              = 0;
 244     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 245     info.group_index        = 0;
 246     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 247     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 248     info.parent.status_mask = 1ull<<16 /* l2c */;
 249     info.func               = __cvmx_error_handle_l2t_err_ded_err;
 250     info.user_info          = (long)
 251         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
 252         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 253         "    given index) are checked for double bit errors(DBEs).\n"
 254         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 255         "    DBEs also generated an interrupt(if enabled).\n";
 256     fail |= cvmx_error_add(&info);
 257
 258     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 259     info.status_addr        = CVMX_L2T_ERR;
 260     info.status_mask        = 1ull<<24 /* lckerr */;
 261     info.enable_addr        = CVMX_L2T_ERR;
 262     info.enable_mask        = 1ull<<25 /* lck_intena */;
 263     info.flags              = 0;
 264     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 265     info.group_index        = 0;
 266     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 267     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 268     info.parent.status_mask = 1ull<<16 /* l2c */;
 269     info.func               = __cvmx_error_handle_l2t_err_lckerr;
 270     info.user_info          = (long)
 271         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
 272         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 273         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 274         "    successfully, however the address is NOT locked.\n"
 275         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 276         "    into account. For example, if diagnostic PPx has\n"
 277         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 278         "    been previously LOCKED, then an attempt to LOCK the\n"
 279         "    last available SET0 would result in a LCKERR. (This\n"
 280         "    is to ensure that at least 1 SET at each INDEX is\n"
 281         "    not LOCKED for general use by other PPs).\n";
 282     fail |= cvmx_error_add(&info);
 283
 284     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 285     info.status_addr        = CVMX_L2T_ERR;
 286     info.status_mask        = 1ull<<26 /* lckerr2 */;
 287     info.enable_addr        = CVMX_L2T_ERR;
 288     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
 289     info.flags              = 0;
 290     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 291     info.group_index        = 0;
 292     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 293     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 294     info.parent.status_mask = 1ull<<16 /* l2c */;
 295     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
 296     info.user_info          = (long)
 297         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 298         "    could not find an available/unlocked set (for\n"
 299         "    replacement).\n"
 300         "    Most likely, this is a result of SW mixing SET\n"
 301         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 302         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 303         "    then a Rd/Wr Miss from PP#n will be unable\n"
 304         "    to determine a 'valid' replacement set (since LOCKED\n"
 305         "    addresses should NEVER be replaced).\n"
 306         "    If such an event occurs, the HW will select the smallest\n"
 307         "    available SET(specified by UMSK'x)' as the replacement\n"
 308         "    set, and the address is unlocked.\n";
 309     fail |= cvmx_error_add(&info);
 310
 311     /* CVMX_NPI_INT_SUM */
 312     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 313     info.status_addr        = CVMX_NPI_INT_SUM;
 314     info.status_mask        = 1ull<<0 /* rml_rto */;
 315     info.enable_addr        = CVMX_NPI_INT_ENB;
 316     info.enable_mask        = 1ull<<0 /* rml_rto */;
 317     info.flags              = 0;
 318     info.group              = CVMX_ERROR_GROUP_PCI;
 319     info.group_index        = 0;
 320     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 321     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 322     info.parent.status_mask = 1ull<<3 /* npi */;
 323     info.func               = __cvmx_error_display;
 324     info.user_info          = (long)
 325         "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
 326         "    back from a RSL after sending a read command to\n"
 327         "    a RSL.\n";
 328     fail |= cvmx_error_add(&info);
 329
 330     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 331     info.status_addr        = CVMX_NPI_INT_SUM;
 332     info.status_mask        = 1ull<<1 /* rml_wto */;
 333     info.enable_addr        = CVMX_NPI_INT_ENB;
 334     info.enable_mask        = 1ull<<1 /* rml_wto */;
 335     info.flags              = 0;
 336     info.group              = CVMX_ERROR_GROUP_PCI;
 337     info.group_index        = 0;
 338     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 339     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 340     info.parent.status_mask = 1ull<<3 /* npi */;
 341     info.func               = __cvmx_error_display;
 342     info.user_info          = (long)
 343         "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
 344         "    back from a RSL after sending a write command to\n"
 345         "    a RSL.\n";
 346     fail |= cvmx_error_add(&info);
 347
 348     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 349     info.status_addr        = CVMX_NPI_INT_SUM;
 350     info.status_mask        = 1ull<<3 /* po0_2sml */;
 351     info.enable_addr        = CVMX_NPI_INT_ENB;
 352     info.enable_mask        = 1ull<<3 /* po0_2sml */;
 353     info.flags              = 0;
 354     info.group              = CVMX_ERROR_GROUP_PCI;
 355     info.group_index        = 0;
 356     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 357     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 358     info.parent.status_mask = 1ull<<3 /* npi */;
 359     info.func               = __cvmx_error_display;
 360     info.user_info          = (long)
 361         "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
 362         "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
 363     fail |= cvmx_error_add(&info);
 364
 365     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 366     info.status_addr        = CVMX_NPI_INT_SUM;
 367     info.status_mask        = 1ull<<4 /* po1_2sml */;
 368     info.enable_addr        = CVMX_NPI_INT_ENB;
 369     info.enable_mask        = 1ull<<4 /* po1_2sml */;
 370     info.flags              = 0;
 371     info.group              = CVMX_ERROR_GROUP_PCI;
 372     info.group_index        = 0;
 373     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 374     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 375     info.parent.status_mask = 1ull<<3 /* npi */;
 376     info.func               = __cvmx_error_display;
 377     info.user_info          = (long)
 378         "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
 379         "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
 380     fail |= cvmx_error_add(&info);
 381
 382     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 383     info.status_addr        = CVMX_NPI_INT_SUM;
 384     info.status_mask        = 1ull<<5 /* po2_2sml */;
 385     info.enable_addr        = CVMX_NPI_INT_ENB;
 386     info.enable_mask        = 1ull<<5 /* po2_2sml */;
 387     info.flags              = 0;
 388     info.group              = CVMX_ERROR_GROUP_PCI;
 389     info.group_index        = 0;
 390     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 391     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 392     info.parent.status_mask = 1ull<<3 /* npi */;
 393     info.func               = __cvmx_error_display;
 394     info.user_info          = (long)
 395         "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
 396         "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
 397     fail |= cvmx_error_add(&info);
 398
 399     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 400     info.status_addr        = CVMX_NPI_INT_SUM;
 401     info.status_mask        = 1ull<<6 /* po3_2sml */;
 402     info.enable_addr        = CVMX_NPI_INT_ENB;
 403     info.enable_mask        = 1ull<<6 /* po3_2sml */;
 404     info.flags              = 0;
 405     info.group              = CVMX_ERROR_GROUP_PCI;
 406     info.group_index        = 0;
 407     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 408     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 409     info.parent.status_mask = 1ull<<3 /* npi */;
 410     info.func               = __cvmx_error_display;
 411     info.user_info          = (long)
 412         "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
 413         "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
 414     fail |= cvmx_error_add(&info);
 415
 416     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 417     info.status_addr        = CVMX_NPI_INT_SUM;
 418     info.status_mask        = 1ull<<7 /* i0_rtout */;
 419     info.enable_addr        = CVMX_NPI_INT_ENB;
 420     info.enable_mask        = 1ull<<7 /* i0_rtout */;
 421     info.flags              = 0;
 422     info.group              = CVMX_ERROR_GROUP_PCI;
 423     info.group_index        = 0;
 424     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 425     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 426     info.parent.status_mask = 1ull<<3 /* npi */;
 427     info.func               = __cvmx_error_display;
 428     info.user_info          = (long)
 429         "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 430         "    read instructions.\n";
 431     fail |= cvmx_error_add(&info);
 432
 433     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 434     info.status_addr        = CVMX_NPI_INT_SUM;
 435     info.status_mask        = 1ull<<8 /* i1_rtout */;
 436     info.enable_addr        = CVMX_NPI_INT_ENB;
 437     info.enable_mask        = 1ull<<8 /* i1_rtout */;
 438     info.flags              = 0;
 439     info.group              = CVMX_ERROR_GROUP_PCI;
 440     info.group_index        = 0;
 441     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 442     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 443     info.parent.status_mask = 1ull<<3 /* npi */;
 444     info.func               = __cvmx_error_display;
 445     info.user_info          = (long)
 446         "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 447         "    read instructions.\n";
 448     fail |= cvmx_error_add(&info);
 449
 450     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 451     info.status_addr        = CVMX_NPI_INT_SUM;
 452     info.status_mask        = 1ull<<9 /* i2_rtout */;
 453     info.enable_addr        = CVMX_NPI_INT_ENB;
 454     info.enable_mask        = 1ull<<9 /* i2_rtout */;
 455     info.flags              = 0;
 456     info.group              = CVMX_ERROR_GROUP_PCI;
 457     info.group_index        = 0;
 458     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 459     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 460     info.parent.status_mask = 1ull<<3 /* npi */;
 461     info.func               = __cvmx_error_display;
 462     info.user_info          = (long)
 463         "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
 464         "    read instructions.\n";
 465     fail |= cvmx_error_add(&info);
 466
 467     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 468     info.status_addr        = CVMX_NPI_INT_SUM;
 469     info.status_mask        = 1ull<<10 /* i3_rtout */;
 470     info.enable_addr        = CVMX_NPI_INT_ENB;
 471     info.enable_mask        = 1ull<<10 /* i3_rtout */;
 472     info.flags              = 0;
 473     info.group              = CVMX_ERROR_GROUP_PCI;
 474     info.group_index        = 0;
 475     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 476     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 477     info.parent.status_mask = 1ull<<3 /* npi */;
 478     info.func               = __cvmx_error_display;
 479     info.user_info          = (long)
 480         "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
 481         "    read instructions.\n";
 482     fail |= cvmx_error_add(&info);
 483
 484     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 485     info.status_addr        = CVMX_NPI_INT_SUM;
 486     info.status_mask        = 1ull<<11 /* i0_overf */;
 487     info.enable_addr        = CVMX_NPI_INT_ENB;
 488     info.enable_mask        = 1ull<<11 /* i0_overf */;
 489     info.flags              = 0;
 490     info.group              = CVMX_ERROR_GROUP_PCI;
 491     info.group_index        = 0;
 492     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 493     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 494     info.parent.status_mask = 1ull<<3 /* npi */;
 495     info.func               = __cvmx_error_display;
 496     info.user_info          = (long)
 497         "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
 498         "    doorbell count was set.\n";
 499     fail |= cvmx_error_add(&info);
 500
 501     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 502     info.status_addr        = CVMX_NPI_INT_SUM;
 503     info.status_mask        = 1ull<<12 /* i1_overf */;
 504     info.enable_addr        = CVMX_NPI_INT_ENB;
 505     info.enable_mask        = 1ull<<12 /* i1_overf */;
 506     info.flags              = 0;
 507     info.group              = CVMX_ERROR_GROUP_PCI;
 508     info.group_index        = 0;
 509     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 510     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 511     info.parent.status_mask = 1ull<<3 /* npi */;
 512     info.func               = __cvmx_error_display;
 513     info.user_info          = (long)
 514         "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
 515         "    doorbell count was set.\n";
 516     fail |= cvmx_error_add(&info);
 517
 518     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 519     info.status_addr        = CVMX_NPI_INT_SUM;
 520     info.status_mask        = 1ull<<13 /* i2_overf */;
 521     info.enable_addr        = CVMX_NPI_INT_ENB;
 522     info.enable_mask        = 1ull<<13 /* i2_overf */;
 523     info.flags              = 0;
 524     info.group              = CVMX_ERROR_GROUP_PCI;
 525     info.group_index        = 0;
 526     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 527     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 528     info.parent.status_mask = 1ull<<3 /* npi */;
 529     info.func               = __cvmx_error_display;
 530     info.user_info          = (long)
 531         "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
 532         "    doorbell count was set.\n";
 533     fail |= cvmx_error_add(&info);
 534
 535     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 536     info.status_addr        = CVMX_NPI_INT_SUM;
 537     info.status_mask        = 1ull<<14 /* i3_overf */;
 538     info.enable_addr        = CVMX_NPI_INT_ENB;
 539     info.enable_mask        = 1ull<<14 /* i3_overf */;
 540     info.flags              = 0;
 541     info.group              = CVMX_ERROR_GROUP_PCI;
 542     info.group_index        = 0;
 543     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 544     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 545     info.parent.status_mask = 1ull<<3 /* npi */;
 546     info.func               = __cvmx_error_display;
 547     info.user_info          = (long)
 548         "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
 549         "    doorbell count was set.\n";
 550     fail |= cvmx_error_add(&info);
 551
 552     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 553     info.status_addr        = CVMX_NPI_INT_SUM;
 554     info.status_mask        = 1ull<<15 /* p0_rtout */;
 555     info.enable_addr        = CVMX_NPI_INT_ENB;
 556     info.enable_mask        = 1ull<<15 /* p0_rtout */;
 557     info.flags              = 0;
 558     info.group              = CVMX_ERROR_GROUP_PCI;
 559     info.group_index        = 0;
 560     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 561     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 562     info.parent.status_mask = 1ull<<3 /* npi */;
 563     info.func               = __cvmx_error_display;
 564     info.user_info          = (long)
 565         "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 566         "    read packet data.\n";
 567     fail |= cvmx_error_add(&info);
 568
 569     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 570     info.status_addr        = CVMX_NPI_INT_SUM;
 571     info.status_mask        = 1ull<<16 /* p1_rtout */;
 572     info.enable_addr        = CVMX_NPI_INT_ENB;
 573     info.enable_mask        = 1ull<<16 /* p1_rtout */;
 574     info.flags              = 0;
 575     info.group              = CVMX_ERROR_GROUP_PCI;
 576     info.group_index        = 0;
 577     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 578     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 579     info.parent.status_mask = 1ull<<3 /* npi */;
 580     info.func               = __cvmx_error_display;
 581     info.user_info          = (long)
 582         "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 583         "    read packet data.\n";
 584     fail |= cvmx_error_add(&info);
 585
 586     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 587     info.status_addr        = CVMX_NPI_INT_SUM;
 588     info.status_mask        = 1ull<<17 /* p2_rtout */;
 589     info.enable_addr        = CVMX_NPI_INT_ENB;
 590     info.enable_mask        = 1ull<<17 /* p2_rtout */;
 591     info.flags              = 0;
 592     info.group              = CVMX_ERROR_GROUP_PCI;
 593     info.group_index        = 0;
 594     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 595     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 596     info.parent.status_mask = 1ull<<3 /* npi */;
 597     info.func               = __cvmx_error_display;
 598     info.user_info          = (long)
 599         "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
 600         "    read packet data.\n";
 601     fail |= cvmx_error_add(&info);
 602
 603     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 604     info.status_addr        = CVMX_NPI_INT_SUM;
 605     info.status_mask        = 1ull<<18 /* p3_rtout */;
 606     info.enable_addr        = CVMX_NPI_INT_ENB;
 607     info.enable_mask        = 1ull<<18 /* p3_rtout */;
 608     info.flags              = 0;
 609     info.group              = CVMX_ERROR_GROUP_PCI;
 610     info.group_index        = 0;
 611     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 612     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 613     info.parent.status_mask = 1ull<<3 /* npi */;
 614     info.func               = __cvmx_error_display;
 615     info.user_info          = (long)
 616         "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
 617         "    read packet data.\n";
 618     fail |= cvmx_error_add(&info);
 619
 620     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 621     info.status_addr        = CVMX_NPI_INT_SUM;
 622     info.status_mask        = 1ull<<19 /* p0_perr */;
 623     info.enable_addr        = CVMX_NPI_INT_ENB;
 624     info.enable_mask        = 1ull<<19 /* p0_perr */;
 625     info.flags              = 0;
 626     info.group              = CVMX_ERROR_GROUP_PCI;
 627     info.group_index        = 0;
 628     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 629     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 630     info.parent.status_mask = 1ull<<3 /* npi */;
 631     info.func               = __cvmx_error_display;
 632     info.user_info          = (long)
 633         "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
 634         "    data this bit may be set.\n";
 635     fail |= cvmx_error_add(&info);
 636
 637     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 638     info.status_addr        = CVMX_NPI_INT_SUM;
 639     info.status_mask        = 1ull<<20 /* p1_perr */;
 640     info.enable_addr        = CVMX_NPI_INT_ENB;
 641     info.enable_mask        = 1ull<<20 /* p1_perr */;
 642     info.flags              = 0;
 643     info.group              = CVMX_ERROR_GROUP_PCI;
 644     info.group_index        = 0;
 645     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 646     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 647     info.parent.status_mask = 1ull<<3 /* npi */;
 648     info.func               = __cvmx_error_display;
 649     info.user_info          = (long)
 650         "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
 651         "    data this bit may be set.\n";
 652     fail |= cvmx_error_add(&info);
 653
 654     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 655     info.status_addr        = CVMX_NPI_INT_SUM;
 656     info.status_mask        = 1ull<<21 /* p2_perr */;
 657     info.enable_addr        = CVMX_NPI_INT_ENB;
 658     info.enable_mask        = 1ull<<21 /* p2_perr */;
 659     info.flags              = 0;
 660     info.group              = CVMX_ERROR_GROUP_PCI;
 661     info.group_index        = 0;
 662     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 663     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 664     info.parent.status_mask = 1ull<<3 /* npi */;
 665     info.func               = __cvmx_error_display;
 666     info.user_info          = (long)
 667         "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
 668         "    data this bit may be set.\n";
 669     fail |= cvmx_error_add(&info);
 670
 671     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 672     info.status_addr        = CVMX_NPI_INT_SUM;
 673     info.status_mask        = 1ull<<22 /* p3_perr */;
 674     info.enable_addr        = CVMX_NPI_INT_ENB;
 675     info.enable_mask        = 1ull<<22 /* p3_perr */;
 676     info.flags              = 0;
 677     info.group              = CVMX_ERROR_GROUP_PCI;
 678     info.group_index        = 0;
 679     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 680     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 681     info.parent.status_mask = 1ull<<3 /* npi */;
 682     info.func               = __cvmx_error_display;
 683     info.user_info          = (long)
 684         "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
 685         "    data this bit may be set.\n";
 686     fail |= cvmx_error_add(&info);
 687
 688     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 689     info.status_addr        = CVMX_NPI_INT_SUM;
 690     info.status_mask        = 1ull<<23 /* g0_rtout */;
 691     info.enable_addr        = CVMX_NPI_INT_ENB;
 692     info.enable_mask        = 1ull<<23 /* g0_rtout */;
 693     info.flags              = 0;
 694     info.group              = CVMX_ERROR_GROUP_PCI;
 695     info.group_index        = 0;
 696     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 697     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 698     info.parent.status_mask = 1ull<<3 /* npi */;
 699     info.func               = __cvmx_error_display;
 700     info.user_info          = (long)
 701         "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 702         "    read a gather list.\n";
 703     fail |= cvmx_error_add(&info);
 704
 705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 706     info.status_addr        = CVMX_NPI_INT_SUM;
 707     info.status_mask        = 1ull<<24 /* g1_rtout */;
 708     info.enable_addr        = CVMX_NPI_INT_ENB;
 709     info.enable_mask        = 1ull<<24 /* g1_rtout */;
 710     info.flags              = 0;
 711     info.group              = CVMX_ERROR_GROUP_PCI;
 712     info.group_index        = 0;
 713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 715     info.parent.status_mask = 1ull<<3 /* npi */;
 716     info.func               = __cvmx_error_display;
 717     info.user_info          = (long)
 718         "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 719         "    read a gather list.\n";
 720     fail |= cvmx_error_add(&info);
 721
 722     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 723     info.status_addr        = CVMX_NPI_INT_SUM;
 724     info.status_mask        = 1ull<<25 /* g2_rtout */;
 725     info.enable_addr        = CVMX_NPI_INT_ENB;
 726     info.enable_mask        = 1ull<<25 /* g2_rtout */;
 727     info.flags              = 0;
 728     info.group              = CVMX_ERROR_GROUP_PCI;
 729     info.group_index        = 0;
 730     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 731     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 732     info.parent.status_mask = 1ull<<3 /* npi */;
 733     info.func               = __cvmx_error_display;
 734     info.user_info          = (long)
 735         "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
 736         "    read a gather list.\n";
 737     fail |= cvmx_error_add(&info);
 738
 739     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 740     info.status_addr        = CVMX_NPI_INT_SUM;
 741     info.status_mask        = 1ull<<26 /* g3_rtout */;
 742     info.enable_addr        = CVMX_NPI_INT_ENB;
 743     info.enable_mask        = 1ull<<26 /* g3_rtout */;
 744     info.flags              = 0;
 745     info.group              = CVMX_ERROR_GROUP_PCI;
 746     info.group_index        = 0;
 747     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 748     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 749     info.parent.status_mask = 1ull<<3 /* npi */;
 750     info.func               = __cvmx_error_display;
 751     info.user_info          = (long)
 752         "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
 753         "    read a gather list.\n";
 754     fail |= cvmx_error_add(&info);
 755
 756     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 757     info.status_addr        = CVMX_NPI_INT_SUM;
 758     info.status_mask        = 1ull<<27 /* p0_pperr */;
 759     info.enable_addr        = CVMX_NPI_INT_ENB;
 760     info.enable_mask        = 1ull<<27 /* p0_pperr */;
 761     info.flags              = 0;
 762     info.group              = CVMX_ERROR_GROUP_PCI;
 763     info.group_index        = 0;
 764     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 765     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 766     info.parent.status_mask = 1ull<<3 /* npi */;
 767     info.func               = __cvmx_error_display;
 768     info.user_info          = (long)
 769         "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
 770         "    pointer-pair, this bit may be set.\n";
 771     fail |= cvmx_error_add(&info);
 772
 773     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 774     info.status_addr        = CVMX_NPI_INT_SUM;
 775     info.status_mask        = 1ull<<28 /* p1_pperr */;
 776     info.enable_addr        = CVMX_NPI_INT_ENB;
 777     info.enable_mask        = 1ull<<28 /* p1_pperr */;
 778     info.flags              = 0;
 779     info.group              = CVMX_ERROR_GROUP_PCI;
 780     info.group_index        = 0;
 781     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 782     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 783     info.parent.status_mask = 1ull<<3 /* npi */;
 784     info.func               = __cvmx_error_display;
 785     info.user_info          = (long)
 786         "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
 787         "    pointer-pair, this bit may be set.\n";
 788     fail |= cvmx_error_add(&info);
 789
 790     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 791     info.status_addr        = CVMX_NPI_INT_SUM;
 792     info.status_mask        = 1ull<<29 /* p2_pperr */;
 793     info.enable_addr        = CVMX_NPI_INT_ENB;
 794     info.enable_mask        = 1ull<<29 /* p2_pperr */;
 795     info.flags              = 0;
 796     info.group              = CVMX_ERROR_GROUP_PCI;
 797     info.group_index        = 0;
 798     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 799     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 800     info.parent.status_mask = 1ull<<3 /* npi */;
 801     info.func               = __cvmx_error_display;
 802     info.user_info          = (long)
 803         "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
 804         "    pointer-pair, this bit may be set.\n";
 805     fail |= cvmx_error_add(&info);
 806
 807     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 808     info.status_addr        = CVMX_NPI_INT_SUM;
 809     info.status_mask        = 1ull<<30 /* p3_pperr */;
 810     info.enable_addr        = CVMX_NPI_INT_ENB;
 811     info.enable_mask        = 1ull<<30 /* p3_pperr */;
 812     info.flags              = 0;
 813     info.group              = CVMX_ERROR_GROUP_PCI;
 814     info.group_index        = 0;
 815     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 816     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 817     info.parent.status_mask = 1ull<<3 /* npi */;
 818     info.func               = __cvmx_error_display;
 819     info.user_info          = (long)
 820         "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
 821         "    pointer-pair, this bit may be set.\n";
 822     fail |= cvmx_error_add(&info);
 823
 824     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 825     info.status_addr        = CVMX_NPI_INT_SUM;
 826     info.status_mask        = 1ull<<31 /* p0_ptout */;
 827     info.enable_addr        = CVMX_NPI_INT_ENB;
 828     info.enable_mask        = 1ull<<31 /* p0_ptout */;
 829     info.flags              = 0;
 830     info.group              = CVMX_ERROR_GROUP_PCI;
 831     info.group_index        = 0;
 832     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 833     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 834     info.parent.status_mask = 1ull<<3 /* npi */;
 835     info.func               = __cvmx_error_display;
 836     info.user_info          = (long)
 837         "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
 838         "    pair.\n";
 839     fail |= cvmx_error_add(&info);
 840
 841     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 842     info.status_addr        = CVMX_NPI_INT_SUM;
 843     info.status_mask        = 1ull<<32 /* p1_ptout */;
 844     info.enable_addr        = CVMX_NPI_INT_ENB;
 845     info.enable_mask        = 1ull<<32 /* p1_ptout */;
 846     info.flags              = 0;
 847     info.group              = CVMX_ERROR_GROUP_PCI;
 848     info.group_index        = 0;
 849     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 850     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 851     info.parent.status_mask = 1ull<<3 /* npi */;
 852     info.func               = __cvmx_error_display;
 853     info.user_info          = (long)
 854         "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
 855         "    pair.\n";
 856     fail |= cvmx_error_add(&info);
 857
 858     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 859     info.status_addr        = CVMX_NPI_INT_SUM;
 860     info.status_mask        = 1ull<<33 /* p2_ptout */;
 861     info.enable_addr        = CVMX_NPI_INT_ENB;
 862     info.enable_mask        = 1ull<<33 /* p2_ptout */;
 863     info.flags              = 0;
 864     info.group              = CVMX_ERROR_GROUP_PCI;
 865     info.group_index        = 0;
 866     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 867     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 868     info.parent.status_mask = 1ull<<3 /* npi */;
 869     info.func               = __cvmx_error_display;
 870     info.user_info          = (long)
 871         "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
 872         "    pair.\n";
 873     fail |= cvmx_error_add(&info);
 874
 875     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 876     info.status_addr        = CVMX_NPI_INT_SUM;
 877     info.status_mask        = 1ull<<34 /* p3_ptout */;
 878     info.enable_addr        = CVMX_NPI_INT_ENB;
 879     info.enable_mask        = 1ull<<34 /* p3_ptout */;
 880     info.flags              = 0;
 881     info.group              = CVMX_ERROR_GROUP_PCI;
 882     info.group_index        = 0;
 883     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 884     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 885     info.parent.status_mask = 1ull<<3 /* npi */;
 886     info.func               = __cvmx_error_display;
 887     info.user_info          = (long)
 888         "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
 889         "    pair.\n";
 890     fail |= cvmx_error_add(&info);
 891
 892     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 893     info.status_addr        = CVMX_NPI_INT_SUM;
 894     info.status_mask        = 1ull<<35 /* i0_pperr */;
 895     info.enable_addr        = CVMX_NPI_INT_ENB;
 896     info.enable_mask        = 1ull<<35 /* i0_pperr */;
 897     info.flags              = 0;
 898     info.group              = CVMX_ERROR_GROUP_PCI;
 899     info.group_index        = 0;
 900     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 901     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 902     info.parent.status_mask = 1ull<<3 /* npi */;
 903     info.func               = __cvmx_error_display;
 904     info.user_info          = (long)
 905         "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
 906         "    this bit may be set.\n";
 907     fail |= cvmx_error_add(&info);
 908
 909     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 910     info.status_addr        = CVMX_NPI_INT_SUM;
 911     info.status_mask        = 1ull<<36 /* i1_pperr */;
 912     info.enable_addr        = CVMX_NPI_INT_ENB;
 913     info.enable_mask        = 1ull<<36 /* i1_pperr */;
 914     info.flags              = 0;
 915     info.group              = CVMX_ERROR_GROUP_PCI;
 916     info.group_index        = 0;
 917     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 918     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 919     info.parent.status_mask = 1ull<<3 /* npi */;
 920     info.func               = __cvmx_error_display;
 921     info.user_info          = (long)
 922         "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
 923         "    this bit may be set.\n";
 924     fail |= cvmx_error_add(&info);
 925
 926     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 927     info.status_addr        = CVMX_NPI_INT_SUM;
 928     info.status_mask        = 1ull<<37 /* i2_pperr */;
 929     info.enable_addr        = CVMX_NPI_INT_ENB;
 930     info.enable_mask        = 1ull<<37 /* i2_pperr */;
 931     info.flags              = 0;
 932     info.group              = CVMX_ERROR_GROUP_PCI;
 933     info.group_index        = 0;
 934     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 935     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 936     info.parent.status_mask = 1ull<<3 /* npi */;
 937     info.func               = __cvmx_error_display;
 938     info.user_info          = (long)
 939         "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
 940         "    this bit may be set.\n";
 941     fail |= cvmx_error_add(&info);
 942
 943     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 944     info.status_addr        = CVMX_NPI_INT_SUM;
 945     info.status_mask        = 1ull<<38 /* i3_pperr */;
 946     info.enable_addr        = CVMX_NPI_INT_ENB;
 947     info.enable_mask        = 1ull<<38 /* i3_pperr */;
 948     info.flags              = 0;
 949     info.group              = CVMX_ERROR_GROUP_PCI;
 950     info.group_index        = 0;
 951     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 952     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 953     info.parent.status_mask = 1ull<<3 /* npi */;
 954     info.func               = __cvmx_error_display;
 955     info.user_info          = (long)
 956         "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
 957         "    this bit may be set.\n";
 958     fail |= cvmx_error_add(&info);
 959
 960     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 961     info.status_addr        = CVMX_NPI_INT_SUM;
 962     info.status_mask        = 1ull<<39 /* win_rto */;
 963     info.enable_addr        = CVMX_NPI_INT_ENB;
 964     info.enable_mask        = 1ull<<39 /* win_rto */;
 965     info.flags              = 0;
 966     info.group              = CVMX_ERROR_GROUP_PCI;
 967     info.group_index        = 0;
 968     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 969     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 970     info.parent.status_mask = 1ull<<3 /* npi */;
 971     info.func               = __cvmx_error_display;
 972     info.user_info          = (long)
 973         "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
 974     fail |= cvmx_error_add(&info);
 975
 976     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 977     info.status_addr        = CVMX_NPI_INT_SUM;
 978     info.status_mask        = 1ull<<40 /* p_dperr */;
 979     info.enable_addr        = CVMX_NPI_INT_ENB;
 980     info.enable_mask        = 1ull<<40 /* p_dperr */;
 981     info.flags              = 0;
 982     info.group              = CVMX_ERROR_GROUP_PCI;
 983     info.group_index        = 0;
 984     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 985     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 986     info.parent.status_mask = 1ull<<3 /* npi */;
 987     info.func               = __cvmx_error_display;
 988     info.user_info          = (long)
 989         "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
 990         "    from the PCI this bit may be set.\n";
 991     fail |= cvmx_error_add(&info);
 992
 993     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 994     info.status_addr        = CVMX_NPI_INT_SUM;
 995     info.status_mask        = 1ull<<41 /* iobdma */;
 996     info.enable_addr        = CVMX_NPI_INT_ENB;
 997     info.enable_mask        = 1ull<<41 /* iobdma */;
 998     info.flags              = 0;
 999     info.group              = CVMX_ERROR_GROUP_PCI;
1000     info.group_index        = 0;
1001     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1002     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1003     info.parent.status_mask = 1ull<<3 /* npi */;
1004     info.func               = __cvmx_error_display;
1005     info.user_info          = (long)
1006         "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
1007     fail |= cvmx_error_add(&info);
1008
1009     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1010     info.status_addr        = CVMX_NPI_INT_SUM;
1011     info.status_mask        = 0;
1012     info.enable_addr        = 0;
1013     info.enable_mask        = 0;
1014     info.flags              = 0;
1015     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1016     info.group_index        = 0;
1017     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1018     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1019     info.parent.status_mask = 1ull<<3 /* npi */;
1020     info.func               = __cvmx_error_decode;
1021     info.user_info          = 0;
1022     fail |= cvmx_error_add(&info);
1023
1024     /* CVMX_NPI_PCI_INT_SUM2 */
1025     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1026     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1027     info.status_mask        = 1ull<<0 /* tr_wabt */;
1028     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1029     info.enable_mask        = 1ull<<0 /* rtr_wabt */;
1030     info.flags              = 0;
1031     info.group              = CVMX_ERROR_GROUP_PCI;
1032     info.group_index        = 0;
1033     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1034     info.parent.status_addr = CVMX_NPI_INT_SUM;
1035     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1036     info.func               = __cvmx_error_display;
1037     info.user_info          = (long)
1038         "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
1039     fail |= cvmx_error_add(&info);
1040
1041     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1042     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1043     info.status_mask        = 1ull<<1 /* mr_wabt */;
1044     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1045     info.enable_mask        = 1ull<<1 /* rmr_wabt */;
1046     info.flags              = 0;
1047     info.group              = CVMX_ERROR_GROUP_PCI;
1048     info.group_index        = 0;
1049     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1050     info.parent.status_addr = CVMX_NPI_INT_SUM;
1051     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1052     info.func               = __cvmx_error_display;
1053     info.user_info          = (long)
1054         "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
1055     fail |= cvmx_error_add(&info);
1056
1057     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1058     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1059     info.status_mask        = 1ull<<2 /* mr_wtto */;
1060     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1061     info.enable_mask        = 1ull<<2 /* rmr_wtto */;
1062     info.flags              = 0;
1063     info.group              = CVMX_ERROR_GROUP_PCI;
1064     info.group_index        = 0;
1065     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1066     info.parent.status_addr = CVMX_NPI_INT_SUM;
1067     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1068     info.func               = __cvmx_error_display;
1069     info.user_info          = (long)
1070         "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
1071     fail |= cvmx_error_add(&info);
1072
1073     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1074     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1075     info.status_mask        = 1ull<<3 /* tr_abt */;
1076     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1077     info.enable_mask        = 1ull<<3 /* rtr_abt */;
1078     info.flags              = 0;
1079     info.group              = CVMX_ERROR_GROUP_PCI;
1080     info.group_index        = 0;
1081     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1082     info.parent.status_addr = CVMX_NPI_INT_SUM;
1083     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1084     info.func               = __cvmx_error_display;
1085     info.user_info          = (long)
1086         "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
1087     fail |= cvmx_error_add(&info);
1088
1089     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1090     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1091     info.status_mask        = 1ull<<4 /* mr_abt */;
1092     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1093     info.enable_mask        = 1ull<<4 /* rmr_abt */;
1094     info.flags              = 0;
1095     info.group              = CVMX_ERROR_GROUP_PCI;
1096     info.group_index        = 0;
1097     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1098     info.parent.status_addr = CVMX_NPI_INT_SUM;
1099     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1100     info.func               = __cvmx_error_display;
1101     info.user_info          = (long)
1102         "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
1103     fail |= cvmx_error_add(&info);
1104
1105     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1106     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1107     info.status_mask        = 1ull<<5 /* mr_tto */;
1108     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1109     info.enable_mask        = 1ull<<5 /* rmr_tto */;
1110     info.flags              = 0;
1111     info.group              = CVMX_ERROR_GROUP_PCI;
1112     info.group_index        = 0;
1113     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1114     info.parent.status_addr = CVMX_NPI_INT_SUM;
1115     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1116     info.func               = __cvmx_error_display;
1117     info.user_info          = (long)
1118         "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
1119     fail |= cvmx_error_add(&info);
1120
1121     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1122     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1123     info.status_mask        = 1ull<<6 /* msi_per */;
1124     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1125     info.enable_mask        = 1ull<<6 /* rmsi_per */;
1126     info.flags              = 0;
1127     info.group              = CVMX_ERROR_GROUP_PCI;
1128     info.group_index        = 0;
1129     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1130     info.parent.status_addr = CVMX_NPI_INT_SUM;
1131     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1132     info.func               = __cvmx_error_display;
1133     info.user_info          = (long)
1134         "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
1135     fail |= cvmx_error_add(&info);
1136
1137     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1138     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1139     info.status_mask        = 1ull<<7 /* msi_tabt */;
1140     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1141     info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
1142     info.flags              = 0;
1143     info.group              = CVMX_ERROR_GROUP_PCI;
1144     info.group_index        = 0;
1145     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1146     info.parent.status_addr = CVMX_NPI_INT_SUM;
1147     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1148     info.func               = __cvmx_error_display;
1149     info.user_info          = (long)
1150         "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
1151     fail |= cvmx_error_add(&info);
1152
1153     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1154     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1155     info.status_mask        = 1ull<<8 /* msi_mabt */;
1156     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1157     info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
1158     info.flags              = 0;
1159     info.group              = CVMX_ERROR_GROUP_PCI;
1160     info.group_index        = 0;
1161     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1162     info.parent.status_addr = CVMX_NPI_INT_SUM;
1163     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1164     info.func               = __cvmx_error_display;
1165     info.user_info          = (long)
1166         "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
1167     fail |= cvmx_error_add(&info);
1168
1169     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1170     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1171     info.status_mask        = 1ull<<9 /* msc_msg */;
1172     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1173     info.enable_mask        = 1ull<<9 /* rmsc_msg */;
1174     info.flags              = 0;
1175     info.group              = CVMX_ERROR_GROUP_PCI;
1176     info.group_index        = 0;
1177     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1178     info.parent.status_addr = CVMX_NPI_INT_SUM;
1179     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1180     info.func               = __cvmx_error_display;
1181     info.user_info          = (long)
1182         "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
1183     fail |= cvmx_error_add(&info);
1184
1185     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1186     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1187     info.status_mask        = 1ull<<10 /* tsr_abt */;
1188     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1189     info.enable_mask        = 1ull<<10 /* rtsr_abt */;
1190     info.flags              = 0;
1191     info.group              = CVMX_ERROR_GROUP_PCI;
1192     info.group_index        = 0;
1193     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1194     info.parent.status_addr = CVMX_NPI_INT_SUM;
1195     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1196     info.func               = __cvmx_error_display;
1197     info.user_info          = (long)
1198         "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
1199     fail |= cvmx_error_add(&info);
1200
1201     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1202     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1203     info.status_mask        = 1ull<<11 /* serr */;
1204     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1205     info.enable_mask        = 1ull<<11 /* rserr */;
1206     info.flags              = 0;
1207     info.group              = CVMX_ERROR_GROUP_PCI;
1208     info.group_index        = 0;
1209     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1210     info.parent.status_addr = CVMX_NPI_INT_SUM;
1211     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1212     info.func               = __cvmx_error_display;
1213     info.user_info          = (long)
1214         "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
1215     fail |= cvmx_error_add(&info);
1216
1217     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1218     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1219     info.status_mask        = 1ull<<12 /* aperr */;
1220     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1221     info.enable_mask        = 1ull<<12 /* raperr */;
1222     info.flags              = 0;
1223     info.group              = CVMX_ERROR_GROUP_PCI;
1224     info.group_index        = 0;
1225     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1226     info.parent.status_addr = CVMX_NPI_INT_SUM;
1227     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1228     info.func               = __cvmx_error_display;
1229     info.user_info          = (long)
1230         "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
1231     fail |= cvmx_error_add(&info);
1232
1233     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1234     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1235     info.status_mask        = 1ull<<13 /* dperr */;
1236     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1237     info.enable_mask        = 1ull<<13 /* rdperr */;
1238     info.flags              = 0;
1239     info.group              = CVMX_ERROR_GROUP_PCI;
1240     info.group_index        = 0;
1241     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1242     info.parent.status_addr = CVMX_NPI_INT_SUM;
1243     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1244     info.func               = __cvmx_error_display;
1245     info.user_info          = (long)
1246         "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
1247     fail |= cvmx_error_add(&info);
1248
1249     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1250     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1251     info.status_mask        = 1ull<<14 /* ill_rwr */;
1252     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1253     info.enable_mask        = 1ull<<14 /* ill_rwr */;
1254     info.flags              = 0;
1255     info.group              = CVMX_ERROR_GROUP_PCI;
1256     info.group_index        = 0;
1257     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1258     info.parent.status_addr = CVMX_NPI_INT_SUM;
1259     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1260     info.func               = __cvmx_error_display;
1261     info.user_info          = (long)
1262         "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
1263     fail |= cvmx_error_add(&info);
1264
1265     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1266     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1267     info.status_mask        = 1ull<<15 /* ill_rrd */;
1268     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1269     info.enable_mask        = 1ull<<15 /* ill_rrd */;
1270     info.flags              = 0;
1271     info.group              = CVMX_ERROR_GROUP_PCI;
1272     info.group_index        = 0;
1273     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1274     info.parent.status_addr = CVMX_NPI_INT_SUM;
1275     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1276     info.func               = __cvmx_error_display;
1277     info.user_info          = (long)
1278         "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
1279     fail |= cvmx_error_add(&info);
1280
1281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1282     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1283     info.status_mask        = 1ull<<31 /* win_wr */;
1284     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1285     info.enable_mask        = 1ull<<31 /* win_wr */;
1286     info.flags              = 0;
1287     info.group              = CVMX_ERROR_GROUP_PCI;
1288     info.group_index        = 0;
1289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1290     info.parent.status_addr = CVMX_NPI_INT_SUM;
1291     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1292     info.func               = __cvmx_error_display;
1293     info.user_info          = (long)
1294         "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
1295         "    Read-Address Register took place.\n";
1296     fail |= cvmx_error_add(&info);
1297
1298     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1299     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1300     info.status_mask        = 1ull<<32 /* ill_wr */;
1301     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1302     info.enable_mask        = 1ull<<32 /* ill_wr */;
1303     info.flags              = 0;
1304     info.group              = CVMX_ERROR_GROUP_PCI;
1305     info.group_index        = 0;
1306     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1307     info.parent.status_addr = CVMX_NPI_INT_SUM;
1308     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1309     info.func               = __cvmx_error_display;
1310     info.user_info          = (long)
1311         "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
1312         "    when the mem area is disabled.\n";
1313     fail |= cvmx_error_add(&info);
1314
1315     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1316     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1317     info.status_mask        = 1ull<<33 /* ill_rd */;
1318     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1319     info.enable_mask        = 1ull<<33 /* ill_rd */;
1320     info.flags              = 0;
1321     info.group              = CVMX_ERROR_GROUP_PCI;
1322     info.group_index        = 0;
1323     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1324     info.parent.status_addr = CVMX_NPI_INT_SUM;
1325     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1326     info.func               = __cvmx_error_display;
1327     info.user_info          = (long)
1328         "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
1329         "    when the mem area is disabled.\n";
1330     fail |= cvmx_error_add(&info);
1331
1332     /* CVMX_GMXX_BAD_REG(0) */
1333     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1334     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1335     info.status_mask        = 1ull<<0 /* out_col */;
1336     info.enable_addr        = 0;
1337     info.enable_mask        = 0;
1338     info.flags              = 0;
1339     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1340     info.group_index        = 0;
1341     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1342     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1343     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1344     info.func               = __cvmx_error_display;
1345     info.user_info          = (long)
1346         "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
1347     fail |= cvmx_error_add(&info);
1348
1349     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1350     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1351     info.status_mask        = 1ull<<1 /* ncb_ovr */;
1352     info.enable_addr        = 0;
1353     info.enable_mask        = 0;
1354     info.flags              = 0;
1355     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1356     info.group_index        = 0;
1357     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1358     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1359     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1360     info.func               = __cvmx_error_display;
1361     info.user_info          = (long)
1362         "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
1363     fail |= cvmx_error_add(&info);
1364
1365     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1366     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1367     info.status_mask        = 0xffffull<<2 /* out_ovr */;
1368     info.enable_addr        = 0;
1369     info.enable_mask        = 0;
1370     info.flags              = 0;
1371     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1372     info.group_index        = 0;
1373     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1374     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1375     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1376     info.func               = __cvmx_error_display;
1377     info.user_info          = (long)
1378         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1379     fail |= cvmx_error_add(&info);
1380
1381     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1382     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1383     info.status_mask        = 0xfull<<22 /* loststat */;
1384     info.enable_addr        = 0;
1385     info.enable_mask        = 0;
1386     info.flags              = 0;
1387     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1388     info.group_index        = 0;
1389     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1390     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1391     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1392     info.func               = __cvmx_error_display;
1393     info.user_info          = (long)
1394         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
1395         "    TX Stats are corrupted\n";
1396     fail |= cvmx_error_add(&info);
1397
1398     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1399     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1400     info.status_mask        = 1ull<<26 /* statovr */;
1401     info.enable_addr        = 0;
1402     info.enable_mask        = 0;
1403     info.flags              = 0;
1404     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1405     info.group_index        = 0;
1406     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1407     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1408     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1409     info.func               = __cvmx_error_display;
1410     info.user_info          = (long)
1411         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
1412     fail |= cvmx_error_add(&info);
1413
1414     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1415     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1416     info.status_mask        = 0xfull<<27 /* inb_nxa */;
1417     info.enable_addr        = 0;
1418     info.enable_mask        = 0;
1419     info.flags              = 0;
1420     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1421     info.group_index        = 0;
1422     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1423     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1424     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1425     info.func               = __cvmx_error_display;
1426     info.user_info          = (long)
1427         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1428     fail |= cvmx_error_add(&info);
1429
1430     /* CVMX_GMXX_RXX_INT_REG(0,0) */
1431     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1432     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1433     info.status_mask        = 1ull<<1 /* carext */;
1434     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1435     info.enable_mask        = 1ull<<1 /* carext */;
1436     info.flags              = 0;
1437     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1438     info.group_index        = 0;
1439     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1440     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1441     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1442     info.func               = __cvmx_error_display;
1443     info.user_info          = (long)
1444         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
1445     fail |= cvmx_error_add(&info);
1446
1447     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1448     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1449     info.status_mask        = 1ull<<2 /* maxerr */;
1450     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1451     info.enable_mask        = 1ull<<2 /* maxerr */;
1452     info.flags              = 0;
1453     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1454     info.group_index        = 0;
1455     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1456     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1457     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1458     info.func               = __cvmx_error_display;
1459     info.user_info          = (long)
1460         "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
1461     fail |= cvmx_error_add(&info);
1462
1463     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1464     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1465     info.status_mask        = 1ull<<5 /* alnerr */;
1466     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1467     info.enable_mask        = 1ull<<5 /* alnerr */;
1468     info.flags              = 0;
1469     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1470     info.group_index        = 0;
1471     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1472     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1473     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1474     info.func               = __cvmx_error_display;
1475     info.user_info          = (long)
1476         "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
1477     fail |= cvmx_error_add(&info);
1478
1479     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1480     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1481     info.status_mask        = 1ull<<6 /* lenerr */;
1482     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1483     info.enable_mask        = 1ull<<6 /* lenerr */;
1484     info.flags              = 0;
1485     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1486     info.group_index        = 0;
1487     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1488     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1489     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1490     info.func               = __cvmx_error_display;
1491     info.user_info          = (long)
1492         "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
1493     fail |= cvmx_error_add(&info);
1494
1495     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1496     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1497     info.status_mask        = 1ull<<8 /* skperr */;
1498     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1499     info.enable_mask        = 1ull<<8 /* skperr */;
1500     info.flags              = 0;
1501     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1502     info.group_index        = 0;
1503     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1504     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1505     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1506     info.func               = __cvmx_error_display;
1507     info.user_info          = (long)
1508         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
1509     fail |= cvmx_error_add(&info);
1510
1511     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1512     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1513     info.status_mask        = 1ull<<9 /* niberr */;
1514     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1515     info.enable_mask        = 1ull<<9 /* niberr */;
1516     info.flags              = 0;
1517     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1518     info.group_index        = 0;
1519     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1520     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1521     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1522     info.func               = __cvmx_error_display;
1523     info.user_info          = (long)
1524         "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1525     fail |= cvmx_error_add(&info);
1526
1527     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1528     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1529     info.status_mask        = 1ull<<10 /* ovrerr */;
1530     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1531     info.enable_mask        = 1ull<<10 /* ovrerr */;
1532     info.flags              = 0;
1533     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1534     info.group_index        = 0;
1535     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1536     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1537     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1538     info.func               = __cvmx_error_display;
1539     info.user_info          = (long)
1540         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1541         "    This interrupt should never assert\n";
1542     fail |= cvmx_error_add(&info);
1543
1544     /* CVMX_GMXX_RXX_INT_REG(1,0) */
1545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1546     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1547     info.status_mask        = 1ull<<1 /* carext */;
1548     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1549     info.enable_mask        = 1ull<<1 /* carext */;
1550     info.flags              = 0;
1551     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1552     info.group_index        = 1;
1553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1554     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1555     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1556     info.func               = __cvmx_error_display;
1557     info.user_info          = (long)
1558         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
1559     fail |= cvmx_error_add(&info);
1560
1561     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1562     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1563     info.status_mask        = 1ull<<2 /* maxerr */;
1564     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1565     info.enable_mask        = 1ull<<2 /* maxerr */;
1566     info.flags              = 0;
1567     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1568     info.group_index        = 1;
1569     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1570     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1571     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1572     info.func               = __cvmx_error_display;
1573     info.user_info          = (long)
1574         "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
1575     fail |= cvmx_error_add(&info);
1576
1577     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1578     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1579     info.status_mask        = 1ull<<5 /* alnerr */;
1580     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1581     info.enable_mask        = 1ull<<5 /* alnerr */;
1582     info.flags              = 0;
1583     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1584     info.group_index        = 1;
1585     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1586     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1587     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1588     info.func               = __cvmx_error_display;
1589     info.user_info          = (long)
1590         "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
1591     fail |= cvmx_error_add(&info);
1592
1593     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1594     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1595     info.status_mask        = 1ull<<6 /* lenerr */;
1596     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1597     info.enable_mask        = 1ull<<6 /* lenerr */;
1598     info.flags              = 0;
1599     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1600     info.group_index        = 1;
1601     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1602     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1603     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1604     info.func               = __cvmx_error_display;
1605     info.user_info          = (long)
1606         "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
1607     fail |= cvmx_error_add(&info);
1608
1609     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1610     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1611     info.status_mask        = 1ull<<8 /* skperr */;
1612     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1613     info.enable_mask        = 1ull<<8 /* skperr */;
1614     info.flags              = 0;
1615     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1616     info.group_index        = 1;
1617     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1618     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1619     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1620     info.func               = __cvmx_error_display;
1621     info.user_info          = (long)
1622         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1623     fail |= cvmx_error_add(&info);
1624
1625     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1626     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1627     info.status_mask        = 1ull<<9 /* niberr */;
1628     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1629     info.enable_mask        = 1ull<<9 /* niberr */;
1630     info.flags              = 0;
1631     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1632     info.group_index        = 1;
1633     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1634     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1635     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1636     info.func               = __cvmx_error_display;
1637     info.user_info          = (long)
1638         "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1639     fail |= cvmx_error_add(&info);
1640
1641     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1642     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1643     info.status_mask        = 1ull<<10 /* ovrerr */;
1644     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1645     info.enable_mask        = 1ull<<10 /* ovrerr */;
1646     info.flags              = 0;
1647     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1648     info.group_index        = 1;
1649     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1650     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1651     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1652     info.func               = __cvmx_error_display;
1653     info.user_info          = (long)
1654         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1655         "    This interrupt should never assert\n";
1656     fail |= cvmx_error_add(&info);
1657
1658     /* CVMX_GMXX_RXX_INT_REG(2,0) */
1659     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1660     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1661     info.status_mask        = 1ull<<1 /* carext */;
1662     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1663     info.enable_mask        = 1ull<<1 /* carext */;
1664     info.flags              = 0;
1665     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1666     info.group_index        = 2;
1667     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1668     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1669     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1670     info.func               = __cvmx_error_display;
1671     info.user_info          = (long)
1672         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
1673     fail |= cvmx_error_add(&info);
1674
1675     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1676     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1677     info.status_mask        = 1ull<<2 /* maxerr */;
1678     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1679     info.enable_mask        = 1ull<<2 /* maxerr */;
1680     info.flags              = 0;
1681     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1682     info.group_index        = 2;
1683     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1684     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1685     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1686     info.func               = __cvmx_error_display;
1687     info.user_info          = (long)
1688         "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
1689     fail |= cvmx_error_add(&info);
1690
1691     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1692     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1693     info.status_mask        = 1ull<<5 /* alnerr */;
1694     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1695     info.enable_mask        = 1ull<<5 /* alnerr */;
1696     info.flags              = 0;
1697     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1698     info.group_index        = 2;
1699     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1700     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1701     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1702     info.func               = __cvmx_error_display;
1703     info.user_info          = (long)
1704         "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
1705     fail |= cvmx_error_add(&info);
1706
1707     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1708     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1709     info.status_mask        = 1ull<<6 /* lenerr */;
1710     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1711     info.enable_mask        = 1ull<<6 /* lenerr */;
1712     info.flags              = 0;
1713     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1714     info.group_index        = 2;
1715     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1716     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1717     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1718     info.func               = __cvmx_error_display;
1719     info.user_info          = (long)
1720         "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
1721     fail |= cvmx_error_add(&info);
1722
1723     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1724     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1725     info.status_mask        = 1ull<<8 /* skperr */;
1726     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1727     info.enable_mask        = 1ull<<8 /* skperr */;
1728     info.flags              = 0;
1729     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1730     info.group_index        = 2;
1731     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1732     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1733     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1734     info.func               = __cvmx_error_display;
1735     info.user_info          = (long)
1736         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
1737     fail |= cvmx_error_add(&info);
1738
1739     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1740     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1741     info.status_mask        = 1ull<<9 /* niberr */;
1742     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1743     info.enable_mask        = 1ull<<9 /* niberr */;
1744     info.flags              = 0;
1745     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1746     info.group_index        = 2;
1747     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1748     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1749     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1750     info.func               = __cvmx_error_display;
1751     info.user_info          = (long)
1752         "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1753     fail |= cvmx_error_add(&info);
1754
1755     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1756     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1757     info.status_mask        = 1ull<<10 /* ovrerr */;
1758     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1759     info.enable_mask        = 1ull<<10 /* ovrerr */;
1760     info.flags              = 0;
1761     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1762     info.group_index        = 2;
1763     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1764     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1765     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1766     info.func               = __cvmx_error_display;
1767     info.user_info          = (long)
1768         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1769         "    This interrupt should never assert\n";
1770     fail |= cvmx_error_add(&info);
1771
1772     /* CVMX_GMXX_RXX_INT_REG(3,0) */
1773     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1774     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1775     info.status_mask        = 1ull<<1 /* carext */;
1776     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1777     info.enable_mask        = 1ull<<1 /* carext */;
1778     info.flags              = 0;
1779     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1780     info.group_index        = 3;
1781     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1782     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1783     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1784     info.func               = __cvmx_error_display;
1785     info.user_info          = (long)
1786         "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
1787     fail |= cvmx_error_add(&info);
1788
1789     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1790     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1791     info.status_mask        = 1ull<<2 /* maxerr */;
1792     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1793     info.enable_mask        = 1ull<<2 /* maxerr */;
1794     info.flags              = 0;
1795     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1796     info.group_index        = 3;
1797     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1798     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1799     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1800     info.func               = __cvmx_error_display;
1801     info.user_info          = (long)
1802         "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
1803     fail |= cvmx_error_add(&info);
1804
1805     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1806     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1807     info.status_mask        = 1ull<<5 /* alnerr */;
1808     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1809     info.enable_mask        = 1ull<<5 /* alnerr */;
1810     info.flags              = 0;
1811     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1812     info.group_index        = 3;
1813     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1814     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1815     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1816     info.func               = __cvmx_error_display;
1817     info.user_info          = (long)
1818         "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
1819     fail |= cvmx_error_add(&info);
1820
1821     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1822     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1823     info.status_mask        = 1ull<<6 /* lenerr */;
1824     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1825     info.enable_mask        = 1ull<<6 /* lenerr */;
1826     info.flags              = 0;
1827     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1828     info.group_index        = 3;
1829     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1830     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1831     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1832     info.func               = __cvmx_error_display;
1833     info.user_info          = (long)
1834         "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
1835     fail |= cvmx_error_add(&info);
1836
1837     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1838     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1839     info.status_mask        = 1ull<<8 /* skperr */;
1840     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1841     info.enable_mask        = 1ull<<8 /* skperr */;
1842     info.flags              = 0;
1843     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1844     info.group_index        = 3;
1845     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1846     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1847     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1848     info.func               = __cvmx_error_display;
1849     info.user_info          = (long)
1850         "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
1851     fail |= cvmx_error_add(&info);
1852
1853     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1854     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1855     info.status_mask        = 1ull<<9 /* niberr */;
1856     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1857     info.enable_mask        = 1ull<<9 /* niberr */;
1858     info.flags              = 0;
1859     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1860     info.group_index        = 3;
1861     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1862     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1863     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1864     info.func               = __cvmx_error_display;
1865     info.user_info          = (long)
1866         "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1867     fail |= cvmx_error_add(&info);
1868
1869     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1870     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1871     info.status_mask        = 1ull<<10 /* ovrerr */;
1872     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1873     info.enable_mask        = 1ull<<10 /* ovrerr */;
1874     info.flags              = 0;
1875     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1876     info.group_index        = 3;
1877     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1878     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1879     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1880     info.func               = __cvmx_error_display;
1881     info.user_info          = (long)
1882         "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1883         "    This interrupt should never assert\n";
1884     fail |= cvmx_error_add(&info);
1885
1886     /* CVMX_GMXX_TX_INT_REG(0) */
1887     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1888     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
1889     info.status_mask        = 1ull<<0 /* pko_nxa */;
1890     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
1891     info.enable_mask        = 1ull<<0 /* pko_nxa */;
1892     info.flags              = 0;
1893     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1894     info.group_index        = 0;
1895     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1896     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1897     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1898     info.func               = __cvmx_error_display;
1899     info.user_info          = (long)
1900         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
1901     fail |= cvmx_error_add(&info);
1902
1903     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1904     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
1905     info.status_mask        = 1ull<<1 /* ncb_nxa */;
1906     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
1907     info.enable_mask        = 1ull<<1 /* ncb_nxa */;
1908     info.flags              = 0;
1909     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1910     info.group_index        = 0;
1911     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1912     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1913     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1914     info.func               = __cvmx_error_display;
1915     info.user_info          = (long)
1916         "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
1917     fail |= cvmx_error_add(&info);
1918
1919     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1920     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
1921     info.status_mask        = 0xfull<<2 /* undflw */;
1922     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
1923     info.enable_mask        = 0xfull<<2 /* undflw */;
1924     info.flags              = 0;
1925     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1926     info.group_index        = 0;
1927     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1928     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1929     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1930     info.func               = __cvmx_error_display;
1931     info.user_info          = (long)
1932         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
1933     fail |= cvmx_error_add(&info);
1934
1935     /* CVMX_GMXX_BAD_REG(1) */
1936     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1937     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1938     info.status_mask        = 1ull<<0 /* out_col */;
1939     info.enable_addr        = 0;
1940     info.enable_mask        = 0;
1941     info.flags              = 0;
1942     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1943     info.group_index        = 16;
1944     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1945     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1946     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1947     info.func               = __cvmx_error_display;
1948     info.user_info          = (long)
1949         "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
1950     fail |= cvmx_error_add(&info);
1951
1952     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1953     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1954     info.status_mask        = 1ull<<1 /* ncb_ovr */;
1955     info.enable_addr        = 0;
1956     info.enable_mask        = 0;
1957     info.flags              = 0;
1958     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1959     info.group_index        = 16;
1960     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1961     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1962     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1963     info.func               = __cvmx_error_display;
1964     info.user_info          = (long)
1965         "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
1966     fail |= cvmx_error_add(&info);
1967
1968     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1969     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1970     info.status_mask        = 0xffffull<<2 /* out_ovr */;
1971     info.enable_addr        = 0;
1972     info.enable_mask        = 0;
1973     info.flags              = 0;
1974     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1975     info.group_index        = 16;
1976     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1977     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1978     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1979     info.func               = __cvmx_error_display;
1980     info.user_info          = (long)
1981         "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1982     fail |= cvmx_error_add(&info);
1983
1984     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1985     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1986     info.status_mask        = 0xfull<<22 /* loststat */;
1987     info.enable_addr        = 0;
1988     info.enable_mask        = 0;
1989     info.flags              = 0;
1990     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1991     info.group_index        = 16;
1992     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1993     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1994     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1995     info.func               = __cvmx_error_display;
1996     info.user_info          = (long)
1997         "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
1998         "    TX Stats are corrupted\n";
1999     fail |= cvmx_error_add(&info);
2000
2001     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2002     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2003     info.status_mask        = 1ull<<26 /* statovr */;
2004     info.enable_addr        = 0;
2005     info.enable_mask        = 0;
2006     info.flags              = 0;
2007     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2008     info.group_index        = 16;
2009     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2010     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2011     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2012     info.func               = __cvmx_error_display;
2013     info.user_info          = (long)
2014         "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
2015     fail |= cvmx_error_add(&info);
2016
2017     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2018     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2019     info.status_mask        = 0xfull<<27 /* inb_nxa */;
2020     info.enable_addr        = 0;
2021     info.enable_mask        = 0;
2022     info.flags              = 0;
2023     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2024     info.group_index        = 16;
2025     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2026     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2027     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2028     info.func               = __cvmx_error_display;
2029     info.user_info          = (long)
2030         "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
2031     fail |= cvmx_error_add(&info);
2032
2033     /* CVMX_GMXX_RXX_INT_REG(0,1) */
2034     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2035     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2036     info.status_mask        = 1ull<<1 /* carext */;
2037     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2038     info.enable_mask        = 1ull<<1 /* carext */;
2039     info.flags              = 0;
2040     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2041     info.group_index        = 16;
2042     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2043     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2044     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2045     info.func               = __cvmx_error_display;
2046     info.user_info          = (long)
2047         "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
2048     fail |= cvmx_error_add(&info);
2049
2050     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2051     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2052     info.status_mask        = 1ull<<2 /* maxerr */;
2053     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2054     info.enable_mask        = 1ull<<2 /* maxerr */;
2055     info.flags              = 0;
2056     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2057     info.group_index        = 16;
2058     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2059     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2060     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2061     info.func               = __cvmx_error_display;
2062     info.user_info          = (long)
2063         "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
2064     fail |= cvmx_error_add(&info);
2065
2066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2067     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2068     info.status_mask        = 1ull<<5 /* alnerr */;
2069     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2070     info.enable_mask        = 1ull<<5 /* alnerr */;
2071     info.flags              = 0;
2072     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2073     info.group_index        = 16;
2074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2075     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2076     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2077     info.func               = __cvmx_error_display;
2078     info.user_info          = (long)
2079         "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
2080     fail |= cvmx_error_add(&info);
2081
2082     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2083     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2084     info.status_mask        = 1ull<<6 /* lenerr */;
2085     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2086     info.enable_mask        = 1ull<<6 /* lenerr */;
2087     info.flags              = 0;
2088     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2089     info.group_index        = 16;
2090     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2091     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2092     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2093     info.func               = __cvmx_error_display;
2094     info.user_info          = (long)
2095         "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
2096     fail |= cvmx_error_add(&info);
2097
2098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2099     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2100     info.status_mask        = 1ull<<8 /* skperr */;
2101     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2102     info.enable_mask        = 1ull<<8 /* skperr */;
2103     info.flags              = 0;
2104     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2105     info.group_index        = 16;
2106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2107     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2108     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2109     info.func               = __cvmx_error_display;
2110     info.user_info          = (long)
2111         "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
2112     fail |= cvmx_error_add(&info);
2113
2114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2115     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2116     info.status_mask        = 1ull<<9 /* niberr */;
2117     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2118     info.enable_mask        = 1ull<<9 /* niberr */;
2119     info.flags              = 0;
2120     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2121     info.group_index        = 16;
2122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2123     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2124     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2125     info.func               = __cvmx_error_display;
2126     info.user_info          = (long)
2127         "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2128     fail |= cvmx_error_add(&info);
2129
2130     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2131     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2132     info.status_mask        = 1ull<<10 /* ovrerr */;
2133     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2134     info.enable_mask        = 1ull<<10 /* ovrerr */;
2135     info.flags              = 0;
2136     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2137     info.group_index        = 16;
2138     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2139     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2140     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2141     info.func               = __cvmx_error_display;
2142     info.user_info          = (long)
2143         "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2144         "    This interrupt should never assert\n";
2145     fail |= cvmx_error_add(&info);
2146
2147     /* CVMX_GMXX_RXX_INT_REG(1,1) */
2148     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2149     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2150     info.status_mask        = 1ull<<1 /* carext */;
2151     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2152     info.enable_mask        = 1ull<<1 /* carext */;
2153     info.flags              = 0;
2154     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2155     info.group_index        = 17;
2156     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2157     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2158     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2159     info.func               = __cvmx_error_display;
2160     info.user_info          = (long)
2161         "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
2162     fail |= cvmx_error_add(&info);
2163
2164     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2165     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2166     info.status_mask        = 1ull<<2 /* maxerr */;
2167     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2168     info.enable_mask        = 1ull<<2 /* maxerr */;
2169     info.flags              = 0;
2170     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2171     info.group_index        = 17;
2172     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2173     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2174     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2175     info.func               = __cvmx_error_display;
2176     info.user_info          = (long)
2177         "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
2178     fail |= cvmx_error_add(&info);
2179
2180     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2181     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2182     info.status_mask        = 1ull<<5 /* alnerr */;
2183     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2184     info.enable_mask        = 1ull<<5 /* alnerr */;
2185     info.flags              = 0;
2186     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2187     info.group_index        = 17;
2188     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2189     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2190     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2191     info.func               = __cvmx_error_display;
2192     info.user_info          = (long)
2193         "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
2194     fail |= cvmx_error_add(&info);
2195
2196     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2197     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2198     info.status_mask        = 1ull<<6 /* lenerr */;
2199     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2200     info.enable_mask        = 1ull<<6 /* lenerr */;
2201     info.flags              = 0;
2202     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2203     info.group_index        = 17;
2204     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2205     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2206     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2207     info.func               = __cvmx_error_display;
2208     info.user_info          = (long)
2209         "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
2210     fail |= cvmx_error_add(&info);
2211
2212     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2213     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2214     info.status_mask        = 1ull<<8 /* skperr */;
2215     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2216     info.enable_mask        = 1ull<<8 /* skperr */;
2217     info.flags              = 0;
2218     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2219     info.group_index        = 17;
2220     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2221     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2222     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2223     info.func               = __cvmx_error_display;
2224     info.user_info          = (long)
2225         "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
2226     fail |= cvmx_error_add(&info);
2227
2228     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2229     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2230     info.status_mask        = 1ull<<9 /* niberr */;
2231     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2232     info.enable_mask        = 1ull<<9 /* niberr */;
2233     info.flags              = 0;
2234     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2235     info.group_index        = 17;
2236     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2237     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2238     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2239     info.func               = __cvmx_error_display;
2240     info.user_info          = (long)
2241         "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2242     fail |= cvmx_error_add(&info);
2243
2244     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2245     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2246     info.status_mask        = 1ull<<10 /* ovrerr */;
2247     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2248     info.enable_mask        = 1ull<<10 /* ovrerr */;
2249     info.flags              = 0;
2250     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2251     info.group_index        = 17;
2252     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2253     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2254     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2255     info.func               = __cvmx_error_display;
2256     info.user_info          = (long)
2257         "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2258         "    This interrupt should never assert\n";
2259     fail |= cvmx_error_add(&info);
2260
2261     /* CVMX_GMXX_RXX_INT_REG(2,1) */
2262     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2263     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2264     info.status_mask        = 1ull<<1 /* carext */;
2265     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2266     info.enable_mask        = 1ull<<1 /* carext */;
2267     info.flags              = 0;
2268     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2269     info.group_index        = 18;
2270     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2271     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2272     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2273     info.func               = __cvmx_error_display;
2274     info.user_info          = (long)
2275         "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
2276     fail |= cvmx_error_add(&info);
2277
2278     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2279     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2280     info.status_mask        = 1ull<<2 /* maxerr */;
2281     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2282     info.enable_mask        = 1ull<<2 /* maxerr */;
2283     info.flags              = 0;
2284     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2285     info.group_index        = 18;
2286     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2287     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2288     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2289     info.func               = __cvmx_error_display;
2290     info.user_info          = (long)
2291         "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
2292     fail |= cvmx_error_add(&info);
2293
2294     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2295     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2296     info.status_mask        = 1ull<<5 /* alnerr */;
2297     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2298     info.enable_mask        = 1ull<<5 /* alnerr */;
2299     info.flags              = 0;
2300     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2301     info.group_index        = 18;
2302     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2303     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2304     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2305     info.func               = __cvmx_error_display;
2306     info.user_info          = (long)
2307         "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
2308     fail |= cvmx_error_add(&info);
2309
2310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2311     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2312     info.status_mask        = 1ull<<6 /* lenerr */;
2313     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2314     info.enable_mask        = 1ull<<6 /* lenerr */;
2315     info.flags              = 0;
2316     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2317     info.group_index        = 18;
2318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2319     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2320     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2321     info.func               = __cvmx_error_display;
2322     info.user_info          = (long)
2323         "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
2324     fail |= cvmx_error_add(&info);
2325
2326     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2327     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2328     info.status_mask        = 1ull<<8 /* skperr */;
2329     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2330     info.enable_mask        = 1ull<<8 /* skperr */;
2331     info.flags              = 0;
2332     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2333     info.group_index        = 18;
2334     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2335     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2336     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2337     info.func               = __cvmx_error_display;
2338     info.user_info          = (long)
2339         "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
2340     fail |= cvmx_error_add(&info);
2341
2342     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2343     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2344     info.status_mask        = 1ull<<9 /* niberr */;
2345     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2346     info.enable_mask        = 1ull<<9 /* niberr */;
2347     info.flags              = 0;
2348     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2349     info.group_index        = 18;
2350     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2351     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2352     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2353     info.func               = __cvmx_error_display;
2354     info.user_info          = (long)
2355         "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2356     fail |= cvmx_error_add(&info);
2357
2358     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2359     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2360     info.status_mask        = 1ull<<10 /* ovrerr */;
2361     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2362     info.enable_mask        = 1ull<<10 /* ovrerr */;
2363     info.flags              = 0;
2364     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2365     info.group_index        = 18;
2366     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2367     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2368     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2369     info.func               = __cvmx_error_display;
2370     info.user_info          = (long)
2371         "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2372         "    This interrupt should never assert\n";
2373     fail |= cvmx_error_add(&info);
2374
2375     /* CVMX_GMXX_RXX_INT_REG(3,1) */
2376     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2377     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2378     info.status_mask        = 1ull<<1 /* carext */;
2379     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2380     info.enable_mask        = 1ull<<1 /* carext */;
2381     info.flags              = 0;
2382     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2383     info.group_index        = 19;
2384     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2385     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2386     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2387     info.func               = __cvmx_error_display;
2388     info.user_info          = (long)
2389         "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
2390     fail |= cvmx_error_add(&info);
2391
2392     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2393     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2394     info.status_mask        = 1ull<<2 /* maxerr */;
2395     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2396     info.enable_mask        = 1ull<<2 /* maxerr */;
2397     info.flags              = 0;
2398     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2399     info.group_index        = 19;
2400     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2401     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2402     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2403     info.func               = __cvmx_error_display;
2404     info.user_info          = (long)
2405         "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
2406     fail |= cvmx_error_add(&info);
2407
2408     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2409     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2410     info.status_mask        = 1ull<<5 /* alnerr */;
2411     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2412     info.enable_mask        = 1ull<<5 /* alnerr */;
2413     info.flags              = 0;
2414     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2415     info.group_index        = 19;
2416     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2417     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2418     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2419     info.func               = __cvmx_error_display;
2420     info.user_info          = (long)
2421         "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
2422     fail |= cvmx_error_add(&info);
2423
2424     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2425     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2426     info.status_mask        = 1ull<<6 /* lenerr */;
2427     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2428     info.enable_mask        = 1ull<<6 /* lenerr */;
2429     info.flags              = 0;
2430     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2431     info.group_index        = 19;
2432     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2433     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2434     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2435     info.func               = __cvmx_error_display;
2436     info.user_info          = (long)
2437         "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
2438     fail |= cvmx_error_add(&info);
2439
2440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2441     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2442     info.status_mask        = 1ull<<8 /* skperr */;
2443     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2444     info.enable_mask        = 1ull<<8 /* skperr */;
2445     info.flags              = 0;
2446     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2447     info.group_index        = 19;
2448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2449     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2450     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2451     info.func               = __cvmx_error_display;
2452     info.user_info          = (long)
2453         "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
2454     fail |= cvmx_error_add(&info);
2455
2456     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2457     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2458     info.status_mask        = 1ull<<9 /* niberr */;
2459     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2460     info.enable_mask        = 1ull<<9 /* niberr */;
2461     info.flags              = 0;
2462     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2463     info.group_index        = 19;
2464     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2465     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2466     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2467     info.func               = __cvmx_error_display;
2468     info.user_info          = (long)
2469         "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2470     fail |= cvmx_error_add(&info);
2471
2472     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2473     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2474     info.status_mask        = 1ull<<10 /* ovrerr */;
2475     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2476     info.enable_mask        = 1ull<<10 /* ovrerr */;
2477     info.flags              = 0;
2478     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2479     info.group_index        = 19;
2480     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2481     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2482     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2483     info.func               = __cvmx_error_display;
2484     info.user_info          = (long)
2485         "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2486         "    This interrupt should never assert\n";
2487     fail |= cvmx_error_add(&info);
2488
2489     /* CVMX_GMXX_TX_INT_REG(1) */
2490     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2491     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2492     info.status_mask        = 1ull<<0 /* pko_nxa */;
2493     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2494     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2495     info.flags              = 0;
2496     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2497     info.group_index        = 16;
2498     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2499     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2500     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2501     info.func               = __cvmx_error_display;
2502     info.user_info          = (long)
2503         "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2504     fail |= cvmx_error_add(&info);
2505
2506     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2507     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2508     info.status_mask        = 1ull<<1 /* ncb_nxa */;
2509     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2510     info.enable_mask        = 1ull<<1 /* ncb_nxa */;
2511     info.flags              = 0;
2512     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2513     info.group_index        = 16;
2514     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2515     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2516     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2517     info.func               = __cvmx_error_display;
2518     info.user_info          = (long)
2519         "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
2520     fail |= cvmx_error_add(&info);
2521
2522     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2523     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2524     info.status_mask        = 0xfull<<2 /* undflw */;
2525     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2526     info.enable_mask        = 0xfull<<2 /* undflw */;
2527     info.flags              = 0;
2528     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2529     info.group_index        = 16;
2530     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2531     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2532     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2533     info.func               = __cvmx_error_display;
2534     info.user_info          = (long)
2535         "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
2536     fail |= cvmx_error_add(&info);
2537
2538     /* CVMX_IPD_INT_SUM */
2539     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2540     info.status_addr        = CVMX_IPD_INT_SUM;
2541     info.status_mask        = 1ull<<0 /* prc_par0 */;
2542     info.enable_addr        = CVMX_IPD_INT_ENB;
2543     info.enable_mask        = 1ull<<0 /* prc_par0 */;
2544     info.flags              = 0;
2545     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2546     info.group_index        = 0;
2547     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2548     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2549     info.parent.status_mask = 1ull<<9 /* ipd */;
2550     info.func               = __cvmx_error_display;
2551     info.user_info          = (long)
2552         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2553         "    [31:0] of the PBM memory.\n";
2554     fail |= cvmx_error_add(&info);
2555
2556     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2557     info.status_addr        = CVMX_IPD_INT_SUM;
2558     info.status_mask        = 1ull<<1 /* prc_par1 */;
2559     info.enable_addr        = CVMX_IPD_INT_ENB;
2560     info.enable_mask        = 1ull<<1 /* prc_par1 */;
2561     info.flags              = 0;
2562     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2563     info.group_index        = 0;
2564     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2565     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2566     info.parent.status_mask = 1ull<<9 /* ipd */;
2567     info.func               = __cvmx_error_display;
2568     info.user_info          = (long)
2569         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2570         "    [63:32] of the PBM memory.\n";
2571     fail |= cvmx_error_add(&info);
2572
2573     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2574     info.status_addr        = CVMX_IPD_INT_SUM;
2575     info.status_mask        = 1ull<<2 /* prc_par2 */;
2576     info.enable_addr        = CVMX_IPD_INT_ENB;
2577     info.enable_mask        = 1ull<<2 /* prc_par2 */;
2578     info.flags              = 0;
2579     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2580     info.group_index        = 0;
2581     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2582     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2583     info.parent.status_mask = 1ull<<9 /* ipd */;
2584     info.func               = __cvmx_error_display;
2585     info.user_info          = (long)
2586         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2587         "    [95:64] of the PBM memory.\n";
2588     fail |= cvmx_error_add(&info);
2589
2590     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2591     info.status_addr        = CVMX_IPD_INT_SUM;
2592     info.status_mask        = 1ull<<3 /* prc_par3 */;
2593     info.enable_addr        = CVMX_IPD_INT_ENB;
2594     info.enable_mask        = 1ull<<3 /* prc_par3 */;
2595     info.flags              = 0;
2596     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2597     info.group_index        = 0;
2598     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2599     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2600     info.parent.status_mask = 1ull<<9 /* ipd */;
2601     info.func               = __cvmx_error_display;
2602     info.user_info          = (long)
2603         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2604         "    [127:96] of the PBM memory.\n";
2605     fail |= cvmx_error_add(&info);
2606
2607     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2608     info.status_addr        = CVMX_IPD_INT_SUM;
2609     info.status_mask        = 1ull<<4 /* bp_sub */;
2610     info.enable_addr        = CVMX_IPD_INT_ENB;
2611     info.enable_mask        = 1ull<<4 /* bp_sub */;
2612     info.flags              = 0;
2613     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2614     info.group_index        = 0;
2615     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2616     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2617     info.parent.status_mask = 1ull<<9 /* ipd */;
2618     info.func               = __cvmx_error_display;
2619     info.user_info          = (long)
2620         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2621         "    supplied illegal value.\n";
2622     fail |= cvmx_error_add(&info);
2623
2624     /* CVMX_SPXX_INT_REG(0) */
2625     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2626     info.status_addr        = CVMX_SPXX_INT_REG(0);
2627     info.status_mask        = 1ull<<0 /* prtnxa */;
2628     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2629     info.enable_mask        = 1ull<<0 /* prtnxa */;
2630     info.flags              = 0;
2631     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2632     info.group_index        = 0;
2633     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2634     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2635     info.parent.status_mask = 1ull<<18 /* spx0 */;
2636     info.func               = __cvmx_error_display;
2637     info.user_info          = (long)
2638         "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
2639     fail |= cvmx_error_add(&info);
2640
2641     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2642     info.status_addr        = CVMX_SPXX_INT_REG(0);
2643     info.status_mask        = 1ull<<1 /* abnorm */;
2644     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2645     info.enable_mask        = 1ull<<1 /* abnorm */;
2646     info.flags              = 0;
2647     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2648     info.group_index        = 0;
2649     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2650     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2651     info.parent.status_mask = 1ull<<18 /* spx0 */;
2652     info.func               = __cvmx_error_display;
2653     info.user_info          = (long)
2654         "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
2655     fail |= cvmx_error_add(&info);
2656
2657     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2658     info.status_addr        = CVMX_SPXX_INT_REG(0);
2659     info.status_mask        = 1ull<<4 /* spiovr */;
2660     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2661     info.enable_mask        = 1ull<<4 /* spiovr */;
2662     info.flags              = 0;
2663     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2664     info.group_index        = 0;
2665     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2666     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2667     info.parent.status_mask = 1ull<<18 /* spx0 */;
2668     info.func               = __cvmx_error_display;
2669     info.user_info          = (long)
2670         "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
2671     fail |= cvmx_error_add(&info);
2672
2673     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2674     info.status_addr        = CVMX_SPXX_INT_REG(0);
2675     info.status_mask        = 1ull<<5 /* clserr */;
2676     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2677     info.enable_mask        = 1ull<<5 /* clserr */;
2678     info.flags              = 0;
2679     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2680     info.group_index        = 0;
2681     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2682     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2683     info.parent.status_mask = 1ull<<18 /* spx0 */;
2684     info.func               = __cvmx_error_display;
2685     info.user_info          = (long)
2686         "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
2687     fail |= cvmx_error_add(&info);
2688
2689     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2690     info.status_addr        = CVMX_SPXX_INT_REG(0);
2691     info.status_mask        = 1ull<<6 /* drwnng */;
2692     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2693     info.enable_mask        = 1ull<<6 /* drwnng */;
2694     info.flags              = 0;
2695     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2696     info.group_index        = 0;
2697     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2698     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2699     info.parent.status_mask = 1ull<<18 /* spx0 */;
2700     info.func               = __cvmx_error_display;
2701     info.user_info          = (long)
2702         "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
2703     fail |= cvmx_error_add(&info);
2704
2705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2706     info.status_addr        = CVMX_SPXX_INT_REG(0);
2707     info.status_mask        = 1ull<<7 /* rsverr */;
2708     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2709     info.enable_mask        = 1ull<<7 /* rsverr */;
2710     info.flags              = 0;
2711     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2712     info.group_index        = 0;
2713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2715     info.parent.status_mask = 1ull<<18 /* spx0 */;
2716     info.func               = __cvmx_error_display;
2717     info.user_info          = (long)
2718         "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
2719     fail |= cvmx_error_add(&info);
2720
2721     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2722     info.status_addr        = CVMX_SPXX_INT_REG(0);
2723     info.status_mask        = 1ull<<8 /* tpaovr */;
2724     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2725     info.enable_mask        = 1ull<<8 /* tpaovr */;
2726     info.flags              = 0;
2727     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2728     info.group_index        = 0;
2729     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2730     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2731     info.parent.status_mask = 1ull<<18 /* spx0 */;
2732     info.func               = __cvmx_error_display;
2733     info.user_info          = (long)
2734         "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
2735     fail |= cvmx_error_add(&info);
2736
2737     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2738     info.status_addr        = CVMX_SPXX_INT_REG(0);
2739     info.status_mask        = 1ull<<9 /* diperr */;
2740     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2741     info.enable_mask        = 1ull<<9 /* diperr */;
2742     info.flags              = 0;
2743     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2744     info.group_index        = 0;
2745     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2746     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2747     info.parent.status_mask = 1ull<<18 /* spx0 */;
2748     info.func               = __cvmx_error_display;
2749     info.user_info          = (long)
2750         "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
2751     fail |= cvmx_error_add(&info);
2752
2753     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2754     info.status_addr        = CVMX_SPXX_INT_REG(0);
2755     info.status_mask        = 1ull<<10 /* syncerr */;
2756     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2757     info.enable_mask        = 1ull<<10 /* syncerr */;
2758     info.flags              = 0;
2759     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2760     info.group_index        = 0;
2761     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2762     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2763     info.parent.status_mask = 1ull<<18 /* spx0 */;
2764     info.func               = __cvmx_error_display;
2765     info.user_info          = (long)
2766         "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
2767         "    SPX_ERR_CTL[ERRCNT]\n";
2768     fail |= cvmx_error_add(&info);
2769
2770     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2771     info.status_addr        = CVMX_SPXX_INT_REG(0);
2772     info.status_mask        = 1ull<<11 /* calerr */;
2773     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
2774     info.enable_mask        = 1ull<<11 /* calerr */;
2775     info.flags              = 0;
2776     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2777     info.group_index        = 0;
2778     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2779     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2780     info.parent.status_mask = 1ull<<18 /* spx0 */;
2781     info.func               = __cvmx_error_display;
2782     info.user_info          = (long)
2783         "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
2784     fail |= cvmx_error_add(&info);
2785
2786     /* CVMX_STXX_INT_REG(0) */
2787     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2788     info.status_addr        = CVMX_STXX_INT_REG(0);
2789     info.status_mask        = 1ull<<0 /* calpar0 */;
2790     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2791     info.enable_mask        = 1ull<<0 /* calpar0 */;
2792     info.flags              = 0;
2793     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2794     info.group_index        = 0;
2795     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2796     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2797     info.parent.status_mask = 1ull<<18 /* spx0 */;
2798     info.func               = __cvmx_error_display;
2799     info.user_info          = (long)
2800         "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
2801     fail |= cvmx_error_add(&info);
2802
2803     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2804     info.status_addr        = CVMX_STXX_INT_REG(0);
2805     info.status_mask        = 1ull<<1 /* calpar1 */;
2806     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2807     info.enable_mask        = 1ull<<1 /* calpar1 */;
2808     info.flags              = 0;
2809     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2810     info.group_index        = 0;
2811     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2812     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2813     info.parent.status_mask = 1ull<<18 /* spx0 */;
2814     info.func               = __cvmx_error_display;
2815     info.user_info          = (long)
2816         "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
2817     fail |= cvmx_error_add(&info);
2818
2819     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2820     info.status_addr        = CVMX_STXX_INT_REG(0);
2821     info.status_mask        = 1ull<<2 /* ovrbst */;
2822     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2823     info.enable_mask        = 1ull<<2 /* ovrbst */;
2824     info.flags              = 0;
2825     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2826     info.group_index        = 0;
2827     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2828     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2829     info.parent.status_mask = 1ull<<18 /* spx0 */;
2830     info.func               = __cvmx_error_display;
2831     info.user_info          = (long)
2832         "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
2833     fail |= cvmx_error_add(&info);
2834
2835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2836     info.status_addr        = CVMX_STXX_INT_REG(0);
2837     info.status_mask        = 1ull<<3 /* datovr */;
2838     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2839     info.enable_mask        = 1ull<<3 /* datovr */;
2840     info.flags              = 0;
2841     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2842     info.group_index        = 0;
2843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2844     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2845     info.parent.status_mask = 1ull<<18 /* spx0 */;
2846     info.func               = __cvmx_error_display;
2847     info.user_info          = (long)
2848         "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
2849     fail |= cvmx_error_add(&info);
2850
2851     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2852     info.status_addr        = CVMX_STXX_INT_REG(0);
2853     info.status_mask        = 1ull<<4 /* diperr */;
2854     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2855     info.enable_mask        = 1ull<<4 /* diperr */;
2856     info.flags              = 0;
2857     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2858     info.group_index        = 0;
2859     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2860     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2861     info.parent.status_mask = 1ull<<18 /* spx0 */;
2862     info.func               = __cvmx_error_display;
2863     info.user_info          = (long)
2864         "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
2865     fail |= cvmx_error_add(&info);
2866
2867     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2868     info.status_addr        = CVMX_STXX_INT_REG(0);
2869     info.status_mask        = 1ull<<5 /* nosync */;
2870     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2871     info.enable_mask        = 1ull<<5 /* nosync */;
2872     info.flags              = 0;
2873     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2874     info.group_index        = 0;
2875     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2876     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2877     info.parent.status_mask = 1ull<<18 /* spx0 */;
2878     info.func               = __cvmx_error_display;
2879     info.user_info          = (long)
2880         "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
2881     fail |= cvmx_error_add(&info);
2882
2883     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2884     info.status_addr        = CVMX_STXX_INT_REG(0);
2885     info.status_mask        = 1ull<<6 /* unxfrm */;
2886     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2887     info.enable_mask        = 1ull<<6 /* unxfrm */;
2888     info.flags              = 0;
2889     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2890     info.group_index        = 0;
2891     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2892     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2893     info.parent.status_mask = 1ull<<18 /* spx0 */;
2894     info.func               = __cvmx_error_display;
2895     info.user_info          = (long)
2896         "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
2897     fail |= cvmx_error_add(&info);
2898
2899     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2900     info.status_addr        = CVMX_STXX_INT_REG(0);
2901     info.status_mask        = 1ull<<7 /* frmerr */;
2902     info.enable_addr        = CVMX_STXX_INT_MSK(0);
2903     info.enable_mask        = 1ull<<7 /* frmerr */;
2904     info.flags              = 0;
2905     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2906     info.group_index        = 0;
2907     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2908     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2909     info.parent.status_mask = 1ull<<18 /* spx0 */;
2910     info.func               = __cvmx_error_display;
2911     info.user_info          = (long)
2912         "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
2913     fail |= cvmx_error_add(&info);
2914
2915     /* CVMX_POW_ECC_ERR */
2916     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2917     info.status_addr        = CVMX_POW_ECC_ERR;
2918     info.status_mask        = 1ull<<0 /* sbe */;
2919     info.enable_addr        = CVMX_POW_ECC_ERR;
2920     info.enable_mask        = 1ull<<2 /* sbe_ie */;
2921     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2922     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2923     info.group_index        = 0;
2924     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2925     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2926     info.parent.status_mask = 1ull<<12 /* pow */;
2927     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
2928     info.user_info          = (long)
2929         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2930     fail |= cvmx_error_add(&info);
2931
2932     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2933     info.status_addr        = CVMX_POW_ECC_ERR;
2934     info.status_mask        = 1ull<<1 /* dbe */;
2935     info.enable_addr        = CVMX_POW_ECC_ERR;
2936     info.enable_mask        = 1ull<<3 /* dbe_ie */;
2937     info.flags              = 0;
2938     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2939     info.group_index        = 0;
2940     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2941     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2942     info.parent.status_mask = 1ull<<12 /* pow */;
2943     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
2944     info.user_info          = (long)
2945         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2946     fail |= cvmx_error_add(&info);
2947
2948     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2949     info.status_addr        = CVMX_POW_ECC_ERR;
2950     info.status_mask        = 1ull<<12 /* rpe */;
2951     info.enable_addr        = CVMX_POW_ECC_ERR;
2952     info.enable_mask        = 1ull<<13 /* rpe_ie */;
2953     info.flags              = 0;
2954     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2955     info.group_index        = 0;
2956     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2957     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2958     info.parent.status_mask = 1ull<<12 /* pow */;
2959     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
2960     info.user_info          = (long)
2961         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2962     fail |= cvmx_error_add(&info);
2963
2964     /* CVMX_SPXX_INT_REG(1) */
2965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2966     info.status_addr        = CVMX_SPXX_INT_REG(1);
2967     info.status_mask        = 1ull<<0 /* prtnxa */;
2968     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
2969     info.enable_mask        = 1ull<<0 /* prtnxa */;
2970     info.flags              = 0;
2971     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2972     info.group_index        = 16;
2973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2974     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2975     info.parent.status_mask = 1ull<<19 /* spx1 */;
2976     info.func               = __cvmx_error_display;
2977     info.user_info          = (long)
2978         "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
2979     fail |= cvmx_error_add(&info);
2980
2981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2982     info.status_addr        = CVMX_SPXX_INT_REG(1);
2983     info.status_mask        = 1ull<<1 /* abnorm */;
2984     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
2985     info.enable_mask        = 1ull<<1 /* abnorm */;
2986     info.flags              = 0;
2987     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2988     info.group_index        = 16;
2989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2990     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2991     info.parent.status_mask = 1ull<<19 /* spx1 */;
2992     info.func               = __cvmx_error_display;
2993     info.user_info          = (long)
2994         "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
2995     fail |= cvmx_error_add(&info);
2996
2997     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2998     info.status_addr        = CVMX_SPXX_INT_REG(1);
2999     info.status_mask        = 1ull<<4 /* spiovr */;
3000     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3001     info.enable_mask        = 1ull<<4 /* spiovr */;
3002     info.flags              = 0;
3003     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3004     info.group_index        = 16;
3005     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3006     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3007     info.parent.status_mask = 1ull<<19 /* spx1 */;
3008     info.func               = __cvmx_error_display;
3009     info.user_info          = (long)
3010         "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
3011     fail |= cvmx_error_add(&info);
3012
3013     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3014     info.status_addr        = CVMX_SPXX_INT_REG(1);
3015     info.status_mask        = 1ull<<5 /* clserr */;
3016     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3017     info.enable_mask        = 1ull<<5 /* clserr */;
3018     info.flags              = 0;
3019     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3020     info.group_index        = 16;
3021     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3022     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3023     info.parent.status_mask = 1ull<<19 /* spx1 */;
3024     info.func               = __cvmx_error_display;
3025     info.user_info          = (long)
3026         "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
3027     fail |= cvmx_error_add(&info);
3028
3029     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3030     info.status_addr        = CVMX_SPXX_INT_REG(1);
3031     info.status_mask        = 1ull<<6 /* drwnng */;
3032     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3033     info.enable_mask        = 1ull<<6 /* drwnng */;
3034     info.flags              = 0;
3035     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3036     info.group_index        = 16;
3037     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3038     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3039     info.parent.status_mask = 1ull<<19 /* spx1 */;
3040     info.func               = __cvmx_error_display;
3041     info.user_info          = (long)
3042         "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
3043     fail |= cvmx_error_add(&info);
3044
3045     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3046     info.status_addr        = CVMX_SPXX_INT_REG(1);
3047     info.status_mask        = 1ull<<7 /* rsverr */;
3048     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3049     info.enable_mask        = 1ull<<7 /* rsverr */;
3050     info.flags              = 0;
3051     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3052     info.group_index        = 16;
3053     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3054     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3055     info.parent.status_mask = 1ull<<19 /* spx1 */;
3056     info.func               = __cvmx_error_display;
3057     info.user_info          = (long)
3058         "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
3059     fail |= cvmx_error_add(&info);
3060
3061     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3062     info.status_addr        = CVMX_SPXX_INT_REG(1);
3063     info.status_mask        = 1ull<<8 /* tpaovr */;
3064     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3065     info.enable_mask        = 1ull<<8 /* tpaovr */;
3066     info.flags              = 0;
3067     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3068     info.group_index        = 16;
3069     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3070     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3071     info.parent.status_mask = 1ull<<19 /* spx1 */;
3072     info.func               = __cvmx_error_display;
3073     info.user_info          = (long)
3074         "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
3075     fail |= cvmx_error_add(&info);
3076
3077     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3078     info.status_addr        = CVMX_SPXX_INT_REG(1);
3079     info.status_mask        = 1ull<<9 /* diperr */;
3080     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3081     info.enable_mask        = 1ull<<9 /* diperr */;
3082     info.flags              = 0;
3083     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3084     info.group_index        = 16;
3085     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3086     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3087     info.parent.status_mask = 1ull<<19 /* spx1 */;
3088     info.func               = __cvmx_error_display;
3089     info.user_info          = (long)
3090         "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
3091     fail |= cvmx_error_add(&info);
3092
3093     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3094     info.status_addr        = CVMX_SPXX_INT_REG(1);
3095     info.status_mask        = 1ull<<10 /* syncerr */;
3096     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3097     info.enable_mask        = 1ull<<10 /* syncerr */;
3098     info.flags              = 0;
3099     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3100     info.group_index        = 16;
3101     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3102     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3103     info.parent.status_mask = 1ull<<19 /* spx1 */;
3104     info.func               = __cvmx_error_display;
3105     info.user_info          = (long)
3106         "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
3107         "    SPX_ERR_CTL[ERRCNT]\n";
3108     fail |= cvmx_error_add(&info);
3109
3110     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3111     info.status_addr        = CVMX_SPXX_INT_REG(1);
3112     info.status_mask        = 1ull<<11 /* calerr */;
3113     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3114     info.enable_mask        = 1ull<<11 /* calerr */;
3115     info.flags              = 0;
3116     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3117     info.group_index        = 16;
3118     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3119     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3120     info.parent.status_mask = 1ull<<19 /* spx1 */;
3121     info.func               = __cvmx_error_display;
3122     info.user_info          = (long)
3123         "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
3124     fail |= cvmx_error_add(&info);
3125
3126     /* CVMX_STXX_INT_REG(1) */
3127     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3128     info.status_addr        = CVMX_STXX_INT_REG(1);
3129     info.status_mask        = 1ull<<0 /* calpar0 */;
3130     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3131     info.enable_mask        = 1ull<<0 /* calpar0 */;
3132     info.flags              = 0;
3133     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3134     info.group_index        = 16;
3135     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3136     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3137     info.parent.status_mask = 1ull<<19 /* spx1 */;
3138     info.func               = __cvmx_error_display;
3139     info.user_info          = (long)
3140         "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
3141     fail |= cvmx_error_add(&info);
3142
3143     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3144     info.status_addr        = CVMX_STXX_INT_REG(1);
3145     info.status_mask        = 1ull<<1 /* calpar1 */;
3146     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3147     info.enable_mask        = 1ull<<1 /* calpar1 */;
3148     info.flags              = 0;
3149     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3150     info.group_index        = 16;
3151     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3152     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3153     info.parent.status_mask = 1ull<<19 /* spx1 */;
3154     info.func               = __cvmx_error_display;
3155     info.user_info          = (long)
3156         "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
3157     fail |= cvmx_error_add(&info);
3158
3159     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3160     info.status_addr        = CVMX_STXX_INT_REG(1);
3161     info.status_mask        = 1ull<<2 /* ovrbst */;
3162     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3163     info.enable_mask        = 1ull<<2 /* ovrbst */;
3164     info.flags              = 0;
3165     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3166     info.group_index        = 16;
3167     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3168     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3169     info.parent.status_mask = 1ull<<19 /* spx1 */;
3170     info.func               = __cvmx_error_display;
3171     info.user_info          = (long)
3172         "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
3173     fail |= cvmx_error_add(&info);
3174
3175     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3176     info.status_addr        = CVMX_STXX_INT_REG(1);
3177     info.status_mask        = 1ull<<3 /* datovr */;
3178     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3179     info.enable_mask        = 1ull<<3 /* datovr */;
3180     info.flags              = 0;
3181     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3182     info.group_index        = 16;
3183     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3184     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3185     info.parent.status_mask = 1ull<<19 /* spx1 */;
3186     info.func               = __cvmx_error_display;
3187     info.user_info          = (long)
3188         "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
3189     fail |= cvmx_error_add(&info);
3190
3191     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3192     info.status_addr        = CVMX_STXX_INT_REG(1);
3193     info.status_mask        = 1ull<<4 /* diperr */;
3194     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3195     info.enable_mask        = 1ull<<4 /* diperr */;
3196     info.flags              = 0;
3197     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3198     info.group_index        = 16;
3199     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3200     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3201     info.parent.status_mask = 1ull<<19 /* spx1 */;
3202     info.func               = __cvmx_error_display;
3203     info.user_info          = (long)
3204         "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
3205     fail |= cvmx_error_add(&info);
3206
3207     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3208     info.status_addr        = CVMX_STXX_INT_REG(1);
3209     info.status_mask        = 1ull<<5 /* nosync */;
3210     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3211     info.enable_mask        = 1ull<<5 /* nosync */;
3212     info.flags              = 0;
3213     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3214     info.group_index        = 16;
3215     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3216     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3217     info.parent.status_mask = 1ull<<19 /* spx1 */;
3218     info.func               = __cvmx_error_display;
3219     info.user_info          = (long)
3220         "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
3221     fail |= cvmx_error_add(&info);
3222
3223     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3224     info.status_addr        = CVMX_STXX_INT_REG(1);
3225     info.status_mask        = 1ull<<6 /* unxfrm */;
3226     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3227     info.enable_mask        = 1ull<<6 /* unxfrm */;
3228     info.flags              = 0;
3229     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3230     info.group_index        = 16;
3231     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3232     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3233     info.parent.status_mask = 1ull<<19 /* spx1 */;
3234     info.func               = __cvmx_error_display;
3235     info.user_info          = (long)
3236         "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
3237     fail |= cvmx_error_add(&info);
3238
3239     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3240     info.status_addr        = CVMX_STXX_INT_REG(1);
3241     info.status_mask        = 1ull<<7 /* frmerr */;
3242     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3243     info.enable_mask        = 1ull<<7 /* frmerr */;
3244     info.flags              = 0;
3245     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3246     info.group_index        = 16;
3247     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3248     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3249     info.parent.status_mask = 1ull<<19 /* spx1 */;
3250     info.func               = __cvmx_error_display;
3251     info.user_info          = (long)
3252         "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
3253     fail |= cvmx_error_add(&info);
3254
3255     /* CVMX_ASXX_INT_REG(0) */
3256     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3257     info.status_addr        = CVMX_ASXX_INT_REG(0);
3258     info.status_mask        = 0xfull<<8 /* txpsh */;
3259     info.enable_addr        = CVMX_ASXX_INT_EN(0);
3260     info.enable_mask        = 0xfull<<8 /* txpsh */;
3261     info.flags              = 0;
3262     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3263     info.group_index        = 0;
3264     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3265     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3266     info.parent.status_mask = 1ull<<22 /* asx0 */;
3267     info.func               = __cvmx_error_display;
3268     info.user_info          = (long)
3269         "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
3270     fail |= cvmx_error_add(&info);
3271
3272     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3273     info.status_addr        = CVMX_ASXX_INT_REG(0);
3274     info.status_mask        = 0xfull<<4 /* txpop */;
3275     info.enable_addr        = CVMX_ASXX_INT_EN(0);
3276     info.enable_mask        = 0xfull<<4 /* txpop */;
3277     info.flags              = 0;
3278     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3279     info.group_index        = 0;
3280     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3281     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3282     info.parent.status_mask = 1ull<<22 /* asx0 */;
3283     info.func               = __cvmx_error_display;
3284     info.user_info          = (long)
3285         "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
3286     fail |= cvmx_error_add(&info);
3287
3288     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3289     info.status_addr        = CVMX_ASXX_INT_REG(0);
3290     info.status_mask        = 0xfull<<0 /* ovrflw */;
3291     info.enable_addr        = CVMX_ASXX_INT_EN(0);
3292     info.enable_mask        = 0xfull<<0 /* ovrflw */;
3293     info.flags              = 0;
3294     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3295     info.group_index        = 0;
3296     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3297     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3298     info.parent.status_mask = 1ull<<22 /* asx0 */;
3299     info.func               = __cvmx_error_display;
3300     info.user_info          = (long)
3301         "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
3302     fail |= cvmx_error_add(&info);
3303
3304     /* CVMX_ASXX_INT_REG(1) */
3305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3306     info.status_addr        = CVMX_ASXX_INT_REG(1);
3307     info.status_mask        = 0xfull<<8 /* txpsh */;
3308     info.enable_addr        = CVMX_ASXX_INT_EN(1);
3309     info.enable_mask        = 0xfull<<8 /* txpsh */;
3310     info.flags              = 0;
3311     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3312     info.group_index        = 16;
3313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3314     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3315     info.parent.status_mask = 1ull<<23 /* asx1 */;
3316     info.func               = __cvmx_error_display;
3317     info.user_info          = (long)
3318         "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
3319     fail |= cvmx_error_add(&info);
3320
3321     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3322     info.status_addr        = CVMX_ASXX_INT_REG(1);
3323     info.status_mask        = 0xfull<<4 /* txpop */;
3324     info.enable_addr        = CVMX_ASXX_INT_EN(1);
3325     info.enable_mask        = 0xfull<<4 /* txpop */;
3326     info.flags              = 0;
3327     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3328     info.group_index        = 16;
3329     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3330     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3331     info.parent.status_mask = 1ull<<23 /* asx1 */;
3332     info.func               = __cvmx_error_display;
3333     info.user_info          = (long)
3334         "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
3335     fail |= cvmx_error_add(&info);
3336
3337     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3338     info.status_addr        = CVMX_ASXX_INT_REG(1);
3339     info.status_mask        = 0xfull<<0 /* ovrflw */;
3340     info.enable_addr        = CVMX_ASXX_INT_EN(1);
3341     info.enable_mask        = 0xfull<<0 /* ovrflw */;
3342     info.flags              = 0;
3343     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3344     info.group_index        = 16;
3345     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3346     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3347     info.parent.status_mask = 1ull<<23 /* asx1 */;
3348     info.func               = __cvmx_error_display;
3349     info.user_info          = (long)
3350         "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
3351     fail |= cvmx_error_add(&info);
3352
3353     /* CVMX_PKO_REG_ERROR */
3354     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3355     info.status_addr        = CVMX_PKO_REG_ERROR;
3356     info.status_mask        = 1ull<<0 /* parity */;
3357     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3358     info.enable_mask        = 1ull<<0 /* parity */;
3359     info.flags              = 0;
3360     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3361     info.group_index        = 0;
3362     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3363     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3364     info.parent.status_mask = 1ull<<10 /* pko */;
3365     info.func               = __cvmx_error_display;
3366     info.user_info          = (long)
3367         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
3368     fail |= cvmx_error_add(&info);
3369
3370     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3371     info.status_addr        = CVMX_PKO_REG_ERROR;
3372     info.status_mask        = 1ull<<1 /* doorbell */;
3373     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3374     info.enable_mask        = 1ull<<1 /* doorbell */;
3375     info.flags              = 0;
3376     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3377     info.group_index        = 0;
3378     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3379     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3380     info.parent.status_mask = 1ull<<10 /* pko */;
3381     info.func               = __cvmx_error_display;
3382     info.user_info          = (long)
3383         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
3384     fail |= cvmx_error_add(&info);
3385
3386     /* CVMX_TIM_REG_ERROR */
3387     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3388     info.status_addr        = CVMX_TIM_REG_ERROR;
3389     info.status_mask        = 0xffffull<<0 /* mask */;
3390     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
3391     info.enable_mask        = 0xffffull<<0 /* mask */;
3392     info.flags              = 0;
3393     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3394     info.group_index        = 0;
3395     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3396     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3397     info.parent.status_mask = 1ull<<11 /* tim */;
3398     info.func               = __cvmx_error_display;
3399     info.user_info          = (long)
3400         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
3401     fail |= cvmx_error_add(&info);
3402
3403     /* CVMX_KEY_INT_SUM */
3404     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3405     info.status_addr        = CVMX_KEY_INT_SUM;
3406     info.status_mask        = 1ull<<0 /* ked0_sbe */;
3407     info.enable_addr        = CVMX_KEY_INT_ENB;
3408     info.enable_mask        = 1ull<<0 /* ked0_sbe */;
3409     info.flags              = 0;
3410     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3411     info.group_index        = 0;
3412     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3413     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3414     info.parent.status_mask = 1ull<<4 /* key */;
3415     info.func               = __cvmx_error_display;
3416     info.user_info          = (long)
3417         "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
3418 ;
3419     fail |= cvmx_error_add(&info);
3420
3421     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3422     info.status_addr        = CVMX_KEY_INT_SUM;
3423     info.status_mask        = 1ull<<1 /* ked0_dbe */;
3424     info.enable_addr        = CVMX_KEY_INT_ENB;
3425     info.enable_mask        = 1ull<<1 /* ked0_dbe */;
3426     info.flags              = 0;
3427     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3428     info.group_index        = 0;
3429     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3430     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3431     info.parent.status_mask = 1ull<<4 /* key */;
3432     info.func               = __cvmx_error_display;
3433     info.user_info          = (long)
3434         "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
3435 ;
3436     fail |= cvmx_error_add(&info);
3437
3438     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3439     info.status_addr        = CVMX_KEY_INT_SUM;
3440     info.status_mask        = 1ull<<2 /* ked1_sbe */;
3441     info.enable_addr        = CVMX_KEY_INT_ENB;
3442     info.enable_mask        = 1ull<<2 /* ked1_sbe */;
3443     info.flags              = 0;
3444     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3445     info.group_index        = 0;
3446     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3447     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3448     info.parent.status_mask = 1ull<<4 /* key */;
3449     info.func               = __cvmx_error_display;
3450     info.user_info          = (long)
3451         "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
3452 ;
3453     fail |= cvmx_error_add(&info);
3454
3455     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3456     info.status_addr        = CVMX_KEY_INT_SUM;
3457     info.status_mask        = 1ull<<3 /* ked1_dbe */;
3458     info.enable_addr        = CVMX_KEY_INT_ENB;
3459     info.enable_mask        = 1ull<<3 /* ked1_dbe */;
3460     info.flags              = 0;
3461     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3462     info.group_index        = 0;
3463     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3464     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3465     info.parent.status_mask = 1ull<<4 /* key */;
3466     info.func               = __cvmx_error_display;
3467     info.user_info          = (long)
3468         "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
3469 ;
3470     fail |= cvmx_error_add(&info);
3471
3472     /* CVMX_MIO_BOOT_ERR */
3473     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3474     info.status_addr        = CVMX_MIO_BOOT_ERR;
3475     info.status_mask        = 1ull<<0 /* adr_err */;
3476     info.enable_addr        = CVMX_MIO_BOOT_INT;
3477     info.enable_mask        = 1ull<<0 /* adr_int */;
3478     info.flags              = 0;
3479     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3480     info.group_index        = 0;
3481     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3482     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3483     info.parent.status_mask = 1ull<<0 /* mio */;
3484     info.func               = __cvmx_error_display;
3485     info.user_info          = (long)
3486         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
3487     fail |= cvmx_error_add(&info);
3488
3489     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3490     info.status_addr        = CVMX_MIO_BOOT_ERR;
3491     info.status_mask        = 1ull<<1 /* wait_err */;
3492     info.enable_addr        = CVMX_MIO_BOOT_INT;
3493     info.enable_mask        = 1ull<<1 /* wait_int */;
3494     info.flags              = 0;
3495     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3496     info.group_index        = 0;
3497     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3498     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3499     info.parent.status_mask = 1ull<<0 /* mio */;
3500     info.func               = __cvmx_error_display;
3501     info.user_info          = (long)
3502         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
3503     fail |= cvmx_error_add(&info);
3504
3505     /* CVMX_PIP_INT_REG */
3506     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3507     info.status_addr        = CVMX_PIP_INT_REG;
3508     info.status_mask        = 1ull<<3 /* prtnxa */;
3509     info.enable_addr        = CVMX_PIP_INT_EN;
3510     info.enable_mask        = 1ull<<3 /* prtnxa */;
3511     info.flags              = 0;
3512     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3513     info.group_index        = 0;
3514     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3515     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3516     info.parent.status_mask = 1ull<<20 /* pip */;
3517     info.func               = __cvmx_error_display;
3518     info.user_info          = (long)
3519         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
3520     fail |= cvmx_error_add(&info);
3521
3522     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3523     info.status_addr        = CVMX_PIP_INT_REG;
3524     info.status_mask        = 1ull<<4 /* badtag */;
3525     info.enable_addr        = CVMX_PIP_INT_EN;
3526     info.enable_mask        = 1ull<<4 /* badtag */;
3527     info.flags              = 0;
3528     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3529     info.group_index        = 0;
3530     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3531     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3532     info.parent.status_mask = 1ull<<20 /* pip */;
3533     info.func               = __cvmx_error_display;
3534     info.user_info          = (long)
3535         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
3536     fail |= cvmx_error_add(&info);
3537
3538     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3539     info.status_addr        = CVMX_PIP_INT_REG;
3540     info.status_mask        = 1ull<<5 /* skprunt */;
3541     info.enable_addr        = CVMX_PIP_INT_EN;
3542     info.enable_mask        = 1ull<<5 /* skprunt */;
3543     info.flags              = 0;
3544     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3545     info.group_index        = 0;
3546     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3547     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3548     info.parent.status_mask = 1ull<<20 /* pip */;
3549     info.func               = __cvmx_error_display;
3550     info.user_info          = (long)
3551         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
3552         "    This interrupt can occur with received PARTIAL\n"
3553         "    packets that are truncated to SKIP bytes or\n"
3554         "    smaller.\n";
3555     fail |= cvmx_error_add(&info);
3556
3557     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3558     info.status_addr        = CVMX_PIP_INT_REG;
3559     info.status_mask        = 1ull<<6 /* todoovr */;
3560     info.enable_addr        = CVMX_PIP_INT_EN;
3561     info.enable_mask        = 1ull<<6 /* todoovr */;
3562     info.flags              = 0;
3563     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3564     info.group_index        = 0;
3565     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3566     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3567     info.parent.status_mask = 1ull<<20 /* pip */;
3568     info.func               = __cvmx_error_display;
3569     info.user_info          = (long)
3570         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
3571     fail |= cvmx_error_add(&info);
3572
3573     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3574     info.status_addr        = CVMX_PIP_INT_REG;
3575     info.status_mask        = 1ull<<7 /* feperr */;
3576     info.enable_addr        = CVMX_PIP_INT_EN;
3577     info.enable_mask        = 1ull<<7 /* feperr */;
3578     info.flags              = 0;
3579     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3580     info.group_index        = 0;
3581     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3582     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3583     info.parent.status_mask = 1ull<<20 /* pip */;
3584     info.func               = __cvmx_error_display;
3585     info.user_info          = (long)
3586         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
3587     fail |= cvmx_error_add(&info);
3588
3589     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3590     info.status_addr        = CVMX_PIP_INT_REG;
3591     info.status_mask        = 1ull<<8 /* beperr */;
3592     info.enable_addr        = CVMX_PIP_INT_EN;
3593     info.enable_mask        = 1ull<<8 /* beperr */;
3594     info.flags              = 0;
3595     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3596     info.group_index        = 0;
3597     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3598     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3599     info.parent.status_mask = 1ull<<20 /* pip */;
3600     info.func               = __cvmx_error_display;
3601     info.user_info          = (long)
3602         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
3603     fail |= cvmx_error_add(&info);
3604
3605     /* CVMX_FPA_INT_SUM */
3606     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3607     info.status_addr        = CVMX_FPA_INT_SUM;
3608     info.status_mask        = 1ull<<0 /* fed0_sbe */;
3609     info.enable_addr        = CVMX_FPA_INT_ENB;
3610     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
3611     info.flags              = 0;
3612     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3613     info.group_index        = 0;
3614     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3615     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3616     info.parent.status_mask = 1ull<<5 /* fpa */;
3617     info.func               = __cvmx_error_display;
3618     info.user_info          = (long)
3619         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
3620     fail |= cvmx_error_add(&info);
3621
3622     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3623     info.status_addr        = CVMX_FPA_INT_SUM;
3624     info.status_mask        = 1ull<<1 /* fed0_dbe */;
3625     info.enable_addr        = CVMX_FPA_INT_ENB;
3626     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
3627     info.flags              = 0;
3628     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3629     info.group_index        = 0;
3630     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3631     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3632     info.parent.status_mask = 1ull<<5 /* fpa */;
3633     info.func               = __cvmx_error_display;
3634     info.user_info          = (long)
3635         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
3636     fail |= cvmx_error_add(&info);
3637
3638     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3639     info.status_addr        = CVMX_FPA_INT_SUM;
3640     info.status_mask        = 1ull<<2 /* fed1_sbe */;
3641     info.enable_addr        = CVMX_FPA_INT_ENB;
3642     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
3643     info.flags              = 0;
3644     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3645     info.group_index        = 0;
3646     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3647     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3648     info.parent.status_mask = 1ull<<5 /* fpa */;
3649     info.func               = __cvmx_error_display;
3650     info.user_info          = (long)
3651         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
3652     fail |= cvmx_error_add(&info);
3653
3654     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3655     info.status_addr        = CVMX_FPA_INT_SUM;
3656     info.status_mask        = 1ull<<3 /* fed1_dbe */;
3657     info.enable_addr        = CVMX_FPA_INT_ENB;
3658     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
3659     info.flags              = 0;
3660     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3661     info.group_index        = 0;
3662     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3663     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3664     info.parent.status_mask = 1ull<<5 /* fpa */;
3665     info.func               = __cvmx_error_display;
3666     info.user_info          = (long)
3667         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
3668     fail |= cvmx_error_add(&info);
3669
3670     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3671     info.status_addr        = CVMX_FPA_INT_SUM;
3672     info.status_mask        = 1ull<<4 /* q0_und */;
3673     info.enable_addr        = CVMX_FPA_INT_ENB;
3674     info.enable_mask        = 1ull<<4 /* q0_und */;
3675     info.flags              = 0;
3676     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3677     info.group_index        = 0;
3678     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3679     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3680     info.parent.status_mask = 1ull<<5 /* fpa */;
3681     info.func               = __cvmx_error_display;
3682     info.user_info          = (long)
3683         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
3684         "    negative.\n";
3685     fail |= cvmx_error_add(&info);
3686
3687     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3688     info.status_addr        = CVMX_FPA_INT_SUM;
3689     info.status_mask        = 1ull<<5 /* q0_coff */;
3690     info.enable_addr        = CVMX_FPA_INT_ENB;
3691     info.enable_mask        = 1ull<<5 /* q0_coff */;
3692     info.flags              = 0;
3693     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3694     info.group_index        = 0;
3695     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3696     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3697     info.parent.status_mask = 1ull<<5 /* fpa */;
3698     info.func               = __cvmx_error_display;
3699     info.user_info          = (long)
3700         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
3701         "    the count available is greater than pointers\n"
3702         "    present in the FPA.\n";
3703     fail |= cvmx_error_add(&info);
3704
3705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3706     info.status_addr        = CVMX_FPA_INT_SUM;
3707     info.status_mask        = 1ull<<6 /* q0_perr */;
3708     info.enable_addr        = CVMX_FPA_INT_ENB;
3709     info.enable_mask        = 1ull<<6 /* q0_perr */;
3710     info.flags              = 0;
3711     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3712     info.group_index        = 0;
3713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3715     info.parent.status_mask = 1ull<<5 /* fpa */;
3716     info.func               = __cvmx_error_display;
3717     info.user_info          = (long)
3718         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
3719         "    the L2C does not have the FPA owner ship bit set.\n";
3720     fail |= cvmx_error_add(&info);
3721
3722     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3723     info.status_addr        = CVMX_FPA_INT_SUM;
3724     info.status_mask        = 1ull<<7 /* q1_und */;
3725     info.enable_addr        = CVMX_FPA_INT_ENB;
3726     info.enable_mask        = 1ull<<7 /* q1_und */;
3727     info.flags              = 0;
3728     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3729     info.group_index        = 0;
3730     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3731     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3732     info.parent.status_mask = 1ull<<5 /* fpa */;
3733     info.func               = __cvmx_error_display;
3734     info.user_info          = (long)
3735         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
3736         "    negative.\n";
3737     fail |= cvmx_error_add(&info);
3738
3739     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3740     info.status_addr        = CVMX_FPA_INT_SUM;
3741     info.status_mask        = 1ull<<8 /* q1_coff */;
3742     info.enable_addr        = CVMX_FPA_INT_ENB;
3743     info.enable_mask        = 1ull<<8 /* q1_coff */;
3744     info.flags              = 0;
3745     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3746     info.group_index        = 0;
3747     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3748     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3749     info.parent.status_mask = 1ull<<5 /* fpa */;
3750     info.func               = __cvmx_error_display;
3751     info.user_info          = (long)
3752         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
3753         "    the count available is greater than pointers\n"
3754         "    present in the FPA.\n";
3755     fail |= cvmx_error_add(&info);
3756
3757     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3758     info.status_addr        = CVMX_FPA_INT_SUM;
3759     info.status_mask        = 1ull<<9 /* q1_perr */;
3760     info.enable_addr        = CVMX_FPA_INT_ENB;
3761     info.enable_mask        = 1ull<<9 /* q1_perr */;
3762     info.flags              = 0;
3763     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3764     info.group_index        = 0;
3765     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3766     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3767     info.parent.status_mask = 1ull<<5 /* fpa */;
3768     info.func               = __cvmx_error_display;
3769     info.user_info          = (long)
3770         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
3771         "    the L2C does not have the FPA owner ship bit set.\n";
3772     fail |= cvmx_error_add(&info);
3773
3774     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3775     info.status_addr        = CVMX_FPA_INT_SUM;
3776     info.status_mask        = 1ull<<10 /* q2_und */;
3777     info.enable_addr        = CVMX_FPA_INT_ENB;
3778     info.enable_mask        = 1ull<<10 /* q2_und */;
3779     info.flags              = 0;
3780     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3781     info.group_index        = 0;
3782     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3783     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3784     info.parent.status_mask = 1ull<<5 /* fpa */;
3785     info.func               = __cvmx_error_display;
3786     info.user_info          = (long)
3787         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
3788         "    negative.\n";
3789     fail |= cvmx_error_add(&info);
3790
3791     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3792     info.status_addr        = CVMX_FPA_INT_SUM;
3793     info.status_mask        = 1ull<<11 /* q2_coff */;
3794     info.enable_addr        = CVMX_FPA_INT_ENB;
3795     info.enable_mask        = 1ull<<11 /* q2_coff */;
3796     info.flags              = 0;
3797     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3798     info.group_index        = 0;
3799     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3800     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3801     info.parent.status_mask = 1ull<<5 /* fpa */;
3802     info.func               = __cvmx_error_display;
3803     info.user_info          = (long)
3804         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
3805         "    the count available is greater than than pointers\n"
3806         "    present in the FPA.\n";
3807     fail |= cvmx_error_add(&info);
3808
3809     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3810     info.status_addr        = CVMX_FPA_INT_SUM;
3811     info.status_mask        = 1ull<<12 /* q2_perr */;
3812     info.enable_addr        = CVMX_FPA_INT_ENB;
3813     info.enable_mask        = 1ull<<12 /* q2_perr */;
3814     info.flags              = 0;
3815     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3816     info.group_index        = 0;
3817     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3818     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3819     info.parent.status_mask = 1ull<<5 /* fpa */;
3820     info.func               = __cvmx_error_display;
3821     info.user_info          = (long)
3822         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
3823         "    the L2C does not have the FPA owner ship bit set.\n";
3824     fail |= cvmx_error_add(&info);
3825
3826     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3827     info.status_addr        = CVMX_FPA_INT_SUM;
3828     info.status_mask        = 1ull<<13 /* q3_und */;
3829     info.enable_addr        = CVMX_FPA_INT_ENB;
3830     info.enable_mask        = 1ull<<13 /* q3_und */;
3831     info.flags              = 0;
3832     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3833     info.group_index        = 0;
3834     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3835     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3836     info.parent.status_mask = 1ull<<5 /* fpa */;
3837     info.func               = __cvmx_error_display;
3838     info.user_info          = (long)
3839         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
3840         "    negative.\n";
3841     fail |= cvmx_error_add(&info);
3842
3843     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3844     info.status_addr        = CVMX_FPA_INT_SUM;
3845     info.status_mask        = 1ull<<14 /* q3_coff */;
3846     info.enable_addr        = CVMX_FPA_INT_ENB;
3847     info.enable_mask        = 1ull<<14 /* q3_coff */;
3848     info.flags              = 0;
3849     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3850     info.group_index        = 0;
3851     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3852     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3853     info.parent.status_mask = 1ull<<5 /* fpa */;
3854     info.func               = __cvmx_error_display;
3855     info.user_info          = (long)
3856         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
3857         "    the count available is greater than than pointers\n"
3858         "    present in the FPA.\n";
3859     fail |= cvmx_error_add(&info);
3860
3861     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3862     info.status_addr        = CVMX_FPA_INT_SUM;
3863     info.status_mask        = 1ull<<15 /* q3_perr */;
3864     info.enable_addr        = CVMX_FPA_INT_ENB;
3865     info.enable_mask        = 1ull<<15 /* q3_perr */;
3866     info.flags              = 0;
3867     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3868     info.group_index        = 0;
3869     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3870     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3871     info.parent.status_mask = 1ull<<5 /* fpa */;
3872     info.func               = __cvmx_error_display;
3873     info.user_info          = (long)
3874         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
3875         "    the L2C does not have the FPA owner ship bit set.\n";
3876     fail |= cvmx_error_add(&info);
3877
3878     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3879     info.status_addr        = CVMX_FPA_INT_SUM;
3880     info.status_mask        = 1ull<<16 /* q4_und */;
3881     info.enable_addr        = CVMX_FPA_INT_ENB;
3882     info.enable_mask        = 1ull<<16 /* q4_und */;
3883     info.flags              = 0;
3884     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3885     info.group_index        = 0;
3886     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3887     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3888     info.parent.status_mask = 1ull<<5 /* fpa */;
3889     info.func               = __cvmx_error_display;
3890     info.user_info          = (long)
3891         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
3892         "    negative.\n";
3893     fail |= cvmx_error_add(&info);
3894
3895     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3896     info.status_addr        = CVMX_FPA_INT_SUM;
3897     info.status_mask        = 1ull<<17 /* q4_coff */;
3898     info.enable_addr        = CVMX_FPA_INT_ENB;
3899     info.enable_mask        = 1ull<<17 /* q4_coff */;
3900     info.flags              = 0;
3901     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3902     info.group_index        = 0;
3903     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3904     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3905     info.parent.status_mask = 1ull<<5 /* fpa */;
3906     info.func               = __cvmx_error_display;
3907     info.user_info          = (long)
3908         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
3909         "    the count available is greater than than pointers\n"
3910         "    present in the FPA.\n";
3911     fail |= cvmx_error_add(&info);
3912
3913     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3914     info.status_addr        = CVMX_FPA_INT_SUM;
3915     info.status_mask        = 1ull<<18 /* q4_perr */;
3916     info.enable_addr        = CVMX_FPA_INT_ENB;
3917     info.enable_mask        = 1ull<<18 /* q4_perr */;
3918     info.flags              = 0;
3919     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3920     info.group_index        = 0;
3921     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3922     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3923     info.parent.status_mask = 1ull<<5 /* fpa */;
3924     info.func               = __cvmx_error_display;
3925     info.user_info          = (long)
3926         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
3927         "    the L2C does not have the FPA owner ship bit set.\n";
3928     fail |= cvmx_error_add(&info);
3929
3930     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3931     info.status_addr        = CVMX_FPA_INT_SUM;
3932     info.status_mask        = 1ull<<19 /* q5_und */;
3933     info.enable_addr        = CVMX_FPA_INT_ENB;
3934     info.enable_mask        = 1ull<<19 /* q5_und */;
3935     info.flags              = 0;
3936     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3937     info.group_index        = 0;
3938     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3939     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3940     info.parent.status_mask = 1ull<<5 /* fpa */;
3941     info.func               = __cvmx_error_display;
3942     info.user_info          = (long)
3943         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
3944         "    negative.\n";
3945     fail |= cvmx_error_add(&info);
3946
3947     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3948     info.status_addr        = CVMX_FPA_INT_SUM;
3949     info.status_mask        = 1ull<<20 /* q5_coff */;
3950     info.enable_addr        = CVMX_FPA_INT_ENB;
3951     info.enable_mask        = 1ull<<20 /* q5_coff */;
3952     info.flags              = 0;
3953     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3954     info.group_index        = 0;
3955     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3956     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3957     info.parent.status_mask = 1ull<<5 /* fpa */;
3958     info.func               = __cvmx_error_display;
3959     info.user_info          = (long)
3960         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
3961         "    the count available is greater than than pointers\n"
3962         "    present in the FPA.\n";
3963     fail |= cvmx_error_add(&info);
3964
3965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3966     info.status_addr        = CVMX_FPA_INT_SUM;
3967     info.status_mask        = 1ull<<21 /* q5_perr */;
3968     info.enable_addr        = CVMX_FPA_INT_ENB;
3969     info.enable_mask        = 1ull<<21 /* q5_perr */;
3970     info.flags              = 0;
3971     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3972     info.group_index        = 0;
3973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3974     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3975     info.parent.status_mask = 1ull<<5 /* fpa */;
3976     info.func               = __cvmx_error_display;
3977     info.user_info          = (long)
3978         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
3979         "    the L2C does not have the FPA owner ship bit set.\n";
3980     fail |= cvmx_error_add(&info);
3981
3982     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3983     info.status_addr        = CVMX_FPA_INT_SUM;
3984     info.status_mask        = 1ull<<22 /* q6_und */;
3985     info.enable_addr        = CVMX_FPA_INT_ENB;
3986     info.enable_mask        = 1ull<<22 /* q6_und */;
3987     info.flags              = 0;
3988     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3989     info.group_index        = 0;
3990     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3991     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3992     info.parent.status_mask = 1ull<<5 /* fpa */;
3993     info.func               = __cvmx_error_display;
3994     info.user_info          = (long)
3995         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
3996         "    negative.\n";
3997     fail |= cvmx_error_add(&info);
3998
3999     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4000     info.status_addr        = CVMX_FPA_INT_SUM;
4001     info.status_mask        = 1ull<<23 /* q6_coff */;
4002     info.enable_addr        = CVMX_FPA_INT_ENB;
4003     info.enable_mask        = 1ull<<23 /* q6_coff */;
4004     info.flags              = 0;
4005     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4006     info.group_index        = 0;
4007     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4008     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4009     info.parent.status_mask = 1ull<<5 /* fpa */;
4010     info.func               = __cvmx_error_display;
4011     info.user_info          = (long)
4012         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
4013         "    the count available is greater than than pointers\n"
4014         "    present in the FPA.\n";
4015     fail |= cvmx_error_add(&info);
4016
4017     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4018     info.status_addr        = CVMX_FPA_INT_SUM;
4019     info.status_mask        = 1ull<<24 /* q6_perr */;
4020     info.enable_addr        = CVMX_FPA_INT_ENB;
4021     info.enable_mask        = 1ull<<24 /* q6_perr */;
4022     info.flags              = 0;
4023     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4024     info.group_index        = 0;
4025     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4026     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4027     info.parent.status_mask = 1ull<<5 /* fpa */;
4028     info.func               = __cvmx_error_display;
4029     info.user_info          = (long)
4030         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
4031         "    the L2C does not have the FPA owner ship bit set.\n";
4032     fail |= cvmx_error_add(&info);
4033
4034     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4035     info.status_addr        = CVMX_FPA_INT_SUM;
4036     info.status_mask        = 1ull<<25 /* q7_und */;
4037     info.enable_addr        = CVMX_FPA_INT_ENB;
4038     info.enable_mask        = 1ull<<25 /* q7_und */;
4039     info.flags              = 0;
4040     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4041     info.group_index        = 0;
4042     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4043     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4044     info.parent.status_mask = 1ull<<5 /* fpa */;
4045     info.func               = __cvmx_error_display;
4046     info.user_info          = (long)
4047         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
4048         "    negative.\n";
4049     fail |= cvmx_error_add(&info);
4050
4051     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4052     info.status_addr        = CVMX_FPA_INT_SUM;
4053     info.status_mask        = 1ull<<26 /* q7_coff */;
4054     info.enable_addr        = CVMX_FPA_INT_ENB;
4055     info.enable_mask        = 1ull<<26 /* q7_coff */;
4056     info.flags              = 0;
4057     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4058     info.group_index        = 0;
4059     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4060     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4061     info.parent.status_mask = 1ull<<5 /* fpa */;
4062     info.func               = __cvmx_error_display;
4063     info.user_info          = (long)
4064         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
4065         "    the count available is greater than than pointers\n"
4066         "    present in the FPA.\n";
4067     fail |= cvmx_error_add(&info);
4068
4069     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4070     info.status_addr        = CVMX_FPA_INT_SUM;
4071     info.status_mask        = 1ull<<27 /* q7_perr */;
4072     info.enable_addr        = CVMX_FPA_INT_ENB;
4073     info.enable_mask        = 1ull<<27 /* q7_perr */;
4074     info.flags              = 0;
4075     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4076     info.group_index        = 0;
4077     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4078     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4079     info.parent.status_mask = 1ull<<5 /* fpa */;
4080     info.func               = __cvmx_error_display;
4081     info.user_info          = (long)
4082         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
4083         "    the L2C does not have the FPA owner ship bit set.\n";
4084     fail |= cvmx_error_add(&info);
4085
4086     /* CVMX_LMCX_MEM_CFG0(0) */
4087     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4088     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
4089     info.status_mask        = 0xfull<<21 /* sec_err */;
4090     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
4091     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
4092     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4093     info.group              = CVMX_ERROR_GROUP_LMC;
4094     info.group_index        = 0;
4095     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4096     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4097     info.parent.status_mask = 1ull<<17 /* lmc */;
4098     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
4099     info.user_info          = (long)
4100         "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4101         "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
4102         "    [21] corresponds to DQ[63:0], Phase0\n"
4103         "    [22] corresponds to DQ[127:64], Phase0\n"
4104         "    [23] corresponds to DQ[63:0], Phase1\n"
4105         "    [24] corresponds to DQ[127:64], Phase1\n"
4106         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4107         "    [21] corresponds to DQ[63:0], Phase0, cycle0\n"
4108         "    [22] corresponds to DQ[63:0], Phase0, cycle1\n"
4109         "    [23] corresponds to DQ[63:0], Phase1, cycle0\n"
4110         "    [24] corresponds to DQ[63:0], Phase1, cycle1\n"
4111         "    Write of 1 will clear the corresponding error bit\n";
4112     fail |= cvmx_error_add(&info);
4113
4114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4115     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
4116     info.status_mask        = 0xfull<<25 /* ded_err */;
4117     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
4118     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
4119     info.flags              = 0;
4120     info.group              = CVMX_ERROR_GROUP_LMC;
4121     info.group_index        = 0;
4122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4123     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4124     info.parent.status_mask = 1ull<<17 /* lmc */;
4125     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
4126     info.user_info          = (long)
4127         "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4128         "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
4129         "    [25] corresponds to DQ[63:0], Phase0\n"
4130         "    [26] corresponds to DQ[127:64], Phase0\n"
4131         "    [27] corresponds to DQ[63:0], Phase1\n"
4132         "    [28] corresponds to DQ[127:64], Phase1\n"
4133         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4134         "    [25] corresponds to DQ[63:0], Phase0, cycle0\n"
4135         "    [26] corresponds to DQ[63:0], Phase0, cycle1\n"
4136         "    [27] corresponds to DQ[63:0], Phase1, cycle0\n"
4137         "    [28] corresponds to DQ[63:0], Phase1, cycle1\n"
4138         "    Write of 1 will clear the corresponding error bit\n";
4139     fail |= cvmx_error_add(&info);
4140
4141     /* CVMX_DFA_ERR */
4142     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4143     info.status_addr        = CVMX_DFA_ERR;
4144     info.status_mask        = 1ull<<1 /* cp2sbe */;
4145     info.enable_addr        = 0;
4146     info.enable_mask        = 0;
4147     info.flags              = 0;
4148     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4149     info.group_index        = 0;
4150     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4151     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4152     info.parent.status_mask = 1ull<<6 /* dfa */;
4153     info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
4154     info.user_info          = (long)
4155         "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
4156         "    When set, a single bit error had been detected and\n"
4157         "    corrected for a PP-generated QW Mode read\n"
4158         "    transaction.\n"
4159         "    If the CP2DBE=0, then the CP2SYN contains the\n"
4160         "    failing syndrome (used during correction).\n"
4161         "    Refer to CP2ECCENA.\n"
4162         "    If the CP2SBINA had previously been enabled(set),\n"
4163         "    an interrupt will be posted. Software can clear\n"
4164         "    the interrupt by writing a 1 to this register bit.\n"
4165         "    See also: DFA_MEMFADR CSR which contains more data\n"
4166         "    about the memory address/control to help isolate\n"
4167         "    the failure.\n"
4168         "    NOTE: PP-generated LW Mode Read transactions\n"
4169         "    do not participate in ECC check/correct).\n";
4170     fail |= cvmx_error_add(&info);
4171
4172     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4173     info.status_addr        = CVMX_DFA_ERR;
4174     info.status_mask        = 1ull<<2 /* cp2dbe */;
4175     info.enable_addr        = 0;
4176     info.enable_mask        = 0;
4177     info.flags              = 0;
4178     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4179     info.group_index        = 0;
4180     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4181     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4182     info.parent.status_mask = 1ull<<6 /* dfa */;
4183     info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
4184     info.user_info          = (long)
4185         "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
4186         "    When set, a double bit error had been detected\n"
4187         "    for a PP-generated QW Mode read transaction.\n"
4188         "    The CP2SYN contains the failing syndrome.\n"
4189         "     NOTE: PP-generated LW Mode Read transactions\n"
4190         "    do not participate in ECC check/correct).\n"
4191         "    Refer to CP2ECCENA.\n"
4192         "    If the CP2DBINA had previously been enabled(set),\n"
4193         "    an interrupt will be posted. Software can clear\n"
4194         "    the interrupt by writing a 1 to this register bit.\n"
4195         "    See also: DFA_MEMFADR CSR which contains more data\n"
4196         "    about the memory address/control to help isolate\n"
4197         "    the failure.\n";
4198     fail |= cvmx_error_add(&info);
4199
4200     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4201     info.status_addr        = CVMX_DFA_ERR;
4202     info.status_mask        = 1ull<<14 /* dtesbe */;
4203     info.enable_addr        = 0;
4204     info.enable_mask        = 0;
4205     info.flags              = 0;
4206     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4207     info.group_index        = 0;
4208     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4209     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4210     info.parent.status_mask = 1ull<<6 /* dfa */;
4211     info.func               = __cvmx_error_handle_dfa_err_dtesbe;
4212     info.user_info          = (long)
4213         "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
4214         "    When set, a single bit error had been detected and\n"
4215         "    corrected for a DTE-generated 36b SIMPLE Mode read\n"
4216         "    transaction.\n"
4217         "    If the DTEDBE=0, then the DTESYN contains the\n"
4218         "    failing syndrome (used during correction).\n"
4219         "    NOTE: DTE-generated 18b SIMPLE Mode Read\n"
4220         "    transactions do not participate in ECC check/correct).\n"
4221         "    If the DTESBINA had previously been enabled(set),\n"
4222         "    an interrupt will be posted. Software can clear\n"
4223         "    the interrupt by writing a 1 to this register bit.\n"
4224         "    See also: DFA_MEMFADR CSR which contains more data\n"
4225         "    about the memory address/control to help isolate\n"
4226         "    the failure.\n";
4227     fail |= cvmx_error_add(&info);
4228
4229     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4230     info.status_addr        = CVMX_DFA_ERR;
4231     info.status_mask        = 1ull<<15 /* dtedbe */;
4232     info.enable_addr        = 0;
4233     info.enable_mask        = 0;
4234     info.flags              = 0;
4235     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4236     info.group_index        = 0;
4237     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4238     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4239     info.parent.status_mask = 1ull<<6 /* dfa */;
4240     info.func               = __cvmx_error_handle_dfa_err_dtedbe;
4241     info.user_info          = (long)
4242         "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
4243         "    When set, a double bit error had been detected\n"
4244         "    for a DTE-generated 36b SIMPLE Mode read transaction.\n"
4245         "    The DTESYN contains the failing syndrome.\n"
4246         "    If the DTEDBINA had previously been enabled(set),\n"
4247         "    an interrupt will be posted. Software can clear\n"
4248         "    the interrupt by writing a 1 to this register bit.\n"
4249         "    See also: DFA_MEMFADR CSR which contains more data\n"
4250         "    about the memory address/control to help isolate\n"
4251         "    the failure.\n"
4252         "    NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
4253         "    do not participate in ECC check/correct).\n";
4254     fail |= cvmx_error_add(&info);
4255
4256     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4257     info.status_addr        = CVMX_DFA_ERR;
4258     info.status_mask        = 1ull<<26 /* dteperr */;
4259     info.enable_addr        = 0;
4260     info.enable_mask        = 0;
4261     info.flags              = 0;
4262     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4263     info.group_index        = 0;
4264     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4265     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4266     info.parent.status_mask = 1ull<<6 /* dfa */;
4267     info.func               = __cvmx_error_handle_dfa_err_dteperr;
4268     info.user_info          = (long)
4269         "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
4270         "    When set, all DTE-generated 18b SIMPLE Mode read\n"
4271         "    transactions which encounter a parity error (across\n"
4272         "    the 17b of data) are reported.\n";
4273     fail |= cvmx_error_add(&info);
4274
4275     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4276     info.status_addr        = CVMX_DFA_ERR;
4277     info.status_mask        = 1ull<<29 /* cp2perr */;
4278     info.enable_addr        = 0;
4279     info.enable_mask        = 0;
4280     info.flags              = 0;
4281     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4282     info.group_index        = 0;
4283     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4284     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4285     info.parent.status_mask = 1ull<<6 /* dfa */;
4286     info.func               = __cvmx_error_handle_dfa_err_cp2perr;
4287     info.user_info          = (long)
4288         "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
4289         "    When set, a parity error had been detected for a\n"
4290         "    PP-generated LW Mode read transaction.\n"
4291         "    If the CP2PINA had previously been enabled(set),\n"
4292         "    an interrupt will be posted. Software can clear\n"
4293         "    the interrupt by writing a 1 to this register bit.\n"
4294         "    See also: DFA_MEMFADR CSR which contains more data\n"
4295         "    about the memory address/control to help isolate\n"
4296         "    the failure.\n";
4297     fail |= cvmx_error_add(&info);
4298
4299     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4300     info.status_addr        = CVMX_DFA_ERR;
4301     info.status_mask        = 1ull<<31 /* dblovf */;
4302     info.enable_addr        = 0;
4303     info.enable_mask        = 0;
4304     info.flags              = 0;
4305     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4306     info.group_index        = 0;
4307     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4308     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4309     info.parent.status_mask = 1ull<<6 /* dfa */;
4310     info.func               = __cvmx_error_handle_dfa_err_dblovf;
4311     info.user_info          = (long)
4312         "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
4313         "    When set, the 20b accumulated doorbell register\n"
4314         "    had overflowed (SW wrote too many doorbell requests).\n"
4315         "    If the DBLINA had previously been enabled(set),\n"
4316         "    an interrupt will be posted. Software can clear\n"
4317         "    the interrupt by writing a 1 to this register bit.\n"
4318         "    NOTE: Detection of a Doorbell Register overflow\n"
4319         "    is a catastrophic error which may leave the DFA\n"
4320         "    HW in an unrecoverable state.\n";
4321     fail |= cvmx_error_add(&info);
4322
4323     /* CVMX_IOB_INT_SUM */
4324     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4325     info.status_addr        = CVMX_IOB_INT_SUM;
4326     info.status_mask        = 1ull<<0 /* np_sop */;
4327     info.enable_addr        = CVMX_IOB_INT_ENB;
4328     info.enable_mask        = 1ull<<0 /* np_sop */;
4329     info.flags              = 0;
4330     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4331     info.group_index        = 0;
4332     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4333     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4334     info.parent.status_mask = 1ull<<30 /* iob */;
4335     info.func               = __cvmx_error_display;
4336     info.user_info          = (long)
4337         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
4338         "    port for a non-passthrough packet.\n"
4339         "    The first detected error associated with bits [3:0]\n"
4340         "    of this register will only be set here. A new bit\n"
4341         "    can be set when the previous reported bit is cleared.\n";
4342     fail |= cvmx_error_add(&info);
4343
4344     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4345     info.status_addr        = CVMX_IOB_INT_SUM;
4346     info.status_mask        = 1ull<<1 /* np_eop */;
4347     info.enable_addr        = CVMX_IOB_INT_ENB;
4348     info.enable_mask        = 1ull<<1 /* np_eop */;
4349     info.flags              = 0;
4350     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4351     info.group_index        = 0;
4352     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4353     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4354     info.parent.status_mask = 1ull<<30 /* iob */;
4355     info.func               = __cvmx_error_display;
4356     info.user_info          = (long)
4357         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
4358         "    port for a non-passthrough packet.\n"
4359         "    The first detected error associated with bits [3:0]\n"
4360         "    of this register will only be set here. A new bit\n"
4361         "    can be set when the previous reported bit is cleared.\n";
4362     fail |= cvmx_error_add(&info);
4363
4364     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4365     info.status_addr        = CVMX_IOB_INT_SUM;
4366     info.status_mask        = 1ull<<2 /* p_sop */;
4367     info.enable_addr        = CVMX_IOB_INT_ENB;
4368     info.enable_mask        = 1ull<<2 /* p_sop */;
4369     info.flags              = 0;
4370     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4371     info.group_index        = 0;
4372     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4373     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4374     info.parent.status_mask = 1ull<<30 /* iob */;
4375     info.func               = __cvmx_error_display;
4376     info.user_info          = (long)
4377         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
4378         "    port for a passthrough packet.\n"
4379         "    The first detected error associated with bits [3:0]\n"
4380         "    of this register will only be set here. A new bit\n"
4381         "    can be set when the previous reported bit is cleared.\n";
4382     fail |= cvmx_error_add(&info);
4383
4384     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4385     info.status_addr        = CVMX_IOB_INT_SUM;
4386     info.status_mask        = 1ull<<3 /* p_eop */;
4387     info.enable_addr        = CVMX_IOB_INT_ENB;
4388     info.enable_mask        = 1ull<<3 /* p_eop */;
4389     info.flags              = 0;
4390     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4391     info.group_index        = 0;
4392     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4393     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4394     info.parent.status_mask = 1ull<<30 /* iob */;
4395     info.func               = __cvmx_error_display;
4396     info.user_info          = (long)
4397         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
4398         "    port for a passthrough packet.\n"
4399         "    The first detected error associated with bits [3:0]\n"
4400         "    of this register will only be set here. A new bit\n"
4401         "    can be set when the previous reported bit is cleared.\n";
4402     fail |= cvmx_error_add(&info);
4403
4404     /* CVMX_ZIP_ERROR */
4405     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4406     info.status_addr        = CVMX_ZIP_ERROR;
4407     info.status_mask        = 1ull<<0 /* doorbell */;
4408     info.enable_addr        = CVMX_ZIP_INT_MASK;
4409     info.enable_mask        = 1ull<<0 /* doorbell */;
4410     info.flags              = 0;
4411     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4412     info.group_index        = 0;
4413     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4414     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4415     info.parent.status_mask = 1ull<<7 /* zip */;
4416     info.func               = __cvmx_error_display;
4417     info.user_info          = (long)
4418         "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4419     fail |= cvmx_error_add(&info);
4420
4421     return fail;
4422 }
4423