sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c

   1 /***********************license start***************
   2  * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
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  20  *     derived from this software without specific prior written
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  28  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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  31  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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  37  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  38  ***********************license end**************************************/
  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn52xxp1.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN52XXP1</h2>
  51  * @dot
  52  * digraph cn52xxp1
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
  59  *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
  60  *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
  61  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  62  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1"];
  63  *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
  64  *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
  65  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  66  *     cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"];
  67  *     cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
  68  *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
  69  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
  70  *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
  71  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
  72  *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
  73  *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
  74  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
  75  *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
  76  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
  77  *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
  78  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
  79  *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
  80  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
  81  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  82  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
  83  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  84  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
  85  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  86  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
  87  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  88  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
  89  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  90  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
  91  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
  92  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
  93  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
  94  *     cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
  95  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
  96  *     cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
  97  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
  98  *     cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
  99  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
 100  *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
 101  *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
 102  *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
 103  *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
 104  *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
 105  *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
 106  *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
 107  *     cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
 108  *     cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
 109  *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
 110  *     cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
 111  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
 112  *     cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
 113  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 114  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
 115  *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 116  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
 117  *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 118  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
 119  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 120  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
 121  *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
 122  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
 123  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
 124  *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
 125  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
 126  *     cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
 127  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
 128  *     cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
 129  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
 130  *     cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
 131  *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
 132  *     cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
 133  *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
 134  *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
 135  *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
 136  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 137  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 138  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 139  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
 140  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 141  *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
 142  *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
 143  *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
 144  *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
 145  *     cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
 146  * }
 147  * @enddot
 148  */
 149 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 150 #include <asm/octeon/cvmx.h>
 151 #include <asm/octeon/cvmx-error.h>
 152 #include <asm/octeon/cvmx-error-custom.h>
 153 #include <asm/octeon/cvmx-csr-typedefs.h>
 154 #else
 155 #include "cvmx.h"
 156 #include "cvmx-error.h"
 157 #include "cvmx-error-custom.h"
 158 #endif
 159
 160 int cvmx_error_initialize_cn52xxp1(void);
 161
 162 int cvmx_error_initialize_cn52xxp1(void)
 163 {
 164     cvmx_error_info_t info;
 165     int fail = 0;
 166
 167     /* CVMX_CIU_INTX_SUM0(0) */
 168     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 169     info.status_addr        = CVMX_CIU_INTX_SUM0(0);
 170     info.status_mask        = 0;
 171     info.enable_addr        = 0;
 172     info.enable_mask        = 0;
 173     info.flags              = 0;
 174     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 175     info.group_index        = 0;
 176     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 177     info.parent.status_addr = 0;
 178     info.parent.status_mask = 0;
 179     info.func               = __cvmx_error_decode;
 180     info.user_info          = 0;
 181     fail |= cvmx_error_add(&info);
 182
 183     /* CVMX_MIXX_ISR(0) */
 184     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 185     info.status_addr        = CVMX_MIXX_ISR(0);
 186     info.status_mask        = 1ull<<0 /* odblovf */;
 187     info.enable_addr        = CVMX_MIXX_INTENA(0);
 188     info.enable_mask        = 1ull<<0 /* ovfena */;
 189     info.flags              = 0;
 190     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 191     info.group_index        = 0;
 192     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 193     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 194     info.parent.status_mask = 1ull<<62 /* mii */;
 195     info.func               = __cvmx_error_display;
 196     info.user_info          = (long)
 197         "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
 198         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
 199         "    with a value greater than the remaining #of\n"
 200         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
 201         "    the following occurs:\n"
 202         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
 203         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 204         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 205         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 206         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
 207         "    interrupt is reported for this event.\n"
 208         "    SW should keep track of the #I-Ring Entries in use\n"
 209         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
 210         "    future ODBELL writes don't exceed the size of the\n"
 211         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
 212         "    SW must reclaim O-Ring Entries by writing to the\n"
 213         "    MIX_ORCNT[ORCNT]. .\n"
 214         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
 215         "    If it occurs, it's an indication that SW has\n"
 216         "    overwritten the O-Ring buffer, and the only recourse\n"
 217         "    is a HW reset.\n";
 218     fail |= cvmx_error_add(&info);
 219
 220     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 221     info.status_addr        = CVMX_MIXX_ISR(0);
 222     info.status_mask        = 1ull<<1 /* idblovf */;
 223     info.enable_addr        = CVMX_MIXX_INTENA(0);
 224     info.enable_mask        = 1ull<<1 /* ivfena */;
 225     info.flags              = 0;
 226     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 227     info.group_index        = 0;
 228     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 229     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 230     info.parent.status_mask = 1ull<<62 /* mii */;
 231     info.func               = __cvmx_error_display;
 232     info.user_info          = (long)
 233         "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
 234         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
 235         "    with a value greater than the remaining #of\n"
 236         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
 237         "    the following occurs:\n"
 238         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
 239         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 240         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 241         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 242         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
 243         "    interrupt is reported for this event.\n"
 244         "    SW should keep track of the #I-Ring Entries in use\n"
 245         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
 246         "    future IDBELL writes don't exceed the size of the\n"
 247         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
 248         "    SW must reclaim I-Ring Entries by keeping track of the\n"
 249         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
 250         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
 251         "    total #packets(not IRing Entries) and SW must further\n"
 252         "    keep track of the # of I-Ring Entries associated with\n"
 253         "    each packet as they are processed.\n"
 254         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
 255         "    If it occurs, it's an indication that SW has\n"
 256         "    overwritten the I-Ring buffer, and the only recourse\n"
 257         "    is a HW reset.\n";
 258     fail |= cvmx_error_add(&info);
 259
 260     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 261     info.status_addr        = CVMX_MIXX_ISR(0);
 262     info.status_mask        = 1ull<<4 /* data_drp */;
 263     info.enable_addr        = CVMX_MIXX_INTENA(0);
 264     info.enable_mask        = 1ull<<4 /* data_drpena */;
 265     info.flags              = 0;
 266     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 267     info.group_index        = 0;
 268     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 269     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 270     info.parent.status_mask = 1ull<<62 /* mii */;
 271     info.func               = __cvmx_error_display;
 272     info.user_info          = (long)
 273         "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
 274         "    If this does occur, the DATA_DRP is set and the\n"
 275         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
 276         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 277         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
 278         "    interrupt is reported for this event.\n";
 279     fail |= cvmx_error_add(&info);
 280
 281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 282     info.status_addr        = CVMX_MIXX_ISR(0);
 283     info.status_mask        = 1ull<<5 /* irun */;
 284     info.enable_addr        = CVMX_MIXX_INTENA(0);
 285     info.enable_mask        = 1ull<<5 /* irunena */;
 286     info.flags              = 0;
 287     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 288     info.group_index        = 0;
 289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 290     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 291     info.parent.status_mask = 1ull<<62 /* mii */;
 292     info.func               = __cvmx_error_display;
 293     info.user_info          = (long)
 294         "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
 295         "    If SW writes a larger value than what is currently\n"
 296         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
 297         "    underflow condition.\n"
 298         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
 299         "    NOTE: If an IRUN underflow condition is detected,\n"
 300         "    the integrity of the MIX/AGL HW state has\n"
 301         "    been compromised. To recover, SW must issue a\n"
 302         "    software reset sequence (see: MIX_CTL[RESET]\n";
 303     fail |= cvmx_error_add(&info);
 304
 305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 306     info.status_addr        = CVMX_MIXX_ISR(0);
 307     info.status_mask        = 1ull<<6 /* orun */;
 308     info.enable_addr        = CVMX_MIXX_INTENA(0);
 309     info.enable_mask        = 1ull<<6 /* orunena */;
 310     info.flags              = 0;
 311     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 312     info.group_index        = 0;
 313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 314     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 315     info.parent.status_mask = 1ull<<62 /* mii */;
 316     info.func               = __cvmx_error_display;
 317     info.user_info          = (long)
 318         "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
 319         "    If SW writes a larger value than what is currently\n"
 320         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
 321         "    underflow condition.\n"
 322         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
 323         "    NOTE: If an ORUN underflow condition is detected,\n"
 324         "    the integrity of the MIX/AGL HW state has\n"
 325         "    been compromised. To recover, SW must issue a\n"
 326         "    software reset sequence (see: MIX_CTL[RESET]\n";
 327     fail |= cvmx_error_add(&info);
 328
 329     /* CVMX_CIU_INT_SUM1 */
 330     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 331     info.status_addr        = CVMX_CIU_INT_SUM1;
 332     info.status_mask        = 0;
 333     info.enable_addr        = 0;
 334     info.enable_mask        = 0;
 335     info.flags              = 0;
 336     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 337     info.group_index        = 0;
 338     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 339     info.parent.status_addr = 0;
 340     info.parent.status_mask = 0;
 341     info.func               = __cvmx_error_decode;
 342     info.user_info          = 0;
 343     fail |= cvmx_error_add(&info);
 344
 345     /* CVMX_MIXX_ISR(1) */
 346     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 347     info.status_addr        = CVMX_MIXX_ISR(1);
 348     info.status_mask        = 1ull<<0 /* odblovf */;
 349     info.enable_addr        = CVMX_MIXX_INTENA(1);
 350     info.enable_mask        = 1ull<<0 /* ovfena */;
 351     info.flags              = 0;
 352     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 353     info.group_index        = 1;
 354     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 355     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 356     info.parent.status_mask = 1ull<<18 /* mii1 */;
 357     info.func               = __cvmx_error_display;
 358     info.user_info          = (long)
 359         "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
 360         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
 361         "    with a value greater than the remaining #of\n"
 362         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
 363         "    the following occurs:\n"
 364         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
 365         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 366         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 367         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 368         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
 369         "    interrupt is reported for this event.\n"
 370         "    SW should keep track of the #I-Ring Entries in use\n"
 371         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
 372         "    future ODBELL writes don't exceed the size of the\n"
 373         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
 374         "    SW must reclaim O-Ring Entries by writing to the\n"
 375         "    MIX_ORCNT[ORCNT]. .\n"
 376         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
 377         "    If it occurs, it's an indication that SW has\n"
 378         "    overwritten the O-Ring buffer, and the only recourse\n"
 379         "    is a HW reset.\n";
 380     fail |= cvmx_error_add(&info);
 381
 382     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 383     info.status_addr        = CVMX_MIXX_ISR(1);
 384     info.status_mask        = 1ull<<1 /* idblovf */;
 385     info.enable_addr        = CVMX_MIXX_INTENA(1);
 386     info.enable_mask        = 1ull<<1 /* ivfena */;
 387     info.flags              = 0;
 388     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 389     info.group_index        = 1;
 390     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 391     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 392     info.parent.status_mask = 1ull<<18 /* mii1 */;
 393     info.func               = __cvmx_error_display;
 394     info.user_info          = (long)
 395         "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
 396         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
 397         "    with a value greater than the remaining #of\n"
 398         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
 399         "    the following occurs:\n"
 400         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
 401         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 402         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 403         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 404         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
 405         "    interrupt is reported for this event.\n"
 406         "    SW should keep track of the #I-Ring Entries in use\n"
 407         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
 408         "    future IDBELL writes don't exceed the size of the\n"
 409         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
 410         "    SW must reclaim I-Ring Entries by keeping track of the\n"
 411         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
 412         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
 413         "    total #packets(not IRing Entries) and SW must further\n"
 414         "    keep track of the # of I-Ring Entries associated with\n"
 415         "    each packet as they are processed.\n"
 416         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
 417         "    If it occurs, it's an indication that SW has\n"
 418         "    overwritten the I-Ring buffer, and the only recourse\n"
 419         "    is a HW reset.\n";
 420     fail |= cvmx_error_add(&info);
 421
 422     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 423     info.status_addr        = CVMX_MIXX_ISR(1);
 424     info.status_mask        = 1ull<<4 /* data_drp */;
 425     info.enable_addr        = CVMX_MIXX_INTENA(1);
 426     info.enable_mask        = 1ull<<4 /* data_drpena */;
 427     info.flags              = 0;
 428     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 429     info.group_index        = 1;
 430     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 431     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 432     info.parent.status_mask = 1ull<<18 /* mii1 */;
 433     info.func               = __cvmx_error_display;
 434     info.user_info          = (long)
 435         "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
 436         "    If this does occur, the DATA_DRP is set and the\n"
 437         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
 438         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 439         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
 440         "    interrupt is reported for this event.\n";
 441     fail |= cvmx_error_add(&info);
 442
 443     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 444     info.status_addr        = CVMX_MIXX_ISR(1);
 445     info.status_mask        = 1ull<<5 /* irun */;
 446     info.enable_addr        = CVMX_MIXX_INTENA(1);
 447     info.enable_mask        = 1ull<<5 /* irunena */;
 448     info.flags              = 0;
 449     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 450     info.group_index        = 1;
 451     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 452     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 453     info.parent.status_mask = 1ull<<18 /* mii1 */;
 454     info.func               = __cvmx_error_display;
 455     info.user_info          = (long)
 456         "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
 457         "    If SW writes a larger value than what is currently\n"
 458         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
 459         "    underflow condition.\n"
 460         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
 461         "    NOTE: If an IRUN underflow condition is detected,\n"
 462         "    the integrity of the MIX/AGL HW state has\n"
 463         "    been compromised. To recover, SW must issue a\n"
 464         "    software reset sequence (see: MIX_CTL[RESET]\n";
 465     fail |= cvmx_error_add(&info);
 466
 467     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 468     info.status_addr        = CVMX_MIXX_ISR(1);
 469     info.status_mask        = 1ull<<6 /* orun */;
 470     info.enable_addr        = CVMX_MIXX_INTENA(1);
 471     info.enable_mask        = 1ull<<6 /* orunena */;
 472     info.flags              = 0;
 473     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 474     info.group_index        = 1;
 475     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 476     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 477     info.parent.status_mask = 1ull<<18 /* mii1 */;
 478     info.func               = __cvmx_error_display;
 479     info.user_info          = (long)
 480         "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
 481         "    If SW writes a larger value than what is currently\n"
 482         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
 483         "    underflow condition.\n"
 484         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
 485         "    NOTE: If an ORUN underflow condition is detected,\n"
 486         "    the integrity of the MIX/AGL HW state has\n"
 487         "    been compromised. To recover, SW must issue a\n"
 488         "    software reset sequence (see: MIX_CTL[RESET]\n";
 489     fail |= cvmx_error_add(&info);
 490
 491     /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
 492     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 493     info.status_addr        = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 494     info.status_mask        = 0;
 495     info.enable_addr        = 0;
 496     info.enable_mask        = 0;
 497     info.flags              = 0;
 498     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 499     info.group_index        = 0;
 500     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 501     info.parent.status_addr = 0;
 502     info.parent.status_mask = 0;
 503     info.func               = __cvmx_error_decode;
 504     info.user_info          = 0;
 505     fail |= cvmx_error_add(&info);
 506
 507     /* CVMX_L2C_INT_STAT */
 508     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 509     info.status_addr        = CVMX_L2C_INT_STAT;
 510     info.status_mask        = 1ull<<3 /* l2tsec */;
 511     info.enable_addr        = CVMX_L2C_INT_EN;
 512     info.enable_mask        = 1ull<<3 /* l2tsecen */;
 513     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 514     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 515     info.group_index        = 0;
 516     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 517     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 518     info.parent.status_mask = 1ull<<16 /* l2c */;
 519     info.func               = __cvmx_error_display;
 520     info.user_info          = (long)
 521         "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
 522         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 523         "    given index) are checked for single bit errors(SBEs).\n"
 524         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 525         "    SBEs are auto corrected in HW and generate an\n"
 526         "    interrupt(if enabled).\n"
 527         "    NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
 528     fail |= cvmx_error_add(&info);
 529
 530     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 531     info.status_addr        = CVMX_L2C_INT_STAT;
 532     info.status_mask        = 1ull<<5 /* l2dsec */;
 533     info.enable_addr        = CVMX_L2C_INT_EN;
 534     info.enable_mask        = 1ull<<5 /* l2dsecen */;
 535     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 536     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 537     info.group_index        = 0;
 538     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 539     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 540     info.parent.status_mask = 1ull<<16 /* l2c */;
 541     info.func               = __cvmx_error_display;
 542     info.user_info          = (long)
 543         "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
 544         "    NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
 545     fail |= cvmx_error_add(&info);
 546
 547     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 548     info.status_addr        = CVMX_L2C_INT_STAT;
 549     info.status_mask        = 1ull<<0 /* oob1 */;
 550     info.enable_addr        = CVMX_L2C_INT_EN;
 551     info.enable_mask        = 1ull<<0 /* oob1en */;
 552     info.flags              = 0;
 553     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 554     info.group_index        = 0;
 555     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 556     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 557     info.parent.status_mask = 1ull<<16 /* l2c */;
 558     info.func               = __cvmx_error_display;
 559     info.user_info          = (long)
 560         "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
 561     fail |= cvmx_error_add(&info);
 562
 563     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 564     info.status_addr        = CVMX_L2C_INT_STAT;
 565     info.status_mask        = 1ull<<1 /* oob2 */;
 566     info.enable_addr        = CVMX_L2C_INT_EN;
 567     info.enable_mask        = 1ull<<1 /* oob2en */;
 568     info.flags              = 0;
 569     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 570     info.group_index        = 0;
 571     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 572     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 573     info.parent.status_mask = 1ull<<16 /* l2c */;
 574     info.func               = __cvmx_error_display;
 575     info.user_info          = (long)
 576         "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
 577     fail |= cvmx_error_add(&info);
 578
 579     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 580     info.status_addr        = CVMX_L2C_INT_STAT;
 581     info.status_mask        = 1ull<<2 /* oob3 */;
 582     info.enable_addr        = CVMX_L2C_INT_EN;
 583     info.enable_mask        = 1ull<<2 /* oob3en */;
 584     info.flags              = 0;
 585     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 586     info.group_index        = 0;
 587     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 588     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 589     info.parent.status_mask = 1ull<<16 /* l2c */;
 590     info.func               = __cvmx_error_display;
 591     info.user_info          = (long)
 592         "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
 593     fail |= cvmx_error_add(&info);
 594
 595     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 596     info.status_addr        = CVMX_L2C_INT_STAT;
 597     info.status_mask        = 1ull<<4 /* l2tded */;
 598     info.enable_addr        = CVMX_L2C_INT_EN;
 599     info.enable_mask        = 1ull<<4 /* l2tdeden */;
 600     info.flags              = 0;
 601     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 602     info.group_index        = 0;
 603     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 604     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 605     info.parent.status_mask = 1ull<<16 /* l2c */;
 606     info.func               = __cvmx_error_display;
 607     info.user_info          = (long)
 608         "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
 609         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 610         "    given index) are checked for double bit errors(DBEs).\n"
 611         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 612         "    DBEs also generated an interrupt(if enabled).\n"
 613         "    NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
 614     fail |= cvmx_error_add(&info);
 615
 616     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 617     info.status_addr        = CVMX_L2C_INT_STAT;
 618     info.status_mask        = 1ull<<6 /* l2dded */;
 619     info.enable_addr        = CVMX_L2C_INT_EN;
 620     info.enable_mask        = 1ull<<6 /* l2ddeden */;
 621     info.flags              = 0;
 622     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 623     info.group_index        = 0;
 624     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 625     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 626     info.parent.status_mask = 1ull<<16 /* l2c */;
 627     info.func               = __cvmx_error_display;
 628     info.user_info          = (long)
 629         "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
 630         "    NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
 631     fail |= cvmx_error_add(&info);
 632
 633     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 634     info.status_addr        = CVMX_L2C_INT_STAT;
 635     info.status_mask        = 1ull<<7 /* lck */;
 636     info.enable_addr        = CVMX_L2C_INT_EN;
 637     info.enable_mask        = 1ull<<7 /* lckena */;
 638     info.flags              = 0;
 639     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 640     info.group_index        = 0;
 641     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 642     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 643     info.parent.status_mask = 1ull<<16 /* l2c */;
 644     info.func               = __cvmx_error_display;
 645     info.user_info          = (long)
 646         "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
 647         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 648         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 649         "    successfully, however the address is NOT locked.\n"
 650         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 651         "    into account. For example, if diagnostic PPx has\n"
 652         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 653         "    been previously LOCKED, then an attempt to LOCK the\n"
 654         "    last available SET0 would result in a LCKERR. (This\n"
 655         "    is to ensure that at least 1 SET at each INDEX is\n"
 656         "    not LOCKED for general use by other PPs).\n"
 657         "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
 658     fail |= cvmx_error_add(&info);
 659
 660     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 661     info.status_addr        = CVMX_L2C_INT_STAT;
 662     info.status_mask        = 1ull<<8 /* lck2 */;
 663     info.enable_addr        = CVMX_L2C_INT_EN;
 664     info.enable_mask        = 1ull<<8 /* lck2ena */;
 665     info.flags              = 0;
 666     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 667     info.group_index        = 0;
 668     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 669     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 670     info.parent.status_mask = 1ull<<16 /* l2c */;
 671     info.func               = __cvmx_error_display;
 672     info.user_info          = (long)
 673         "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 674         "    could not find an available/unlocked set (for\n"
 675         "    replacement).\n"
 676         "    Most likely, this is a result of SW mixing SET\n"
 677         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 678         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 679         "    then a Rd/Wr Miss from PP#n will be unable\n"
 680         "    to determine a 'valid' replacement set (since LOCKED\n"
 681         "    addresses should NEVER be replaced).\n"
 682         "    If such an event occurs, the HW will select the smallest\n"
 683         "    available SET(specified by UMSK'x)' as the replacement\n"
 684         "    set, and the address is unlocked.\n"
 685         "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
 686     fail |= cvmx_error_add(&info);
 687
 688     /* CVMX_L2D_ERR */
 689     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 690     info.status_addr        = CVMX_L2D_ERR;
 691     info.status_mask        = 1ull<<3 /* sec_err */;
 692     info.enable_addr        = CVMX_L2D_ERR;
 693     info.enable_mask        = 1ull<<1 /* sec_intena */;
 694     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 695     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 696     info.group_index        = 0;
 697     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 698     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 699     info.parent.status_mask = 1ull<<16 /* l2c */;
 700     info.func               = __cvmx_error_handle_l2d_err_sec_err;
 701     info.user_info          = (long)
 702         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
 703     fail |= cvmx_error_add(&info);
 704
 705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 706     info.status_addr        = CVMX_L2D_ERR;
 707     info.status_mask        = 1ull<<4 /* ded_err */;
 708     info.enable_addr        = CVMX_L2D_ERR;
 709     info.enable_mask        = 1ull<<2 /* ded_intena */;
 710     info.flags              = 0;
 711     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 712     info.group_index        = 0;
 713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 714     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 715     info.parent.status_mask = 1ull<<16 /* l2c */;
 716     info.func               = __cvmx_error_handle_l2d_err_ded_err;
 717     info.user_info          = (long)
 718         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
 719     fail |= cvmx_error_add(&info);
 720
 721     /* CVMX_L2T_ERR */
 722     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 723     info.status_addr        = CVMX_L2T_ERR;
 724     info.status_mask        = 1ull<<3 /* sec_err */;
 725     info.enable_addr        = CVMX_L2T_ERR;
 726     info.enable_mask        = 1ull<<1 /* sec_intena */;
 727     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 728     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 729     info.group_index        = 0;
 730     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 731     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 732     info.parent.status_mask = 1ull<<16 /* l2c */;
 733     info.func               = __cvmx_error_handle_l2t_err_sec_err;
 734     info.user_info          = (long)
 735         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
 736         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 737         "    given index) are checked for single bit errors(SBEs).\n"
 738         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 739         "    SBEs are auto corrected in HW and generate an\n"
 740         "    interrupt(if enabled).\n";
 741     fail |= cvmx_error_add(&info);
 742
 743     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 744     info.status_addr        = CVMX_L2T_ERR;
 745     info.status_mask        = 1ull<<4 /* ded_err */;
 746     info.enable_addr        = CVMX_L2T_ERR;
 747     info.enable_mask        = 1ull<<2 /* ded_intena */;
 748     info.flags              = 0;
 749     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 750     info.group_index        = 0;
 751     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 752     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 753     info.parent.status_mask = 1ull<<16 /* l2c */;
 754     info.func               = __cvmx_error_handle_l2t_err_ded_err;
 755     info.user_info          = (long)
 756         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
 757         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 758         "    given index) are checked for double bit errors(DBEs).\n"
 759         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 760         "    DBEs also generated an interrupt(if enabled).\n";
 761     fail |= cvmx_error_add(&info);
 762
 763     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 764     info.status_addr        = CVMX_L2T_ERR;
 765     info.status_mask        = 1ull<<24 /* lckerr */;
 766     info.enable_addr        = CVMX_L2T_ERR;
 767     info.enable_mask        = 1ull<<25 /* lck_intena */;
 768     info.flags              = 0;
 769     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 770     info.group_index        = 0;
 771     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 772     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 773     info.parent.status_mask = 1ull<<16 /* l2c */;
 774     info.func               = __cvmx_error_handle_l2t_err_lckerr;
 775     info.user_info          = (long)
 776         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
 777         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 778         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 779         "    successfully, however the address is NOT locked.\n"
 780         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 781         "    into account. For example, if diagnostic PPx has\n"
 782         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 783         "    been previously LOCKED, then an attempt to LOCK the\n"
 784         "    last available SET0 would result in a LCKERR. (This\n"
 785         "    is to ensure that at least 1 SET at each INDEX is\n"
 786         "    not LOCKED for general use by other PPs).\n";
 787     fail |= cvmx_error_add(&info);
 788
 789     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 790     info.status_addr        = CVMX_L2T_ERR;
 791     info.status_mask        = 1ull<<26 /* lckerr2 */;
 792     info.enable_addr        = CVMX_L2T_ERR;
 793     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
 794     info.flags              = 0;
 795     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 796     info.group_index        = 0;
 797     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 798     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 799     info.parent.status_mask = 1ull<<16 /* l2c */;
 800     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
 801     info.user_info          = (long)
 802         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 803         "    could not find an available/unlocked set (for\n"
 804         "    replacement).\n"
 805         "    Most likely, this is a result of SW mixing SET\n"
 806         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 807         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 808         "    then a Rd/Wr Miss from PP#n will be unable\n"
 809         "    to determine a 'valid' replacement set (since LOCKED\n"
 810         "    addresses should NEVER be replaced).\n"
 811         "    If such an event occurs, the HW will select the smallest\n"
 812         "    available SET(specified by UMSK'x)' as the replacement\n"
 813         "    set, and the address is unlocked.\n";
 814     fail |= cvmx_error_add(&info);
 815
 816     /* CVMX_AGL_GMX_BAD_REG */
 817     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 818     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 819     info.status_mask        = 1ull<<32 /* ovrflw */;
 820     info.enable_addr        = 0;
 821     info.enable_mask        = 0;
 822     info.flags              = 0;
 823     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 824     info.group_index        = 0;
 825     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 826     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 827     info.parent.status_mask = 1ull<<28 /* agl */;
 828     info.func               = __cvmx_error_display;
 829     info.user_info          = (long)
 830         "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
 831     fail |= cvmx_error_add(&info);
 832
 833     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 834     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 835     info.status_mask        = 1ull<<33 /* txpop */;
 836     info.enable_addr        = 0;
 837     info.enable_mask        = 0;
 838     info.flags              = 0;
 839     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 840     info.group_index        = 0;
 841     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 842     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 843     info.parent.status_mask = 1ull<<28 /* agl */;
 844     info.func               = __cvmx_error_display;
 845     info.user_info          = (long)
 846         "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
 847     fail |= cvmx_error_add(&info);
 848
 849     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 850     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 851     info.status_mask        = 1ull<<34 /* txpsh */;
 852     info.enable_addr        = 0;
 853     info.enable_mask        = 0;
 854     info.flags              = 0;
 855     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 856     info.group_index        = 0;
 857     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 858     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 859     info.parent.status_mask = 1ull<<28 /* agl */;
 860     info.func               = __cvmx_error_display;
 861     info.user_info          = (long)
 862         "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
 863     fail |= cvmx_error_add(&info);
 864
 865     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 866     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 867     info.status_mask        = 1ull<<35 /* ovrflw1 */;
 868     info.enable_addr        = 0;
 869     info.enable_mask        = 0;
 870     info.flags              = 0;
 871     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 872     info.group_index        = 0;
 873     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 874     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 875     info.parent.status_mask = 1ull<<28 /* agl */;
 876     info.func               = __cvmx_error_display;
 877     info.user_info          = (long)
 878         "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
 879     fail |= cvmx_error_add(&info);
 880
 881     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 882     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 883     info.status_mask        = 1ull<<36 /* txpop1 */;
 884     info.enable_addr        = 0;
 885     info.enable_mask        = 0;
 886     info.flags              = 0;
 887     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 888     info.group_index        = 0;
 889     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 890     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 891     info.parent.status_mask = 1ull<<28 /* agl */;
 892     info.func               = __cvmx_error_display;
 893     info.user_info          = (long)
 894         "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
 895     fail |= cvmx_error_add(&info);
 896
 897     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 898     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 899     info.status_mask        = 1ull<<37 /* txpsh1 */;
 900     info.enable_addr        = 0;
 901     info.enable_mask        = 0;
 902     info.flags              = 0;
 903     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 904     info.group_index        = 0;
 905     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 906     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 907     info.parent.status_mask = 1ull<<28 /* agl */;
 908     info.func               = __cvmx_error_display;
 909     info.user_info          = (long)
 910         "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
 911     fail |= cvmx_error_add(&info);
 912
 913     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 914     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 915     info.status_mask        = 0x3ull<<2 /* out_ovr */;
 916     info.enable_addr        = 0;
 917     info.enable_mask        = 0;
 918     info.flags              = 0;
 919     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 920     info.group_index        = 0;
 921     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 922     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 923     info.parent.status_mask = 1ull<<28 /* agl */;
 924     info.func               = __cvmx_error_display;
 925     info.user_info          = (long)
 926         "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
 927     fail |= cvmx_error_add(&info);
 928
 929     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 930     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 931     info.status_mask        = 1ull<<22 /* loststat */;
 932     info.enable_addr        = 0;
 933     info.enable_mask        = 0;
 934     info.flags              = 0;
 935     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 936     info.group_index        = 0;
 937     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 938     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 939     info.parent.status_mask = 1ull<<28 /* agl */;
 940     info.func               = __cvmx_error_display;
 941     info.user_info          = (long)
 942         "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
 943         "    TX Stats are corrupted\n";
 944     fail |= cvmx_error_add(&info);
 945
 946     /* CVMX_AGL_GMX_RXX_INT_REG(0) */
 947     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 948     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
 949     info.status_mask        = 1ull<<8 /* skperr */;
 950     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
 951     info.enable_mask        = 1ull<<8 /* skperr */;
 952     info.flags              = 0;
 953     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 954     info.group_index        = 0;
 955     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 956     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 957     info.parent.status_mask = 1ull<<28 /* agl */;
 958     info.func               = __cvmx_error_display;
 959     info.user_info          = (long)
 960         "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
 961     fail |= cvmx_error_add(&info);
 962
 963     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 964     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
 965     info.status_mask        = 1ull<<10 /* ovrerr */;
 966     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
 967     info.enable_mask        = 1ull<<10 /* ovrerr */;
 968     info.flags              = 0;
 969     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 970     info.group_index        = 0;
 971     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 972     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 973     info.parent.status_mask = 1ull<<28 /* agl */;
 974     info.func               = __cvmx_error_display;
 975     info.user_info          = (long)
 976         "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
 977         "    This interrupt should never assert\n";
 978     fail |= cvmx_error_add(&info);
 979
 980     /* CVMX_AGL_GMX_RXX_INT_REG(1) */
 981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 982     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
 983     info.status_mask        = 1ull<<8 /* skperr */;
 984     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
 985     info.enable_mask        = 1ull<<8 /* skperr */;
 986     info.flags              = 0;
 987     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 988     info.group_index        = 1;
 989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 990     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 991     info.parent.status_mask = 1ull<<28 /* agl */;
 992     info.func               = __cvmx_error_display;
 993     info.user_info          = (long)
 994         "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
 995     fail |= cvmx_error_add(&info);
 996
 997     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 998     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
 999     info.status_mask        = 1ull<<10 /* ovrerr */;
1000     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
1001     info.enable_mask        = 1ull<<10 /* ovrerr */;
1002     info.flags              = 0;
1003     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
1004     info.group_index        = 1;
1005     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1006     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1007     info.parent.status_mask = 1ull<<28 /* agl */;
1008     info.func               = __cvmx_error_display;
1009     info.user_info          = (long)
1010         "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
1011         "    This interrupt should never assert\n";
1012     fail |= cvmx_error_add(&info);
1013
1014     /* CVMX_AGL_GMX_TX_INT_REG */
1015     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1016     info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
1017     info.status_mask        = 1ull<<0 /* pko_nxa */;
1018     info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
1019     info.enable_mask        = 1ull<<0 /* pko_nxa */;
1020     info.flags              = 0;
1021     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
1022     info.group_index        = 0;
1023     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1024     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1025     info.parent.status_mask = 1ull<<28 /* agl */;
1026     info.func               = __cvmx_error_display;
1027     info.user_info          = (long)
1028         "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
1029     fail |= cvmx_error_add(&info);
1030
1031     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1032     info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
1033     info.status_mask        = 0x3ull<<2 /* undflw */;
1034     info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
1035     info.enable_mask        = 0x3ull<<2 /* undflw */;
1036     info.flags              = 0;
1037     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
1038     info.group_index        = 0;
1039     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1040     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1041     info.parent.status_mask = 1ull<<28 /* agl */;
1042     info.func               = __cvmx_error_display;
1043     info.user_info          = (long)
1044         "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
1045     fail |= cvmx_error_add(&info);
1046
1047     /* CVMX_GMXX_BAD_REG(0) */
1048     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1049     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1050     info.status_mask        = 0xfull<<2 /* out_ovr */;
1051     info.enable_addr        = 0;
1052     info.enable_mask        = 0;
1053     info.flags              = 0;
1054     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1055     info.group_index        = 0;
1056     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1057     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1058     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1059     info.func               = __cvmx_error_display;
1060     info.user_info          = (long)
1061         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1062     fail |= cvmx_error_add(&info);
1063
1064     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1065     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1066     info.status_mask        = 0xfull<<22 /* loststat */;
1067     info.enable_addr        = 0;
1068     info.enable_mask        = 0;
1069     info.flags              = 0;
1070     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1071     info.group_index        = 0;
1072     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1073     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1074     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1075     info.func               = __cvmx_error_display;
1076     info.user_info          = (long)
1077         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
1078         "    In SGMII, one bit per port\n"
1079         "    In XAUI, only port0 is used\n"
1080         "    TX Stats are corrupted\n";
1081     fail |= cvmx_error_add(&info);
1082
1083     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1084     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1085     info.status_mask        = 1ull<<26 /* statovr */;
1086     info.enable_addr        = 0;
1087     info.enable_mask        = 0;
1088     info.flags              = 0;
1089     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1090     info.group_index        = 0;
1091     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1092     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1093     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1094     info.func               = __cvmx_error_display;
1095     info.user_info          = (long)
1096         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
1097         "    The common FIFO to SGMII and XAUI had an overflow\n"
1098         "    TX Stats are corrupted\n";
1099     fail |= cvmx_error_add(&info);
1100
1101     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1102     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1103     info.status_mask        = 0xfull<<27 /* inb_nxa */;
1104     info.enable_addr        = 0;
1105     info.enable_mask        = 0;
1106     info.flags              = 0;
1107     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1108     info.group_index        = 0;
1109     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1110     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1111     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1112     info.func               = __cvmx_error_display;
1113     info.user_info          = (long)
1114         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1115     fail |= cvmx_error_add(&info);
1116
1117     /* CVMX_GMXX_RXX_INT_REG(0,0) */
1118     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1119     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1120     info.status_mask        = 1ull<<1 /* carext */;
1121     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1122     info.enable_mask        = 1ull<<1 /* carext */;
1123     info.flags              = 0;
1124     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1125     info.group_index        = 0;
1126     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1127     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1128     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1129     info.func               = __cvmx_error_display;
1130     info.user_info          = (long)
1131         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
1132         "    (SGMII/1000Base-X only)\n";
1133     fail |= cvmx_error_add(&info);
1134
1135     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1136     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1137     info.status_mask        = 1ull<<8 /* skperr */;
1138     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1139     info.enable_mask        = 1ull<<8 /* skperr */;
1140     info.flags              = 0;
1141     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1142     info.group_index        = 0;
1143     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1144     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1145     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1146     info.func               = __cvmx_error_display;
1147     info.user_info          = (long)
1148         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
1149     fail |= cvmx_error_add(&info);
1150
1151     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1152     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1153     info.status_mask        = 1ull<<10 /* ovrerr */;
1154     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1155     info.enable_mask        = 1ull<<10 /* ovrerr */;
1156     info.flags              = 0;
1157     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1158     info.group_index        = 0;
1159     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1160     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1161     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1162     info.func               = __cvmx_error_display;
1163     info.user_info          = (long)
1164         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1165         "    This interrupt should never assert\n"
1166         "    (SGMII/1000Base-X only)\n";
1167     fail |= cvmx_error_add(&info);
1168
1169     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1170     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1171     info.status_mask        = 1ull<<20 /* loc_fault */;
1172     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1173     info.enable_mask        = 1ull<<20 /* loc_fault */;
1174     info.flags              = 0;
1175     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1176     info.group_index        = 0;
1177     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1178     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1179     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1180     info.func               = __cvmx_error_display;
1181     info.user_info          = (long)
1182         "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1183         "    (XAUI Mode only)\n";
1184     fail |= cvmx_error_add(&info);
1185
1186     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1187     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1188     info.status_mask        = 1ull<<21 /* rem_fault */;
1189     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1190     info.enable_mask        = 1ull<<21 /* rem_fault */;
1191     info.flags              = 0;
1192     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1193     info.group_index        = 0;
1194     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1195     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1196     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1197     info.func               = __cvmx_error_display;
1198     info.user_info          = (long)
1199         "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1200         "    (XAUI Mode only)\n";
1201     fail |= cvmx_error_add(&info);
1202
1203     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1204     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1205     info.status_mask        = 1ull<<22 /* bad_seq */;
1206     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1207     info.enable_mask        = 1ull<<22 /* bad_seq */;
1208     info.flags              = 0;
1209     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1210     info.group_index        = 0;
1211     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1212     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1213     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1214     info.func               = __cvmx_error_display;
1215     info.user_info          = (long)
1216         "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1217         "    (XAUI Mode only)\n";
1218     fail |= cvmx_error_add(&info);
1219
1220     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1221     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1222     info.status_mask        = 1ull<<23 /* bad_term */;
1223     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1224     info.enable_mask        = 1ull<<23 /* bad_term */;
1225     info.flags              = 0;
1226     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1227     info.group_index        = 0;
1228     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1229     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1230     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1231     info.func               = __cvmx_error_display;
1232     info.user_info          = (long)
1233         "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
1234         "    than /T/.  The error propagation control\n"
1235         "    character /E/ will be included as part of the\n"
1236         "    frame and does not cause a frame termination.\n"
1237         "    (XAUI Mode only)\n";
1238     fail |= cvmx_error_add(&info);
1239
1240     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1241     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1242     info.status_mask        = 1ull<<24 /* unsop */;
1243     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1244     info.enable_mask        = 1ull<<24 /* unsop */;
1245     info.flags              = 0;
1246     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1247     info.group_index        = 0;
1248     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1249     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1250     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1251     info.func               = __cvmx_error_display;
1252     info.user_info          = (long)
1253         "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
1254         "    (XAUI Mode only)\n";
1255     fail |= cvmx_error_add(&info);
1256
1257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1258     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1259     info.status_mask        = 1ull<<25 /* uneop */;
1260     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1261     info.enable_mask        = 1ull<<25 /* uneop */;
1262     info.flags              = 0;
1263     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1264     info.group_index        = 0;
1265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1266     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1267     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1268     info.func               = __cvmx_error_display;
1269     info.user_info          = (long)
1270         "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
1271         "    (XAUI Mode only)\n";
1272     fail |= cvmx_error_add(&info);
1273
1274     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1275     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1276     info.status_mask        = 1ull<<26 /* undat */;
1277     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1278     info.enable_mask        = 1ull<<26 /* undat */;
1279     info.flags              = 0;
1280     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1281     info.group_index        = 0;
1282     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1283     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1284     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1285     info.func               = __cvmx_error_display;
1286     info.user_info          = (long)
1287         "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
1288         "    (XAUI Mode only)\n";
1289     fail |= cvmx_error_add(&info);
1290
1291     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1292     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1293     info.status_mask        = 1ull<<27 /* hg2fld */;
1294     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1295     info.enable_mask        = 1ull<<27 /* hg2fld */;
1296     info.flags              = 0;
1297     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1298     info.group_index        = 0;
1299     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1300     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1301     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1302     info.func               = __cvmx_error_display;
1303     info.user_info          = (long)
1304         "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1305         "    1) MSG_TYPE field not 6'b00_0000\n"
1306         "       i.e. it is not a FLOW CONTROL message, which\n"
1307         "       is the only defined type for HiGig2\n"
1308         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1309         "       which is the only defined type for HiGig2\n"
1310         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1311         "       Physical Link nor 4'b0010 for Logical Link.\n"
1312         "       Those are the only two defined types in HiGig2\n";
1313     fail |= cvmx_error_add(&info);
1314
1315     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1316     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1317     info.status_mask        = 1ull<<28 /* hg2cc */;
1318     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1319     info.enable_mask        = 1ull<<28 /* hg2cc */;
1320     info.flags              = 0;
1321     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1322     info.group_index        = 0;
1323     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1324     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1325     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1326     info.func               = __cvmx_error_display;
1327     info.user_info          = (long)
1328         "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1329         "    Set when either CRC8 error detected or when\n"
1330         "    a Control Character is found in the message\n"
1331         "    bytes after the K.SOM\n"
1332         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1333         "          i.e. a HiGig2 message that results in HG2CC\n"
1334         "          getting set, will never set HG2FLD.\n";
1335     fail |= cvmx_error_add(&info);
1336
1337     /* CVMX_GMXX_RXX_INT_REG(1,0) */
1338     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1339     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1340     info.status_mask        = 1ull<<1 /* carext */;
1341     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1342     info.enable_mask        = 1ull<<1 /* carext */;
1343     info.flags              = 0;
1344     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1345     info.group_index        = 1;
1346     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1347     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1348     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1349     info.func               = __cvmx_error_display;
1350     info.user_info          = (long)
1351         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
1352         "    (SGMII/1000Base-X only)\n";
1353     fail |= cvmx_error_add(&info);
1354
1355     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1356     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1357     info.status_mask        = 1ull<<8 /* skperr */;
1358     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1359     info.enable_mask        = 1ull<<8 /* skperr */;
1360     info.flags              = 0;
1361     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1362     info.group_index        = 1;
1363     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1364     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1365     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1366     info.func               = __cvmx_error_display;
1367     info.user_info          = (long)
1368         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1369     fail |= cvmx_error_add(&info);
1370
1371     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1372     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1373     info.status_mask        = 1ull<<10 /* ovrerr */;
1374     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1375     info.enable_mask        = 1ull<<10 /* ovrerr */;
1376     info.flags              = 0;
1377     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1378     info.group_index        = 1;
1379     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1380     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1381     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1382     info.func               = __cvmx_error_display;
1383     info.user_info          = (long)
1384         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1385         "    This interrupt should never assert\n"
1386         "    (SGMII/1000Base-X only)\n";
1387     fail |= cvmx_error_add(&info);
1388
1389     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1390     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1391     info.status_mask        = 1ull<<20 /* loc_fault */;
1392     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1393     info.enable_mask        = 1ull<<20 /* loc_fault */;
1394     info.flags              = 0;
1395     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1396     info.group_index        = 1;
1397     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1398     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1399     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1400     info.func               = __cvmx_error_display;
1401     info.user_info          = (long)
1402         "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1403         "    (XAUI Mode only)\n";
1404     fail |= cvmx_error_add(&info);
1405
1406     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1407     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1408     info.status_mask        = 1ull<<21 /* rem_fault */;
1409     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1410     info.enable_mask        = 1ull<<21 /* rem_fault */;
1411     info.flags              = 0;
1412     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1413     info.group_index        = 1;
1414     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1415     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1416     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1417     info.func               = __cvmx_error_display;
1418     info.user_info          = (long)
1419         "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1420         "    (XAUI Mode only)\n";
1421     fail |= cvmx_error_add(&info);
1422
1423     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1424     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1425     info.status_mask        = 1ull<<22 /* bad_seq */;
1426     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1427     info.enable_mask        = 1ull<<22 /* bad_seq */;
1428     info.flags              = 0;
1429     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1430     info.group_index        = 1;
1431     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1432     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1433     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1434     info.func               = __cvmx_error_display;
1435     info.user_info          = (long)
1436         "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1437         "    (XAUI Mode only)\n";
1438     fail |= cvmx_error_add(&info);
1439
1440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1441     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1442     info.status_mask        = 1ull<<23 /* bad_term */;
1443     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1444     info.enable_mask        = 1ull<<23 /* bad_term */;
1445     info.flags              = 0;
1446     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1447     info.group_index        = 1;
1448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1449     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1450     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1451     info.func               = __cvmx_error_display;
1452     info.user_info          = (long)
1453         "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
1454         "    than /T/.  The error propagation control\n"
1455         "    character /E/ will be included as part of the\n"
1456         "    frame and does not cause a frame termination.\n"
1457         "    (XAUI Mode only)\n";
1458     fail |= cvmx_error_add(&info);
1459
1460     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1461     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1462     info.status_mask        = 1ull<<24 /* unsop */;
1463     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1464     info.enable_mask        = 1ull<<24 /* unsop */;
1465     info.flags              = 0;
1466     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1467     info.group_index        = 1;
1468     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1469     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1470     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1471     info.func               = __cvmx_error_display;
1472     info.user_info          = (long)
1473         "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
1474         "    (XAUI Mode only)\n";
1475     fail |= cvmx_error_add(&info);
1476
1477     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1478     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1479     info.status_mask        = 1ull<<25 /* uneop */;
1480     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1481     info.enable_mask        = 1ull<<25 /* uneop */;
1482     info.flags              = 0;
1483     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1484     info.group_index        = 1;
1485     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1486     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1487     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1488     info.func               = __cvmx_error_display;
1489     info.user_info          = (long)
1490         "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
1491         "    (XAUI Mode only)\n";
1492     fail |= cvmx_error_add(&info);
1493
1494     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1495     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1496     info.status_mask        = 1ull<<26 /* undat */;
1497     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1498     info.enable_mask        = 1ull<<26 /* undat */;
1499     info.flags              = 0;
1500     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1501     info.group_index        = 1;
1502     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1503     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1504     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1505     info.func               = __cvmx_error_display;
1506     info.user_info          = (long)
1507         "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
1508         "    (XAUI Mode only)\n";
1509     fail |= cvmx_error_add(&info);
1510
1511     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1512     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1513     info.status_mask        = 1ull<<27 /* hg2fld */;
1514     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1515     info.enable_mask        = 1ull<<27 /* hg2fld */;
1516     info.flags              = 0;
1517     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1518     info.group_index        = 1;
1519     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1520     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1521     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1522     info.func               = __cvmx_error_display;
1523     info.user_info          = (long)
1524         "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1525         "    1) MSG_TYPE field not 6'b00_0000\n"
1526         "       i.e. it is not a FLOW CONTROL message, which\n"
1527         "       is the only defined type for HiGig2\n"
1528         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1529         "       which is the only defined type for HiGig2\n"
1530         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1531         "       Physical Link nor 4'b0010 for Logical Link.\n"
1532         "       Those are the only two defined types in HiGig2\n";
1533     fail |= cvmx_error_add(&info);
1534
1535     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1536     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1537     info.status_mask        = 1ull<<28 /* hg2cc */;
1538     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1539     info.enable_mask        = 1ull<<28 /* hg2cc */;
1540     info.flags              = 0;
1541     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1542     info.group_index        = 1;
1543     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1544     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1545     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1546     info.func               = __cvmx_error_display;
1547     info.user_info          = (long)
1548         "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1549         "    Set when either CRC8 error detected or when\n"
1550         "    a Control Character is found in the message\n"
1551         "    bytes after the K.SOM\n"
1552         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1553         "          i.e. a HiGig2 message that results in HG2CC\n"
1554         "          getting set, will never set HG2FLD.\n";
1555     fail |= cvmx_error_add(&info);
1556
1557     /* CVMX_GMXX_RXX_INT_REG(2,0) */
1558     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1559     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1560     info.status_mask        = 1ull<<1 /* carext */;
1561     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1562     info.enable_mask        = 1ull<<1 /* carext */;
1563     info.flags              = 0;
1564     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1565     info.group_index        = 2;
1566     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1567     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1568     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1569     info.func               = __cvmx_error_display;
1570     info.user_info          = (long)
1571         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
1572         "    (SGMII/1000Base-X only)\n";
1573     fail |= cvmx_error_add(&info);
1574
1575     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1576     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1577     info.status_mask        = 1ull<<8 /* skperr */;
1578     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1579     info.enable_mask        = 1ull<<8 /* skperr */;
1580     info.flags              = 0;
1581     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1582     info.group_index        = 2;
1583     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1584     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1585     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1586     info.func               = __cvmx_error_display;
1587     info.user_info          = (long)
1588         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
1589     fail |= cvmx_error_add(&info);
1590
1591     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1592     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1593     info.status_mask        = 1ull<<10 /* ovrerr */;
1594     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1595     info.enable_mask        = 1ull<<10 /* ovrerr */;
1596     info.flags              = 0;
1597     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1598     info.group_index        = 2;
1599     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1600     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1601     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1602     info.func               = __cvmx_error_display;
1603     info.user_info          = (long)
1604         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1605         "    This interrupt should never assert\n"
1606         "    (SGMII/1000Base-X only)\n";
1607     fail |= cvmx_error_add(&info);
1608
1609     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1610     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1611     info.status_mask        = 1ull<<20 /* loc_fault */;
1612     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1613     info.enable_mask        = 1ull<<20 /* loc_fault */;
1614     info.flags              = 0;
1615     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1616     info.group_index        = 2;
1617     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1618     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1619     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1620     info.func               = __cvmx_error_display;
1621     info.user_info          = (long)
1622         "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1623         "    (XAUI Mode only)\n";
1624     fail |= cvmx_error_add(&info);
1625
1626     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1627     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1628     info.status_mask        = 1ull<<21 /* rem_fault */;
1629     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1630     info.enable_mask        = 1ull<<21 /* rem_fault */;
1631     info.flags              = 0;
1632     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1633     info.group_index        = 2;
1634     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1635     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1636     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1637     info.func               = __cvmx_error_display;
1638     info.user_info          = (long)
1639         "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1640         "    (XAUI Mode only)\n";
1641     fail |= cvmx_error_add(&info);
1642
1643     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1644     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1645     info.status_mask        = 1ull<<22 /* bad_seq */;
1646     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1647     info.enable_mask        = 1ull<<22 /* bad_seq */;
1648     info.flags              = 0;
1649     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1650     info.group_index        = 2;
1651     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1652     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1653     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1654     info.func               = __cvmx_error_display;
1655     info.user_info          = (long)
1656         "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1657         "    (XAUI Mode only)\n";
1658     fail |= cvmx_error_add(&info);
1659
1660     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1661     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1662     info.status_mask        = 1ull<<23 /* bad_term */;
1663     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1664     info.enable_mask        = 1ull<<23 /* bad_term */;
1665     info.flags              = 0;
1666     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1667     info.group_index        = 2;
1668     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1669     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1670     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1671     info.func               = __cvmx_error_display;
1672     info.user_info          = (long)
1673         "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
1674         "    than /T/.  The error propagation control\n"
1675         "    character /E/ will be included as part of the\n"
1676         "    frame and does not cause a frame termination.\n"
1677         "    (XAUI Mode only)\n";
1678     fail |= cvmx_error_add(&info);
1679
1680     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1681     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1682     info.status_mask        = 1ull<<24 /* unsop */;
1683     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1684     info.enable_mask        = 1ull<<24 /* unsop */;
1685     info.flags              = 0;
1686     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1687     info.group_index        = 2;
1688     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1689     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1690     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1691     info.func               = __cvmx_error_display;
1692     info.user_info          = (long)
1693         "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
1694         "    (XAUI Mode only)\n";
1695     fail |= cvmx_error_add(&info);
1696
1697     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1698     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1699     info.status_mask        = 1ull<<25 /* uneop */;
1700     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1701     info.enable_mask        = 1ull<<25 /* uneop */;
1702     info.flags              = 0;
1703     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1704     info.group_index        = 2;
1705     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1706     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1707     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1708     info.func               = __cvmx_error_display;
1709     info.user_info          = (long)
1710         "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
1711         "    (XAUI Mode only)\n";
1712     fail |= cvmx_error_add(&info);
1713
1714     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1715     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1716     info.status_mask        = 1ull<<26 /* undat */;
1717     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1718     info.enable_mask        = 1ull<<26 /* undat */;
1719     info.flags              = 0;
1720     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1721     info.group_index        = 2;
1722     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1723     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1724     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1725     info.func               = __cvmx_error_display;
1726     info.user_info          = (long)
1727         "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
1728         "    (XAUI Mode only)\n";
1729     fail |= cvmx_error_add(&info);
1730
1731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1732     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1733     info.status_mask        = 1ull<<27 /* hg2fld */;
1734     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1735     info.enable_mask        = 1ull<<27 /* hg2fld */;
1736     info.flags              = 0;
1737     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1738     info.group_index        = 2;
1739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1740     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1741     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1742     info.func               = __cvmx_error_display;
1743     info.user_info          = (long)
1744         "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1745         "    1) MSG_TYPE field not 6'b00_0000\n"
1746         "       i.e. it is not a FLOW CONTROL message, which\n"
1747         "       is the only defined type for HiGig2\n"
1748         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1749         "       which is the only defined type for HiGig2\n"
1750         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1751         "       Physical Link nor 4'b0010 for Logical Link.\n"
1752         "       Those are the only two defined types in HiGig2\n";
1753     fail |= cvmx_error_add(&info);
1754
1755     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1756     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1757     info.status_mask        = 1ull<<28 /* hg2cc */;
1758     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1759     info.enable_mask        = 1ull<<28 /* hg2cc */;
1760     info.flags              = 0;
1761     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1762     info.group_index        = 2;
1763     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1764     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1765     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1766     info.func               = __cvmx_error_display;
1767     info.user_info          = (long)
1768         "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1769         "    Set when either CRC8 error detected or when\n"
1770         "    a Control Character is found in the message\n"
1771         "    bytes after the K.SOM\n"
1772         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1773         "          i.e. a HiGig2 message that results in HG2CC\n"
1774         "          getting set, will never set HG2FLD.\n";
1775     fail |= cvmx_error_add(&info);
1776
1777     /* CVMX_GMXX_RXX_INT_REG(3,0) */
1778     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1779     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1780     info.status_mask        = 1ull<<1 /* carext */;
1781     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1782     info.enable_mask        = 1ull<<1 /* carext */;
1783     info.flags              = 0;
1784     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1785     info.group_index        = 3;
1786     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1787     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1788     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1789     info.func               = __cvmx_error_display;
1790     info.user_info          = (long)
1791         "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
1792         "    (SGMII/1000Base-X only)\n";
1793     fail |= cvmx_error_add(&info);
1794
1795     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1796     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1797     info.status_mask        = 1ull<<8 /* skperr */;
1798     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1799     info.enable_mask        = 1ull<<8 /* skperr */;
1800     info.flags              = 0;
1801     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1802     info.group_index        = 3;
1803     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1804     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1805     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1806     info.func               = __cvmx_error_display;
1807     info.user_info          = (long)
1808         "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
1809     fail |= cvmx_error_add(&info);
1810
1811     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1812     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1813     info.status_mask        = 1ull<<10 /* ovrerr */;
1814     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1815     info.enable_mask        = 1ull<<10 /* ovrerr */;
1816     info.flags              = 0;
1817     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1818     info.group_index        = 3;
1819     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1820     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1821     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1822     info.func               = __cvmx_error_display;
1823     info.user_info          = (long)
1824         "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1825         "    This interrupt should never assert\n"
1826         "    (SGMII/1000Base-X only)\n";
1827     fail |= cvmx_error_add(&info);
1828
1829     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1830     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1831     info.status_mask        = 1ull<<20 /* loc_fault */;
1832     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1833     info.enable_mask        = 1ull<<20 /* loc_fault */;
1834     info.flags              = 0;
1835     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1836     info.group_index        = 3;
1837     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1838     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1839     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1840     info.func               = __cvmx_error_display;
1841     info.user_info          = (long)
1842         "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1843         "    (XAUI Mode only)\n";
1844     fail |= cvmx_error_add(&info);
1845
1846     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1847     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1848     info.status_mask        = 1ull<<21 /* rem_fault */;
1849     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1850     info.enable_mask        = 1ull<<21 /* rem_fault */;
1851     info.flags              = 0;
1852     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1853     info.group_index        = 3;
1854     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1855     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1856     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1857     info.func               = __cvmx_error_display;
1858     info.user_info          = (long)
1859         "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1860         "    (XAUI Mode only)\n";
1861     fail |= cvmx_error_add(&info);
1862
1863     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1864     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1865     info.status_mask        = 1ull<<22 /* bad_seq */;
1866     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1867     info.enable_mask        = 1ull<<22 /* bad_seq */;
1868     info.flags              = 0;
1869     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1870     info.group_index        = 3;
1871     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1872     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1873     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1874     info.func               = __cvmx_error_display;
1875     info.user_info          = (long)
1876         "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1877         "    (XAUI Mode only)\n";
1878     fail |= cvmx_error_add(&info);
1879
1880     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1881     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1882     info.status_mask        = 1ull<<23 /* bad_term */;
1883     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1884     info.enable_mask        = 1ull<<23 /* bad_term */;
1885     info.flags              = 0;
1886     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1887     info.group_index        = 3;
1888     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1889     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1890     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1891     info.func               = __cvmx_error_display;
1892     info.user_info          = (long)
1893         "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
1894         "    than /T/.  The error propagation control\n"
1895         "    character /E/ will be included as part of the\n"
1896         "    frame and does not cause a frame termination.\n"
1897         "    (XAUI Mode only)\n";
1898     fail |= cvmx_error_add(&info);
1899
1900     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1901     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1902     info.status_mask        = 1ull<<24 /* unsop */;
1903     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1904     info.enable_mask        = 1ull<<24 /* unsop */;
1905     info.flags              = 0;
1906     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1907     info.group_index        = 3;
1908     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1909     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1910     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1911     info.func               = __cvmx_error_display;
1912     info.user_info          = (long)
1913         "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
1914         "    (XAUI Mode only)\n";
1915     fail |= cvmx_error_add(&info);
1916
1917     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1918     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1919     info.status_mask        = 1ull<<25 /* uneop */;
1920     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1921     info.enable_mask        = 1ull<<25 /* uneop */;
1922     info.flags              = 0;
1923     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1924     info.group_index        = 3;
1925     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1926     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1927     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1928     info.func               = __cvmx_error_display;
1929     info.user_info          = (long)
1930         "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
1931         "    (XAUI Mode only)\n";
1932     fail |= cvmx_error_add(&info);
1933
1934     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1935     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1936     info.status_mask        = 1ull<<26 /* undat */;
1937     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1938     info.enable_mask        = 1ull<<26 /* undat */;
1939     info.flags              = 0;
1940     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1941     info.group_index        = 3;
1942     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1943     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1944     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1945     info.func               = __cvmx_error_display;
1946     info.user_info          = (long)
1947         "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
1948         "    (XAUI Mode only)\n";
1949     fail |= cvmx_error_add(&info);
1950
1951     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1952     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1953     info.status_mask        = 1ull<<27 /* hg2fld */;
1954     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1955     info.enable_mask        = 1ull<<27 /* hg2fld */;
1956     info.flags              = 0;
1957     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1958     info.group_index        = 3;
1959     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1960     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1961     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1962     info.func               = __cvmx_error_display;
1963     info.user_info          = (long)
1964         "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1965         "    1) MSG_TYPE field not 6'b00_0000\n"
1966         "       i.e. it is not a FLOW CONTROL message, which\n"
1967         "       is the only defined type for HiGig2\n"
1968         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1969         "       which is the only defined type for HiGig2\n"
1970         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1971         "       Physical Link nor 4'b0010 for Logical Link.\n"
1972         "       Those are the only two defined types in HiGig2\n";
1973     fail |= cvmx_error_add(&info);
1974
1975     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1976     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1977     info.status_mask        = 1ull<<28 /* hg2cc */;
1978     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1979     info.enable_mask        = 1ull<<28 /* hg2cc */;
1980     info.flags              = 0;
1981     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1982     info.group_index        = 3;
1983     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1984     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1985     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1986     info.func               = __cvmx_error_display;
1987     info.user_info          = (long)
1988         "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1989         "    Set when either CRC8 error detected or when\n"
1990         "    a Control Character is found in the message\n"
1991         "    bytes after the K.SOM\n"
1992         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1993         "          i.e. a HiGig2 message that results in HG2CC\n"
1994         "          getting set, will never set HG2FLD.\n";
1995     fail |= cvmx_error_add(&info);
1996
1997     /* CVMX_GMXX_TX_INT_REG(0) */
1998     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1999     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2000     info.status_mask        = 1ull<<0 /* pko_nxa */;
2001     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2002     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2003     info.flags              = 0;
2004     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2005     info.group_index        = 0;
2006     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2007     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2008     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2009     info.func               = __cvmx_error_display;
2010     info.user_info          = (long)
2011         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2012     fail |= cvmx_error_add(&info);
2013
2014     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2015     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2016     info.status_mask        = 0xfull<<2 /* undflw */;
2017     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2018     info.enable_mask        = 0xfull<<2 /* undflw */;
2019     info.flags              = 0;
2020     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2021     info.group_index        = 0;
2022     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2023     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2024     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2025     info.func               = __cvmx_error_display;
2026     info.user_info          = (long)
2027         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
2028     fail |= cvmx_error_add(&info);
2029
2030     /* CVMX_MIO_BOOT_ERR */
2031     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2032     info.status_addr        = CVMX_MIO_BOOT_ERR;
2033     info.status_mask        = 1ull<<0 /* adr_err */;
2034     info.enable_addr        = CVMX_MIO_BOOT_INT;
2035     info.enable_mask        = 1ull<<0 /* adr_int */;
2036     info.flags              = 0;
2037     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2038     info.group_index        = 0;
2039     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2040     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2041     info.parent.status_mask = 1ull<<0 /* mio */;
2042     info.func               = __cvmx_error_display;
2043     info.user_info          = (long)
2044         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
2045     fail |= cvmx_error_add(&info);
2046
2047     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2048     info.status_addr        = CVMX_MIO_BOOT_ERR;
2049     info.status_mask        = 1ull<<1 /* wait_err */;
2050     info.enable_addr        = CVMX_MIO_BOOT_INT;
2051     info.enable_mask        = 1ull<<1 /* wait_int */;
2052     info.flags              = 0;
2053     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2054     info.group_index        = 0;
2055     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2056     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2057     info.parent.status_mask = 1ull<<0 /* mio */;
2058     info.func               = __cvmx_error_display;
2059     info.user_info          = (long)
2060         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
2061     fail |= cvmx_error_add(&info);
2062
2063     /* CVMX_IPD_INT_SUM */
2064     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2065     info.status_addr        = CVMX_IPD_INT_SUM;
2066     info.status_mask        = 1ull<<0 /* prc_par0 */;
2067     info.enable_addr        = CVMX_IPD_INT_ENB;
2068     info.enable_mask        = 1ull<<0 /* prc_par0 */;
2069     info.flags              = 0;
2070     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2071     info.group_index        = 0;
2072     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2073     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2074     info.parent.status_mask = 1ull<<9 /* ipd */;
2075     info.func               = __cvmx_error_display;
2076     info.user_info          = (long)
2077         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2078         "    [31:0] of the PBM memory.\n";
2079     fail |= cvmx_error_add(&info);
2080
2081     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2082     info.status_addr        = CVMX_IPD_INT_SUM;
2083     info.status_mask        = 1ull<<1 /* prc_par1 */;
2084     info.enable_addr        = CVMX_IPD_INT_ENB;
2085     info.enable_mask        = 1ull<<1 /* prc_par1 */;
2086     info.flags              = 0;
2087     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2088     info.group_index        = 0;
2089     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2090     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2091     info.parent.status_mask = 1ull<<9 /* ipd */;
2092     info.func               = __cvmx_error_display;
2093     info.user_info          = (long)
2094         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2095         "    [63:32] of the PBM memory.\n";
2096     fail |= cvmx_error_add(&info);
2097
2098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2099     info.status_addr        = CVMX_IPD_INT_SUM;
2100     info.status_mask        = 1ull<<2 /* prc_par2 */;
2101     info.enable_addr        = CVMX_IPD_INT_ENB;
2102     info.enable_mask        = 1ull<<2 /* prc_par2 */;
2103     info.flags              = 0;
2104     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2105     info.group_index        = 0;
2106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2107     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2108     info.parent.status_mask = 1ull<<9 /* ipd */;
2109     info.func               = __cvmx_error_display;
2110     info.user_info          = (long)
2111         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2112         "    [95:64] of the PBM memory.\n";
2113     fail |= cvmx_error_add(&info);
2114
2115     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2116     info.status_addr        = CVMX_IPD_INT_SUM;
2117     info.status_mask        = 1ull<<3 /* prc_par3 */;
2118     info.enable_addr        = CVMX_IPD_INT_ENB;
2119     info.enable_mask        = 1ull<<3 /* prc_par3 */;
2120     info.flags              = 0;
2121     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2122     info.group_index        = 0;
2123     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2124     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2125     info.parent.status_mask = 1ull<<9 /* ipd */;
2126     info.func               = __cvmx_error_display;
2127     info.user_info          = (long)
2128         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2129         "    [127:96] of the PBM memory.\n";
2130     fail |= cvmx_error_add(&info);
2131
2132     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2133     info.status_addr        = CVMX_IPD_INT_SUM;
2134     info.status_mask        = 1ull<<4 /* bp_sub */;
2135     info.enable_addr        = CVMX_IPD_INT_ENB;
2136     info.enable_mask        = 1ull<<4 /* bp_sub */;
2137     info.flags              = 0;
2138     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2139     info.group_index        = 0;
2140     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2141     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2142     info.parent.status_mask = 1ull<<9 /* ipd */;
2143     info.func               = __cvmx_error_display;
2144     info.user_info          = (long)
2145         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2146         "    supplied illegal value.\n";
2147     fail |= cvmx_error_add(&info);
2148
2149     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2150     info.status_addr        = CVMX_IPD_INT_SUM;
2151     info.status_mask        = 1ull<<5 /* dc_ovr */;
2152     info.enable_addr        = CVMX_IPD_INT_ENB;
2153     info.enable_mask        = 1ull<<5 /* dc_ovr */;
2154     info.flags              = 0;
2155     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2156     info.group_index        = 0;
2157     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2158     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2159     info.parent.status_mask = 1ull<<9 /* ipd */;
2160     info.func               = __cvmx_error_display;
2161     info.user_info          = (long)
2162         "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
2163     fail |= cvmx_error_add(&info);
2164
2165     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2166     info.status_addr        = CVMX_IPD_INT_SUM;
2167     info.status_mask        = 1ull<<6 /* cc_ovr */;
2168     info.enable_addr        = CVMX_IPD_INT_ENB;
2169     info.enable_mask        = 1ull<<6 /* cc_ovr */;
2170     info.flags              = 0;
2171     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2172     info.group_index        = 0;
2173     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2174     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2175     info.parent.status_mask = 1ull<<9 /* ipd */;
2176     info.func               = __cvmx_error_display;
2177     info.user_info          = (long)
2178         "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
2179     fail |= cvmx_error_add(&info);
2180
2181     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2182     info.status_addr        = CVMX_IPD_INT_SUM;
2183     info.status_mask        = 1ull<<7 /* c_coll */;
2184     info.enable_addr        = CVMX_IPD_INT_ENB;
2185     info.enable_mask        = 1ull<<7 /* c_coll */;
2186     info.flags              = 0;
2187     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2188     info.group_index        = 0;
2189     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2190     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2191     info.parent.status_mask = 1ull<<9 /* ipd */;
2192     info.func               = __cvmx_error_display;
2193     info.user_info          = (long)
2194         "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
2195         "    collides.\n";
2196     fail |= cvmx_error_add(&info);
2197
2198     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2199     info.status_addr        = CVMX_IPD_INT_SUM;
2200     info.status_mask        = 1ull<<8 /* d_coll */;
2201     info.enable_addr        = CVMX_IPD_INT_ENB;
2202     info.enable_mask        = 1ull<<8 /* d_coll */;
2203     info.flags              = 0;
2204     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2205     info.group_index        = 0;
2206     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2207     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2208     info.parent.status_mask = 1ull<<9 /* ipd */;
2209     info.func               = __cvmx_error_display;
2210     info.user_info          = (long)
2211         "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
2212         "    collides.\n";
2213     fail |= cvmx_error_add(&info);
2214
2215     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2216     info.status_addr        = CVMX_IPD_INT_SUM;
2217     info.status_mask        = 1ull<<9 /* bc_ovr */;
2218     info.enable_addr        = CVMX_IPD_INT_ENB;
2219     info.enable_mask        = 1ull<<9 /* bc_ovr */;
2220     info.flags              = 0;
2221     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2222     info.group_index        = 0;
2223     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2224     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2225     info.parent.status_mask = 1ull<<9 /* ipd */;
2226     info.func               = __cvmx_error_display;
2227     info.user_info          = (long)
2228         "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
2229     fail |= cvmx_error_add(&info);
2230
2231     /* CVMX_TIM_REG_ERROR */
2232     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2233     info.status_addr        = CVMX_TIM_REG_ERROR;
2234     info.status_mask        = 0xffffull<<0 /* mask */;
2235     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
2236     info.enable_mask        = 0xffffull<<0 /* mask */;
2237     info.flags              = 0;
2238     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2239     info.group_index        = 0;
2240     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2241     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2242     info.parent.status_mask = 1ull<<11 /* tim */;
2243     info.func               = __cvmx_error_display;
2244     info.user_info          = (long)
2245         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2246     fail |= cvmx_error_add(&info);
2247
2248     /* CVMX_POW_ECC_ERR */
2249     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2250     info.status_addr        = CVMX_POW_ECC_ERR;
2251     info.status_mask        = 1ull<<0 /* sbe */;
2252     info.enable_addr        = CVMX_POW_ECC_ERR;
2253     info.enable_mask        = 1ull<<2 /* sbe_ie */;
2254     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2255     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2256     info.group_index        = 0;
2257     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2258     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2259     info.parent.status_mask = 1ull<<12 /* pow */;
2260     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
2261     info.user_info          = (long)
2262         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2263     fail |= cvmx_error_add(&info);
2264
2265     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2266     info.status_addr        = CVMX_POW_ECC_ERR;
2267     info.status_mask        = 1ull<<1 /* dbe */;
2268     info.enable_addr        = CVMX_POW_ECC_ERR;
2269     info.enable_mask        = 1ull<<3 /* dbe_ie */;
2270     info.flags              = 0;
2271     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2272     info.group_index        = 0;
2273     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2274     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2275     info.parent.status_mask = 1ull<<12 /* pow */;
2276     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
2277     info.user_info          = (long)
2278         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2279     fail |= cvmx_error_add(&info);
2280
2281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2282     info.status_addr        = CVMX_POW_ECC_ERR;
2283     info.status_mask        = 1ull<<12 /* rpe */;
2284     info.enable_addr        = CVMX_POW_ECC_ERR;
2285     info.enable_mask        = 1ull<<13 /* rpe_ie */;
2286     info.flags              = 0;
2287     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2288     info.group_index        = 0;
2289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2290     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2291     info.parent.status_mask = 1ull<<12 /* pow */;
2292     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
2293     info.user_info          = (long)
2294         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2295     fail |= cvmx_error_add(&info);
2296
2297     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2298     info.status_addr        = CVMX_POW_ECC_ERR;
2299     info.status_mask        = 0x1fffull<<16 /* iop */;
2300     info.enable_addr        = CVMX_POW_ECC_ERR;
2301     info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
2302     info.flags              = 0;
2303     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2304     info.group_index        = 0;
2305     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2306     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2307     info.parent.status_mask = 1ull<<12 /* pow */;
2308     info.func               = __cvmx_error_handle_pow_ecc_err_iop;
2309     info.user_info          = (long)
2310         "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
2311     fail |= cvmx_error_add(&info);
2312
2313     /* CVMX_USBNX_INT_SUM(1) */
2314     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2315     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2316     info.status_mask        = 1ull<<0 /* pr_po_e */;
2317     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2318     info.enable_mask        = 1ull<<0 /* pr_po_e */;
2319     info.flags              = 0;
2320     info.group              = CVMX_ERROR_GROUP_USB;
2321     info.group_index        = 1;
2322     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2323     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2324     info.parent.status_mask = 1ull<<15 /* usb1 */;
2325     info.func               = __cvmx_error_display;
2326     info.user_info          = (long)
2327         "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
2328     fail |= cvmx_error_add(&info);
2329
2330     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2331     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2332     info.status_mask        = 1ull<<1 /* pr_pu_f */;
2333     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2334     info.enable_mask        = 1ull<<1 /* pr_pu_f */;
2335     info.flags              = 0;
2336     info.group              = CVMX_ERROR_GROUP_USB;
2337     info.group_index        = 1;
2338     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2339     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2340     info.parent.status_mask = 1ull<<15 /* usb1 */;
2341     info.func               = __cvmx_error_display;
2342     info.user_info          = (long)
2343         "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
2344     fail |= cvmx_error_add(&info);
2345
2346     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2347     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2348     info.status_mask        = 1ull<<2 /* nr_po_e */;
2349     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2350     info.enable_mask        = 1ull<<2 /* nr_po_e */;
2351     info.flags              = 0;
2352     info.group              = CVMX_ERROR_GROUP_USB;
2353     info.group_index        = 1;
2354     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2355     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2356     info.parent.status_mask = 1ull<<15 /* usb1 */;
2357     info.func               = __cvmx_error_display;
2358     info.user_info          = (long)
2359         "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
2360     fail |= cvmx_error_add(&info);
2361
2362     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2363     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2364     info.status_mask        = 1ull<<3 /* nr_pu_f */;
2365     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2366     info.enable_mask        = 1ull<<3 /* nr_pu_f */;
2367     info.flags              = 0;
2368     info.group              = CVMX_ERROR_GROUP_USB;
2369     info.group_index        = 1;
2370     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2371     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2372     info.parent.status_mask = 1ull<<15 /* usb1 */;
2373     info.func               = __cvmx_error_display;
2374     info.user_info          = (long)
2375         "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
2376     fail |= cvmx_error_add(&info);
2377
2378     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2379     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2380     info.status_mask        = 1ull<<4 /* lr_po_e */;
2381     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2382     info.enable_mask        = 1ull<<4 /* lr_po_e */;
2383     info.flags              = 0;
2384     info.group              = CVMX_ERROR_GROUP_USB;
2385     info.group_index        = 1;
2386     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2387     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2388     info.parent.status_mask = 1ull<<15 /* usb1 */;
2389     info.func               = __cvmx_error_display;
2390     info.user_info          = (long)
2391         "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
2392     fail |= cvmx_error_add(&info);
2393
2394     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2395     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2396     info.status_mask        = 1ull<<5 /* lr_pu_f */;
2397     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2398     info.enable_mask        = 1ull<<5 /* lr_pu_f */;
2399     info.flags              = 0;
2400     info.group              = CVMX_ERROR_GROUP_USB;
2401     info.group_index        = 1;
2402     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2403     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2404     info.parent.status_mask = 1ull<<15 /* usb1 */;
2405     info.func               = __cvmx_error_display;
2406     info.user_info          = (long)
2407         "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
2408     fail |= cvmx_error_add(&info);
2409
2410     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2411     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2412     info.status_mask        = 1ull<<6 /* pt_po_e */;
2413     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2414     info.enable_mask        = 1ull<<6 /* pt_po_e */;
2415     info.flags              = 0;
2416     info.group              = CVMX_ERROR_GROUP_USB;
2417     info.group_index        = 1;
2418     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2419     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2420     info.parent.status_mask = 1ull<<15 /* usb1 */;
2421     info.func               = __cvmx_error_display;
2422     info.user_info          = (long)
2423         "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
2424     fail |= cvmx_error_add(&info);
2425
2426     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2427     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2428     info.status_mask        = 1ull<<7 /* pt_pu_f */;
2429     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2430     info.enable_mask        = 1ull<<7 /* pt_pu_f */;
2431     info.flags              = 0;
2432     info.group              = CVMX_ERROR_GROUP_USB;
2433     info.group_index        = 1;
2434     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2435     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2436     info.parent.status_mask = 1ull<<15 /* usb1 */;
2437     info.func               = __cvmx_error_display;
2438     info.user_info          = (long)
2439         "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
2440     fail |= cvmx_error_add(&info);
2441
2442     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2443     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2444     info.status_mask        = 1ull<<8 /* nt_po_e */;
2445     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2446     info.enable_mask        = 1ull<<8 /* nt_po_e */;
2447     info.flags              = 0;
2448     info.group              = CVMX_ERROR_GROUP_USB;
2449     info.group_index        = 1;
2450     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2451     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2452     info.parent.status_mask = 1ull<<15 /* usb1 */;
2453     info.func               = __cvmx_error_display;
2454     info.user_info          = (long)
2455         "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
2456     fail |= cvmx_error_add(&info);
2457
2458     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2459     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2460     info.status_mask        = 1ull<<9 /* nt_pu_f */;
2461     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2462     info.enable_mask        = 1ull<<9 /* nt_pu_f */;
2463     info.flags              = 0;
2464     info.group              = CVMX_ERROR_GROUP_USB;
2465     info.group_index        = 1;
2466     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2467     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2468     info.parent.status_mask = 1ull<<15 /* usb1 */;
2469     info.func               = __cvmx_error_display;
2470     info.user_info          = (long)
2471         "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
2472     fail |= cvmx_error_add(&info);
2473
2474     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2475     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2476     info.status_mask        = 1ull<<10 /* lt_po_e */;
2477     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2478     info.enable_mask        = 1ull<<10 /* lt_po_e */;
2479     info.flags              = 0;
2480     info.group              = CVMX_ERROR_GROUP_USB;
2481     info.group_index        = 1;
2482     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2483     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2484     info.parent.status_mask = 1ull<<15 /* usb1 */;
2485     info.func               = __cvmx_error_display;
2486     info.user_info          = (long)
2487         "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
2488     fail |= cvmx_error_add(&info);
2489
2490     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2491     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2492     info.status_mask        = 1ull<<11 /* lt_pu_f */;
2493     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2494     info.enable_mask        = 1ull<<11 /* lt_pu_f */;
2495     info.flags              = 0;
2496     info.group              = CVMX_ERROR_GROUP_USB;
2497     info.group_index        = 1;
2498     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2499     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2500     info.parent.status_mask = 1ull<<15 /* usb1 */;
2501     info.func               = __cvmx_error_display;
2502     info.user_info          = (long)
2503         "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
2504     fail |= cvmx_error_add(&info);
2505
2506     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2507     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2508     info.status_mask        = 1ull<<12 /* dcred_e */;
2509     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2510     info.enable_mask        = 1ull<<12 /* dcred_e */;
2511     info.flags              = 0;
2512     info.group              = CVMX_ERROR_GROUP_USB;
2513     info.group_index        = 1;
2514     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2515     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2516     info.parent.status_mask = 1ull<<15 /* usb1 */;
2517     info.func               = __cvmx_error_display;
2518     info.user_info          = (long)
2519         "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
2520     fail |= cvmx_error_add(&info);
2521
2522     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2523     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2524     info.status_mask        = 1ull<<13 /* dcred_f */;
2525     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2526     info.enable_mask        = 1ull<<13 /* dcred_f */;
2527     info.flags              = 0;
2528     info.group              = CVMX_ERROR_GROUP_USB;
2529     info.group_index        = 1;
2530     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2531     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2532     info.parent.status_mask = 1ull<<15 /* usb1 */;
2533     info.func               = __cvmx_error_display;
2534     info.user_info          = (long)
2535         "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
2536     fail |= cvmx_error_add(&info);
2537
2538     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2539     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2540     info.status_mask        = 1ull<<14 /* l2c_s_e */;
2541     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2542     info.enable_mask        = 1ull<<14 /* l2c_s_e */;
2543     info.flags              = 0;
2544     info.group              = CVMX_ERROR_GROUP_USB;
2545     info.group_index        = 1;
2546     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2547     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2548     info.parent.status_mask = 1ull<<15 /* usb1 */;
2549     info.func               = __cvmx_error_display;
2550     info.user_info          = (long)
2551         "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
2552     fail |= cvmx_error_add(&info);
2553
2554     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2555     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2556     info.status_mask        = 1ull<<15 /* l2c_a_f */;
2557     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2558     info.enable_mask        = 1ull<<15 /* l2c_a_f */;
2559     info.flags              = 0;
2560     info.group              = CVMX_ERROR_GROUP_USB;
2561     info.group_index        = 1;
2562     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2563     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2564     info.parent.status_mask = 1ull<<15 /* usb1 */;
2565     info.func               = __cvmx_error_display;
2566     info.user_info          = (long)
2567         "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n";
2568     fail |= cvmx_error_add(&info);
2569
2570     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2571     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2572     info.status_mask        = 1ull<<16 /* lt_fi_e */;
2573     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2574     info.enable_mask        = 1ull<<16 /* l2_fi_e */;
2575     info.flags              = 0;
2576     info.group              = CVMX_ERROR_GROUP_USB;
2577     info.group_index        = 1;
2578     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2579     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2580     info.parent.status_mask = 1ull<<15 /* usb1 */;
2581     info.func               = __cvmx_error_display;
2582     info.user_info          = (long)
2583         "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
2584     fail |= cvmx_error_add(&info);
2585
2586     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2587     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2588     info.status_mask        = 1ull<<17 /* lt_fi_f */;
2589     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2590     info.enable_mask        = 1ull<<17 /* l2_fi_f */;
2591     info.flags              = 0;
2592     info.group              = CVMX_ERROR_GROUP_USB;
2593     info.group_index        = 1;
2594     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2595     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2596     info.parent.status_mask = 1ull<<15 /* usb1 */;
2597     info.func               = __cvmx_error_display;
2598     info.user_info          = (long)
2599         "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
2600     fail |= cvmx_error_add(&info);
2601
2602     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2603     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2604     info.status_mask        = 1ull<<18 /* rg_fi_e */;
2605     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2606     info.enable_mask        = 1ull<<18 /* rg_fi_e */;
2607     info.flags              = 0;
2608     info.group              = CVMX_ERROR_GROUP_USB;
2609     info.group_index        = 1;
2610     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2611     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2612     info.parent.status_mask = 1ull<<15 /* usb1 */;
2613     info.func               = __cvmx_error_display;
2614     info.user_info          = (long)
2615         "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
2616     fail |= cvmx_error_add(&info);
2617
2618     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2619     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2620     info.status_mask        = 1ull<<19 /* rg_fi_f */;
2621     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2622     info.enable_mask        = 1ull<<19 /* rg_fi_f */;
2623     info.flags              = 0;
2624     info.group              = CVMX_ERROR_GROUP_USB;
2625     info.group_index        = 1;
2626     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2627     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2628     info.parent.status_mask = 1ull<<15 /* usb1 */;
2629     info.func               = __cvmx_error_display;
2630     info.user_info          = (long)
2631         "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
2632     fail |= cvmx_error_add(&info);
2633
2634     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2635     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2636     info.status_mask        = 1ull<<20 /* rq_q2_f */;
2637     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2638     info.enable_mask        = 1ull<<20 /* rq_q2_f */;
2639     info.flags              = 0;
2640     info.group              = CVMX_ERROR_GROUP_USB;
2641     info.group_index        = 1;
2642     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2643     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2644     info.parent.status_mask = 1ull<<15 /* usb1 */;
2645     info.func               = __cvmx_error_display;
2646     info.user_info          = (long)
2647         "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
2648     fail |= cvmx_error_add(&info);
2649
2650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2651     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2652     info.status_mask        = 1ull<<21 /* rq_q2_e */;
2653     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2654     info.enable_mask        = 1ull<<21 /* rq_q2_e */;
2655     info.flags              = 0;
2656     info.group              = CVMX_ERROR_GROUP_USB;
2657     info.group_index        = 1;
2658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2659     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2660     info.parent.status_mask = 1ull<<15 /* usb1 */;
2661     info.func               = __cvmx_error_display;
2662     info.user_info          = (long)
2663         "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
2664     fail |= cvmx_error_add(&info);
2665
2666     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2667     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2668     info.status_mask        = 1ull<<22 /* rq_q3_f */;
2669     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2670     info.enable_mask        = 1ull<<22 /* rq_q3_f */;
2671     info.flags              = 0;
2672     info.group              = CVMX_ERROR_GROUP_USB;
2673     info.group_index        = 1;
2674     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2675     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2676     info.parent.status_mask = 1ull<<15 /* usb1 */;
2677     info.func               = __cvmx_error_display;
2678     info.user_info          = (long)
2679         "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
2680     fail |= cvmx_error_add(&info);
2681
2682     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2683     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2684     info.status_mask        = 1ull<<23 /* rq_q3_e */;
2685     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2686     info.enable_mask        = 1ull<<23 /* rq_q3_e */;
2687     info.flags              = 0;
2688     info.group              = CVMX_ERROR_GROUP_USB;
2689     info.group_index        = 1;
2690     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2691     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2692     info.parent.status_mask = 1ull<<15 /* usb1 */;
2693     info.func               = __cvmx_error_display;
2694     info.user_info          = (long)
2695         "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
2696     fail |= cvmx_error_add(&info);
2697
2698     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2699     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2700     info.status_mask        = 1ull<<24 /* uod_pe */;
2701     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2702     info.enable_mask        = 1ull<<24 /* uod_pe */;
2703     info.flags              = 0;
2704     info.group              = CVMX_ERROR_GROUP_USB;
2705     info.group_index        = 1;
2706     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2707     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2708     info.parent.status_mask = 1ull<<15 /* usb1 */;
2709     info.func               = __cvmx_error_display;
2710     info.user_info          = (long)
2711         "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n";
2712     fail |= cvmx_error_add(&info);
2713
2714     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2715     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2716     info.status_mask        = 1ull<<25 /* uod_pf */;
2717     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2718     info.enable_mask        = 1ull<<25 /* uod_pf */;
2719     info.flags              = 0;
2720     info.group              = CVMX_ERROR_GROUP_USB;
2721     info.group_index        = 1;
2722     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2723     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2724     info.parent.status_mask = 1ull<<15 /* usb1 */;
2725     info.func               = __cvmx_error_display;
2726     info.user_info          = (long)
2727         "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n";
2728     fail |= cvmx_error_add(&info);
2729
2730     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2731     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2732     info.status_mask        = 1ull<<32 /* ltl_f_pe */;
2733     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2734     info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
2735     info.flags              = 0;
2736     info.group              = CVMX_ERROR_GROUP_USB;
2737     info.group_index        = 1;
2738     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2739     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2740     info.parent.status_mask = 1ull<<15 /* usb1 */;
2741     info.func               = __cvmx_error_display;
2742     info.user_info          = (long)
2743         "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
2744     fail |= cvmx_error_add(&info);
2745
2746     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2747     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2748     info.status_mask        = 1ull<<33 /* ltl_f_pf */;
2749     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2750     info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
2751     info.flags              = 0;
2752     info.group              = CVMX_ERROR_GROUP_USB;
2753     info.group_index        = 1;
2754     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2755     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2756     info.parent.status_mask = 1ull<<15 /* usb1 */;
2757     info.func               = __cvmx_error_display;
2758     info.user_info          = (long)
2759         "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
2760     fail |= cvmx_error_add(&info);
2761
2762     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2763     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2764     info.status_mask        = 1ull<<34 /* nd4o_rpe */;
2765     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2766     info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
2767     info.flags              = 0;
2768     info.group              = CVMX_ERROR_GROUP_USB;
2769     info.group_index        = 1;
2770     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2771     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2772     info.parent.status_mask = 1ull<<15 /* usb1 */;
2773     info.func               = __cvmx_error_display;
2774     info.user_info          = (long)
2775         "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
2776     fail |= cvmx_error_add(&info);
2777
2778     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2779     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2780     info.status_mask        = 1ull<<35 /* nd4o_rpf */;
2781     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2782     info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
2783     info.flags              = 0;
2784     info.group              = CVMX_ERROR_GROUP_USB;
2785     info.group_index        = 1;
2786     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2787     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2788     info.parent.status_mask = 1ull<<15 /* usb1 */;
2789     info.func               = __cvmx_error_display;
2790     info.user_info          = (long)
2791         "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
2792     fail |= cvmx_error_add(&info);
2793
2794     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2795     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2796     info.status_mask        = 1ull<<36 /* nd4o_dpe */;
2797     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2798     info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
2799     info.flags              = 0;
2800     info.group              = CVMX_ERROR_GROUP_USB;
2801     info.group_index        = 1;
2802     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2803     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2804     info.parent.status_mask = 1ull<<15 /* usb1 */;
2805     info.func               = __cvmx_error_display;
2806     info.user_info          = (long)
2807         "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
2808     fail |= cvmx_error_add(&info);
2809
2810     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2811     info.status_addr        = CVMX_USBNX_INT_SUM(1);
2812     info.status_mask        = 1ull<<37 /* nd4o_dpf */;
2813     info.enable_addr        = CVMX_USBNX_INT_ENB(1);
2814     info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
2815     info.flags              = 0;
2816     info.group              = CVMX_ERROR_GROUP_USB;
2817     info.group_index        = 1;
2818     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2819     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2820     info.parent.status_mask = 1ull<<15 /* usb1 */;
2821     info.func               = __cvmx_error_display;
2822     info.user_info          = (long)
2823         "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
2824     fail |= cvmx_error_add(&info);
2825
2826     /* CVMX_PEXP_NPEI_INT_SUM */
2827     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2828     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2829     info.status_mask        = 1ull<<59 /* c0_ldwn */;
2830     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2831     info.enable_mask        = 1ull<<59 /* c0_ldwn */;
2832     info.flags              = 0;
2833     info.group              = CVMX_ERROR_GROUP_PCI;
2834     info.group_index        = 0;
2835     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2836     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2837     info.parent.status_mask = 1ull<<3 /* npei */;
2838     info.func               = __cvmx_error_display;
2839     info.user_info          = (long)
2840         "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
2841     fail |= cvmx_error_add(&info);
2842
2843     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2844     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2845     info.status_mask        = 1ull<<21 /* c0_se */;
2846     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2847     info.enable_mask        = 1ull<<21 /* c0_se */;
2848     info.flags              = 0;
2849     info.group              = CVMX_ERROR_GROUP_PCI;
2850     info.group_index        = 0;
2851     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2852     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2853     info.parent.status_mask = 1ull<<3 /* npei */;
2854     info.func               = __cvmx_error_display;
2855     info.user_info          = (long)
2856         "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
2857         "    Pcie Core 0. (cfg_sys_err_rc)\n";
2858     fail |= cvmx_error_add(&info);
2859
2860     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2861     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2862     info.status_mask        = 1ull<<38 /* c0_un_b0 */;
2863     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2864     info.enable_mask        = 1ull<<38 /* c0_un_b0 */;
2865     info.flags              = 0;
2866     info.group              = CVMX_ERROR_GROUP_PCI;
2867     info.group_index        = 0;
2868     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2869     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2870     info.parent.status_mask = 1ull<<3 /* npei */;
2871     info.func               = __cvmx_error_display;
2872     info.user_info          = (long)
2873         "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
2874         "    Core 0.\n";
2875     fail |= cvmx_error_add(&info);
2876
2877     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2878     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2879     info.status_mask        = 1ull<<39 /* c0_un_b1 */;
2880     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2881     info.enable_mask        = 1ull<<39 /* c0_un_b1 */;
2882     info.flags              = 0;
2883     info.group              = CVMX_ERROR_GROUP_PCI;
2884     info.group_index        = 0;
2885     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2886     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2887     info.parent.status_mask = 1ull<<3 /* npei */;
2888     info.func               = __cvmx_error_display;
2889     info.user_info          = (long)
2890         "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
2891         "    Core 0.\n";
2892     fail |= cvmx_error_add(&info);
2893
2894     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2895     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2896     info.status_mask        = 1ull<<40 /* c0_un_b2 */;
2897     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2898     info.enable_mask        = 1ull<<40 /* c0_un_b2 */;
2899     info.flags              = 0;
2900     info.group              = CVMX_ERROR_GROUP_PCI;
2901     info.group_index        = 0;
2902     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2903     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2904     info.parent.status_mask = 1ull<<3 /* npei */;
2905     info.func               = __cvmx_error_display;
2906     info.user_info          = (long)
2907         "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
2908         "    Core 0.\n";
2909     fail |= cvmx_error_add(&info);
2910
2911     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2912     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2913     info.status_mask        = 1ull<<42 /* c0_un_bx */;
2914     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2915     info.enable_mask        = 1ull<<42 /* c0_un_bx */;
2916     info.flags              = 0;
2917     info.group              = CVMX_ERROR_GROUP_PCI;
2918     info.group_index        = 0;
2919     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2920     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2921     info.parent.status_mask = 1ull<<3 /* npei */;
2922     info.func               = __cvmx_error_display;
2923     info.user_info          = (long)
2924         "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
2925         "    Core 0.\n";
2926     fail |= cvmx_error_add(&info);
2927
2928     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2929     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2930     info.status_mask        = 1ull<<53 /* c0_un_wf */;
2931     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2932     info.enable_mask        = 1ull<<53 /* c0_un_wf */;
2933     info.flags              = 0;
2934     info.group              = CVMX_ERROR_GROUP_PCI;
2935     info.group_index        = 0;
2936     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2937     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2938     info.parent.status_mask = 1ull<<3 /* npei */;
2939     info.func               = __cvmx_error_display;
2940     info.user_info          = (long)
2941         "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
2942         "    register. Core0.\n";
2943     fail |= cvmx_error_add(&info);
2944
2945     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2946     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2947     info.status_mask        = 1ull<<41 /* c0_un_wi */;
2948     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2949     info.enable_mask        = 1ull<<41 /* c0_un_wi */;
2950     info.flags              = 0;
2951     info.group              = CVMX_ERROR_GROUP_PCI;
2952     info.group_index        = 0;
2953     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2954     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2955     info.parent.status_mask = 1ull<<3 /* npei */;
2956     info.func               = __cvmx_error_display;
2957     info.user_info          = (long)
2958         "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
2959         "    Core 0.\n";
2960     fail |= cvmx_error_add(&info);
2961
2962     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2963     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2964     info.status_mask        = 1ull<<33 /* c0_up_b0 */;
2965     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2966     info.enable_mask        = 1ull<<33 /* c0_up_b0 */;
2967     info.flags              = 0;
2968     info.group              = CVMX_ERROR_GROUP_PCI;
2969     info.group_index        = 0;
2970     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2971     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2972     info.parent.status_mask = 1ull<<3 /* npei */;
2973     info.func               = __cvmx_error_display;
2974     info.user_info          = (long)
2975         "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
2976         "    Core 0.\n";
2977     fail |= cvmx_error_add(&info);
2978
2979     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2980     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2981     info.status_mask        = 1ull<<34 /* c0_up_b1 */;
2982     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
2983     info.enable_mask        = 1ull<<34 /* c0_up_b1 */;
2984     info.flags              = 0;
2985     info.group              = CVMX_ERROR_GROUP_PCI;
2986     info.group_index        = 0;
2987     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2988     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2989     info.parent.status_mask = 1ull<<3 /* npei */;
2990     info.func               = __cvmx_error_display;
2991     info.user_info          = (long)
2992         "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
2993         "    Core 0.\n";
2994     fail |= cvmx_error_add(&info);
2995
2996     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2997     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
2998     info.status_mask        = 1ull<<35 /* c0_up_b2 */;
2999     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3000     info.enable_mask        = 1ull<<35 /* c0_up_b2 */;
3001     info.flags              = 0;
3002     info.group              = CVMX_ERROR_GROUP_PCI;
3003     info.group_index        = 0;
3004     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3005     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3006     info.parent.status_mask = 1ull<<3 /* npei */;
3007     info.func               = __cvmx_error_display;
3008     info.user_info          = (long)
3009         "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3010         "    Core 0.\n";
3011     fail |= cvmx_error_add(&info);
3012
3013     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3014     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3015     info.status_mask        = 1ull<<37 /* c0_up_bx */;
3016     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3017     info.enable_mask        = 1ull<<37 /* c0_up_bx */;
3018     info.flags              = 0;
3019     info.group              = CVMX_ERROR_GROUP_PCI;
3020     info.group_index        = 0;
3021     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3022     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3023     info.parent.status_mask = 1ull<<3 /* npei */;
3024     info.func               = __cvmx_error_display;
3025     info.user_info          = (long)
3026         "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3027         "    Core 0.\n";
3028     fail |= cvmx_error_add(&info);
3029
3030     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3031     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3032     info.status_mask        = 1ull<<55 /* c0_up_wf */;
3033     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3034     info.enable_mask        = 1ull<<55 /* c0_up_wf */;
3035     info.flags              = 0;
3036     info.group              = CVMX_ERROR_GROUP_PCI;
3037     info.group_index        = 0;
3038     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3039     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3040     info.parent.status_mask = 1ull<<3 /* npei */;
3041     info.func               = __cvmx_error_display;
3042     info.user_info          = (long)
3043         "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3044         "    register. Core0.\n";
3045     fail |= cvmx_error_add(&info);
3046
3047     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3048     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3049     info.status_mask        = 1ull<<36 /* c0_up_wi */;
3050     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3051     info.enable_mask        = 1ull<<36 /* c0_up_wi */;
3052     info.flags              = 0;
3053     info.group              = CVMX_ERROR_GROUP_PCI;
3054     info.group_index        = 0;
3055     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3056     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3057     info.parent.status_mask = 1ull<<3 /* npei */;
3058     info.func               = __cvmx_error_display;
3059     info.user_info          = (long)
3060         "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3061         "    Core 0.\n";
3062     fail |= cvmx_error_add(&info);
3063
3064     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3065     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3066     info.status_mask        = 1ull<<23 /* c0_wake */;
3067     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3068     info.enable_mask        = 1ull<<23 /* c0_wake */;
3069     info.flags              = 0;
3070     info.group              = CVMX_ERROR_GROUP_PCI;
3071     info.group_index        = 0;
3072     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3073     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3074     info.parent.status_mask = 1ull<<3 /* npei */;
3075     info.func               = __cvmx_error_display;
3076     info.user_info          = (long)
3077         "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
3078         "    Pcie Core 0. (wake_n)\n"
3079         "    Octeon will never generate this interrupt.\n";
3080     fail |= cvmx_error_add(&info);
3081
3082     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3083     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3084     info.status_mask        = 1ull<<22 /* crs0_dr */;
3085     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3086     info.enable_mask        = 1ull<<22 /* crs0_dr */;
3087     info.flags              = 0;
3088     info.group              = CVMX_ERROR_GROUP_PCI;
3089     info.group_index        = 0;
3090     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3091     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3092     info.parent.status_mask = 1ull<<3 /* npei */;
3093     info.func               = __cvmx_error_display;
3094     info.user_info          = (long)
3095         "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
3096     fail |= cvmx_error_add(&info);
3097
3098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3099     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3100     info.status_mask        = 1ull<<20 /* crs0_er */;
3101     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3102     info.enable_mask        = 1ull<<20 /* crs0_er */;
3103     info.flags              = 0;
3104     info.group              = CVMX_ERROR_GROUP_PCI;
3105     info.group_index        = 0;
3106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3107     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3108     info.parent.status_mask = 1ull<<3 /* npei */;
3109     info.func               = __cvmx_error_display;
3110     info.user_info          = (long)
3111         "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
3112     fail |= cvmx_error_add(&info);
3113
3114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3115     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3116     info.status_mask        = 1ull<<60 /* c1_ldwn */;
3117     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3118     info.enable_mask        = 1ull<<60 /* c1_ldwn */;
3119     info.flags              = 0;
3120     info.group              = CVMX_ERROR_GROUP_PCI;
3121     info.group_index        = 1;
3122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3123     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3124     info.parent.status_mask = 1ull<<3 /* npei */;
3125     info.func               = __cvmx_error_display;
3126     info.user_info          = (long)
3127         "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
3128     fail |= cvmx_error_add(&info);
3129
3130     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3131     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3132     info.status_mask        = 1ull<<28 /* c1_se */;
3133     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3134     info.enable_mask        = 1ull<<28 /* c1_se */;
3135     info.flags              = 0;
3136     info.group              = CVMX_ERROR_GROUP_PCI;
3137     info.group_index        = 1;
3138     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3139     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3140     info.parent.status_mask = 1ull<<3 /* npei */;
3141     info.func               = __cvmx_error_display;
3142     info.user_info          = (long)
3143         "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
3144         "    Pcie Core 1. (cfg_sys_err_rc)\n";
3145     fail |= cvmx_error_add(&info);
3146
3147     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3148     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3149     info.status_mask        = 1ull<<48 /* c1_un_b0 */;
3150     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3151     info.enable_mask        = 1ull<<48 /* c1_un_b0 */;
3152     info.flags              = 0;
3153     info.group              = CVMX_ERROR_GROUP_PCI;
3154     info.group_index        = 1;
3155     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3156     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3157     info.parent.status_mask = 1ull<<3 /* npei */;
3158     info.func               = __cvmx_error_display;
3159     info.user_info          = (long)
3160         "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
3161         "    Core 1.\n";
3162     fail |= cvmx_error_add(&info);
3163
3164     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3165     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3166     info.status_mask        = 1ull<<49 /* c1_un_b1 */;
3167     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3168     info.enable_mask        = 1ull<<49 /* c1_un_b1 */;
3169     info.flags              = 0;
3170     info.group              = CVMX_ERROR_GROUP_PCI;
3171     info.group_index        = 1;
3172     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3173     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3174     info.parent.status_mask = 1ull<<3 /* npei */;
3175     info.func               = __cvmx_error_display;
3176     info.user_info          = (long)
3177         "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
3178         "    Core 1.\n";
3179     fail |= cvmx_error_add(&info);
3180
3181     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3182     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3183     info.status_mask        = 1ull<<50 /* c1_un_b2 */;
3184     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3185     info.enable_mask        = 1ull<<50 /* c1_un_b2 */;
3186     info.flags              = 0;
3187     info.group              = CVMX_ERROR_GROUP_PCI;
3188     info.group_index        = 1;
3189     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3190     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3191     info.parent.status_mask = 1ull<<3 /* npei */;
3192     info.func               = __cvmx_error_display;
3193     info.user_info          = (long)
3194         "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
3195         "    Core 1.\n";
3196     fail |= cvmx_error_add(&info);
3197
3198     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3199     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3200     info.status_mask        = 1ull<<52 /* c1_un_bx */;
3201     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3202     info.enable_mask        = 1ull<<52 /* c1_un_bx */;
3203     info.flags              = 0;
3204     info.group              = CVMX_ERROR_GROUP_PCI;
3205     info.group_index        = 1;
3206     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3207     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3208     info.parent.status_mask = 1ull<<3 /* npei */;
3209     info.func               = __cvmx_error_display;
3210     info.user_info          = (long)
3211         "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
3212         "    Core 1.\n";
3213     fail |= cvmx_error_add(&info);
3214
3215     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3216     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3217     info.status_mask        = 1ull<<54 /* c1_un_wf */;
3218     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3219     info.enable_mask        = 1ull<<54 /* c1_un_wf */;
3220     info.flags              = 0;
3221     info.group              = CVMX_ERROR_GROUP_PCI;
3222     info.group_index        = 1;
3223     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3224     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3225     info.parent.status_mask = 1ull<<3 /* npei */;
3226     info.func               = __cvmx_error_display;
3227     info.user_info          = (long)
3228         "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
3229         "    register. Core1.\n";
3230     fail |= cvmx_error_add(&info);
3231
3232     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3233     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3234     info.status_mask        = 1ull<<51 /* c1_un_wi */;
3235     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3236     info.enable_mask        = 1ull<<51 /* c1_un_wi */;
3237     info.flags              = 0;
3238     info.group              = CVMX_ERROR_GROUP_PCI;
3239     info.group_index        = 1;
3240     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3241     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3242     info.parent.status_mask = 1ull<<3 /* npei */;
3243     info.func               = __cvmx_error_display;
3244     info.user_info          = (long)
3245         "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
3246         "    Core 1.\n";
3247     fail |= cvmx_error_add(&info);
3248
3249     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3250     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3251     info.status_mask        = 1ull<<43 /* c1_up_b0 */;
3252     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3253     info.enable_mask        = 1ull<<43 /* c1_up_b0 */;
3254     info.flags              = 0;
3255     info.group              = CVMX_ERROR_GROUP_PCI;
3256     info.group_index        = 1;
3257     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3258     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3259     info.parent.status_mask = 1ull<<3 /* npei */;
3260     info.func               = __cvmx_error_display;
3261     info.user_info          = (long)
3262         "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
3263         "    Core 1.\n";
3264     fail |= cvmx_error_add(&info);
3265
3266     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3267     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3268     info.status_mask        = 1ull<<44 /* c1_up_b1 */;
3269     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3270     info.enable_mask        = 1ull<<44 /* c1_up_b1 */;
3271     info.flags              = 0;
3272     info.group              = CVMX_ERROR_GROUP_PCI;
3273     info.group_index        = 1;
3274     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3275     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3276     info.parent.status_mask = 1ull<<3 /* npei */;
3277     info.func               = __cvmx_error_display;
3278     info.user_info          = (long)
3279         "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
3280         "    Core 1.\n";
3281     fail |= cvmx_error_add(&info);
3282
3283     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3284     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3285     info.status_mask        = 1ull<<45 /* c1_up_b2 */;
3286     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3287     info.enable_mask        = 1ull<<45 /* c1_up_b2 */;
3288     info.flags              = 0;
3289     info.group              = CVMX_ERROR_GROUP_PCI;
3290     info.group_index        = 1;
3291     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3292     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3293     info.parent.status_mask = 1ull<<3 /* npei */;
3294     info.func               = __cvmx_error_display;
3295     info.user_info          = (long)
3296         "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3297         "    Core 1.\n";
3298     fail |= cvmx_error_add(&info);
3299
3300     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3301     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3302     info.status_mask        = 1ull<<47 /* c1_up_bx */;
3303     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3304     info.enable_mask        = 1ull<<47 /* c1_up_bx */;
3305     info.flags              = 0;
3306     info.group              = CVMX_ERROR_GROUP_PCI;
3307     info.group_index        = 1;
3308     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3309     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3310     info.parent.status_mask = 1ull<<3 /* npei */;
3311     info.func               = __cvmx_error_display;
3312     info.user_info          = (long)
3313         "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3314         "    Core 1.\n";
3315     fail |= cvmx_error_add(&info);
3316
3317     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3318     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3319     info.status_mask        = 1ull<<56 /* c1_up_wf */;
3320     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3321     info.enable_mask        = 1ull<<56 /* c1_up_wf */;
3322     info.flags              = 0;
3323     info.group              = CVMX_ERROR_GROUP_PCI;
3324     info.group_index        = 1;
3325     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3326     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3327     info.parent.status_mask = 1ull<<3 /* npei */;
3328     info.func               = __cvmx_error_display;
3329     info.user_info          = (long)
3330         "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3331         "    register. Core1.\n";
3332     fail |= cvmx_error_add(&info);
3333
3334     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3335     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3336     info.status_mask        = 1ull<<46 /* c1_up_wi */;
3337     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3338     info.enable_mask        = 1ull<<46 /* c1_up_wi */;
3339     info.flags              = 0;
3340     info.group              = CVMX_ERROR_GROUP_PCI;
3341     info.group_index        = 1;
3342     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3343     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3344     info.parent.status_mask = 1ull<<3 /* npei */;
3345     info.func               = __cvmx_error_display;
3346     info.user_info          = (long)
3347         "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3348         "    Core 1.\n";
3349     fail |= cvmx_error_add(&info);
3350
3351     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3352     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3353     info.status_mask        = 1ull<<30 /* c1_wake */;
3354     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3355     info.enable_mask        = 1ull<<30 /* c1_wake */;
3356     info.flags              = 0;
3357     info.group              = CVMX_ERROR_GROUP_PCI;
3358     info.group_index        = 1;
3359     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3360     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3361     info.parent.status_mask = 1ull<<3 /* npei */;
3362     info.func               = __cvmx_error_display;
3363     info.user_info          = (long)
3364         "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
3365         "    Pcie Core 1. (wake_n)\n"
3366         "    Octeon will never generate this interrupt.\n";
3367     fail |= cvmx_error_add(&info);
3368
3369     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3370     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3371     info.status_mask        = 1ull<<29 /* crs1_dr */;
3372     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3373     info.enable_mask        = 1ull<<29 /* crs1_dr */;
3374     info.flags              = 0;
3375     info.group              = CVMX_ERROR_GROUP_PCI;
3376     info.group_index        = 1;
3377     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3378     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3379     info.parent.status_mask = 1ull<<3 /* npei */;
3380     info.func               = __cvmx_error_display;
3381     info.user_info          = (long)
3382         "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
3383     fail |= cvmx_error_add(&info);
3384
3385     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3386     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3387     info.status_mask        = 1ull<<27 /* crs1_er */;
3388     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3389     info.enable_mask        = 1ull<<27 /* crs1_er */;
3390     info.flags              = 0;
3391     info.group              = CVMX_ERROR_GROUP_PCI;
3392     info.group_index        = 1;
3393     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3394     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3395     info.parent.status_mask = 1ull<<3 /* npei */;
3396     info.func               = __cvmx_error_display;
3397     info.user_info          = (long)
3398         "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
3399     fail |= cvmx_error_add(&info);
3400
3401     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3402     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3403     info.status_mask        = 1ull<<2 /* bar0_to */;
3404     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3405     info.enable_mask        = 1ull<<2 /* bar0_to */;
3406     info.flags              = 0;
3407     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3408     info.group_index        = 0;
3409     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3410     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3411     info.parent.status_mask = 1ull<<3 /* npei */;
3412     info.func               = __cvmx_error_display;
3413     info.user_info          = (long)
3414         "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
3415         "    read-data/commit in 0xffff core clocks.\n";
3416     fail |= cvmx_error_add(&info);
3417
3418     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3419     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3420     info.status_mask        = 1ull<<4 /* dma0dbo */;
3421     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3422     info.enable_mask        = 1ull<<4 /* dma0dbo */;
3423     info.flags              = 0;
3424     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3425     info.group_index        = 0;
3426     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3427     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3428     info.parent.status_mask = 1ull<<3 /* npei */;
3429     info.func               = __cvmx_error_display;
3430     info.user_info          = (long)
3431         "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell count overflow.\n"
3432         "    Bit[32] of the doorbell count was set.\n";
3433     fail |= cvmx_error_add(&info);
3434
3435     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3436     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3437     info.status_mask        = 1ull<<5 /* dma1dbo */;
3438     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3439     info.enable_mask        = 1ull<<5 /* dma1dbo */;
3440     info.flags              = 0;
3441     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3442     info.group_index        = 0;
3443     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3444     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3445     info.parent.status_mask = 1ull<<3 /* npei */;
3446     info.func               = __cvmx_error_display;
3447     info.user_info          = (long)
3448         "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell count overflow.\n"
3449         "    Bit[32] of the doorbell count was set.\n";
3450     fail |= cvmx_error_add(&info);
3451
3452     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3453     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3454     info.status_mask        = 1ull<<6 /* dma2dbo */;
3455     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3456     info.enable_mask        = 1ull<<6 /* dma2dbo */;
3457     info.flags              = 0;
3458     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3459     info.group_index        = 0;
3460     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3461     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3462     info.parent.status_mask = 1ull<<3 /* npei */;
3463     info.func               = __cvmx_error_display;
3464     info.user_info          = (long)
3465         "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell count overflow.\n"
3466         "    Bit[32] of the doorbell count was set.\n";
3467     fail |= cvmx_error_add(&info);
3468
3469     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3470     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3471     info.status_mask        = 1ull<<7 /* dma3dbo */;
3472     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3473     info.enable_mask        = 1ull<<7 /* dma3dbo */;
3474     info.flags              = 0;
3475     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3476     info.group_index        = 0;
3477     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3478     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3479     info.parent.status_mask = 1ull<<3 /* npei */;
3480     info.func               = __cvmx_error_display;
3481     info.user_info          = (long)
3482         "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell count overflow.\n"
3483         "    Bit[32] of the doorbell count was set.\n";
3484     fail |= cvmx_error_add(&info);
3485
3486     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3487     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3488     info.status_mask        = 1ull<<3 /* iob2big */;
3489     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3490     info.enable_mask        = 1ull<<3 /* iob2big */;
3491     info.flags              = 0;
3492     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3493     info.group_index        = 0;
3494     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3495     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3496     info.parent.status_mask = 1ull<<3 /* npei */;
3497     info.func               = __cvmx_error_display;
3498     info.user_info          = (long)
3499         "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
3500     fail |= cvmx_error_add(&info);
3501
3502     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3503     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3504     info.status_mask        = 1ull<<0 /* rml_rto */;
3505     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3506     info.enable_mask        = 1ull<<0 /* rml_rto */;
3507     info.flags              = 0;
3508     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3509     info.group_index        = 0;
3510     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3511     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3512     info.parent.status_mask = 1ull<<3 /* npei */;
3513     info.func               = __cvmx_error_display;
3514     info.user_info          = (long)
3515         "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
3516     fail |= cvmx_error_add(&info);
3517
3518     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3519     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3520     info.status_mask        = 1ull<<1 /* rml_wto */;
3521     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3522     info.enable_mask        = 1ull<<1 /* rml_wto */;
3523     info.flags              = 0;
3524     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3525     info.group_index        = 0;
3526     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3527     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3528     info.parent.status_mask = 1ull<<3 /* npei */;
3529     info.func               = __cvmx_error_display;
3530     info.user_info          = (long)
3531         "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
3532     fail |= cvmx_error_add(&info);
3533
3534     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3535     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3536     info.status_mask        = 0;
3537     info.enable_addr        = 0;
3538     info.enable_mask        = 0;
3539     info.flags              = 0;
3540     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3541     info.group_index        = 0;
3542     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3543     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3544     info.parent.status_mask = 1ull<<3 /* npei */;
3545     info.func               = __cvmx_error_decode;
3546     info.user_info          = 0;
3547     fail |= cvmx_error_add(&info);
3548
3549     /* CVMX_PESCX_DBG_INFO(0) */
3550     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3551     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3552     info.status_mask        = 1ull<<0 /* spoison */;
3553     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3554     info.enable_mask        = 1ull<<0 /* spoison */;
3555     info.flags              = 0;
3556     info.group              = CVMX_ERROR_GROUP_PCI;
3557     info.group_index        = 0;
3558     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3559     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3560     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3561     info.func               = __cvmx_error_display;
3562     info.user_info          = (long)
3563         "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
3564         "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3565     fail |= cvmx_error_add(&info);
3566
3567     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3568     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3569     info.status_mask        = 1ull<<2 /* rtlplle */;
3570     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3571     info.enable_mask        = 1ull<<2 /* rtlplle */;
3572     info.flags              = 0;
3573     info.group              = CVMX_ERROR_GROUP_PCI;
3574     info.group_index        = 0;
3575     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3576     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3577     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3578     info.func               = __cvmx_error_display;
3579     info.user_info          = (long)
3580         "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
3581         "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3582     fail |= cvmx_error_add(&info);
3583
3584     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3585     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3586     info.status_mask        = 1ull<<3 /* recrce */;
3587     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3588     info.enable_mask        = 1ull<<3 /* recrce */;
3589     info.flags              = 0;
3590     info.group              = CVMX_ERROR_GROUP_PCI;
3591     info.group_index        = 0;
3592     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3593     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3594     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3595     info.func               = __cvmx_error_display;
3596     info.user_info          = (long)
3597         "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
3598         "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3599     fail |= cvmx_error_add(&info);
3600
3601     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3602     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3603     info.status_mask        = 1ull<<4 /* rpoison */;
3604     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3605     info.enable_mask        = 1ull<<4 /* rpoison */;
3606     info.flags              = 0;
3607     info.group              = CVMX_ERROR_GROUP_PCI;
3608     info.group_index        = 0;
3609     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3610     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3611     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3612     info.func               = __cvmx_error_display;
3613     info.user_info          = (long)
3614         "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
3615         "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3616     fail |= cvmx_error_add(&info);
3617
3618     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3619     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3620     info.status_mask        = 1ull<<5 /* rcemrc */;
3621     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3622     info.enable_mask        = 1ull<<5 /* rcemrc */;
3623     info.flags              = 0;
3624     info.group              = CVMX_ERROR_GROUP_PCI;
3625     info.group_index        = 0;
3626     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3627     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3628     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3629     info.func               = __cvmx_error_display;
3630     info.user_info          = (long)
3631         "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3632         "    pedc_radm_correctable_err\n";
3633     fail |= cvmx_error_add(&info);
3634
3635     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3636     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3637     info.status_mask        = 1ull<<6 /* rnfemrc */;
3638     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3639     info.enable_mask        = 1ull<<6 /* rnfemrc */;
3640     info.flags              = 0;
3641     info.group              = CVMX_ERROR_GROUP_PCI;
3642     info.group_index        = 0;
3643     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3644     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3645     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3646     info.func               = __cvmx_error_display;
3647     info.user_info          = (long)
3648         "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3649         "    pedc_radm_nonfatal_err\n";
3650     fail |= cvmx_error_add(&info);
3651
3652     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3653     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3654     info.status_mask        = 1ull<<7 /* rfemrc */;
3655     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3656     info.enable_mask        = 1ull<<7 /* rfemrc */;
3657     info.flags              = 0;
3658     info.group              = CVMX_ERROR_GROUP_PCI;
3659     info.group_index        = 0;
3660     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3661     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3662     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3663     info.func               = __cvmx_error_display;
3664     info.user_info          = (long)
3665         "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3666         "    pedc_radm_fatal_err\n"
3667         "    Bit set when a message with ERR_FATAL is set.\n";
3668     fail |= cvmx_error_add(&info);
3669
3670     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3671     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3672     info.status_mask        = 1ull<<8 /* rpmerc */;
3673     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3674     info.enable_mask        = 1ull<<8 /* rpmerc */;
3675     info.flags              = 0;
3676     info.group              = CVMX_ERROR_GROUP_PCI;
3677     info.group_index        = 0;
3678     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3679     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3680     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3681     info.func               = __cvmx_error_display;
3682     info.user_info          = (long)
3683         "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
3684         "    pedc_radm_pm_pme\n";
3685     fail |= cvmx_error_add(&info);
3686
3687     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3688     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3689     info.status_mask        = 1ull<<9 /* rptamrc */;
3690     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3691     info.enable_mask        = 1ull<<9 /* rptamrc */;
3692     info.flags              = 0;
3693     info.group              = CVMX_ERROR_GROUP_PCI;
3694     info.group_index        = 0;
3695     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3696     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3697     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3698     info.func               = __cvmx_error_display;
3699     info.user_info          = (long)
3700         "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3701         "    (RC Mode only)\n"
3702         "    pedc_radm_pm_to_ack\n";
3703     fail |= cvmx_error_add(&info);
3704
3705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3706     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3707     info.status_mask        = 1ull<<10 /* rumep */;
3708     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3709     info.enable_mask        = 1ull<<10 /* rumep */;
3710     info.flags              = 0;
3711     info.group              = CVMX_ERROR_GROUP_PCI;
3712     info.group_index        = 0;
3713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3714     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3715     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3716     info.func               = __cvmx_error_display;
3717     info.user_info          = (long)
3718         "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3719         "    pedc_radm_msg_unlock\n";
3720     fail |= cvmx_error_add(&info);
3721
3722     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3723     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3724     info.status_mask        = 1ull<<11 /* rvdm */;
3725     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3726     info.enable_mask        = 1ull<<11 /* rvdm */;
3727     info.flags              = 0;
3728     info.group              = CVMX_ERROR_GROUP_PCI;
3729     info.group_index        = 0;
3730     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3731     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3732     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3733     info.func               = __cvmx_error_display;
3734     info.user_info          = (long)
3735         "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
3736         "    pedc_radm_vendor_msg\n";
3737     fail |= cvmx_error_add(&info);
3738
3739     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3740     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3741     info.status_mask        = 1ull<<12 /* acto */;
3742     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3743     info.enable_mask        = 1ull<<12 /* acto */;
3744     info.flags              = 0;
3745     info.group              = CVMX_ERROR_GROUP_PCI;
3746     info.group_index        = 0;
3747     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3748     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3749     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3750     info.func               = __cvmx_error_display;
3751     info.user_info          = (long)
3752         "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
3753         "    pedc_radm_cpl_timeout\n";
3754     fail |= cvmx_error_add(&info);
3755
3756     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3757     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3758     info.status_mask        = 1ull<<13 /* rte */;
3759     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3760     info.enable_mask        = 1ull<<13 /* rte */;
3761     info.flags              = 0;
3762     info.group              = CVMX_ERROR_GROUP_PCI;
3763     info.group_index        = 0;
3764     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3765     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3766     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3767     info.func               = __cvmx_error_display;
3768     info.user_info          = (long)
3769         "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
3770         "    xdlh_replay_timeout_err\n"
3771         "    This bit is set when the REPLAY_TIMER expires in\n"
3772         "    the PCIE core. The probability of this bit being\n"
3773         "    set will increase with the traffic load.\n";
3774     fail |= cvmx_error_add(&info);
3775
3776     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3777     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3778     info.status_mask        = 1ull<<14 /* mre */;
3779     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3780     info.enable_mask        = 1ull<<14 /* mre */;
3781     info.flags              = 0;
3782     info.group              = CVMX_ERROR_GROUP_PCI;
3783     info.group_index        = 0;
3784     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3785     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3786     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3787     info.func               = __cvmx_error_display;
3788     info.user_info          = (long)
3789         "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
3790         "    xdlh_replay_num_rlover_err\n";
3791     fail |= cvmx_error_add(&info);
3792
3793     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3794     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3795     info.status_mask        = 1ull<<15 /* rdwdle */;
3796     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3797     info.enable_mask        = 1ull<<15 /* rdwdle */;
3798     info.flags              = 0;
3799     info.group              = CVMX_ERROR_GROUP_PCI;
3800     info.group_index        = 0;
3801     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3802     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3803     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3804     info.func               = __cvmx_error_display;
3805     info.user_info          = (long)
3806         "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3807         "    rdlh_bad_dllp_err\n";
3808     fail |= cvmx_error_add(&info);
3809
3810     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3811     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3812     info.status_mask        = 1ull<<16 /* rtwdle */;
3813     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3814     info.enable_mask        = 1ull<<16 /* rtwdle */;
3815     info.flags              = 0;
3816     info.group              = CVMX_ERROR_GROUP_PCI;
3817     info.group_index        = 0;
3818     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3819     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3820     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3821     info.func               = __cvmx_error_display;
3822     info.user_info          = (long)
3823         "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3824         "    rdlh_bad_tlp_err\n";
3825     fail |= cvmx_error_add(&info);
3826
3827     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3828     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3829     info.status_mask        = 1ull<<17 /* dpeoosd */;
3830     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3831     info.enable_mask        = 1ull<<17 /* dpeoosd */;
3832     info.flags              = 0;
3833     info.group              = CVMX_ERROR_GROUP_PCI;
3834     info.group_index        = 0;
3835     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3836     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3837     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3838     info.func               = __cvmx_error_display;
3839     info.user_info          = (long)
3840         "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3841         "    rdlh_prot_err\n";
3842     fail |= cvmx_error_add(&info);
3843
3844     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3845     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3846     info.status_mask        = 1ull<<18 /* fcpvwt */;
3847     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3848     info.enable_mask        = 1ull<<18 /* fcpvwt */;
3849     info.flags              = 0;
3850     info.group              = CVMX_ERROR_GROUP_PCI;
3851     info.group_index        = 0;
3852     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3853     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3854     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3855     info.func               = __cvmx_error_display;
3856     info.user_info          = (long)
3857         "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3858         "    rtlh_fc_prot_err\n";
3859     fail |= cvmx_error_add(&info);
3860
3861     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3862     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3863     info.status_mask        = 1ull<<19 /* rpe */;
3864     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3865     info.enable_mask        = 1ull<<19 /* rpe */;
3866     info.flags              = 0;
3867     info.group              = CVMX_ERROR_GROUP_PCI;
3868     info.group_index        = 0;
3869     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3870     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3871     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3872     info.func               = __cvmx_error_display;
3873     info.user_info          = (long)
3874         "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
3875         "    (RxStatus = 3b100) or disparity error\n"
3876         "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3877         "    be asserted.\n"
3878         "    rmlh_rcvd_err\n";
3879     fail |= cvmx_error_add(&info);
3880
3881     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3882     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3883     info.status_mask        = 1ull<<20 /* fcuv */;
3884     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3885     info.enable_mask        = 1ull<<20 /* fcuv */;
3886     info.flags              = 0;
3887     info.group              = CVMX_ERROR_GROUP_PCI;
3888     info.group_index        = 0;
3889     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3890     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3891     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3892     info.func               = __cvmx_error_display;
3893     info.user_info          = (long)
3894         "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3895         "    int_xadm_fc_prot_err\n";
3896     fail |= cvmx_error_add(&info);
3897
3898     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3899     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3900     info.status_mask        = 1ull<<21 /* rqo */;
3901     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3902     info.enable_mask        = 1ull<<21 /* rqo */;
3903     info.flags              = 0;
3904     info.group              = CVMX_ERROR_GROUP_PCI;
3905     info.group_index        = 0;
3906     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3907     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3908     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3909     info.func               = __cvmx_error_display;
3910     info.user_info          = (long)
3911         "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
3912         "    flow control advertisements are ignored\n"
3913         "    radm_qoverflow\n";
3914     fail |= cvmx_error_add(&info);
3915
3916     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3917     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3918     info.status_mask        = 1ull<<22 /* rauc */;
3919     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3920     info.enable_mask        = 1ull<<22 /* rauc */;
3921     info.flags              = 0;
3922     info.group              = CVMX_ERROR_GROUP_PCI;
3923     info.group_index        = 0;
3924     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3925     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3926     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3927     info.func               = __cvmx_error_display;
3928     info.user_info          = (long)
3929         "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
3930         "    radm_unexp_cpl_err\n";
3931     fail |= cvmx_error_add(&info);
3932
3933     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3934     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3935     info.status_mask        = 1ull<<23 /* racur */;
3936     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3937     info.enable_mask        = 1ull<<23 /* racur */;
3938     info.flags              = 0;
3939     info.group              = CVMX_ERROR_GROUP_PCI;
3940     info.group_index        = 0;
3941     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3942     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3943     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3944     info.func               = __cvmx_error_display;
3945     info.user_info          = (long)
3946         "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
3947         "    radm_rcvd_cpl_ur\n";
3948     fail |= cvmx_error_add(&info);
3949
3950     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3951     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3952     info.status_mask        = 1ull<<24 /* racca */;
3953     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3954     info.enable_mask        = 1ull<<24 /* racca */;
3955     info.flags              = 0;
3956     info.group              = CVMX_ERROR_GROUP_PCI;
3957     info.group_index        = 0;
3958     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3959     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3960     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3961     info.func               = __cvmx_error_display;
3962     info.user_info          = (long)
3963         "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
3964         "    radm_rcvd_cpl_ca\n";
3965     fail |= cvmx_error_add(&info);
3966
3967     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3968     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3969     info.status_mask        = 1ull<<25 /* caar */;
3970     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3971     info.enable_mask        = 1ull<<25 /* caar */;
3972     info.flags              = 0;
3973     info.group              = CVMX_ERROR_GROUP_PCI;
3974     info.group_index        = 0;
3975     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3976     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3977     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3978     info.func               = __cvmx_error_display;
3979     info.user_info          = (long)
3980         "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
3981         "    radm_rcvd_ca_req\n"
3982         "    This bit will never be set because Octeon does\n"
3983         "    not generate Completer Aborts.\n";
3984     fail |= cvmx_error_add(&info);
3985
3986     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3987     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3988     info.status_mask        = 1ull<<26 /* rarwdns */;
3989     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3990     info.enable_mask        = 1ull<<26 /* rarwdns */;
3991     info.flags              = 0;
3992     info.group              = CVMX_ERROR_GROUP_PCI;
3993     info.group_index        = 0;
3994     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3995     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3996     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3997     info.func               = __cvmx_error_display;
3998     info.user_info          = (long)
3999         "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
4000         "    radm_rcvd_ur_req\n";
4001     fail |= cvmx_error_add(&info);
4002
4003     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4004     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4005     info.status_mask        = 1ull<<27 /* ramtlp */;
4006     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4007     info.enable_mask        = 1ull<<27 /* ramtlp */;
4008     info.flags              = 0;
4009     info.group              = CVMX_ERROR_GROUP_PCI;
4010     info.group_index        = 0;
4011     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4012     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4013     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4014     info.func               = __cvmx_error_display;
4015     info.user_info          = (long)
4016         "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
4017         "    radm_mlf_tlp_err\n";
4018     fail |= cvmx_error_add(&info);
4019
4020     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4021     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4022     info.status_mask        = 1ull<<28 /* racpp */;
4023     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4024     info.enable_mask        = 1ull<<28 /* racpp */;
4025     info.flags              = 0;
4026     info.group              = CVMX_ERROR_GROUP_PCI;
4027     info.group_index        = 0;
4028     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4029     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4030     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4031     info.func               = __cvmx_error_display;
4032     info.user_info          = (long)
4033         "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
4034         "    radm_rcvd_cpl_poisoned\n";
4035     fail |= cvmx_error_add(&info);
4036
4037     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4038     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4039     info.status_mask        = 1ull<<29 /* rawwpp */;
4040     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4041     info.enable_mask        = 1ull<<29 /* rawwpp */;
4042     info.flags              = 0;
4043     info.group              = CVMX_ERROR_GROUP_PCI;
4044     info.group_index        = 0;
4045     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4046     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4047     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4048     info.func               = __cvmx_error_display;
4049     info.user_info          = (long)
4050         "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
4051         "    radm_rcvd_wreq_poisoned\n";
4052     fail |= cvmx_error_add(&info);
4053
4054     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4055     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4056     info.status_mask        = 1ull<<30 /* ecrc_e */;
4057     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4058     info.enable_mask        = 1ull<<30 /* ecrc_e */;
4059     info.flags              = 0;
4060     info.group              = CVMX_ERROR_GROUP_PCI;
4061     info.group_index        = 0;
4062     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4063     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4064     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4065     info.func               = __cvmx_error_display;
4066     info.user_info          = (long)
4067         "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
4068         "    radm_ecrc_err\n";
4069     fail |= cvmx_error_add(&info);
4070
4071     /* CVMX_PESCX_DBG_INFO(1) */
4072     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4073     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4074     info.status_mask        = 1ull<<0 /* spoison */;
4075     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4076     info.enable_mask        = 1ull<<0 /* spoison */;
4077     info.flags              = 0;
4078     info.group              = CVMX_ERROR_GROUP_PCI;
4079     info.group_index        = 1;
4080     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4081     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4082     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4083     info.func               = __cvmx_error_display;
4084     info.user_info          = (long)
4085         "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
4086         "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
4087     fail |= cvmx_error_add(&info);
4088
4089     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4090     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4091     info.status_mask        = 1ull<<2 /* rtlplle */;
4092     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4093     info.enable_mask        = 1ull<<2 /* rtlplle */;
4094     info.flags              = 0;
4095     info.group              = CVMX_ERROR_GROUP_PCI;
4096     info.group_index        = 1;
4097     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4098     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4099     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4100     info.func               = __cvmx_error_display;
4101     info.user_info          = (long)
4102         "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
4103         "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
4104     fail |= cvmx_error_add(&info);
4105
4106     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4107     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4108     info.status_mask        = 1ull<<3 /* recrce */;
4109     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4110     info.enable_mask        = 1ull<<3 /* recrce */;
4111     info.flags              = 0;
4112     info.group              = CVMX_ERROR_GROUP_PCI;
4113     info.group_index        = 1;
4114     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4115     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4116     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4117     info.func               = __cvmx_error_display;
4118     info.user_info          = (long)
4119         "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
4120         "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
4121     fail |= cvmx_error_add(&info);
4122
4123     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4124     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4125     info.status_mask        = 1ull<<4 /* rpoison */;
4126     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4127     info.enable_mask        = 1ull<<4 /* rpoison */;
4128     info.flags              = 0;
4129     info.group              = CVMX_ERROR_GROUP_PCI;
4130     info.group_index        = 1;
4131     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4132     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4133     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4134     info.func               = __cvmx_error_display;
4135     info.user_info          = (long)
4136         "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
4137         "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
4138     fail |= cvmx_error_add(&info);
4139
4140     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4141     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4142     info.status_mask        = 1ull<<5 /* rcemrc */;
4143     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4144     info.enable_mask        = 1ull<<5 /* rcemrc */;
4145     info.flags              = 0;
4146     info.group              = CVMX_ERROR_GROUP_PCI;
4147     info.group_index        = 1;
4148     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4149     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4150     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4151     info.func               = __cvmx_error_display;
4152     info.user_info          = (long)
4153         "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
4154         "    pedc_radm_correctable_err\n";
4155     fail |= cvmx_error_add(&info);
4156
4157     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4158     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4159     info.status_mask        = 1ull<<6 /* rnfemrc */;
4160     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4161     info.enable_mask        = 1ull<<6 /* rnfemrc */;
4162     info.flags              = 0;
4163     info.group              = CVMX_ERROR_GROUP_PCI;
4164     info.group_index        = 1;
4165     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4166     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4167     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4168     info.func               = __cvmx_error_display;
4169     info.user_info          = (long)
4170         "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
4171         "    pedc_radm_nonfatal_err\n";
4172     fail |= cvmx_error_add(&info);
4173
4174     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4175     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4176     info.status_mask        = 1ull<<7 /* rfemrc */;
4177     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4178     info.enable_mask        = 1ull<<7 /* rfemrc */;
4179     info.flags              = 0;
4180     info.group              = CVMX_ERROR_GROUP_PCI;
4181     info.group_index        = 1;
4182     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4183     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4184     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4185     info.func               = __cvmx_error_display;
4186     info.user_info          = (long)
4187         "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
4188         "    pedc_radm_fatal_err\n"
4189         "    Bit set when a message with ERR_FATAL is set.\n";
4190     fail |= cvmx_error_add(&info);
4191
4192     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4193     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4194     info.status_mask        = 1ull<<8 /* rpmerc */;
4195     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4196     info.enable_mask        = 1ull<<8 /* rpmerc */;
4197     info.flags              = 0;
4198     info.group              = CVMX_ERROR_GROUP_PCI;
4199     info.group_index        = 1;
4200     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4201     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4202     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4203     info.func               = __cvmx_error_display;
4204     info.user_info          = (long)
4205         "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
4206         "    pedc_radm_pm_pme\n";
4207     fail |= cvmx_error_add(&info);
4208
4209     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4210     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4211     info.status_mask        = 1ull<<9 /* rptamrc */;
4212     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4213     info.enable_mask        = 1ull<<9 /* rptamrc */;
4214     info.flags              = 0;
4215     info.group              = CVMX_ERROR_GROUP_PCI;
4216     info.group_index        = 1;
4217     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4218     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4219     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4220     info.func               = __cvmx_error_display;
4221     info.user_info          = (long)
4222         "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
4223         "    (RC Mode only)\n"
4224         "    pedc_radm_pm_to_ack\n";
4225     fail |= cvmx_error_add(&info);
4226
4227     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4228     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4229     info.status_mask        = 1ull<<10 /* rumep */;
4230     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4231     info.enable_mask        = 1ull<<10 /* rumep */;
4232     info.flags              = 0;
4233     info.group              = CVMX_ERROR_GROUP_PCI;
4234     info.group_index        = 1;
4235     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4236     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4237     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4238     info.func               = __cvmx_error_display;
4239     info.user_info          = (long)
4240         "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
4241         "    pedc_radm_msg_unlock\n";
4242     fail |= cvmx_error_add(&info);
4243
4244     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4245     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4246     info.status_mask        = 1ull<<11 /* rvdm */;
4247     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4248     info.enable_mask        = 1ull<<11 /* rvdm */;
4249     info.flags              = 0;
4250     info.group              = CVMX_ERROR_GROUP_PCI;
4251     info.group_index        = 1;
4252     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4253     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4254     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4255     info.func               = __cvmx_error_display;
4256     info.user_info          = (long)
4257         "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
4258         "    pedc_radm_vendor_msg\n";
4259     fail |= cvmx_error_add(&info);
4260
4261     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4262     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4263     info.status_mask        = 1ull<<12 /* acto */;
4264     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4265     info.enable_mask        = 1ull<<12 /* acto */;
4266     info.flags              = 0;
4267     info.group              = CVMX_ERROR_GROUP_PCI;
4268     info.group_index        = 1;
4269     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4270     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4271     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4272     info.func               = __cvmx_error_display;
4273     info.user_info          = (long)
4274         "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
4275         "    pedc_radm_cpl_timeout\n";
4276     fail |= cvmx_error_add(&info);
4277
4278     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4279     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4280     info.status_mask        = 1ull<<13 /* rte */;
4281     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4282     info.enable_mask        = 1ull<<13 /* rte */;
4283     info.flags              = 0;
4284     info.group              = CVMX_ERROR_GROUP_PCI;
4285     info.group_index        = 1;
4286     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4287     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4288     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4289     info.func               = __cvmx_error_display;
4290     info.user_info          = (long)
4291         "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
4292         "    xdlh_replay_timeout_err\n"
4293         "    This bit is set when the REPLAY_TIMER expires in\n"
4294         "    the PCIE core. The probability of this bit being\n"
4295         "    set will increase with the traffic load.\n";
4296     fail |= cvmx_error_add(&info);
4297
4298     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4299     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4300     info.status_mask        = 1ull<<14 /* mre */;
4301     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4302     info.enable_mask        = 1ull<<14 /* mre */;
4303     info.flags              = 0;
4304     info.group              = CVMX_ERROR_GROUP_PCI;
4305     info.group_index        = 1;
4306     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4307     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4308     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4309     info.func               = __cvmx_error_display;
4310     info.user_info          = (long)
4311         "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
4312         "    xdlh_replay_num_rlover_err\n";
4313     fail |= cvmx_error_add(&info);
4314
4315     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4316     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4317     info.status_mask        = 1ull<<15 /* rdwdle */;
4318     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4319     info.enable_mask        = 1ull<<15 /* rdwdle */;
4320     info.flags              = 0;
4321     info.group              = CVMX_ERROR_GROUP_PCI;
4322     info.group_index        = 1;
4323     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4324     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4325     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4326     info.func               = __cvmx_error_display;
4327     info.user_info          = (long)
4328         "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
4329         "    rdlh_bad_dllp_err\n";
4330     fail |= cvmx_error_add(&info);
4331
4332     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4333     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4334     info.status_mask        = 1ull<<16 /* rtwdle */;
4335     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4336     info.enable_mask        = 1ull<<16 /* rtwdle */;
4337     info.flags              = 0;
4338     info.group              = CVMX_ERROR_GROUP_PCI;
4339     info.group_index        = 1;
4340     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4341     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4342     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4343     info.func               = __cvmx_error_display;
4344     info.user_info          = (long)
4345         "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
4346         "    rdlh_bad_tlp_err\n";
4347     fail |= cvmx_error_add(&info);
4348
4349     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4350     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4351     info.status_mask        = 1ull<<17 /* dpeoosd */;
4352     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4353     info.enable_mask        = 1ull<<17 /* dpeoosd */;
4354     info.flags              = 0;
4355     info.group              = CVMX_ERROR_GROUP_PCI;
4356     info.group_index        = 1;
4357     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4358     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4359     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4360     info.func               = __cvmx_error_display;
4361     info.user_info          = (long)
4362         "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
4363         "    rdlh_prot_err\n";
4364     fail |= cvmx_error_add(&info);
4365
4366     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4367     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4368     info.status_mask        = 1ull<<18 /* fcpvwt */;
4369     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4370     info.enable_mask        = 1ull<<18 /* fcpvwt */;
4371     info.flags              = 0;
4372     info.group              = CVMX_ERROR_GROUP_PCI;
4373     info.group_index        = 1;
4374     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4375     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4376     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4377     info.func               = __cvmx_error_display;
4378     info.user_info          = (long)
4379         "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
4380         "    rtlh_fc_prot_err\n";
4381     fail |= cvmx_error_add(&info);
4382
4383     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4384     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4385     info.status_mask        = 1ull<<19 /* rpe */;
4386     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4387     info.enable_mask        = 1ull<<19 /* rpe */;
4388     info.flags              = 0;
4389     info.group              = CVMX_ERROR_GROUP_PCI;
4390     info.group_index        = 1;
4391     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4392     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4393     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4394     info.func               = __cvmx_error_display;
4395     info.user_info          = (long)
4396         "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
4397         "    (RxStatus = 3b100) or disparity error\n"
4398         "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
4399         "    be asserted.\n"
4400         "    rmlh_rcvd_err\n";
4401     fail |= cvmx_error_add(&info);
4402
4403     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4404     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4405     info.status_mask        = 1ull<<20 /* fcuv */;
4406     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4407     info.enable_mask        = 1ull<<20 /* fcuv */;
4408     info.flags              = 0;
4409     info.group              = CVMX_ERROR_GROUP_PCI;
4410     info.group_index        = 1;
4411     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4412     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4413     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4414     info.func               = __cvmx_error_display;
4415     info.user_info          = (long)
4416         "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
4417         "    int_xadm_fc_prot_err\n";
4418     fail |= cvmx_error_add(&info);
4419
4420     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4421     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4422     info.status_mask        = 1ull<<21 /* rqo */;
4423     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4424     info.enable_mask        = 1ull<<21 /* rqo */;
4425     info.flags              = 0;
4426     info.group              = CVMX_ERROR_GROUP_PCI;
4427     info.group_index        = 1;
4428     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4429     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4430     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4431     info.func               = __cvmx_error_display;
4432     info.user_info          = (long)
4433         "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
4434         "    flow control advertisements are ignored\n"
4435         "    radm_qoverflow\n";
4436     fail |= cvmx_error_add(&info);
4437
4438     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4439     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4440     info.status_mask        = 1ull<<22 /* rauc */;
4441     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4442     info.enable_mask        = 1ull<<22 /* rauc */;
4443     info.flags              = 0;
4444     info.group              = CVMX_ERROR_GROUP_PCI;
4445     info.group_index        = 1;
4446     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4447     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4448     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4449     info.func               = __cvmx_error_display;
4450     info.user_info          = (long)
4451         "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
4452         "    radm_unexp_cpl_err\n";
4453     fail |= cvmx_error_add(&info);
4454
4455     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4456     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4457     info.status_mask        = 1ull<<23 /* racur */;
4458     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4459     info.enable_mask        = 1ull<<23 /* racur */;
4460     info.flags              = 0;
4461     info.group              = CVMX_ERROR_GROUP_PCI;
4462     info.group_index        = 1;
4463     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4464     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4465     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4466     info.func               = __cvmx_error_display;
4467     info.user_info          = (long)
4468         "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
4469         "    radm_rcvd_cpl_ur\n";
4470     fail |= cvmx_error_add(&info);
4471
4472     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4473     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4474     info.status_mask        = 1ull<<24 /* racca */;
4475     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4476     info.enable_mask        = 1ull<<24 /* racca */;
4477     info.flags              = 0;
4478     info.group              = CVMX_ERROR_GROUP_PCI;
4479     info.group_index        = 1;
4480     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4481     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4482     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4483     info.func               = __cvmx_error_display;
4484     info.user_info          = (long)
4485         "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
4486         "    radm_rcvd_cpl_ca\n";
4487     fail |= cvmx_error_add(&info);
4488
4489     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4490     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4491     info.status_mask        = 1ull<<25 /* caar */;
4492     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4493     info.enable_mask        = 1ull<<25 /* caar */;
4494     info.flags              = 0;
4495     info.group              = CVMX_ERROR_GROUP_PCI;
4496     info.group_index        = 1;
4497     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4498     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4499     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4500     info.func               = __cvmx_error_display;
4501     info.user_info          = (long)
4502         "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
4503         "    radm_rcvd_ca_req\n"
4504         "    This bit will never be set because Octeon does\n"
4505         "    not generate Completer Aborts.\n";
4506     fail |= cvmx_error_add(&info);
4507
4508     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4509     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4510     info.status_mask        = 1ull<<26 /* rarwdns */;
4511     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4512     info.enable_mask        = 1ull<<26 /* rarwdns */;
4513     info.flags              = 0;
4514     info.group              = CVMX_ERROR_GROUP_PCI;
4515     info.group_index        = 1;
4516     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4517     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4518     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4519     info.func               = __cvmx_error_display;
4520     info.user_info          = (long)
4521         "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
4522         "    radm_rcvd_ur_req\n";
4523     fail |= cvmx_error_add(&info);
4524
4525     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4526     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4527     info.status_mask        = 1ull<<27 /* ramtlp */;
4528     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4529     info.enable_mask        = 1ull<<27 /* ramtlp */;
4530     info.flags              = 0;
4531     info.group              = CVMX_ERROR_GROUP_PCI;
4532     info.group_index        = 1;
4533     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4534     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4535     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4536     info.func               = __cvmx_error_display;
4537     info.user_info          = (long)
4538         "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
4539         "    radm_mlf_tlp_err\n";
4540     fail |= cvmx_error_add(&info);
4541
4542     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4543     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4544     info.status_mask        = 1ull<<28 /* racpp */;
4545     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4546     info.enable_mask        = 1ull<<28 /* racpp */;
4547     info.flags              = 0;
4548     info.group              = CVMX_ERROR_GROUP_PCI;
4549     info.group_index        = 1;
4550     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4551     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4552     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4553     info.func               = __cvmx_error_display;
4554     info.user_info          = (long)
4555         "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
4556         "    radm_rcvd_cpl_poisoned\n";
4557     fail |= cvmx_error_add(&info);
4558
4559     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4560     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4561     info.status_mask        = 1ull<<29 /* rawwpp */;
4562     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4563     info.enable_mask        = 1ull<<29 /* rawwpp */;
4564     info.flags              = 0;
4565     info.group              = CVMX_ERROR_GROUP_PCI;
4566     info.group_index        = 1;
4567     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4568     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4569     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4570     info.func               = __cvmx_error_display;
4571     info.user_info          = (long)
4572         "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
4573         "    radm_rcvd_wreq_poisoned\n";
4574     fail |= cvmx_error_add(&info);
4575
4576     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4577     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4578     info.status_mask        = 1ull<<30 /* ecrc_e */;
4579     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4580     info.enable_mask        = 1ull<<30 /* ecrc_e */;
4581     info.flags              = 0;
4582     info.group              = CVMX_ERROR_GROUP_PCI;
4583     info.group_index        = 1;
4584     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4585     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4586     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4587     info.func               = __cvmx_error_display;
4588     info.user_info          = (long)
4589         "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
4590         "    radm_ecrc_err\n";
4591     fail |= cvmx_error_add(&info);
4592
4593     /* CVMX_RAD_REG_ERROR */
4594     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4595     info.status_addr        = CVMX_RAD_REG_ERROR;
4596     info.status_mask        = 1ull<<0 /* doorbell */;
4597     info.enable_addr        = CVMX_RAD_REG_INT_MASK;
4598     info.enable_mask        = 1ull<<0 /* doorbell */;
4599     info.flags              = 0;
4600     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4601     info.group_index        = 0;
4602     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4603     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4604     info.parent.status_mask = 1ull<<14 /* rad */;
4605     info.func               = __cvmx_error_display;
4606     info.user_info          = (long)
4607         "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4608     fail |= cvmx_error_add(&info);
4609
4610     /* CVMX_PKO_REG_ERROR */
4611     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4612     info.status_addr        = CVMX_PKO_REG_ERROR;
4613     info.status_mask        = 1ull<<0 /* parity */;
4614     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
4615     info.enable_mask        = 1ull<<0 /* parity */;
4616     info.flags              = 0;
4617     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4618     info.group_index        = 0;
4619     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4620     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4621     info.parent.status_mask = 1ull<<10 /* pko */;
4622     info.func               = __cvmx_error_display;
4623     info.user_info          = (long)
4624         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
4625     fail |= cvmx_error_add(&info);
4626
4627     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4628     info.status_addr        = CVMX_PKO_REG_ERROR;
4629     info.status_mask        = 1ull<<1 /* doorbell */;
4630     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
4631     info.enable_mask        = 1ull<<1 /* doorbell */;
4632     info.flags              = 0;
4633     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4634     info.group_index        = 0;
4635     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4636     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4637     info.parent.status_mask = 1ull<<10 /* pko */;
4638     info.func               = __cvmx_error_display;
4639     info.user_info          = (long)
4640         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4641     fail |= cvmx_error_add(&info);
4642
4643     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4644     info.status_addr        = CVMX_PKO_REG_ERROR;
4645     info.status_mask        = 1ull<<2 /* currzero */;
4646     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
4647     info.enable_mask        = 1ull<<2 /* currzero */;
4648     info.flags              = 0;
4649     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4650     info.group_index        = 0;
4651     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4652     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4653     info.parent.status_mask = 1ull<<10 /* pko */;
4654     info.func               = __cvmx_error_display;
4655     info.user_info          = (long)
4656         "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
4657     fail |= cvmx_error_add(&info);
4658
4659     /* CVMX_PCSX_INTX_REG(0,0) */
4660     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4661     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4662     info.status_mask        = 1ull<<2 /* an_err */;
4663     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4664     info.enable_mask        = 1ull<<2 /* an_err_en */;
4665     info.flags              = 0;
4666     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4667     info.group_index        = 0;
4668     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4669     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4670     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4671     info.func               = __cvmx_error_display;
4672     info.user_info          = (long)
4673         "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
4674     fail |= cvmx_error_add(&info);
4675
4676     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4677     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4678     info.status_mask        = 1ull<<3 /* txfifu */;
4679     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4680     info.enable_mask        = 1ull<<3 /* txfifu_en */;
4681     info.flags              = 0;
4682     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4683     info.group_index        = 0;
4684     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4685     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4686     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4687     info.func               = __cvmx_error_display;
4688     info.user_info          = (long)
4689         "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4690         "    condition\n";
4691     fail |= cvmx_error_add(&info);
4692
4693     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4694     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4695     info.status_mask        = 1ull<<4 /* txfifo */;
4696     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4697     info.enable_mask        = 1ull<<4 /* txfifo_en */;
4698     info.flags              = 0;
4699     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4700     info.group_index        = 0;
4701     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4702     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4703     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4704     info.func               = __cvmx_error_display;
4705     info.user_info          = (long)
4706         "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4707         "    condition\n";
4708     fail |= cvmx_error_add(&info);
4709
4710     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4711     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4712     info.status_mask        = 1ull<<5 /* txbad */;
4713     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4714     info.enable_mask        = 1ull<<5 /* txbad_en */;
4715     info.flags              = 0;
4716     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4717     info.group_index        = 0;
4718     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4719     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4720     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4721     info.func               = __cvmx_error_display;
4722     info.user_info          = (long)
4723         "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4724         "    state. Should never be set during normal operation\n";
4725     fail |= cvmx_error_add(&info);
4726
4727     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4728     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4729     info.status_mask        = 1ull<<7 /* rxbad */;
4730     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4731     info.enable_mask        = 1ull<<7 /* rxbad_en */;
4732     info.flags              = 0;
4733     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4734     info.group_index        = 0;
4735     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4736     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4737     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4738     info.func               = __cvmx_error_display;
4739     info.user_info          = (long)
4740         "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
4741         "    state. Should never be set during normal operation\n";
4742     fail |= cvmx_error_add(&info);
4743
4744     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4745     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4746     info.status_mask        = 1ull<<8 /* rxlock */;
4747     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4748     info.enable_mask        = 1ull<<8 /* rxlock_en */;
4749     info.flags              = 0;
4750     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4751     info.group_index        = 0;
4752     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4753     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4754     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4755     info.func               = __cvmx_error_display;
4756     info.user_info          = (long)
4757         "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4758         "    failure occurs\n"
4759         "    Cannot fire in loopback1 mode\n";
4760     fail |= cvmx_error_add(&info);
4761
4762     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4763     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4764     info.status_mask        = 1ull<<9 /* an_bad */;
4765     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4766     info.enable_mask        = 1ull<<9 /* an_bad_en */;
4767     info.flags              = 0;
4768     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4769     info.group_index        = 0;
4770     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4771     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4772     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4773     info.func               = __cvmx_error_display;
4774     info.user_info          = (long)
4775         "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
4776         "    state. Should never be set during normal operation\n";
4777     fail |= cvmx_error_add(&info);
4778
4779     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4780     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
4781     info.status_mask        = 1ull<<10 /* sync_bad */;
4782     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
4783     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
4784     info.flags              = 0;
4785     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4786     info.group_index        = 0;
4787     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4788     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4789     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4790     info.func               = __cvmx_error_display;
4791     info.user_info          = (long)
4792         "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
4793         "    state. Should never be set during normal operation\n";
4794     fail |= cvmx_error_add(&info);
4795
4796     /* CVMX_PCSX_INTX_REG(1,0) */
4797     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4798     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4799     info.status_mask        = 1ull<<2 /* an_err */;
4800     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4801     info.enable_mask        = 1ull<<2 /* an_err_en */;
4802     info.flags              = 0;
4803     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4804     info.group_index        = 1;
4805     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4806     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4807     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4808     info.func               = __cvmx_error_display;
4809     info.user_info          = (long)
4810         "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
4811     fail |= cvmx_error_add(&info);
4812
4813     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4814     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4815     info.status_mask        = 1ull<<3 /* txfifu */;
4816     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4817     info.enable_mask        = 1ull<<3 /* txfifu_en */;
4818     info.flags              = 0;
4819     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4820     info.group_index        = 1;
4821     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4822     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4823     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4824     info.func               = __cvmx_error_display;
4825     info.user_info          = (long)
4826         "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4827         "    condition\n";
4828     fail |= cvmx_error_add(&info);
4829
4830     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4831     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4832     info.status_mask        = 1ull<<4 /* txfifo */;
4833     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4834     info.enable_mask        = 1ull<<4 /* txfifo_en */;
4835     info.flags              = 0;
4836     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4837     info.group_index        = 1;
4838     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4839     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4840     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4841     info.func               = __cvmx_error_display;
4842     info.user_info          = (long)
4843         "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4844         "    condition\n";
4845     fail |= cvmx_error_add(&info);
4846
4847     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4848     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4849     info.status_mask        = 1ull<<5 /* txbad */;
4850     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4851     info.enable_mask        = 1ull<<5 /* txbad_en */;
4852     info.flags              = 0;
4853     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4854     info.group_index        = 1;
4855     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4856     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4857     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4858     info.func               = __cvmx_error_display;
4859     info.user_info          = (long)
4860         "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4861         "    state. Should never be set during normal operation\n";
4862     fail |= cvmx_error_add(&info);
4863
4864     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4865     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4866     info.status_mask        = 1ull<<7 /* rxbad */;
4867     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4868     info.enable_mask        = 1ull<<7 /* rxbad_en */;
4869     info.flags              = 0;
4870     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4871     info.group_index        = 1;
4872     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4873     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4874     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4875     info.func               = __cvmx_error_display;
4876     info.user_info          = (long)
4877         "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
4878         "    state. Should never be set during normal operation\n";
4879     fail |= cvmx_error_add(&info);
4880
4881     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4882     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4883     info.status_mask        = 1ull<<8 /* rxlock */;
4884     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4885     info.enable_mask        = 1ull<<8 /* rxlock_en */;
4886     info.flags              = 0;
4887     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4888     info.group_index        = 1;
4889     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4890     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4891     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4892     info.func               = __cvmx_error_display;
4893     info.user_info          = (long)
4894         "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4895         "    failure occurs\n"
4896         "    Cannot fire in loopback1 mode\n";
4897     fail |= cvmx_error_add(&info);
4898
4899     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4900     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4901     info.status_mask        = 1ull<<9 /* an_bad */;
4902     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4903     info.enable_mask        = 1ull<<9 /* an_bad_en */;
4904     info.flags              = 0;
4905     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4906     info.group_index        = 1;
4907     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4908     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4909     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4910     info.func               = __cvmx_error_display;
4911     info.user_info          = (long)
4912         "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
4913         "    state. Should never be set during normal operation\n";
4914     fail |= cvmx_error_add(&info);
4915
4916     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4917     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
4918     info.status_mask        = 1ull<<10 /* sync_bad */;
4919     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
4920     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
4921     info.flags              = 0;
4922     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4923     info.group_index        = 1;
4924     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4925     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4926     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4927     info.func               = __cvmx_error_display;
4928     info.user_info          = (long)
4929         "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
4930         "    state. Should never be set during normal operation\n";
4931     fail |= cvmx_error_add(&info);
4932
4933     /* CVMX_PCSX_INTX_REG(2,0) */
4934     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4935     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
4936     info.status_mask        = 1ull<<2 /* an_err */;
4937     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
4938     info.enable_mask        = 1ull<<2 /* an_err_en */;
4939     info.flags              = 0;
4940     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4941     info.group_index        = 2;
4942     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4943     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4944     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4945     info.func               = __cvmx_error_display;
4946     info.user_info          = (long)
4947         "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
4948     fail |= cvmx_error_add(&info);
4949
4950     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4951     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
4952     info.status_mask        = 1ull<<3 /* txfifu */;
4953     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
4954     info.enable_mask        = 1ull<<3 /* txfifu_en */;
4955     info.flags              = 0;
4956     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4957     info.group_index        = 2;
4958     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4959     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4960     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4961     info.func               = __cvmx_error_display;
4962     info.user_info          = (long)
4963         "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4964         "    condition\n";
4965     fail |= cvmx_error_add(&info);
4966
4967     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4968     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
4969     info.status_mask        = 1ull<<4 /* txfifo */;
4970     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
4971     info.enable_mask        = 1ull<<4 /* txfifo_en */;
4972     info.flags              = 0;
4973     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4974     info.group_index        = 2;
4975     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4976     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4977     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4978     info.func               = __cvmx_error_display;
4979     info.user_info          = (long)
4980         "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4981         "    condition\n";
4982     fail |= cvmx_error_add(&info);
4983
4984     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4985     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
4986     info.status_mask        = 1ull<<5 /* txbad */;
4987     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
4988     info.enable_mask        = 1ull<<5 /* txbad_en */;
4989     info.flags              = 0;
4990     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4991     info.group_index        = 2;
4992     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4993     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4994     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4995     info.func               = __cvmx_error_display;
4996     info.user_info          = (long)
4997         "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4998         "    state. Should never be set during normal operation\n";
4999     fail |= cvmx_error_add(&info);
5000
5001     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5002     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5003     info.status_mask        = 1ull<<7 /* rxbad */;
5004     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5005     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5006     info.flags              = 0;
5007     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5008     info.group_index        = 2;
5009     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5010     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5011     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5012     info.func               = __cvmx_error_display;
5013     info.user_info          = (long)
5014         "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5015         "    state. Should never be set during normal operation\n";
5016     fail |= cvmx_error_add(&info);
5017
5018     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5019     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5020     info.status_mask        = 1ull<<8 /* rxlock */;
5021     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5022     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5023     info.flags              = 0;
5024     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5025     info.group_index        = 2;
5026     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5027     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5028     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5029     info.func               = __cvmx_error_display;
5030     info.user_info          = (long)
5031         "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5032         "    failure occurs\n"
5033         "    Cannot fire in loopback1 mode\n";
5034     fail |= cvmx_error_add(&info);
5035
5036     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5037     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5038     info.status_mask        = 1ull<<9 /* an_bad */;
5039     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5040     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5041     info.flags              = 0;
5042     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5043     info.group_index        = 2;
5044     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5045     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5046     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5047     info.func               = __cvmx_error_display;
5048     info.user_info          = (long)
5049         "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5050         "    state. Should never be set during normal operation\n";
5051     fail |= cvmx_error_add(&info);
5052
5053     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5054     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5055     info.status_mask        = 1ull<<10 /* sync_bad */;
5056     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5057     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5058     info.flags              = 0;
5059     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5060     info.group_index        = 2;
5061     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5062     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5063     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5064     info.func               = __cvmx_error_display;
5065     info.user_info          = (long)
5066         "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5067         "    state. Should never be set during normal operation\n";
5068     fail |= cvmx_error_add(&info);
5069
5070     /* CVMX_PCSX_INTX_REG(3,0) */
5071     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5072     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5073     info.status_mask        = 1ull<<2 /* an_err */;
5074     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5075     info.enable_mask        = 1ull<<2 /* an_err_en */;
5076     info.flags              = 0;
5077     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5078     info.group_index        = 3;
5079     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5080     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5081     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5082     info.func               = __cvmx_error_display;
5083     info.user_info          = (long)
5084         "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5085     fail |= cvmx_error_add(&info);
5086
5087     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5088     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5089     info.status_mask        = 1ull<<3 /* txfifu */;
5090     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5091     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5092     info.flags              = 0;
5093     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5094     info.group_index        = 3;
5095     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5096     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5097     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5098     info.func               = __cvmx_error_display;
5099     info.user_info          = (long)
5100         "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5101         "    condition\n";
5102     fail |= cvmx_error_add(&info);
5103
5104     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5105     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5106     info.status_mask        = 1ull<<4 /* txfifo */;
5107     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5108     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5109     info.flags              = 0;
5110     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5111     info.group_index        = 3;
5112     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5113     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5114     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5115     info.func               = __cvmx_error_display;
5116     info.user_info          = (long)
5117         "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5118         "    condition\n";
5119     fail |= cvmx_error_add(&info);
5120
5121     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5122     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5123     info.status_mask        = 1ull<<5 /* txbad */;
5124     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5125     info.enable_mask        = 1ull<<5 /* txbad_en */;
5126     info.flags              = 0;
5127     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5128     info.group_index        = 3;
5129     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5130     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5131     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5132     info.func               = __cvmx_error_display;
5133     info.user_info          = (long)
5134         "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5135         "    state. Should never be set during normal operation\n";
5136     fail |= cvmx_error_add(&info);
5137
5138     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5139     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5140     info.status_mask        = 1ull<<7 /* rxbad */;
5141     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5142     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5143     info.flags              = 0;
5144     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5145     info.group_index        = 3;
5146     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5147     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5148     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5149     info.func               = __cvmx_error_display;
5150     info.user_info          = (long)
5151         "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5152         "    state. Should never be set during normal operation\n";
5153     fail |= cvmx_error_add(&info);
5154
5155     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5156     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5157     info.status_mask        = 1ull<<8 /* rxlock */;
5158     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5159     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5160     info.flags              = 0;
5161     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5162     info.group_index        = 3;
5163     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5164     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5165     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5166     info.func               = __cvmx_error_display;
5167     info.user_info          = (long)
5168         "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5169         "    failure occurs\n"
5170         "    Cannot fire in loopback1 mode\n";
5171     fail |= cvmx_error_add(&info);
5172
5173     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5174     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5175     info.status_mask        = 1ull<<9 /* an_bad */;
5176     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5177     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5178     info.flags              = 0;
5179     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5180     info.group_index        = 3;
5181     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5182     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5183     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5184     info.func               = __cvmx_error_display;
5185     info.user_info          = (long)
5186         "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5187         "    state. Should never be set during normal operation\n";
5188     fail |= cvmx_error_add(&info);
5189
5190     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5191     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
5192     info.status_mask        = 1ull<<10 /* sync_bad */;
5193     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
5194     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5195     info.flags              = 0;
5196     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5197     info.group_index        = 3;
5198     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5199     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5200     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5201     info.func               = __cvmx_error_display;
5202     info.user_info          = (long)
5203         "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5204         "    state. Should never be set during normal operation\n";
5205     fail |= cvmx_error_add(&info);
5206
5207     /* CVMX_PCSXX_INT_REG(0) */
5208     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5209     info.status_addr        = CVMX_PCSXX_INT_REG(0);
5210     info.status_mask        = 1ull<<0 /* txflt */;
5211     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
5212     info.enable_mask        = 1ull<<0 /* txflt_en */;
5213     info.flags              = 0;
5214     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5215     info.group_index        = 0;
5216     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5217     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5218     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5219     info.func               = __cvmx_error_display;
5220     info.user_info          = (long)
5221         "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
5222     fail |= cvmx_error_add(&info);
5223
5224     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5225     info.status_addr        = CVMX_PCSXX_INT_REG(0);
5226     info.status_mask        = 1ull<<1 /* rxbad */;
5227     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
5228     info.enable_mask        = 1ull<<1 /* rxbad_en */;
5229     info.flags              = 0;
5230     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5231     info.group_index        = 0;
5232     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5233     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5234     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5235     info.func               = __cvmx_error_display;
5236     info.user_info          = (long)
5237         "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
5238     fail |= cvmx_error_add(&info);
5239
5240     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5241     info.status_addr        = CVMX_PCSXX_INT_REG(0);
5242     info.status_mask        = 1ull<<2 /* rxsynbad */;
5243     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
5244     info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
5245     info.flags              = 0;
5246     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5247     info.group_index        = 0;
5248     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5249     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5250     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5251     info.func               = __cvmx_error_display;
5252     info.user_info          = (long)
5253         "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
5254         "    in one of the 4 xaui lanes\n";
5255     fail |= cvmx_error_add(&info);
5256
5257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5258     info.status_addr        = CVMX_PCSXX_INT_REG(0);
5259     info.status_mask        = 1ull<<4 /* synlos */;
5260     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
5261     info.enable_mask        = 1ull<<4 /* synlos_en */;
5262     info.flags              = 0;
5263     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5264     info.group_index        = 0;
5265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5266     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5267     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5268     info.func               = __cvmx_error_display;
5269     info.user_info          = (long)
5270         "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
5271     fail |= cvmx_error_add(&info);
5272
5273     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5274     info.status_addr        = CVMX_PCSXX_INT_REG(0);
5275     info.status_mask        = 1ull<<5 /* algnlos */;
5276     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
5277     info.enable_mask        = 1ull<<5 /* algnlos_en */;
5278     info.flags              = 0;
5279     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5280     info.group_index        = 0;
5281     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5282     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5283     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5284     info.func               = __cvmx_error_display;
5285     info.user_info          = (long)
5286         "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
5287     fail |= cvmx_error_add(&info);
5288
5289     /* CVMX_PIP_INT_REG */
5290     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5291     info.status_addr        = CVMX_PIP_INT_REG;
5292     info.status_mask        = 1ull<<3 /* prtnxa */;
5293     info.enable_addr        = CVMX_PIP_INT_EN;
5294     info.enable_mask        = 1ull<<3 /* prtnxa */;
5295     info.flags              = 0;
5296     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5297     info.group_index        = 0;
5298     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5299     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5300     info.parent.status_mask = 1ull<<20 /* pip */;
5301     info.func               = __cvmx_error_display;
5302     info.user_info          = (long)
5303         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
5304     fail |= cvmx_error_add(&info);
5305
5306     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5307     info.status_addr        = CVMX_PIP_INT_REG;
5308     info.status_mask        = 1ull<<4 /* badtag */;
5309     info.enable_addr        = CVMX_PIP_INT_EN;
5310     info.enable_mask        = 1ull<<4 /* badtag */;
5311     info.flags              = 0;
5312     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5313     info.group_index        = 0;
5314     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5315     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5316     info.parent.status_mask = 1ull<<20 /* pip */;
5317     info.func               = __cvmx_error_display;
5318     info.user_info          = (long)
5319         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
5320     fail |= cvmx_error_add(&info);
5321
5322     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5323     info.status_addr        = CVMX_PIP_INT_REG;
5324     info.status_mask        = 1ull<<5 /* skprunt */;
5325     info.enable_addr        = CVMX_PIP_INT_EN;
5326     info.enable_mask        = 1ull<<5 /* skprunt */;
5327     info.flags              = 0;
5328     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5329     info.group_index        = 0;
5330     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5331     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5332     info.parent.status_mask = 1ull<<20 /* pip */;
5333     info.func               = __cvmx_error_display;
5334     info.user_info          = (long)
5335         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
5336         "    This interrupt can occur with received PARTIAL\n"
5337         "    packets that are truncated to SKIP bytes or\n"
5338         "    smaller.\n";
5339     fail |= cvmx_error_add(&info);
5340
5341     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5342     info.status_addr        = CVMX_PIP_INT_REG;
5343     info.status_mask        = 1ull<<6 /* todoovr */;
5344     info.enable_addr        = CVMX_PIP_INT_EN;
5345     info.enable_mask        = 1ull<<6 /* todoovr */;
5346     info.flags              = 0;
5347     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5348     info.group_index        = 0;
5349     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5350     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5351     info.parent.status_mask = 1ull<<20 /* pip */;
5352     info.func               = __cvmx_error_display;
5353     info.user_info          = (long)
5354         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
5355     fail |= cvmx_error_add(&info);
5356
5357     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5358     info.status_addr        = CVMX_PIP_INT_REG;
5359     info.status_mask        = 1ull<<7 /* feperr */;
5360     info.enable_addr        = CVMX_PIP_INT_EN;
5361     info.enable_mask        = 1ull<<7 /* feperr */;
5362     info.flags              = 0;
5363     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5364     info.group_index        = 0;
5365     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5366     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5367     info.parent.status_mask = 1ull<<20 /* pip */;
5368     info.func               = __cvmx_error_display;
5369     info.user_info          = (long)
5370         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
5371     fail |= cvmx_error_add(&info);
5372
5373     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5374     info.status_addr        = CVMX_PIP_INT_REG;
5375     info.status_mask        = 1ull<<8 /* beperr */;
5376     info.enable_addr        = CVMX_PIP_INT_EN;
5377     info.enable_mask        = 1ull<<8 /* beperr */;
5378     info.flags              = 0;
5379     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5380     info.group_index        = 0;
5381     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5382     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5383     info.parent.status_mask = 1ull<<20 /* pip */;
5384     info.func               = __cvmx_error_display;
5385     info.user_info          = (long)
5386         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
5387     fail |= cvmx_error_add(&info);
5388
5389     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5390     info.status_addr        = CVMX_PIP_INT_REG;
5391     info.status_mask        = 1ull<<12 /* punyerr */;
5392     info.enable_addr        = CVMX_PIP_INT_EN;
5393     info.enable_mask        = 1ull<<12 /* punyerr */;
5394     info.flags              = 0;
5395     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5396     info.group_index        = 0;
5397     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5398     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5399     info.parent.status_mask = 1ull<<20 /* pip */;
5400     info.func               = __cvmx_error_display;
5401     info.user_info          = (long)
5402         "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
5403         "    stripping in IPD is enable\n";
5404     fail |= cvmx_error_add(&info);
5405
5406     /* CVMX_FPA_INT_SUM */
5407     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5408     info.status_addr        = CVMX_FPA_INT_SUM;
5409     info.status_mask        = 1ull<<0 /* fed0_sbe */;
5410     info.enable_addr        = CVMX_FPA_INT_ENB;
5411     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
5412     info.flags              = 0;
5413     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5414     info.group_index        = 0;
5415     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5416     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5417     info.parent.status_mask = 1ull<<5 /* fpa */;
5418     info.func               = __cvmx_error_display;
5419     info.user_info          = (long)
5420         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
5421     fail |= cvmx_error_add(&info);
5422
5423     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5424     info.status_addr        = CVMX_FPA_INT_SUM;
5425     info.status_mask        = 1ull<<1 /* fed0_dbe */;
5426     info.enable_addr        = CVMX_FPA_INT_ENB;
5427     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
5428     info.flags              = 0;
5429     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5430     info.group_index        = 0;
5431     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5432     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5433     info.parent.status_mask = 1ull<<5 /* fpa */;
5434     info.func               = __cvmx_error_display;
5435     info.user_info          = (long)
5436         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
5437     fail |= cvmx_error_add(&info);
5438
5439     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5440     info.status_addr        = CVMX_FPA_INT_SUM;
5441     info.status_mask        = 1ull<<2 /* fed1_sbe */;
5442     info.enable_addr        = CVMX_FPA_INT_ENB;
5443     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
5444     info.flags              = 0;
5445     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5446     info.group_index        = 0;
5447     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5448     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5449     info.parent.status_mask = 1ull<<5 /* fpa */;
5450     info.func               = __cvmx_error_display;
5451     info.user_info          = (long)
5452         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
5453     fail |= cvmx_error_add(&info);
5454
5455     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5456     info.status_addr        = CVMX_FPA_INT_SUM;
5457     info.status_mask        = 1ull<<3 /* fed1_dbe */;
5458     info.enable_addr        = CVMX_FPA_INT_ENB;
5459     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
5460     info.flags              = 0;
5461     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5462     info.group_index        = 0;
5463     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5464     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5465     info.parent.status_mask = 1ull<<5 /* fpa */;
5466     info.func               = __cvmx_error_display;
5467     info.user_info          = (long)
5468         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
5469     fail |= cvmx_error_add(&info);
5470
5471     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5472     info.status_addr        = CVMX_FPA_INT_SUM;
5473     info.status_mask        = 1ull<<4 /* q0_und */;
5474     info.enable_addr        = CVMX_FPA_INT_ENB;
5475     info.enable_mask        = 1ull<<4 /* q0_und */;
5476     info.flags              = 0;
5477     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5478     info.group_index        = 0;
5479     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5480     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5481     info.parent.status_mask = 1ull<<5 /* fpa */;
5482     info.func               = __cvmx_error_display;
5483     info.user_info          = (long)
5484         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
5485         "    negative.\n";
5486     fail |= cvmx_error_add(&info);
5487
5488     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5489     info.status_addr        = CVMX_FPA_INT_SUM;
5490     info.status_mask        = 1ull<<5 /* q0_coff */;
5491     info.enable_addr        = CVMX_FPA_INT_ENB;
5492     info.enable_mask        = 1ull<<5 /* q0_coff */;
5493     info.flags              = 0;
5494     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5495     info.group_index        = 0;
5496     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5497     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5498     info.parent.status_mask = 1ull<<5 /* fpa */;
5499     info.func               = __cvmx_error_display;
5500     info.user_info          = (long)
5501         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
5502         "    the count available is greater than pointers\n"
5503         "    present in the FPA.\n";
5504     fail |= cvmx_error_add(&info);
5505
5506     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5507     info.status_addr        = CVMX_FPA_INT_SUM;
5508     info.status_mask        = 1ull<<6 /* q0_perr */;
5509     info.enable_addr        = CVMX_FPA_INT_ENB;
5510     info.enable_mask        = 1ull<<6 /* q0_perr */;
5511     info.flags              = 0;
5512     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5513     info.group_index        = 0;
5514     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5515     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5516     info.parent.status_mask = 1ull<<5 /* fpa */;
5517     info.func               = __cvmx_error_display;
5518     info.user_info          = (long)
5519         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
5520         "    the L2C does not have the FPA owner ship bit set.\n";
5521     fail |= cvmx_error_add(&info);
5522
5523     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5524     info.status_addr        = CVMX_FPA_INT_SUM;
5525     info.status_mask        = 1ull<<7 /* q1_und */;
5526     info.enable_addr        = CVMX_FPA_INT_ENB;
5527     info.enable_mask        = 1ull<<7 /* q1_und */;
5528     info.flags              = 0;
5529     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5530     info.group_index        = 0;
5531     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5532     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5533     info.parent.status_mask = 1ull<<5 /* fpa */;
5534     info.func               = __cvmx_error_display;
5535     info.user_info          = (long)
5536         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
5537         "    negative.\n";
5538     fail |= cvmx_error_add(&info);
5539
5540     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5541     info.status_addr        = CVMX_FPA_INT_SUM;
5542     info.status_mask        = 1ull<<8 /* q1_coff */;
5543     info.enable_addr        = CVMX_FPA_INT_ENB;
5544     info.enable_mask        = 1ull<<8 /* q1_coff */;
5545     info.flags              = 0;
5546     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5547     info.group_index        = 0;
5548     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5549     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5550     info.parent.status_mask = 1ull<<5 /* fpa */;
5551     info.func               = __cvmx_error_display;
5552     info.user_info          = (long)
5553         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
5554         "    the count available is greater than pointers\n"
5555         "    present in the FPA.\n";
5556     fail |= cvmx_error_add(&info);
5557
5558     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5559     info.status_addr        = CVMX_FPA_INT_SUM;
5560     info.status_mask        = 1ull<<9 /* q1_perr */;
5561     info.enable_addr        = CVMX_FPA_INT_ENB;
5562     info.enable_mask        = 1ull<<9 /* q1_perr */;
5563     info.flags              = 0;
5564     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5565     info.group_index        = 0;
5566     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5567     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5568     info.parent.status_mask = 1ull<<5 /* fpa */;
5569     info.func               = __cvmx_error_display;
5570     info.user_info          = (long)
5571         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
5572         "    the L2C does not have the FPA owner ship bit set.\n";
5573     fail |= cvmx_error_add(&info);
5574
5575     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5576     info.status_addr        = CVMX_FPA_INT_SUM;
5577     info.status_mask        = 1ull<<10 /* q2_und */;
5578     info.enable_addr        = CVMX_FPA_INT_ENB;
5579     info.enable_mask        = 1ull<<10 /* q2_und */;
5580     info.flags              = 0;
5581     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5582     info.group_index        = 0;
5583     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5584     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5585     info.parent.status_mask = 1ull<<5 /* fpa */;
5586     info.func               = __cvmx_error_display;
5587     info.user_info          = (long)
5588         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
5589         "    negative.\n";
5590     fail |= cvmx_error_add(&info);
5591
5592     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5593     info.status_addr        = CVMX_FPA_INT_SUM;
5594     info.status_mask        = 1ull<<11 /* q2_coff */;
5595     info.enable_addr        = CVMX_FPA_INT_ENB;
5596     info.enable_mask        = 1ull<<11 /* q2_coff */;
5597     info.flags              = 0;
5598     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5599     info.group_index        = 0;
5600     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5601     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5602     info.parent.status_mask = 1ull<<5 /* fpa */;
5603     info.func               = __cvmx_error_display;
5604     info.user_info          = (long)
5605         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
5606         "    the count available is greater than than pointers\n"
5607         "    present in the FPA.\n";
5608     fail |= cvmx_error_add(&info);
5609
5610     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5611     info.status_addr        = CVMX_FPA_INT_SUM;
5612     info.status_mask        = 1ull<<12 /* q2_perr */;
5613     info.enable_addr        = CVMX_FPA_INT_ENB;
5614     info.enable_mask        = 1ull<<12 /* q2_perr */;
5615     info.flags              = 0;
5616     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5617     info.group_index        = 0;
5618     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5619     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5620     info.parent.status_mask = 1ull<<5 /* fpa */;
5621     info.func               = __cvmx_error_display;
5622     info.user_info          = (long)
5623         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
5624         "    the L2C does not have the FPA owner ship bit set.\n";
5625     fail |= cvmx_error_add(&info);
5626
5627     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5628     info.status_addr        = CVMX_FPA_INT_SUM;
5629     info.status_mask        = 1ull<<13 /* q3_und */;
5630     info.enable_addr        = CVMX_FPA_INT_ENB;
5631     info.enable_mask        = 1ull<<13 /* q3_und */;
5632     info.flags              = 0;
5633     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5634     info.group_index        = 0;
5635     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5636     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5637     info.parent.status_mask = 1ull<<5 /* fpa */;
5638     info.func               = __cvmx_error_display;
5639     info.user_info          = (long)
5640         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
5641         "    negative.\n";
5642     fail |= cvmx_error_add(&info);
5643
5644     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5645     info.status_addr        = CVMX_FPA_INT_SUM;
5646     info.status_mask        = 1ull<<14 /* q3_coff */;
5647     info.enable_addr        = CVMX_FPA_INT_ENB;
5648     info.enable_mask        = 1ull<<14 /* q3_coff */;
5649     info.flags              = 0;
5650     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5651     info.group_index        = 0;
5652     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5653     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5654     info.parent.status_mask = 1ull<<5 /* fpa */;
5655     info.func               = __cvmx_error_display;
5656     info.user_info          = (long)
5657         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
5658         "    the count available is greater than than pointers\n"
5659         "    present in the FPA.\n";
5660     fail |= cvmx_error_add(&info);
5661
5662     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5663     info.status_addr        = CVMX_FPA_INT_SUM;
5664     info.status_mask        = 1ull<<15 /* q3_perr */;
5665     info.enable_addr        = CVMX_FPA_INT_ENB;
5666     info.enable_mask        = 1ull<<15 /* q3_perr */;
5667     info.flags              = 0;
5668     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5669     info.group_index        = 0;
5670     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5671     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5672     info.parent.status_mask = 1ull<<5 /* fpa */;
5673     info.func               = __cvmx_error_display;
5674     info.user_info          = (long)
5675         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
5676         "    the L2C does not have the FPA owner ship bit set.\n";
5677     fail |= cvmx_error_add(&info);
5678
5679     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5680     info.status_addr        = CVMX_FPA_INT_SUM;
5681     info.status_mask        = 1ull<<16 /* q4_und */;
5682     info.enable_addr        = CVMX_FPA_INT_ENB;
5683     info.enable_mask        = 1ull<<16 /* q4_und */;
5684     info.flags              = 0;
5685     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5686     info.group_index        = 0;
5687     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5688     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5689     info.parent.status_mask = 1ull<<5 /* fpa */;
5690     info.func               = __cvmx_error_display;
5691     info.user_info          = (long)
5692         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
5693         "    negative.\n";
5694     fail |= cvmx_error_add(&info);
5695
5696     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5697     info.status_addr        = CVMX_FPA_INT_SUM;
5698     info.status_mask        = 1ull<<17 /* q4_coff */;
5699     info.enable_addr        = CVMX_FPA_INT_ENB;
5700     info.enable_mask        = 1ull<<17 /* q4_coff */;
5701     info.flags              = 0;
5702     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5703     info.group_index        = 0;
5704     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5705     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5706     info.parent.status_mask = 1ull<<5 /* fpa */;
5707     info.func               = __cvmx_error_display;
5708     info.user_info          = (long)
5709         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
5710         "    the count available is greater than than pointers\n"
5711         "    present in the FPA.\n";
5712     fail |= cvmx_error_add(&info);
5713
5714     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5715     info.status_addr        = CVMX_FPA_INT_SUM;
5716     info.status_mask        = 1ull<<18 /* q4_perr */;
5717     info.enable_addr        = CVMX_FPA_INT_ENB;
5718     info.enable_mask        = 1ull<<18 /* q4_perr */;
5719     info.flags              = 0;
5720     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5721     info.group_index        = 0;
5722     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5723     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5724     info.parent.status_mask = 1ull<<5 /* fpa */;
5725     info.func               = __cvmx_error_display;
5726     info.user_info          = (long)
5727         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
5728         "    the L2C does not have the FPA owner ship bit set.\n";
5729     fail |= cvmx_error_add(&info);
5730
5731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5732     info.status_addr        = CVMX_FPA_INT_SUM;
5733     info.status_mask        = 1ull<<19 /* q5_und */;
5734     info.enable_addr        = CVMX_FPA_INT_ENB;
5735     info.enable_mask        = 1ull<<19 /* q5_und */;
5736     info.flags              = 0;
5737     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5738     info.group_index        = 0;
5739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5740     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5741     info.parent.status_mask = 1ull<<5 /* fpa */;
5742     info.func               = __cvmx_error_display;
5743     info.user_info          = (long)
5744         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
5745         "    negative.\n";
5746     fail |= cvmx_error_add(&info);
5747
5748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5749     info.status_addr        = CVMX_FPA_INT_SUM;
5750     info.status_mask        = 1ull<<20 /* q5_coff */;
5751     info.enable_addr        = CVMX_FPA_INT_ENB;
5752     info.enable_mask        = 1ull<<20 /* q5_coff */;
5753     info.flags              = 0;
5754     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5755     info.group_index        = 0;
5756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5757     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5758     info.parent.status_mask = 1ull<<5 /* fpa */;
5759     info.func               = __cvmx_error_display;
5760     info.user_info          = (long)
5761         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
5762         "    the count available is greater than than pointers\n"
5763         "    present in the FPA.\n";
5764     fail |= cvmx_error_add(&info);
5765
5766     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5767     info.status_addr        = CVMX_FPA_INT_SUM;
5768     info.status_mask        = 1ull<<21 /* q5_perr */;
5769     info.enable_addr        = CVMX_FPA_INT_ENB;
5770     info.enable_mask        = 1ull<<21 /* q5_perr */;
5771     info.flags              = 0;
5772     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5773     info.group_index        = 0;
5774     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5775     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5776     info.parent.status_mask = 1ull<<5 /* fpa */;
5777     info.func               = __cvmx_error_display;
5778     info.user_info          = (long)
5779         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
5780         "    the L2C does not have the FPA owner ship bit set.\n";
5781     fail |= cvmx_error_add(&info);
5782
5783     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5784     info.status_addr        = CVMX_FPA_INT_SUM;
5785     info.status_mask        = 1ull<<22 /* q6_und */;
5786     info.enable_addr        = CVMX_FPA_INT_ENB;
5787     info.enable_mask        = 1ull<<22 /* q6_und */;
5788     info.flags              = 0;
5789     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5790     info.group_index        = 0;
5791     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5792     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5793     info.parent.status_mask = 1ull<<5 /* fpa */;
5794     info.func               = __cvmx_error_display;
5795     info.user_info          = (long)
5796         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
5797         "    negative.\n";
5798     fail |= cvmx_error_add(&info);
5799
5800     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5801     info.status_addr        = CVMX_FPA_INT_SUM;
5802     info.status_mask        = 1ull<<23 /* q6_coff */;
5803     info.enable_addr        = CVMX_FPA_INT_ENB;
5804     info.enable_mask        = 1ull<<23 /* q6_coff */;
5805     info.flags              = 0;
5806     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5807     info.group_index        = 0;
5808     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5809     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5810     info.parent.status_mask = 1ull<<5 /* fpa */;
5811     info.func               = __cvmx_error_display;
5812     info.user_info          = (long)
5813         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
5814         "    the count available is greater than than pointers\n"
5815         "    present in the FPA.\n";
5816     fail |= cvmx_error_add(&info);
5817
5818     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5819     info.status_addr        = CVMX_FPA_INT_SUM;
5820     info.status_mask        = 1ull<<24 /* q6_perr */;
5821     info.enable_addr        = CVMX_FPA_INT_ENB;
5822     info.enable_mask        = 1ull<<24 /* q6_perr */;
5823     info.flags              = 0;
5824     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5825     info.group_index        = 0;
5826     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5827     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5828     info.parent.status_mask = 1ull<<5 /* fpa */;
5829     info.func               = __cvmx_error_display;
5830     info.user_info          = (long)
5831         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
5832         "    the L2C does not have the FPA owner ship bit set.\n";
5833     fail |= cvmx_error_add(&info);
5834
5835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5836     info.status_addr        = CVMX_FPA_INT_SUM;
5837     info.status_mask        = 1ull<<25 /* q7_und */;
5838     info.enable_addr        = CVMX_FPA_INT_ENB;
5839     info.enable_mask        = 1ull<<25 /* q7_und */;
5840     info.flags              = 0;
5841     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5842     info.group_index        = 0;
5843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5844     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5845     info.parent.status_mask = 1ull<<5 /* fpa */;
5846     info.func               = __cvmx_error_display;
5847     info.user_info          = (long)
5848         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
5849         "    negative.\n";
5850     fail |= cvmx_error_add(&info);
5851
5852     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5853     info.status_addr        = CVMX_FPA_INT_SUM;
5854     info.status_mask        = 1ull<<26 /* q7_coff */;
5855     info.enable_addr        = CVMX_FPA_INT_ENB;
5856     info.enable_mask        = 1ull<<26 /* q7_coff */;
5857     info.flags              = 0;
5858     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5859     info.group_index        = 0;
5860     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5861     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5862     info.parent.status_mask = 1ull<<5 /* fpa */;
5863     info.func               = __cvmx_error_display;
5864     info.user_info          = (long)
5865         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
5866         "    the count available is greater than than pointers\n"
5867         "    present in the FPA.\n";
5868     fail |= cvmx_error_add(&info);
5869
5870     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5871     info.status_addr        = CVMX_FPA_INT_SUM;
5872     info.status_mask        = 1ull<<27 /* q7_perr */;
5873     info.enable_addr        = CVMX_FPA_INT_ENB;
5874     info.enable_mask        = 1ull<<27 /* q7_perr */;
5875     info.flags              = 0;
5876     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5877     info.group_index        = 0;
5878     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5879     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5880     info.parent.status_mask = 1ull<<5 /* fpa */;
5881     info.func               = __cvmx_error_display;
5882     info.user_info          = (long)
5883         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
5884         "    the L2C does not have the FPA owner ship bit set.\n";
5885     fail |= cvmx_error_add(&info);
5886
5887     /* CVMX_LMCX_MEM_CFG0(0) */
5888     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5889     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
5890     info.status_mask        = 0xfull<<21 /* sec_err */;
5891     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
5892     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
5893     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
5894     info.group              = CVMX_ERROR_GROUP_LMC;
5895     info.group_index        = 0;
5896     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5897     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5898     info.parent.status_mask = 1ull<<17 /* lmc0 */;
5899     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
5900     info.user_info          = (long)
5901         "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
5902         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
5903         "    [0] corresponds to DQ[63:0]_c0_p0\n"
5904         "    [1] corresponds to DQ[63:0]_c0_p1\n"
5905         "    [2] corresponds to DQ[63:0]_c1_p0\n"
5906         "    [3] corresponds to DQ[63:0]_c1_p1\n"
5907         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
5908         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
5909         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
5910         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
5911         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
5912         "      where _cC_pP denotes cycle C and phase P\n"
5913         "    Write of 1 will clear the corresponding error bit\n";
5914     fail |= cvmx_error_add(&info);
5915
5916     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5917     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
5918     info.status_mask        = 0xfull<<25 /* ded_err */;
5919     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
5920     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
5921     info.flags              = 0;
5922     info.group              = CVMX_ERROR_GROUP_LMC;
5923     info.group_index        = 0;
5924     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5925     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5926     info.parent.status_mask = 1ull<<17 /* lmc0 */;
5927     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
5928     info.user_info          = (long)
5929         "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
5930         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
5931         "    [0] corresponds to DQ[63:0]_c0_p0\n"
5932         "    [1] corresponds to DQ[63:0]_c0_p1\n"
5933         "    [2] corresponds to DQ[63:0]_c1_p0\n"
5934         "    [3] corresponds to DQ[63:0]_c1_p1\n"
5935         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
5936         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
5937         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
5938         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
5939         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
5940         "      where _cC_pP denotes cycle C and phase P\n"
5941         "    Write of 1 will clear the corresponding error bit\n";
5942     fail |= cvmx_error_add(&info);
5943
5944     /* CVMX_IOB_INT_SUM */
5945     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5946     info.status_addr        = CVMX_IOB_INT_SUM;
5947     info.status_mask        = 1ull<<0 /* np_sop */;
5948     info.enable_addr        = CVMX_IOB_INT_ENB;
5949     info.enable_mask        = 1ull<<0 /* np_sop */;
5950     info.flags              = 0;
5951     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5952     info.group_index        = 0;
5953     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5954     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5955     info.parent.status_mask = 1ull<<30 /* iob */;
5956     info.func               = __cvmx_error_display;
5957     info.user_info          = (long)
5958         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
5959         "    port for a non-passthrough packet.\n"
5960         "    The first detected error associated with bits [5:0]\n"
5961         "    of this register will only be set here. A new bit\n"
5962         "    can be set when the previous reported bit is cleared.\n";
5963     fail |= cvmx_error_add(&info);
5964
5965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5966     info.status_addr        = CVMX_IOB_INT_SUM;
5967     info.status_mask        = 1ull<<1 /* np_eop */;
5968     info.enable_addr        = CVMX_IOB_INT_ENB;
5969     info.enable_mask        = 1ull<<1 /* np_eop */;
5970     info.flags              = 0;
5971     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5972     info.group_index        = 0;
5973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5974     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5975     info.parent.status_mask = 1ull<<30 /* iob */;
5976     info.func               = __cvmx_error_display;
5977     info.user_info          = (long)
5978         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
5979         "    port for a non-passthrough packet.\n"
5980         "    The first detected error associated with bits [5:0]\n"
5981         "    of this register will only be set here. A new bit\n"
5982         "    can be set when the previous reported bit is cleared.\n";
5983     fail |= cvmx_error_add(&info);
5984
5985     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5986     info.status_addr        = CVMX_IOB_INT_SUM;
5987     info.status_mask        = 1ull<<2 /* p_sop */;
5988     info.enable_addr        = CVMX_IOB_INT_ENB;
5989     info.enable_mask        = 1ull<<2 /* p_sop */;
5990     info.flags              = 0;
5991     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5992     info.group_index        = 0;
5993     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5994     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5995     info.parent.status_mask = 1ull<<30 /* iob */;
5996     info.func               = __cvmx_error_display;
5997     info.user_info          = (long)
5998         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
5999         "    port for a passthrough packet.\n"
6000         "    The first detected error associated with bits [5:0]\n"
6001         "    of this register will only be set here. A new bit\n"
6002         "    can be set when the previous reported bit is cleared.\n";
6003     fail |= cvmx_error_add(&info);
6004
6005     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6006     info.status_addr        = CVMX_IOB_INT_SUM;
6007     info.status_mask        = 1ull<<3 /* p_eop */;
6008     info.enable_addr        = CVMX_IOB_INT_ENB;
6009     info.enable_mask        = 1ull<<3 /* p_eop */;
6010     info.flags              = 0;
6011     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6012     info.group_index        = 0;
6013     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6014     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6015     info.parent.status_mask = 1ull<<30 /* iob */;
6016     info.func               = __cvmx_error_display;
6017     info.user_info          = (long)
6018         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
6019         "    port for a passthrough packet.\n"
6020         "    The first detected error associated with bits [5:0]\n"
6021         "    of this register will only be set here. A new bit\n"
6022         "    can be set when the previous reported bit is cleared.\n";
6023     fail |= cvmx_error_add(&info);
6024
6025     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6026     info.status_addr        = CVMX_IOB_INT_SUM;
6027     info.status_mask        = 1ull<<4 /* np_dat */;
6028     info.enable_addr        = CVMX_IOB_INT_ENB;
6029     info.enable_mask        = 1ull<<4 /* np_dat */;
6030     info.flags              = 0;
6031     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6032     info.group_index        = 0;
6033     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6034     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6035     info.parent.status_mask = 1ull<<30 /* iob */;
6036     info.func               = __cvmx_error_display;
6037     info.user_info          = (long)
6038         "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
6039         "    port for a non-passthrough packet.\n"
6040         "    The first detected error associated with bits [5:0]\n"
6041         "    of this register will only be set here. A new bit\n"
6042         "    can be set when the previous reported bit is cleared.\n";
6043     fail |= cvmx_error_add(&info);
6044
6045     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6046     info.status_addr        = CVMX_IOB_INT_SUM;
6047     info.status_mask        = 1ull<<5 /* p_dat */;
6048     info.enable_addr        = CVMX_IOB_INT_ENB;
6049     info.enable_mask        = 1ull<<5 /* p_dat */;
6050     info.flags              = 0;
6051     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6052     info.group_index        = 0;
6053     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6054     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6055     info.parent.status_mask = 1ull<<30 /* iob */;
6056     info.func               = __cvmx_error_display;
6057     info.user_info          = (long)
6058         "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
6059         "    port for a passthrough packet.\n"
6060         "    The first detected error associated with bits [5:0]\n"
6061         "    of this register will only be set here. A new bit\n"
6062         "    can be set when the previous reported bit is cleared.\n";
6063     fail |= cvmx_error_add(&info);
6064
6065     /* CVMX_USBNX_INT_SUM(0) */
6066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6067     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6068     info.status_mask        = 1ull<<0 /* pr_po_e */;
6069     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6070     info.enable_mask        = 1ull<<0 /* pr_po_e */;
6071     info.flags              = 0;
6072     info.group              = CVMX_ERROR_GROUP_USB;
6073     info.group_index        = 0;
6074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6075     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6076     info.parent.status_mask = 1ull<<13 /* usb */;
6077     info.func               = __cvmx_error_display;
6078     info.user_info          = (long)
6079         "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
6080     fail |= cvmx_error_add(&info);
6081
6082     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6083     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6084     info.status_mask        = 1ull<<1 /* pr_pu_f */;
6085     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6086     info.enable_mask        = 1ull<<1 /* pr_pu_f */;
6087     info.flags              = 0;
6088     info.group              = CVMX_ERROR_GROUP_USB;
6089     info.group_index        = 0;
6090     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6091     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6092     info.parent.status_mask = 1ull<<13 /* usb */;
6093     info.func               = __cvmx_error_display;
6094     info.user_info          = (long)
6095         "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
6096     fail |= cvmx_error_add(&info);
6097
6098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6099     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6100     info.status_mask        = 1ull<<2 /* nr_po_e */;
6101     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6102     info.enable_mask        = 1ull<<2 /* nr_po_e */;
6103     info.flags              = 0;
6104     info.group              = CVMX_ERROR_GROUP_USB;
6105     info.group_index        = 0;
6106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6107     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6108     info.parent.status_mask = 1ull<<13 /* usb */;
6109     info.func               = __cvmx_error_display;
6110     info.user_info          = (long)
6111         "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
6112     fail |= cvmx_error_add(&info);
6113
6114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6115     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6116     info.status_mask        = 1ull<<3 /* nr_pu_f */;
6117     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6118     info.enable_mask        = 1ull<<3 /* nr_pu_f */;
6119     info.flags              = 0;
6120     info.group              = CVMX_ERROR_GROUP_USB;
6121     info.group_index        = 0;
6122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6123     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6124     info.parent.status_mask = 1ull<<13 /* usb */;
6125     info.func               = __cvmx_error_display;
6126     info.user_info          = (long)
6127         "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
6128     fail |= cvmx_error_add(&info);
6129
6130     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6131     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6132     info.status_mask        = 1ull<<4 /* lr_po_e */;
6133     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6134     info.enable_mask        = 1ull<<4 /* lr_po_e */;
6135     info.flags              = 0;
6136     info.group              = CVMX_ERROR_GROUP_USB;
6137     info.group_index        = 0;
6138     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6139     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6140     info.parent.status_mask = 1ull<<13 /* usb */;
6141     info.func               = __cvmx_error_display;
6142     info.user_info          = (long)
6143         "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
6144     fail |= cvmx_error_add(&info);
6145
6146     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6147     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6148     info.status_mask        = 1ull<<5 /* lr_pu_f */;
6149     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6150     info.enable_mask        = 1ull<<5 /* lr_pu_f */;
6151     info.flags              = 0;
6152     info.group              = CVMX_ERROR_GROUP_USB;
6153     info.group_index        = 0;
6154     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6155     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6156     info.parent.status_mask = 1ull<<13 /* usb */;
6157     info.func               = __cvmx_error_display;
6158     info.user_info          = (long)
6159         "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
6160     fail |= cvmx_error_add(&info);
6161
6162     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6163     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6164     info.status_mask        = 1ull<<6 /* pt_po_e */;
6165     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6166     info.enable_mask        = 1ull<<6 /* pt_po_e */;
6167     info.flags              = 0;
6168     info.group              = CVMX_ERROR_GROUP_USB;
6169     info.group_index        = 0;
6170     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6171     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6172     info.parent.status_mask = 1ull<<13 /* usb */;
6173     info.func               = __cvmx_error_display;
6174     info.user_info          = (long)
6175         "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
6176     fail |= cvmx_error_add(&info);
6177
6178     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6179     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6180     info.status_mask        = 1ull<<7 /* pt_pu_f */;
6181     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6182     info.enable_mask        = 1ull<<7 /* pt_pu_f */;
6183     info.flags              = 0;
6184     info.group              = CVMX_ERROR_GROUP_USB;
6185     info.group_index        = 0;
6186     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6187     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6188     info.parent.status_mask = 1ull<<13 /* usb */;
6189     info.func               = __cvmx_error_display;
6190     info.user_info          = (long)
6191         "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
6192     fail |= cvmx_error_add(&info);
6193
6194     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6195     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6196     info.status_mask        = 1ull<<8 /* nt_po_e */;
6197     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6198     info.enable_mask        = 1ull<<8 /* nt_po_e */;
6199     info.flags              = 0;
6200     info.group              = CVMX_ERROR_GROUP_USB;
6201     info.group_index        = 0;
6202     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6203     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6204     info.parent.status_mask = 1ull<<13 /* usb */;
6205     info.func               = __cvmx_error_display;
6206     info.user_info          = (long)
6207         "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
6208     fail |= cvmx_error_add(&info);
6209
6210     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6211     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6212     info.status_mask        = 1ull<<9 /* nt_pu_f */;
6213     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6214     info.enable_mask        = 1ull<<9 /* nt_pu_f */;
6215     info.flags              = 0;
6216     info.group              = CVMX_ERROR_GROUP_USB;
6217     info.group_index        = 0;
6218     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6219     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6220     info.parent.status_mask = 1ull<<13 /* usb */;
6221     info.func               = __cvmx_error_display;
6222     info.user_info          = (long)
6223         "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
6224     fail |= cvmx_error_add(&info);
6225
6226     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6227     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6228     info.status_mask        = 1ull<<10 /* lt_po_e */;
6229     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6230     info.enable_mask        = 1ull<<10 /* lt_po_e */;
6231     info.flags              = 0;
6232     info.group              = CVMX_ERROR_GROUP_USB;
6233     info.group_index        = 0;
6234     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6235     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6236     info.parent.status_mask = 1ull<<13 /* usb */;
6237     info.func               = __cvmx_error_display;
6238     info.user_info          = (long)
6239         "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
6240     fail |= cvmx_error_add(&info);
6241
6242     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6243     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6244     info.status_mask        = 1ull<<11 /* lt_pu_f */;
6245     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6246     info.enable_mask        = 1ull<<11 /* lt_pu_f */;
6247     info.flags              = 0;
6248     info.group              = CVMX_ERROR_GROUP_USB;
6249     info.group_index        = 0;
6250     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6251     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6252     info.parent.status_mask = 1ull<<13 /* usb */;
6253     info.func               = __cvmx_error_display;
6254     info.user_info          = (long)
6255         "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
6256     fail |= cvmx_error_add(&info);
6257
6258     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6259     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6260     info.status_mask        = 1ull<<12 /* dcred_e */;
6261     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6262     info.enable_mask        = 1ull<<12 /* dcred_e */;
6263     info.flags              = 0;
6264     info.group              = CVMX_ERROR_GROUP_USB;
6265     info.group_index        = 0;
6266     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6267     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6268     info.parent.status_mask = 1ull<<13 /* usb */;
6269     info.func               = __cvmx_error_display;
6270     info.user_info          = (long)
6271         "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
6272     fail |= cvmx_error_add(&info);
6273
6274     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6275     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6276     info.status_mask        = 1ull<<13 /* dcred_f */;
6277     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6278     info.enable_mask        = 1ull<<13 /* dcred_f */;
6279     info.flags              = 0;
6280     info.group              = CVMX_ERROR_GROUP_USB;
6281     info.group_index        = 0;
6282     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6283     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6284     info.parent.status_mask = 1ull<<13 /* usb */;
6285     info.func               = __cvmx_error_display;
6286     info.user_info          = (long)
6287         "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
6288     fail |= cvmx_error_add(&info);
6289
6290     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6291     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6292     info.status_mask        = 1ull<<14 /* l2c_s_e */;
6293     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6294     info.enable_mask        = 1ull<<14 /* l2c_s_e */;
6295     info.flags              = 0;
6296     info.group              = CVMX_ERROR_GROUP_USB;
6297     info.group_index        = 0;
6298     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6299     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6300     info.parent.status_mask = 1ull<<13 /* usb */;
6301     info.func               = __cvmx_error_display;
6302     info.user_info          = (long)
6303         "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
6304     fail |= cvmx_error_add(&info);
6305
6306     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6307     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6308     info.status_mask        = 1ull<<15 /* l2c_a_f */;
6309     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6310     info.enable_mask        = 1ull<<15 /* l2c_a_f */;
6311     info.flags              = 0;
6312     info.group              = CVMX_ERROR_GROUP_USB;
6313     info.group_index        = 0;
6314     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6315     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6316     info.parent.status_mask = 1ull<<13 /* usb */;
6317     info.func               = __cvmx_error_display;
6318     info.user_info          = (long)
6319         "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
6320     fail |= cvmx_error_add(&info);
6321
6322     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6323     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6324     info.status_mask        = 1ull<<16 /* lt_fi_e */;
6325     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6326     info.enable_mask        = 1ull<<16 /* l2_fi_e */;
6327     info.flags              = 0;
6328     info.group              = CVMX_ERROR_GROUP_USB;
6329     info.group_index        = 0;
6330     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6331     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6332     info.parent.status_mask = 1ull<<13 /* usb */;
6333     info.func               = __cvmx_error_display;
6334     info.user_info          = (long)
6335         "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
6336     fail |= cvmx_error_add(&info);
6337
6338     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6339     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6340     info.status_mask        = 1ull<<17 /* lt_fi_f */;
6341     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6342     info.enable_mask        = 1ull<<17 /* l2_fi_f */;
6343     info.flags              = 0;
6344     info.group              = CVMX_ERROR_GROUP_USB;
6345     info.group_index        = 0;
6346     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6347     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6348     info.parent.status_mask = 1ull<<13 /* usb */;
6349     info.func               = __cvmx_error_display;
6350     info.user_info          = (long)
6351         "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
6352     fail |= cvmx_error_add(&info);
6353
6354     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6355     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6356     info.status_mask        = 1ull<<18 /* rg_fi_e */;
6357     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6358     info.enable_mask        = 1ull<<18 /* rg_fi_e */;
6359     info.flags              = 0;
6360     info.group              = CVMX_ERROR_GROUP_USB;
6361     info.group_index        = 0;
6362     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6363     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6364     info.parent.status_mask = 1ull<<13 /* usb */;
6365     info.func               = __cvmx_error_display;
6366     info.user_info          = (long)
6367         "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
6368     fail |= cvmx_error_add(&info);
6369
6370     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6371     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6372     info.status_mask        = 1ull<<19 /* rg_fi_f */;
6373     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6374     info.enable_mask        = 1ull<<19 /* rg_fi_f */;
6375     info.flags              = 0;
6376     info.group              = CVMX_ERROR_GROUP_USB;
6377     info.group_index        = 0;
6378     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6379     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6380     info.parent.status_mask = 1ull<<13 /* usb */;
6381     info.func               = __cvmx_error_display;
6382     info.user_info          = (long)
6383         "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
6384     fail |= cvmx_error_add(&info);
6385
6386     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6387     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6388     info.status_mask        = 1ull<<20 /* rq_q2_f */;
6389     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6390     info.enable_mask        = 1ull<<20 /* rq_q2_f */;
6391     info.flags              = 0;
6392     info.group              = CVMX_ERROR_GROUP_USB;
6393     info.group_index        = 0;
6394     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6395     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6396     info.parent.status_mask = 1ull<<13 /* usb */;
6397     info.func               = __cvmx_error_display;
6398     info.user_info          = (long)
6399         "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
6400     fail |= cvmx_error_add(&info);
6401
6402     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6403     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6404     info.status_mask        = 1ull<<21 /* rq_q2_e */;
6405     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6406     info.enable_mask        = 1ull<<21 /* rq_q2_e */;
6407     info.flags              = 0;
6408     info.group              = CVMX_ERROR_GROUP_USB;
6409     info.group_index        = 0;
6410     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6411     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6412     info.parent.status_mask = 1ull<<13 /* usb */;
6413     info.func               = __cvmx_error_display;
6414     info.user_info          = (long)
6415         "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
6416     fail |= cvmx_error_add(&info);
6417
6418     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6419     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6420     info.status_mask        = 1ull<<22 /* rq_q3_f */;
6421     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6422     info.enable_mask        = 1ull<<22 /* rq_q3_f */;
6423     info.flags              = 0;
6424     info.group              = CVMX_ERROR_GROUP_USB;
6425     info.group_index        = 0;
6426     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6427     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6428     info.parent.status_mask = 1ull<<13 /* usb */;
6429     info.func               = __cvmx_error_display;
6430     info.user_info          = (long)
6431         "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
6432     fail |= cvmx_error_add(&info);
6433
6434     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6435     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6436     info.status_mask        = 1ull<<23 /* rq_q3_e */;
6437     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6438     info.enable_mask        = 1ull<<23 /* rq_q3_e */;
6439     info.flags              = 0;
6440     info.group              = CVMX_ERROR_GROUP_USB;
6441     info.group_index        = 0;
6442     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6443     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6444     info.parent.status_mask = 1ull<<13 /* usb */;
6445     info.func               = __cvmx_error_display;
6446     info.user_info          = (long)
6447         "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
6448     fail |= cvmx_error_add(&info);
6449
6450     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6451     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6452     info.status_mask        = 1ull<<24 /* uod_pe */;
6453     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6454     info.enable_mask        = 1ull<<24 /* uod_pe */;
6455     info.flags              = 0;
6456     info.group              = CVMX_ERROR_GROUP_USB;
6457     info.group_index        = 0;
6458     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6459     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6460     info.parent.status_mask = 1ull<<13 /* usb */;
6461     info.func               = __cvmx_error_display;
6462     info.user_info          = (long)
6463         "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
6464     fail |= cvmx_error_add(&info);
6465
6466     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6467     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6468     info.status_mask        = 1ull<<25 /* uod_pf */;
6469     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6470     info.enable_mask        = 1ull<<25 /* uod_pf */;
6471     info.flags              = 0;
6472     info.group              = CVMX_ERROR_GROUP_USB;
6473     info.group_index        = 0;
6474     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6475     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6476     info.parent.status_mask = 1ull<<13 /* usb */;
6477     info.func               = __cvmx_error_display;
6478     info.user_info          = (long)
6479         "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
6480     fail |= cvmx_error_add(&info);
6481
6482     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6483     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6484     info.status_mask        = 1ull<<32 /* ltl_f_pe */;
6485     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6486     info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
6487     info.flags              = 0;
6488     info.group              = CVMX_ERROR_GROUP_USB;
6489     info.group_index        = 0;
6490     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6491     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6492     info.parent.status_mask = 1ull<<13 /* usb */;
6493     info.func               = __cvmx_error_display;
6494     info.user_info          = (long)
6495         "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
6496     fail |= cvmx_error_add(&info);
6497
6498     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6499     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6500     info.status_mask        = 1ull<<33 /* ltl_f_pf */;
6501     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6502     info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
6503     info.flags              = 0;
6504     info.group              = CVMX_ERROR_GROUP_USB;
6505     info.group_index        = 0;
6506     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6507     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6508     info.parent.status_mask = 1ull<<13 /* usb */;
6509     info.func               = __cvmx_error_display;
6510     info.user_info          = (long)
6511         "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
6512     fail |= cvmx_error_add(&info);
6513
6514     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6515     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6516     info.status_mask        = 1ull<<34 /* nd4o_rpe */;
6517     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6518     info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
6519     info.flags              = 0;
6520     info.group              = CVMX_ERROR_GROUP_USB;
6521     info.group_index        = 0;
6522     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6523     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6524     info.parent.status_mask = 1ull<<13 /* usb */;
6525     info.func               = __cvmx_error_display;
6526     info.user_info          = (long)
6527         "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
6528     fail |= cvmx_error_add(&info);
6529
6530     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6531     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6532     info.status_mask        = 1ull<<35 /* nd4o_rpf */;
6533     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6534     info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
6535     info.flags              = 0;
6536     info.group              = CVMX_ERROR_GROUP_USB;
6537     info.group_index        = 0;
6538     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6539     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6540     info.parent.status_mask = 1ull<<13 /* usb */;
6541     info.func               = __cvmx_error_display;
6542     info.user_info          = (long)
6543         "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
6544     fail |= cvmx_error_add(&info);
6545
6546     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6547     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6548     info.status_mask        = 1ull<<36 /* nd4o_dpe */;
6549     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6550     info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
6551     info.flags              = 0;
6552     info.group              = CVMX_ERROR_GROUP_USB;
6553     info.group_index        = 0;
6554     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6555     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6556     info.parent.status_mask = 1ull<<13 /* usb */;
6557     info.func               = __cvmx_error_display;
6558     info.user_info          = (long)
6559         "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
6560     fail |= cvmx_error_add(&info);
6561
6562     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6563     info.status_addr        = CVMX_USBNX_INT_SUM(0);
6564     info.status_mask        = 1ull<<37 /* nd4o_dpf */;
6565     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
6566     info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
6567     info.flags              = 0;
6568     info.group              = CVMX_ERROR_GROUP_USB;
6569     info.group_index        = 0;
6570     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6571     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6572     info.parent.status_mask = 1ull<<13 /* usb */;
6573     info.func               = __cvmx_error_display;
6574     info.user_info          = (long)
6575         "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
6576     fail |= cvmx_error_add(&info);
6577
6578     return fail;
6579 }
6580