sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c

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  37  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  38  ***********************license end**************************************/
  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn56xx.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN56XX</h2>
  51  * @dot
  52  * digraph cn56xx
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
  59  *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
  60  *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
  61  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  62  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
  63  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  64  *     cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"];
  65  *     cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
  66  *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
  67  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
  68  *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
  69  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
  70  *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
  71  *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"];
  72  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
  73  *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
  74  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
  75  *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
  76  *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
  77  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  78  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
  79  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  80  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
  81  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  82  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
  83  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  84  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
  85  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  86  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
  87  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
  88  *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
  89  *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  90  *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
  91  *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  92  *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
  93  *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  94  *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
  95  *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  96  *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
  97  *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
  98  *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
  99  *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"];
 100  *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
 101  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
 102  *     cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
 103  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
 104  *     cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
 105  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
 106  *     cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
 107  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
 108  *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
 109  *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
 110  *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
 111  *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
 112  *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
 113  *     cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
 114  *     cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
 115  *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
 116  *     cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
 117  *     cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"];
 118  *     cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"];
 119  *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 120  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
 121  *     cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 122  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
 123  *     cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 124  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
 125  *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 126  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
 127  *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
 128  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
 129  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 130  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
 131  *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 132  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
 133  *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 134  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
 135  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
 136  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
 137  *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
 138  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
 139  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
 140  *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
 141  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
 142  *     cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
 143  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
 144  *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
 145  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
 146  *     cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
 147  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
 148  *     cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
 149  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
 150  *     cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
 151  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
 152  *     cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
 153  *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
 154  *     cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
 155  *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
 156  *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
 157  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 158  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 159  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 160  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
 161  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 162  *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
 163  *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
 164  *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
 165  *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
 166  *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
 167  *     cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
 168  *     cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
 169  *     cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
 170  *     cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
 171  *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
 172  *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
 173  *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
 174  *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
 175  *     cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
 176  * }
 177  * @enddot
 178  */
 179 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 180 #include <asm/octeon/cvmx.h>
 181 #include <asm/octeon/cvmx-error.h>
 182 #include <asm/octeon/cvmx-error-custom.h>
 183 #include <asm/octeon/cvmx-csr-typedefs.h>
 184 #else
 185 #include "cvmx.h"
 186 #include "cvmx-error.h"
 187 #include "cvmx-error-custom.h"
 188 #endif
 189
 190 int cvmx_error_initialize_cn56xx(void);
 191
 192 int cvmx_error_initialize_cn56xx(void)
 193 {
 194     cvmx_error_info_t info;
 195     int fail = 0;
 196
 197     /* CVMX_CIU_INTX_SUM0(0) */
 198     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 199     info.status_addr        = CVMX_CIU_INTX_SUM0(0);
 200     info.status_mask        = 0;
 201     info.enable_addr        = 0;
 202     info.enable_mask        = 0;
 203     info.flags              = 0;
 204     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 205     info.group_index        = 0;
 206     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 207     info.parent.status_addr = 0;
 208     info.parent.status_mask = 0;
 209     info.func               = __cvmx_error_decode;
 210     info.user_info          = 0;
 211     fail |= cvmx_error_add(&info);
 212
 213     /* CVMX_MIXX_ISR(0) */
 214     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 215     info.status_addr        = CVMX_MIXX_ISR(0);
 216     info.status_mask        = 1ull<<0 /* odblovf */;
 217     info.enable_addr        = CVMX_MIXX_INTENA(0);
 218     info.enable_mask        = 1ull<<0 /* ovfena */;
 219     info.flags              = 0;
 220     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 221     info.group_index        = 0;
 222     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 223     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 224     info.parent.status_mask = 1ull<<62 /* mii */;
 225     info.func               = __cvmx_error_display;
 226     info.user_info          = (long)
 227         "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
 228         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
 229         "    with a value greater than the remaining #of\n"
 230         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
 231         "    the following occurs:\n"
 232         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
 233         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 234         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 235         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 236         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
 237         "    interrupt is reported for this event.\n"
 238         "    SW should keep track of the #I-Ring Entries in use\n"
 239         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
 240         "    future ODBELL writes don't exceed the size of the\n"
 241         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
 242         "    SW must reclaim O-Ring Entries by writing to the\n"
 243         "    MIX_ORCNT[ORCNT]. .\n"
 244         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
 245         "    If it occurs, it's an indication that SW has\n"
 246         "    overwritten the O-Ring buffer, and the only recourse\n"
 247         "    is a HW reset.\n";
 248     fail |= cvmx_error_add(&info);
 249
 250     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 251     info.status_addr        = CVMX_MIXX_ISR(0);
 252     info.status_mask        = 1ull<<1 /* idblovf */;
 253     info.enable_addr        = CVMX_MIXX_INTENA(0);
 254     info.enable_mask        = 1ull<<1 /* ivfena */;
 255     info.flags              = 0;
 256     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 257     info.group_index        = 0;
 258     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 259     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 260     info.parent.status_mask = 1ull<<62 /* mii */;
 261     info.func               = __cvmx_error_display;
 262     info.user_info          = (long)
 263         "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
 264         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
 265         "    with a value greater than the remaining #of\n"
 266         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
 267         "    the following occurs:\n"
 268         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
 269         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 270         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 271         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 272         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
 273         "    interrupt is reported for this event.\n"
 274         "    SW should keep track of the #I-Ring Entries in use\n"
 275         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
 276         "    future IDBELL writes don't exceed the size of the\n"
 277         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
 278         "    SW must reclaim I-Ring Entries by keeping track of the\n"
 279         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
 280         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
 281         "    total #packets(not IRing Entries) and SW must further\n"
 282         "    keep track of the # of I-Ring Entries associated with\n"
 283         "    each packet as they are processed.\n"
 284         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
 285         "    If it occurs, it's an indication that SW has\n"
 286         "    overwritten the I-Ring buffer, and the only recourse\n"
 287         "    is a HW reset.\n";
 288     fail |= cvmx_error_add(&info);
 289
 290     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 291     info.status_addr        = CVMX_MIXX_ISR(0);
 292     info.status_mask        = 1ull<<4 /* data_drp */;
 293     info.enable_addr        = CVMX_MIXX_INTENA(0);
 294     info.enable_mask        = 1ull<<4 /* data_drpena */;
 295     info.flags              = 0;
 296     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 297     info.group_index        = 0;
 298     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 299     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 300     info.parent.status_mask = 1ull<<62 /* mii */;
 301     info.func               = __cvmx_error_display;
 302     info.user_info          = (long)
 303         "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
 304         "    If this does occur, the DATA_DRP is set and the\n"
 305         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
 306         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 307         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
 308         "    interrupt is reported for this event.\n";
 309     fail |= cvmx_error_add(&info);
 310
 311     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 312     info.status_addr        = CVMX_MIXX_ISR(0);
 313     info.status_mask        = 1ull<<5 /* irun */;
 314     info.enable_addr        = CVMX_MIXX_INTENA(0);
 315     info.enable_mask        = 1ull<<5 /* irunena */;
 316     info.flags              = 0;
 317     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 318     info.group_index        = 0;
 319     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 320     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 321     info.parent.status_mask = 1ull<<62 /* mii */;
 322     info.func               = __cvmx_error_display;
 323     info.user_info          = (long)
 324         "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
 325         "    If SW writes a larger value than what is currently\n"
 326         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
 327         "    underflow condition.\n"
 328         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
 329         "    NOTE: If an IRUN underflow condition is detected,\n"
 330         "    the integrity of the MIX/AGL HW state has\n"
 331         "    been compromised. To recover, SW must issue a\n"
 332         "    software reset sequence (see: MIX_CTL[RESET]\n";
 333     fail |= cvmx_error_add(&info);
 334
 335     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 336     info.status_addr        = CVMX_MIXX_ISR(0);
 337     info.status_mask        = 1ull<<6 /* orun */;
 338     info.enable_addr        = CVMX_MIXX_INTENA(0);
 339     info.enable_mask        = 1ull<<6 /* orunena */;
 340     info.flags              = 0;
 341     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 342     info.group_index        = 0;
 343     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 344     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 345     info.parent.status_mask = 1ull<<62 /* mii */;
 346     info.func               = __cvmx_error_display;
 347     info.user_info          = (long)
 348         "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
 349         "    If SW writes a larger value than what is currently\n"
 350         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
 351         "    underflow condition.\n"
 352         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
 353         "    NOTE: If an ORUN underflow condition is detected,\n"
 354         "    the integrity of the MIX/AGL HW state has\n"
 355         "    been compromised. To recover, SW must issue a\n"
 356         "    software reset sequence (see: MIX_CTL[RESET]\n";
 357     fail |= cvmx_error_add(&info);
 358
 359     /* CVMX_CIU_INT_SUM1 */
 360     /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
 361     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 362     info.status_addr        = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 363     info.status_mask        = 0;
 364     info.enable_addr        = 0;
 365     info.enable_mask        = 0;
 366     info.flags              = 0;
 367     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 368     info.group_index        = 0;
 369     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 370     info.parent.status_addr = 0;
 371     info.parent.status_mask = 0;
 372     info.func               = __cvmx_error_decode;
 373     info.user_info          = 0;
 374     fail |= cvmx_error_add(&info);
 375
 376     /* CVMX_L2C_INT_STAT */
 377     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 378     info.status_addr        = CVMX_L2C_INT_STAT;
 379     info.status_mask        = 1ull<<3 /* l2tsec */;
 380     info.enable_addr        = CVMX_L2C_INT_EN;
 381     info.enable_mask        = 1ull<<3 /* l2tsecen */;
 382     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 383     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 384     info.group_index        = 0;
 385     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 386     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 387     info.parent.status_mask = 1ull<<16 /* l2c */;
 388     info.func               = __cvmx_error_display;
 389     info.user_info          = (long)
 390         "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
 391         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 392         "    given index) are checked for single bit errors(SBEs).\n"
 393         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 394         "    SBEs are auto corrected in HW and generate an\n"
 395         "    interrupt(if enabled).\n"
 396         "    NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
 397     fail |= cvmx_error_add(&info);
 398
 399     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 400     info.status_addr        = CVMX_L2C_INT_STAT;
 401     info.status_mask        = 1ull<<5 /* l2dsec */;
 402     info.enable_addr        = CVMX_L2C_INT_EN;
 403     info.enable_mask        = 1ull<<5 /* l2dsecen */;
 404     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 405     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 406     info.group_index        = 0;
 407     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 408     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 409     info.parent.status_mask = 1ull<<16 /* l2c */;
 410     info.func               = __cvmx_error_display;
 411     info.user_info          = (long)
 412         "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
 413         "    NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
 414     fail |= cvmx_error_add(&info);
 415
 416     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 417     info.status_addr        = CVMX_L2C_INT_STAT;
 418     info.status_mask        = 1ull<<0 /* oob1 */;
 419     info.enable_addr        = CVMX_L2C_INT_EN;
 420     info.enable_mask        = 1ull<<0 /* oob1en */;
 421     info.flags              = 0;
 422     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 423     info.group_index        = 0;
 424     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 425     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 426     info.parent.status_mask = 1ull<<16 /* l2c */;
 427     info.func               = __cvmx_error_display;
 428     info.user_info          = (long)
 429         "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
 430     fail |= cvmx_error_add(&info);
 431
 432     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 433     info.status_addr        = CVMX_L2C_INT_STAT;
 434     info.status_mask        = 1ull<<1 /* oob2 */;
 435     info.enable_addr        = CVMX_L2C_INT_EN;
 436     info.enable_mask        = 1ull<<1 /* oob2en */;
 437     info.flags              = 0;
 438     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 439     info.group_index        = 0;
 440     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 441     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 442     info.parent.status_mask = 1ull<<16 /* l2c */;
 443     info.func               = __cvmx_error_display;
 444     info.user_info          = (long)
 445         "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
 446     fail |= cvmx_error_add(&info);
 447
 448     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 449     info.status_addr        = CVMX_L2C_INT_STAT;
 450     info.status_mask        = 1ull<<2 /* oob3 */;
 451     info.enable_addr        = CVMX_L2C_INT_EN;
 452     info.enable_mask        = 1ull<<2 /* oob3en */;
 453     info.flags              = 0;
 454     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 455     info.group_index        = 0;
 456     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 457     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 458     info.parent.status_mask = 1ull<<16 /* l2c */;
 459     info.func               = __cvmx_error_display;
 460     info.user_info          = (long)
 461         "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
 462     fail |= cvmx_error_add(&info);
 463
 464     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 465     info.status_addr        = CVMX_L2C_INT_STAT;
 466     info.status_mask        = 1ull<<4 /* l2tded */;
 467     info.enable_addr        = CVMX_L2C_INT_EN;
 468     info.enable_mask        = 1ull<<4 /* l2tdeden */;
 469     info.flags              = 0;
 470     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 471     info.group_index        = 0;
 472     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 473     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 474     info.parent.status_mask = 1ull<<16 /* l2c */;
 475     info.func               = __cvmx_error_display;
 476     info.user_info          = (long)
 477         "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
 478         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 479         "    given index) are checked for double bit errors(DBEs).\n"
 480         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 481         "    DBEs also generated an interrupt(if enabled).\n"
 482         "    NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
 483     fail |= cvmx_error_add(&info);
 484
 485     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 486     info.status_addr        = CVMX_L2C_INT_STAT;
 487     info.status_mask        = 1ull<<6 /* l2dded */;
 488     info.enable_addr        = CVMX_L2C_INT_EN;
 489     info.enable_mask        = 1ull<<6 /* l2ddeden */;
 490     info.flags              = 0;
 491     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 492     info.group_index        = 0;
 493     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 494     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 495     info.parent.status_mask = 1ull<<16 /* l2c */;
 496     info.func               = __cvmx_error_display;
 497     info.user_info          = (long)
 498         "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
 499         "    NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
 500     fail |= cvmx_error_add(&info);
 501
 502     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 503     info.status_addr        = CVMX_L2C_INT_STAT;
 504     info.status_mask        = 1ull<<7 /* lck */;
 505     info.enable_addr        = CVMX_L2C_INT_EN;
 506     info.enable_mask        = 1ull<<7 /* lckena */;
 507     info.flags              = 0;
 508     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 509     info.group_index        = 0;
 510     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 511     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 512     info.parent.status_mask = 1ull<<16 /* l2c */;
 513     info.func               = __cvmx_error_display;
 514     info.user_info          = (long)
 515         "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
 516         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 517         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 518         "    successfully, however the address is NOT locked.\n"
 519         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 520         "    into account. For example, if diagnostic PPx has\n"
 521         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 522         "    been previously LOCKED, then an attempt to LOCK the\n"
 523         "    last available SET0 would result in a LCKERR. (This\n"
 524         "    is to ensure that at least 1 SET at each INDEX is\n"
 525         "    not LOCKED for general use by other PPs).\n"
 526         "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
 527     fail |= cvmx_error_add(&info);
 528
 529     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 530     info.status_addr        = CVMX_L2C_INT_STAT;
 531     info.status_mask        = 1ull<<8 /* lck2 */;
 532     info.enable_addr        = CVMX_L2C_INT_EN;
 533     info.enable_mask        = 1ull<<8 /* lck2ena */;
 534     info.flags              = 0;
 535     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 536     info.group_index        = 0;
 537     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 538     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 539     info.parent.status_mask = 1ull<<16 /* l2c */;
 540     info.func               = __cvmx_error_display;
 541     info.user_info          = (long)
 542         "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 543         "    could not find an available/unlocked set (for\n"
 544         "    replacement).\n"
 545         "    Most likely, this is a result of SW mixing SET\n"
 546         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 547         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 548         "    then a Rd/Wr Miss from PP#n will be unable\n"
 549         "    to determine a 'valid' replacement set (since LOCKED\n"
 550         "    addresses should NEVER be replaced).\n"
 551         "    If such an event occurs, the HW will select the smallest\n"
 552         "    available SET(specified by UMSK'x)' as the replacement\n"
 553         "    set, and the address is unlocked.\n"
 554         "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
 555     fail |= cvmx_error_add(&info);
 556
 557     /* CVMX_L2D_ERR */
 558     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 559     info.status_addr        = CVMX_L2D_ERR;
 560     info.status_mask        = 1ull<<3 /* sec_err */;
 561     info.enable_addr        = CVMX_L2D_ERR;
 562     info.enable_mask        = 1ull<<1 /* sec_intena */;
 563     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 564     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 565     info.group_index        = 0;
 566     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 567     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 568     info.parent.status_mask = 1ull<<16 /* l2c */;
 569     info.func               = __cvmx_error_handle_l2d_err_sec_err;
 570     info.user_info          = (long)
 571         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
 572     fail |= cvmx_error_add(&info);
 573
 574     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 575     info.status_addr        = CVMX_L2D_ERR;
 576     info.status_mask        = 1ull<<4 /* ded_err */;
 577     info.enable_addr        = CVMX_L2D_ERR;
 578     info.enable_mask        = 1ull<<2 /* ded_intena */;
 579     info.flags              = 0;
 580     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 581     info.group_index        = 0;
 582     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 583     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 584     info.parent.status_mask = 1ull<<16 /* l2c */;
 585     info.func               = __cvmx_error_handle_l2d_err_ded_err;
 586     info.user_info          = (long)
 587         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
 588     fail |= cvmx_error_add(&info);
 589
 590     /* CVMX_L2T_ERR */
 591     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 592     info.status_addr        = CVMX_L2T_ERR;
 593     info.status_mask        = 1ull<<3 /* sec_err */;
 594     info.enable_addr        = CVMX_L2T_ERR;
 595     info.enable_mask        = 1ull<<1 /* sec_intena */;
 596     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 597     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 598     info.group_index        = 0;
 599     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 600     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 601     info.parent.status_mask = 1ull<<16 /* l2c */;
 602     info.func               = __cvmx_error_handle_l2t_err_sec_err;
 603     info.user_info          = (long)
 604         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
 605         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 606         "    given index) are checked for single bit errors(SBEs).\n"
 607         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 608         "    SBEs are auto corrected in HW and generate an\n"
 609         "    interrupt(if enabled).\n";
 610     fail |= cvmx_error_add(&info);
 611
 612     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 613     info.status_addr        = CVMX_L2T_ERR;
 614     info.status_mask        = 1ull<<4 /* ded_err */;
 615     info.enable_addr        = CVMX_L2T_ERR;
 616     info.enable_mask        = 1ull<<2 /* ded_intena */;
 617     info.flags              = 0;
 618     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 619     info.group_index        = 0;
 620     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 621     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 622     info.parent.status_mask = 1ull<<16 /* l2c */;
 623     info.func               = __cvmx_error_handle_l2t_err_ded_err;
 624     info.user_info          = (long)
 625         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
 626         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 627         "    given index) are checked for double bit errors(DBEs).\n"
 628         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 629         "    DBEs also generated an interrupt(if enabled).\n";
 630     fail |= cvmx_error_add(&info);
 631
 632     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 633     info.status_addr        = CVMX_L2T_ERR;
 634     info.status_mask        = 1ull<<24 /* lckerr */;
 635     info.enable_addr        = CVMX_L2T_ERR;
 636     info.enable_mask        = 1ull<<25 /* lck_intena */;
 637     info.flags              = 0;
 638     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 639     info.group_index        = 0;
 640     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 641     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 642     info.parent.status_mask = 1ull<<16 /* l2c */;
 643     info.func               = __cvmx_error_handle_l2t_err_lckerr;
 644     info.user_info          = (long)
 645         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
 646         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 647         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 648         "    successfully, however the address is NOT locked.\n"
 649         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 650         "    into account. For example, if diagnostic PPx has\n"
 651         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 652         "    been previously LOCKED, then an attempt to LOCK the\n"
 653         "    last available SET0 would result in a LCKERR. (This\n"
 654         "    is to ensure that at least 1 SET at each INDEX is\n"
 655         "    not LOCKED for general use by other PPs).\n";
 656     fail |= cvmx_error_add(&info);
 657
 658     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 659     info.status_addr        = CVMX_L2T_ERR;
 660     info.status_mask        = 1ull<<26 /* lckerr2 */;
 661     info.enable_addr        = CVMX_L2T_ERR;
 662     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
 663     info.flags              = 0;
 664     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 665     info.group_index        = 0;
 666     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 667     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 668     info.parent.status_mask = 1ull<<16 /* l2c */;
 669     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
 670     info.user_info          = (long)
 671         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 672         "    could not find an available/unlocked set (for\n"
 673         "    replacement).\n"
 674         "    Most likely, this is a result of SW mixing SET\n"
 675         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 676         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 677         "    then a Rd/Wr Miss from PP#n will be unable\n"
 678         "    to determine a 'valid' replacement set (since LOCKED\n"
 679         "    addresses should NEVER be replaced).\n"
 680         "    If such an event occurs, the HW will select the smallest\n"
 681         "    available SET(specified by UMSK'x)' as the replacement\n"
 682         "    set, and the address is unlocked.\n";
 683     fail |= cvmx_error_add(&info);
 684
 685     /* CVMX_AGL_GMX_BAD_REG */
 686     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 687     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 688     info.status_mask        = 1ull<<32 /* ovrflw */;
 689     info.enable_addr        = 0;
 690     info.enable_mask        = 0;
 691     info.flags              = 0;
 692     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 693     info.group_index        = 0;
 694     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 695     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 696     info.parent.status_mask = 1ull<<28 /* agl */;
 697     info.func               = __cvmx_error_display;
 698     info.user_info          = (long)
 699         "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n";
 700     fail |= cvmx_error_add(&info);
 701
 702     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 703     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 704     info.status_mask        = 1ull<<33 /* txpop */;
 705     info.enable_addr        = 0;
 706     info.enable_mask        = 0;
 707     info.flags              = 0;
 708     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 709     info.group_index        = 0;
 710     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 711     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 712     info.parent.status_mask = 1ull<<28 /* agl */;
 713     info.func               = __cvmx_error_display;
 714     info.user_info          = (long)
 715         "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n";
 716     fail |= cvmx_error_add(&info);
 717
 718     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 719     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 720     info.status_mask        = 1ull<<34 /* txpsh */;
 721     info.enable_addr        = 0;
 722     info.enable_mask        = 0;
 723     info.flags              = 0;
 724     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 725     info.group_index        = 0;
 726     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 727     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 728     info.parent.status_mask = 1ull<<28 /* agl */;
 729     info.func               = __cvmx_error_display;
 730     info.user_info          = (long)
 731         "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n";
 732     fail |= cvmx_error_add(&info);
 733
 734     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 735     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 736     info.status_mask        = 1ull<<2 /* out_ovr */;
 737     info.enable_addr        = 0;
 738     info.enable_mask        = 0;
 739     info.flags              = 0;
 740     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 741     info.group_index        = 0;
 742     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 743     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 744     info.parent.status_mask = 1ull<<28 /* agl */;
 745     info.func               = __cvmx_error_display;
 746     info.user_info          = (long)
 747         "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
 748     fail |= cvmx_error_add(&info);
 749
 750     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 751     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
 752     info.status_mask        = 1ull<<22 /* loststat */;
 753     info.enable_addr        = 0;
 754     info.enable_mask        = 0;
 755     info.flags              = 0;
 756     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 757     info.group_index        = 0;
 758     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 759     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 760     info.parent.status_mask = 1ull<<28 /* agl */;
 761     info.func               = __cvmx_error_display;
 762     info.user_info          = (long)
 763         "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
 764         "    TX Stats are corrupted\n";
 765     fail |= cvmx_error_add(&info);
 766
 767     /* CVMX_AGL_GMX_RXX_INT_REG(0) */
 768     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 769     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
 770     info.status_mask        = 1ull<<8 /* skperr */;
 771     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
 772     info.enable_mask        = 1ull<<8 /* skperr */;
 773     info.flags              = 0;
 774     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 775     info.group_index        = 0;
 776     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 777     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 778     info.parent.status_mask = 1ull<<28 /* agl */;
 779     info.func               = __cvmx_error_display;
 780     info.user_info          = (long)
 781         "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
 782     fail |= cvmx_error_add(&info);
 783
 784     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 785     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
 786     info.status_mask        = 1ull<<10 /* ovrerr */;
 787     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
 788     info.enable_mask        = 1ull<<10 /* ovrerr */;
 789     info.flags              = 0;
 790     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 791     info.group_index        = 0;
 792     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 793     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 794     info.parent.status_mask = 1ull<<28 /* agl */;
 795     info.func               = __cvmx_error_display;
 796     info.user_info          = (long)
 797         "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
 798         "    This interrupt should never assert\n";
 799     fail |= cvmx_error_add(&info);
 800
 801     /* CVMX_AGL_GMX_TX_INT_REG */
 802     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 803     info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
 804     info.status_mask        = 1ull<<0 /* pko_nxa */;
 805     info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
 806     info.enable_mask        = 1ull<<0 /* pko_nxa */;
 807     info.flags              = 0;
 808     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 809     info.group_index        = 0;
 810     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 811     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 812     info.parent.status_mask = 1ull<<28 /* agl */;
 813     info.func               = __cvmx_error_display;
 814     info.user_info          = (long)
 815         "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
 816     fail |= cvmx_error_add(&info);
 817
 818     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 819     info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
 820     info.status_mask        = 1ull<<2 /* undflw */;
 821     info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
 822     info.enable_mask        = 1ull<<2 /* undflw */;
 823     info.flags              = 0;
 824     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 825     info.group_index        = 0;
 826     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 827     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 828     info.parent.status_mask = 1ull<<28 /* agl */;
 829     info.func               = __cvmx_error_display;
 830     info.user_info          = (long)
 831         "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
 832     fail |= cvmx_error_add(&info);
 833
 834     /* CVMX_GMXX_BAD_REG(0) */
 835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 836     info.status_addr        = CVMX_GMXX_BAD_REG(0);
 837     info.status_mask        = 0xfull<<2 /* out_ovr */;
 838     info.enable_addr        = 0;
 839     info.enable_mask        = 0;
 840     info.flags              = 0;
 841     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 842     info.group_index        = 0;
 843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 844     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 845     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 846     info.func               = __cvmx_error_display;
 847     info.user_info          = (long)
 848         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
 849     fail |= cvmx_error_add(&info);
 850
 851     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 852     info.status_addr        = CVMX_GMXX_BAD_REG(0);
 853     info.status_mask        = 0xfull<<22 /* loststat */;
 854     info.enable_addr        = 0;
 855     info.enable_mask        = 0;
 856     info.flags              = 0;
 857     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 858     info.group_index        = 0;
 859     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 860     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 861     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 862     info.func               = __cvmx_error_display;
 863     info.user_info          = (long)
 864         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
 865         "    In SGMII, one bit per port\n"
 866         "    In XAUI, only port0 is used\n"
 867         "    TX Stats are corrupted\n";
 868     fail |= cvmx_error_add(&info);
 869
 870     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 871     info.status_addr        = CVMX_GMXX_BAD_REG(0);
 872     info.status_mask        = 1ull<<26 /* statovr */;
 873     info.enable_addr        = 0;
 874     info.enable_mask        = 0;
 875     info.flags              = 0;
 876     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 877     info.group_index        = 0;
 878     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 879     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 880     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 881     info.func               = __cvmx_error_display;
 882     info.user_info          = (long)
 883         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
 884         "    The common FIFO to SGMII and XAUI had an overflow\n"
 885         "    TX Stats are corrupted\n";
 886     fail |= cvmx_error_add(&info);
 887
 888     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 889     info.status_addr        = CVMX_GMXX_BAD_REG(0);
 890     info.status_mask        = 0xfull<<27 /* inb_nxa */;
 891     info.enable_addr        = 0;
 892     info.enable_mask        = 0;
 893     info.flags              = 0;
 894     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 895     info.group_index        = 0;
 896     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 897     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 898     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 899     info.func               = __cvmx_error_display;
 900     info.user_info          = (long)
 901         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
 902     fail |= cvmx_error_add(&info);
 903
 904     /* CVMX_GMXX_RXX_INT_REG(0,0) */
 905     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 906     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
 907     info.status_mask        = 1ull<<1 /* carext */;
 908     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
 909     info.enable_mask        = 1ull<<1 /* carext */;
 910     info.flags              = 0;
 911     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 912     info.group_index        = 0;
 913     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 914     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 915     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 916     info.func               = __cvmx_error_display;
 917     info.user_info          = (long)
 918         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
 919         "    (SGMII/1000Base-X only)\n";
 920     fail |= cvmx_error_add(&info);
 921
 922     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 923     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
 924     info.status_mask        = 1ull<<8 /* skperr */;
 925     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
 926     info.enable_mask        = 1ull<<8 /* skperr */;
 927     info.flags              = 0;
 928     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 929     info.group_index        = 0;
 930     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 931     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 932     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 933     info.func               = __cvmx_error_display;
 934     info.user_info          = (long)
 935         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
 936     fail |= cvmx_error_add(&info);
 937
 938     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 939     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
 940     info.status_mask        = 1ull<<10 /* ovrerr */;
 941     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
 942     info.enable_mask        = 1ull<<10 /* ovrerr */;
 943     info.flags              = 0;
 944     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 945     info.group_index        = 0;
 946     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 947     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 948     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 949     info.func               = __cvmx_error_display;
 950     info.user_info          = (long)
 951         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
 952         "    This interrupt should never assert\n"
 953         "    (SGMII/1000Base-X only)\n";
 954     fail |= cvmx_error_add(&info);
 955
 956     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 957     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
 958     info.status_mask        = 1ull<<20 /* loc_fault */;
 959     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
 960     info.enable_mask        = 1ull<<20 /* loc_fault */;
 961     info.flags              = 0;
 962     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 963     info.group_index        = 0;
 964     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 965     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 966     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 967     info.func               = __cvmx_error_display;
 968     info.user_info          = (long)
 969         "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
 970         "    (XAUI Mode only)\n";
 971     fail |= cvmx_error_add(&info);
 972
 973     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 974     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
 975     info.status_mask        = 1ull<<21 /* rem_fault */;
 976     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
 977     info.enable_mask        = 1ull<<21 /* rem_fault */;
 978     info.flags              = 0;
 979     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 980     info.group_index        = 0;
 981     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 982     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
 983     info.parent.status_mask = 1ull<<1 /* gmx0 */;
 984     info.func               = __cvmx_error_display;
 985     info.user_info          = (long)
 986         "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
 987         "    (XAUI Mode only)\n";
 988     fail |= cvmx_error_add(&info);
 989
 990     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 991     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
 992     info.status_mask        = 1ull<<22 /* bad_seq */;
 993     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
 994     info.enable_mask        = 1ull<<22 /* bad_seq */;
 995     info.flags              = 0;
 996     info.group              = CVMX_ERROR_GROUP_ETHERNET;
 997     info.group_index        = 0;
 998     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 999     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1000     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1001     info.func               = __cvmx_error_display;
1002     info.user_info          = (long)
1003         "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1004         "    (XAUI Mode only)\n";
1005     fail |= cvmx_error_add(&info);
1006
1007     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1008     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1009     info.status_mask        = 1ull<<23 /* bad_term */;
1010     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1011     info.enable_mask        = 1ull<<23 /* bad_term */;
1012     info.flags              = 0;
1013     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1014     info.group_index        = 0;
1015     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1016     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1017     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1018     info.func               = __cvmx_error_display;
1019     info.user_info          = (long)
1020         "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
1021         "    than /T/.  The error propagation control\n"
1022         "    character /E/ will be included as part of the\n"
1023         "    frame and does not cause a frame termination.\n"
1024         "    (XAUI Mode only)\n";
1025     fail |= cvmx_error_add(&info);
1026
1027     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1028     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1029     info.status_mask        = 1ull<<24 /* unsop */;
1030     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1031     info.enable_mask        = 1ull<<24 /* unsop */;
1032     info.flags              = 0;
1033     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1034     info.group_index        = 0;
1035     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1036     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1037     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1038     info.func               = __cvmx_error_display;
1039     info.user_info          = (long)
1040         "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
1041         "    (XAUI Mode only)\n";
1042     fail |= cvmx_error_add(&info);
1043
1044     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1045     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1046     info.status_mask        = 1ull<<25 /* uneop */;
1047     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1048     info.enable_mask        = 1ull<<25 /* uneop */;
1049     info.flags              = 0;
1050     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1051     info.group_index        = 0;
1052     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1053     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1054     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1055     info.func               = __cvmx_error_display;
1056     info.user_info          = (long)
1057         "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
1058         "    (XAUI Mode only)\n";
1059     fail |= cvmx_error_add(&info);
1060
1061     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1062     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1063     info.status_mask        = 1ull<<26 /* undat */;
1064     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1065     info.enable_mask        = 1ull<<26 /* undat */;
1066     info.flags              = 0;
1067     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1068     info.group_index        = 0;
1069     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1070     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1071     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1072     info.func               = __cvmx_error_display;
1073     info.user_info          = (long)
1074         "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
1075         "    (XAUI Mode only)\n";
1076     fail |= cvmx_error_add(&info);
1077
1078     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1079     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1080     info.status_mask        = 1ull<<27 /* hg2fld */;
1081     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1082     info.enable_mask        = 1ull<<27 /* hg2fld */;
1083     info.flags              = 0;
1084     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1085     info.group_index        = 0;
1086     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1087     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1088     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1089     info.func               = __cvmx_error_display;
1090     info.user_info          = (long)
1091         "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1092         "    1) MSG_TYPE field not 6'b00_0000\n"
1093         "       i.e. it is not a FLOW CONTROL message, which\n"
1094         "       is the only defined type for HiGig2\n"
1095         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1096         "       which is the only defined type for HiGig2\n"
1097         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1098         "       Physical Link nor 4'b0010 for Logical Link.\n"
1099         "       Those are the only two defined types in HiGig2\n";
1100     fail |= cvmx_error_add(&info);
1101
1102     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1103     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1104     info.status_mask        = 1ull<<28 /* hg2cc */;
1105     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1106     info.enable_mask        = 1ull<<28 /* hg2cc */;
1107     info.flags              = 0;
1108     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1109     info.group_index        = 0;
1110     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1111     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1112     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1113     info.func               = __cvmx_error_display;
1114     info.user_info          = (long)
1115         "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1116         "    Set when either CRC8 error detected or when\n"
1117         "    a Control Character is found in the message\n"
1118         "    bytes after the K.SOM\n"
1119         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1120         "          i.e. a HiGig2 message that results in HG2CC\n"
1121         "          getting set, will never set HG2FLD.\n";
1122     fail |= cvmx_error_add(&info);
1123
1124     /* CVMX_GMXX_RXX_INT_REG(1,0) */
1125     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1126     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1127     info.status_mask        = 1ull<<1 /* carext */;
1128     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1129     info.enable_mask        = 1ull<<1 /* carext */;
1130     info.flags              = 0;
1131     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1132     info.group_index        = 1;
1133     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1134     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1135     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1136     info.func               = __cvmx_error_display;
1137     info.user_info          = (long)
1138         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
1139         "    (SGMII/1000Base-X only)\n";
1140     fail |= cvmx_error_add(&info);
1141
1142     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1143     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1144     info.status_mask        = 1ull<<8 /* skperr */;
1145     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1146     info.enable_mask        = 1ull<<8 /* skperr */;
1147     info.flags              = 0;
1148     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1149     info.group_index        = 1;
1150     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1151     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1152     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1153     info.func               = __cvmx_error_display;
1154     info.user_info          = (long)
1155         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1156     fail |= cvmx_error_add(&info);
1157
1158     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1159     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1160     info.status_mask        = 1ull<<10 /* ovrerr */;
1161     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1162     info.enable_mask        = 1ull<<10 /* ovrerr */;
1163     info.flags              = 0;
1164     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1165     info.group_index        = 1;
1166     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1167     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1168     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1169     info.func               = __cvmx_error_display;
1170     info.user_info          = (long)
1171         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1172         "    This interrupt should never assert\n"
1173         "    (SGMII/1000Base-X only)\n";
1174     fail |= cvmx_error_add(&info);
1175
1176     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1177     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1178     info.status_mask        = 1ull<<20 /* loc_fault */;
1179     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1180     info.enable_mask        = 1ull<<20 /* loc_fault */;
1181     info.flags              = 0;
1182     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1183     info.group_index        = 1;
1184     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1185     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1186     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1187     info.func               = __cvmx_error_display;
1188     info.user_info          = (long)
1189         "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1190         "    (XAUI Mode only)\n";
1191     fail |= cvmx_error_add(&info);
1192
1193     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1194     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1195     info.status_mask        = 1ull<<21 /* rem_fault */;
1196     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1197     info.enable_mask        = 1ull<<21 /* rem_fault */;
1198     info.flags              = 0;
1199     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1200     info.group_index        = 1;
1201     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1202     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1203     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1204     info.func               = __cvmx_error_display;
1205     info.user_info          = (long)
1206         "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1207         "    (XAUI Mode only)\n";
1208     fail |= cvmx_error_add(&info);
1209
1210     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1211     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1212     info.status_mask        = 1ull<<22 /* bad_seq */;
1213     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1214     info.enable_mask        = 1ull<<22 /* bad_seq */;
1215     info.flags              = 0;
1216     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1217     info.group_index        = 1;
1218     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1219     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1220     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1221     info.func               = __cvmx_error_display;
1222     info.user_info          = (long)
1223         "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1224         "    (XAUI Mode only)\n";
1225     fail |= cvmx_error_add(&info);
1226
1227     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1228     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1229     info.status_mask        = 1ull<<23 /* bad_term */;
1230     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1231     info.enable_mask        = 1ull<<23 /* bad_term */;
1232     info.flags              = 0;
1233     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1234     info.group_index        = 1;
1235     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1236     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1237     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1238     info.func               = __cvmx_error_display;
1239     info.user_info          = (long)
1240         "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
1241         "    than /T/.  The error propagation control\n"
1242         "    character /E/ will be included as part of the\n"
1243         "    frame and does not cause a frame termination.\n"
1244         "    (XAUI Mode only)\n";
1245     fail |= cvmx_error_add(&info);
1246
1247     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1248     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1249     info.status_mask        = 1ull<<24 /* unsop */;
1250     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1251     info.enable_mask        = 1ull<<24 /* unsop */;
1252     info.flags              = 0;
1253     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1254     info.group_index        = 1;
1255     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1256     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1257     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1258     info.func               = __cvmx_error_display;
1259     info.user_info          = (long)
1260         "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
1261         "    (XAUI Mode only)\n";
1262     fail |= cvmx_error_add(&info);
1263
1264     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1265     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1266     info.status_mask        = 1ull<<25 /* uneop */;
1267     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1268     info.enable_mask        = 1ull<<25 /* uneop */;
1269     info.flags              = 0;
1270     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1271     info.group_index        = 1;
1272     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1273     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1274     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1275     info.func               = __cvmx_error_display;
1276     info.user_info          = (long)
1277         "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
1278         "    (XAUI Mode only)\n";
1279     fail |= cvmx_error_add(&info);
1280
1281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1282     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1283     info.status_mask        = 1ull<<26 /* undat */;
1284     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1285     info.enable_mask        = 1ull<<26 /* undat */;
1286     info.flags              = 0;
1287     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1288     info.group_index        = 1;
1289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1290     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1291     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1292     info.func               = __cvmx_error_display;
1293     info.user_info          = (long)
1294         "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
1295         "    (XAUI Mode only)\n";
1296     fail |= cvmx_error_add(&info);
1297
1298     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1299     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1300     info.status_mask        = 1ull<<27 /* hg2fld */;
1301     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1302     info.enable_mask        = 1ull<<27 /* hg2fld */;
1303     info.flags              = 0;
1304     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1305     info.group_index        = 1;
1306     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1307     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1308     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1309     info.func               = __cvmx_error_display;
1310     info.user_info          = (long)
1311         "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1312         "    1) MSG_TYPE field not 6'b00_0000\n"
1313         "       i.e. it is not a FLOW CONTROL message, which\n"
1314         "       is the only defined type for HiGig2\n"
1315         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1316         "       which is the only defined type for HiGig2\n"
1317         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1318         "       Physical Link nor 4'b0010 for Logical Link.\n"
1319         "       Those are the only two defined types in HiGig2\n";
1320     fail |= cvmx_error_add(&info);
1321
1322     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1323     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1324     info.status_mask        = 1ull<<28 /* hg2cc */;
1325     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1326     info.enable_mask        = 1ull<<28 /* hg2cc */;
1327     info.flags              = 0;
1328     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1329     info.group_index        = 1;
1330     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1331     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1332     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1333     info.func               = __cvmx_error_display;
1334     info.user_info          = (long)
1335         "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1336         "    Set when either CRC8 error detected or when\n"
1337         "    a Control Character is found in the message\n"
1338         "    bytes after the K.SOM\n"
1339         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1340         "          i.e. a HiGig2 message that results in HG2CC\n"
1341         "          getting set, will never set HG2FLD.\n";
1342     fail |= cvmx_error_add(&info);
1343
1344     /* CVMX_GMXX_RXX_INT_REG(2,0) */
1345     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1346     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1347     info.status_mask        = 1ull<<1 /* carext */;
1348     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1349     info.enable_mask        = 1ull<<1 /* carext */;
1350     info.flags              = 0;
1351     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1352     info.group_index        = 2;
1353     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1354     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1355     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1356     info.func               = __cvmx_error_display;
1357     info.user_info          = (long)
1358         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
1359         "    (SGMII/1000Base-X only)\n";
1360     fail |= cvmx_error_add(&info);
1361
1362     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1363     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1364     info.status_mask        = 1ull<<8 /* skperr */;
1365     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1366     info.enable_mask        = 1ull<<8 /* skperr */;
1367     info.flags              = 0;
1368     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1369     info.group_index        = 2;
1370     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1371     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1372     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1373     info.func               = __cvmx_error_display;
1374     info.user_info          = (long)
1375         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
1376     fail |= cvmx_error_add(&info);
1377
1378     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1379     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1380     info.status_mask        = 1ull<<10 /* ovrerr */;
1381     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1382     info.enable_mask        = 1ull<<10 /* ovrerr */;
1383     info.flags              = 0;
1384     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1385     info.group_index        = 2;
1386     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1387     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1388     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1389     info.func               = __cvmx_error_display;
1390     info.user_info          = (long)
1391         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1392         "    This interrupt should never assert\n"
1393         "    (SGMII/1000Base-X only)\n";
1394     fail |= cvmx_error_add(&info);
1395
1396     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1397     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1398     info.status_mask        = 1ull<<20 /* loc_fault */;
1399     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1400     info.enable_mask        = 1ull<<20 /* loc_fault */;
1401     info.flags              = 0;
1402     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1403     info.group_index        = 2;
1404     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1405     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1406     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1407     info.func               = __cvmx_error_display;
1408     info.user_info          = (long)
1409         "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1410         "    (XAUI Mode only)\n";
1411     fail |= cvmx_error_add(&info);
1412
1413     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1414     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1415     info.status_mask        = 1ull<<21 /* rem_fault */;
1416     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1417     info.enable_mask        = 1ull<<21 /* rem_fault */;
1418     info.flags              = 0;
1419     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1420     info.group_index        = 2;
1421     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1422     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1423     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1424     info.func               = __cvmx_error_display;
1425     info.user_info          = (long)
1426         "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1427         "    (XAUI Mode only)\n";
1428     fail |= cvmx_error_add(&info);
1429
1430     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1431     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1432     info.status_mask        = 1ull<<22 /* bad_seq */;
1433     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1434     info.enable_mask        = 1ull<<22 /* bad_seq */;
1435     info.flags              = 0;
1436     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1437     info.group_index        = 2;
1438     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1439     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1440     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1441     info.func               = __cvmx_error_display;
1442     info.user_info          = (long)
1443         "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1444         "    (XAUI Mode only)\n";
1445     fail |= cvmx_error_add(&info);
1446
1447     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1448     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1449     info.status_mask        = 1ull<<23 /* bad_term */;
1450     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1451     info.enable_mask        = 1ull<<23 /* bad_term */;
1452     info.flags              = 0;
1453     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1454     info.group_index        = 2;
1455     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1456     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1457     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1458     info.func               = __cvmx_error_display;
1459     info.user_info          = (long)
1460         "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
1461         "    than /T/.  The error propagation control\n"
1462         "    character /E/ will be included as part of the\n"
1463         "    frame and does not cause a frame termination.\n"
1464         "    (XAUI Mode only)\n";
1465     fail |= cvmx_error_add(&info);
1466
1467     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1468     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1469     info.status_mask        = 1ull<<24 /* unsop */;
1470     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1471     info.enable_mask        = 1ull<<24 /* unsop */;
1472     info.flags              = 0;
1473     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1474     info.group_index        = 2;
1475     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1476     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1477     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1478     info.func               = __cvmx_error_display;
1479     info.user_info          = (long)
1480         "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
1481         "    (XAUI Mode only)\n";
1482     fail |= cvmx_error_add(&info);
1483
1484     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1485     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1486     info.status_mask        = 1ull<<25 /* uneop */;
1487     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1488     info.enable_mask        = 1ull<<25 /* uneop */;
1489     info.flags              = 0;
1490     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1491     info.group_index        = 2;
1492     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1493     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1494     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1495     info.func               = __cvmx_error_display;
1496     info.user_info          = (long)
1497         "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
1498         "    (XAUI Mode only)\n";
1499     fail |= cvmx_error_add(&info);
1500
1501     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1502     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1503     info.status_mask        = 1ull<<26 /* undat */;
1504     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1505     info.enable_mask        = 1ull<<26 /* undat */;
1506     info.flags              = 0;
1507     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1508     info.group_index        = 2;
1509     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1510     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1511     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1512     info.func               = __cvmx_error_display;
1513     info.user_info          = (long)
1514         "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
1515         "    (XAUI Mode only)\n";
1516     fail |= cvmx_error_add(&info);
1517
1518     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1519     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1520     info.status_mask        = 1ull<<27 /* hg2fld */;
1521     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1522     info.enable_mask        = 1ull<<27 /* hg2fld */;
1523     info.flags              = 0;
1524     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1525     info.group_index        = 2;
1526     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1527     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1528     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1529     info.func               = __cvmx_error_display;
1530     info.user_info          = (long)
1531         "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1532         "    1) MSG_TYPE field not 6'b00_0000\n"
1533         "       i.e. it is not a FLOW CONTROL message, which\n"
1534         "       is the only defined type for HiGig2\n"
1535         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1536         "       which is the only defined type for HiGig2\n"
1537         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1538         "       Physical Link nor 4'b0010 for Logical Link.\n"
1539         "       Those are the only two defined types in HiGig2\n";
1540     fail |= cvmx_error_add(&info);
1541
1542     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1543     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
1544     info.status_mask        = 1ull<<28 /* hg2cc */;
1545     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
1546     info.enable_mask        = 1ull<<28 /* hg2cc */;
1547     info.flags              = 0;
1548     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1549     info.group_index        = 2;
1550     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1551     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1552     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1553     info.func               = __cvmx_error_display;
1554     info.user_info          = (long)
1555         "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1556         "    Set when either CRC8 error detected or when\n"
1557         "    a Control Character is found in the message\n"
1558         "    bytes after the K.SOM\n"
1559         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1560         "          i.e. a HiGig2 message that results in HG2CC\n"
1561         "          getting set, will never set HG2FLD.\n";
1562     fail |= cvmx_error_add(&info);
1563
1564     /* CVMX_GMXX_RXX_INT_REG(3,0) */
1565     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1566     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1567     info.status_mask        = 1ull<<1 /* carext */;
1568     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1569     info.enable_mask        = 1ull<<1 /* carext */;
1570     info.flags              = 0;
1571     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1572     info.group_index        = 3;
1573     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1574     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1575     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1576     info.func               = __cvmx_error_display;
1577     info.user_info          = (long)
1578         "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
1579         "    (SGMII/1000Base-X only)\n";
1580     fail |= cvmx_error_add(&info);
1581
1582     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1583     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1584     info.status_mask        = 1ull<<8 /* skperr */;
1585     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1586     info.enable_mask        = 1ull<<8 /* skperr */;
1587     info.flags              = 0;
1588     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1589     info.group_index        = 3;
1590     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1591     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1592     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1593     info.func               = __cvmx_error_display;
1594     info.user_info          = (long)
1595         "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
1596     fail |= cvmx_error_add(&info);
1597
1598     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1599     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1600     info.status_mask        = 1ull<<10 /* ovrerr */;
1601     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1602     info.enable_mask        = 1ull<<10 /* ovrerr */;
1603     info.flags              = 0;
1604     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1605     info.group_index        = 3;
1606     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1607     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1608     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1609     info.func               = __cvmx_error_display;
1610     info.user_info          = (long)
1611         "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1612         "    This interrupt should never assert\n"
1613         "    (SGMII/1000Base-X only)\n";
1614     fail |= cvmx_error_add(&info);
1615
1616     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1617     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1618     info.status_mask        = 1ull<<20 /* loc_fault */;
1619     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1620     info.enable_mask        = 1ull<<20 /* loc_fault */;
1621     info.flags              = 0;
1622     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1623     info.group_index        = 3;
1624     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1625     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1626     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1627     info.func               = __cvmx_error_display;
1628     info.user_info          = (long)
1629         "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1630         "    (XAUI Mode only)\n";
1631     fail |= cvmx_error_add(&info);
1632
1633     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1634     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1635     info.status_mask        = 1ull<<21 /* rem_fault */;
1636     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1637     info.enable_mask        = 1ull<<21 /* rem_fault */;
1638     info.flags              = 0;
1639     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1640     info.group_index        = 3;
1641     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1642     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1643     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1644     info.func               = __cvmx_error_display;
1645     info.user_info          = (long)
1646         "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1647         "    (XAUI Mode only)\n";
1648     fail |= cvmx_error_add(&info);
1649
1650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1651     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1652     info.status_mask        = 1ull<<22 /* bad_seq */;
1653     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1654     info.enable_mask        = 1ull<<22 /* bad_seq */;
1655     info.flags              = 0;
1656     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1657     info.group_index        = 3;
1658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1659     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1660     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1661     info.func               = __cvmx_error_display;
1662     info.user_info          = (long)
1663         "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1664         "    (XAUI Mode only)\n";
1665     fail |= cvmx_error_add(&info);
1666
1667     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1668     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1669     info.status_mask        = 1ull<<23 /* bad_term */;
1670     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1671     info.enable_mask        = 1ull<<23 /* bad_term */;
1672     info.flags              = 0;
1673     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1674     info.group_index        = 3;
1675     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1676     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1677     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1678     info.func               = __cvmx_error_display;
1679     info.user_info          = (long)
1680         "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
1681         "    than /T/.  The error propagation control\n"
1682         "    character /E/ will be included as part of the\n"
1683         "    frame and does not cause a frame termination.\n"
1684         "    (XAUI Mode only)\n";
1685     fail |= cvmx_error_add(&info);
1686
1687     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1688     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1689     info.status_mask        = 1ull<<24 /* unsop */;
1690     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1691     info.enable_mask        = 1ull<<24 /* unsop */;
1692     info.flags              = 0;
1693     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1694     info.group_index        = 3;
1695     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1696     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1697     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1698     info.func               = __cvmx_error_display;
1699     info.user_info          = (long)
1700         "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
1701         "    (XAUI Mode only)\n";
1702     fail |= cvmx_error_add(&info);
1703
1704     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1705     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1706     info.status_mask        = 1ull<<25 /* uneop */;
1707     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1708     info.enable_mask        = 1ull<<25 /* uneop */;
1709     info.flags              = 0;
1710     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1711     info.group_index        = 3;
1712     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1713     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1714     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1715     info.func               = __cvmx_error_display;
1716     info.user_info          = (long)
1717         "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
1718         "    (XAUI Mode only)\n";
1719     fail |= cvmx_error_add(&info);
1720
1721     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1722     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1723     info.status_mask        = 1ull<<26 /* undat */;
1724     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1725     info.enable_mask        = 1ull<<26 /* undat */;
1726     info.flags              = 0;
1727     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1728     info.group_index        = 3;
1729     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1730     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1731     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1732     info.func               = __cvmx_error_display;
1733     info.user_info          = (long)
1734         "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
1735         "    (XAUI Mode only)\n";
1736     fail |= cvmx_error_add(&info);
1737
1738     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1739     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1740     info.status_mask        = 1ull<<27 /* hg2fld */;
1741     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1742     info.enable_mask        = 1ull<<27 /* hg2fld */;
1743     info.flags              = 0;
1744     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1745     info.group_index        = 3;
1746     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1747     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1748     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1749     info.func               = __cvmx_error_display;
1750     info.user_info          = (long)
1751         "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1752         "    1) MSG_TYPE field not 6'b00_0000\n"
1753         "       i.e. it is not a FLOW CONTROL message, which\n"
1754         "       is the only defined type for HiGig2\n"
1755         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1756         "       which is the only defined type for HiGig2\n"
1757         "    3) FC_OBJECT field is neither 4'b0000 for\n"
1758         "       Physical Link nor 4'b0010 for Logical Link.\n"
1759         "       Those are the only two defined types in HiGig2\n";
1760     fail |= cvmx_error_add(&info);
1761
1762     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1763     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
1764     info.status_mask        = 1ull<<28 /* hg2cc */;
1765     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
1766     info.enable_mask        = 1ull<<28 /* hg2cc */;
1767     info.flags              = 0;
1768     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1769     info.group_index        = 3;
1770     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1771     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1772     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1773     info.func               = __cvmx_error_display;
1774     info.user_info          = (long)
1775         "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
1776         "    Set when either CRC8 error detected or when\n"
1777         "    a Control Character is found in the message\n"
1778         "    bytes after the K.SOM\n"
1779         "    NOTE: HG2CC has higher priority than HG2FLD\n"
1780         "          i.e. a HiGig2 message that results in HG2CC\n"
1781         "          getting set, will never set HG2FLD.\n";
1782     fail |= cvmx_error_add(&info);
1783
1784     /* CVMX_GMXX_TX_INT_REG(0) */
1785     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1786     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
1787     info.status_mask        = 1ull<<0 /* pko_nxa */;
1788     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
1789     info.enable_mask        = 1ull<<0 /* pko_nxa */;
1790     info.flags              = 0;
1791     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1792     info.group_index        = 0;
1793     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1794     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1795     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1796     info.func               = __cvmx_error_display;
1797     info.user_info          = (long)
1798         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
1799     fail |= cvmx_error_add(&info);
1800
1801     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1802     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
1803     info.status_mask        = 0xfull<<2 /* undflw */;
1804     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
1805     info.enable_mask        = 0xfull<<2 /* undflw */;
1806     info.flags              = 0;
1807     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1808     info.group_index        = 0;
1809     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1810     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1811     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1812     info.func               = __cvmx_error_display;
1813     info.user_info          = (long)
1814         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
1815     fail |= cvmx_error_add(&info);
1816
1817     /* CVMX_GMXX_BAD_REG(1) */
1818     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1819     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1820     info.status_mask        = 0xfull<<2 /* out_ovr */;
1821     info.enable_addr        = 0;
1822     info.enable_mask        = 0;
1823     info.flags              = 0;
1824     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1825     info.group_index        = 16;
1826     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1827     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1828     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1829     info.func               = __cvmx_error_display;
1830     info.user_info          = (long)
1831         "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1832     fail |= cvmx_error_add(&info);
1833
1834     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1835     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1836     info.status_mask        = 0xfull<<22 /* loststat */;
1837     info.enable_addr        = 0;
1838     info.enable_mask        = 0;
1839     info.flags              = 0;
1840     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1841     info.group_index        = 16;
1842     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1843     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1844     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1845     info.func               = __cvmx_error_display;
1846     info.user_info          = (long)
1847         "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
1848         "    In SGMII, one bit per port\n"
1849         "    In XAUI, only port0 is used\n"
1850         "    TX Stats are corrupted\n";
1851     fail |= cvmx_error_add(&info);
1852
1853     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1854     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1855     info.status_mask        = 1ull<<26 /* statovr */;
1856     info.enable_addr        = 0;
1857     info.enable_mask        = 0;
1858     info.flags              = 0;
1859     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1860     info.group_index        = 16;
1861     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1862     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1863     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1864     info.func               = __cvmx_error_display;
1865     info.user_info          = (long)
1866         "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
1867         "    The common FIFO to SGMII and XAUI had an overflow\n"
1868         "    TX Stats are corrupted\n";
1869     fail |= cvmx_error_add(&info);
1870
1871     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1872     info.status_addr        = CVMX_GMXX_BAD_REG(1);
1873     info.status_mask        = 0xfull<<27 /* inb_nxa */;
1874     info.enable_addr        = 0;
1875     info.enable_mask        = 0;
1876     info.flags              = 0;
1877     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1878     info.group_index        = 16;
1879     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1880     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1881     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1882     info.func               = __cvmx_error_display;
1883     info.user_info          = (long)
1884         "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1885     fail |= cvmx_error_add(&info);
1886
1887     /* CVMX_GMXX_RXX_INT_REG(0,1) */
1888     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1889     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1890     info.status_mask        = 1ull<<1 /* carext */;
1891     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1892     info.enable_mask        = 1ull<<1 /* carext */;
1893     info.flags              = 0;
1894     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1895     info.group_index        = 16;
1896     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1897     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1898     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1899     info.func               = __cvmx_error_display;
1900     info.user_info          = (long)
1901         "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
1902         "    (SGMII/1000Base-X only)\n";
1903     fail |= cvmx_error_add(&info);
1904
1905     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1906     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1907     info.status_mask        = 1ull<<8 /* skperr */;
1908     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1909     info.enable_mask        = 1ull<<8 /* skperr */;
1910     info.flags              = 0;
1911     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1912     info.group_index        = 16;
1913     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1914     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1915     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1916     info.func               = __cvmx_error_display;
1917     info.user_info          = (long)
1918         "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
1919     fail |= cvmx_error_add(&info);
1920
1921     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1922     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1923     info.status_mask        = 1ull<<10 /* ovrerr */;
1924     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1925     info.enable_mask        = 1ull<<10 /* ovrerr */;
1926     info.flags              = 0;
1927     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1928     info.group_index        = 16;
1929     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1930     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1931     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1932     info.func               = __cvmx_error_display;
1933     info.user_info          = (long)
1934         "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
1935         "    This interrupt should never assert\n"
1936         "    (SGMII/1000Base-X only)\n";
1937     fail |= cvmx_error_add(&info);
1938
1939     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1940     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1941     info.status_mask        = 1ull<<20 /* loc_fault */;
1942     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1943     info.enable_mask        = 1ull<<20 /* loc_fault */;
1944     info.flags              = 0;
1945     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1946     info.group_index        = 16;
1947     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1948     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1949     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1950     info.func               = __cvmx_error_display;
1951     info.user_info          = (long)
1952         "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1953         "    (XAUI Mode only)\n";
1954     fail |= cvmx_error_add(&info);
1955
1956     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1957     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1958     info.status_mask        = 1ull<<21 /* rem_fault */;
1959     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1960     info.enable_mask        = 1ull<<21 /* rem_fault */;
1961     info.flags              = 0;
1962     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1963     info.group_index        = 16;
1964     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1965     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1966     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1967     info.func               = __cvmx_error_display;
1968     info.user_info          = (long)
1969         "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1970         "    (XAUI Mode only)\n";
1971     fail |= cvmx_error_add(&info);
1972
1973     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1974     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1975     info.status_mask        = 1ull<<22 /* bad_seq */;
1976     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1977     info.enable_mask        = 1ull<<22 /* bad_seq */;
1978     info.flags              = 0;
1979     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1980     info.group_index        = 16;
1981     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1982     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1983     info.parent.status_mask = 1ull<<2 /* gmx1 */;
1984     info.func               = __cvmx_error_display;
1985     info.user_info          = (long)
1986         "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
1987         "    (XAUI Mode only)\n";
1988     fail |= cvmx_error_add(&info);
1989
1990     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1991     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
1992     info.status_mask        = 1ull<<23 /* bad_term */;
1993     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
1994     info.enable_mask        = 1ull<<23 /* bad_term */;
1995     info.flags              = 0;
1996     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1997     info.group_index        = 16;
1998     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1999     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2000     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2001     info.func               = __cvmx_error_display;
2002     info.user_info          = (long)
2003         "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
2004         "    than /T/.  The error propagation control\n"
2005         "    character /E/ will be included as part of the\n"
2006         "    frame and does not cause a frame termination.\n"
2007         "    (XAUI Mode only)\n";
2008     fail |= cvmx_error_add(&info);
2009
2010     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2011     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2012     info.status_mask        = 1ull<<24 /* unsop */;
2013     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2014     info.enable_mask        = 1ull<<24 /* unsop */;
2015     info.flags              = 0;
2016     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2017     info.group_index        = 16;
2018     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2019     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2020     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2021     info.func               = __cvmx_error_display;
2022     info.user_info          = (long)
2023         "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
2024         "    (XAUI Mode only)\n";
2025     fail |= cvmx_error_add(&info);
2026
2027     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2028     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2029     info.status_mask        = 1ull<<25 /* uneop */;
2030     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2031     info.enable_mask        = 1ull<<25 /* uneop */;
2032     info.flags              = 0;
2033     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2034     info.group_index        = 16;
2035     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2036     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2037     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2038     info.func               = __cvmx_error_display;
2039     info.user_info          = (long)
2040         "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
2041         "    (XAUI Mode only)\n";
2042     fail |= cvmx_error_add(&info);
2043
2044     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2045     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2046     info.status_mask        = 1ull<<26 /* undat */;
2047     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2048     info.enable_mask        = 1ull<<26 /* undat */;
2049     info.flags              = 0;
2050     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2051     info.group_index        = 16;
2052     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2053     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2054     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2055     info.func               = __cvmx_error_display;
2056     info.user_info          = (long)
2057         "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
2058         "    (XAUI Mode only)\n";
2059     fail |= cvmx_error_add(&info);
2060
2061     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2062     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2063     info.status_mask        = 1ull<<27 /* hg2fld */;
2064     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2065     info.enable_mask        = 1ull<<27 /* hg2fld */;
2066     info.flags              = 0;
2067     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2068     info.group_index        = 16;
2069     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2070     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2071     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2072     info.func               = __cvmx_error_display;
2073     info.user_info          = (long)
2074         "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
2075         "    1) MSG_TYPE field not 6'b00_0000\n"
2076         "       i.e. it is not a FLOW CONTROL message, which\n"
2077         "       is the only defined type for HiGig2\n"
2078         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
2079         "       which is the only defined type for HiGig2\n"
2080         "    3) FC_OBJECT field is neither 4'b0000 for\n"
2081         "       Physical Link nor 4'b0010 for Logical Link.\n"
2082         "       Those are the only two defined types in HiGig2\n";
2083     fail |= cvmx_error_add(&info);
2084
2085     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2086     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2087     info.status_mask        = 1ull<<28 /* hg2cc */;
2088     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2089     info.enable_mask        = 1ull<<28 /* hg2cc */;
2090     info.flags              = 0;
2091     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2092     info.group_index        = 16;
2093     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2094     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2095     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2096     info.func               = __cvmx_error_display;
2097     info.user_info          = (long)
2098         "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
2099         "    Set when either CRC8 error detected or when\n"
2100         "    a Control Character is found in the message\n"
2101         "    bytes after the K.SOM\n"
2102         "    NOTE: HG2CC has higher priority than HG2FLD\n"
2103         "          i.e. a HiGig2 message that results in HG2CC\n"
2104         "          getting set, will never set HG2FLD.\n";
2105     fail |= cvmx_error_add(&info);
2106
2107     /* CVMX_GMXX_RXX_INT_REG(1,1) */
2108     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2109     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2110     info.status_mask        = 1ull<<1 /* carext */;
2111     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2112     info.enable_mask        = 1ull<<1 /* carext */;
2113     info.flags              = 0;
2114     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2115     info.group_index        = 17;
2116     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2117     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2118     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2119     info.func               = __cvmx_error_display;
2120     info.user_info          = (long)
2121         "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
2122         "    (SGMII/1000Base-X only)\n";
2123     fail |= cvmx_error_add(&info);
2124
2125     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2126     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2127     info.status_mask        = 1ull<<8 /* skperr */;
2128     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2129     info.enable_mask        = 1ull<<8 /* skperr */;
2130     info.flags              = 0;
2131     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2132     info.group_index        = 17;
2133     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2134     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2135     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2136     info.func               = __cvmx_error_display;
2137     info.user_info          = (long)
2138         "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
2139     fail |= cvmx_error_add(&info);
2140
2141     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2142     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2143     info.status_mask        = 1ull<<10 /* ovrerr */;
2144     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2145     info.enable_mask        = 1ull<<10 /* ovrerr */;
2146     info.flags              = 0;
2147     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2148     info.group_index        = 17;
2149     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2150     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2151     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2152     info.func               = __cvmx_error_display;
2153     info.user_info          = (long)
2154         "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2155         "    This interrupt should never assert\n"
2156         "    (SGMII/1000Base-X only)\n";
2157     fail |= cvmx_error_add(&info);
2158
2159     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2160     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2161     info.status_mask        = 1ull<<20 /* loc_fault */;
2162     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2163     info.enable_mask        = 1ull<<20 /* loc_fault */;
2164     info.flags              = 0;
2165     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2166     info.group_index        = 17;
2167     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2168     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2169     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2170     info.func               = __cvmx_error_display;
2171     info.user_info          = (long)
2172         "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
2173         "    (XAUI Mode only)\n";
2174     fail |= cvmx_error_add(&info);
2175
2176     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2177     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2178     info.status_mask        = 1ull<<21 /* rem_fault */;
2179     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2180     info.enable_mask        = 1ull<<21 /* rem_fault */;
2181     info.flags              = 0;
2182     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2183     info.group_index        = 17;
2184     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2185     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2186     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2187     info.func               = __cvmx_error_display;
2188     info.user_info          = (long)
2189         "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
2190         "    (XAUI Mode only)\n";
2191     fail |= cvmx_error_add(&info);
2192
2193     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2194     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2195     info.status_mask        = 1ull<<22 /* bad_seq */;
2196     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2197     info.enable_mask        = 1ull<<22 /* bad_seq */;
2198     info.flags              = 0;
2199     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2200     info.group_index        = 17;
2201     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2202     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2203     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2204     info.func               = __cvmx_error_display;
2205     info.user_info          = (long)
2206         "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
2207         "    (XAUI Mode only)\n";
2208     fail |= cvmx_error_add(&info);
2209
2210     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2211     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2212     info.status_mask        = 1ull<<23 /* bad_term */;
2213     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2214     info.enable_mask        = 1ull<<23 /* bad_term */;
2215     info.flags              = 0;
2216     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2217     info.group_index        = 17;
2218     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2219     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2220     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2221     info.func               = __cvmx_error_display;
2222     info.user_info          = (long)
2223         "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
2224         "    than /T/.  The error propagation control\n"
2225         "    character /E/ will be included as part of the\n"
2226         "    frame and does not cause a frame termination.\n"
2227         "    (XAUI Mode only)\n";
2228     fail |= cvmx_error_add(&info);
2229
2230     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2231     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2232     info.status_mask        = 1ull<<24 /* unsop */;
2233     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2234     info.enable_mask        = 1ull<<24 /* unsop */;
2235     info.flags              = 0;
2236     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2237     info.group_index        = 17;
2238     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2239     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2240     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2241     info.func               = __cvmx_error_display;
2242     info.user_info          = (long)
2243         "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
2244         "    (XAUI Mode only)\n";
2245     fail |= cvmx_error_add(&info);
2246
2247     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2248     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2249     info.status_mask        = 1ull<<25 /* uneop */;
2250     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2251     info.enable_mask        = 1ull<<25 /* uneop */;
2252     info.flags              = 0;
2253     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2254     info.group_index        = 17;
2255     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2256     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2257     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2258     info.func               = __cvmx_error_display;
2259     info.user_info          = (long)
2260         "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
2261         "    (XAUI Mode only)\n";
2262     fail |= cvmx_error_add(&info);
2263
2264     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2265     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2266     info.status_mask        = 1ull<<26 /* undat */;
2267     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2268     info.enable_mask        = 1ull<<26 /* undat */;
2269     info.flags              = 0;
2270     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2271     info.group_index        = 17;
2272     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2273     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2274     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2275     info.func               = __cvmx_error_display;
2276     info.user_info          = (long)
2277         "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
2278         "    (XAUI Mode only)\n";
2279     fail |= cvmx_error_add(&info);
2280
2281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2282     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2283     info.status_mask        = 1ull<<27 /* hg2fld */;
2284     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2285     info.enable_mask        = 1ull<<27 /* hg2fld */;
2286     info.flags              = 0;
2287     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2288     info.group_index        = 17;
2289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2290     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2291     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2292     info.func               = __cvmx_error_display;
2293     info.user_info          = (long)
2294         "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
2295         "    1) MSG_TYPE field not 6'b00_0000\n"
2296         "       i.e. it is not a FLOW CONTROL message, which\n"
2297         "       is the only defined type for HiGig2\n"
2298         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
2299         "       which is the only defined type for HiGig2\n"
2300         "    3) FC_OBJECT field is neither 4'b0000 for\n"
2301         "       Physical Link nor 4'b0010 for Logical Link.\n"
2302         "       Those are the only two defined types in HiGig2\n";
2303     fail |= cvmx_error_add(&info);
2304
2305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2306     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2307     info.status_mask        = 1ull<<28 /* hg2cc */;
2308     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2309     info.enable_mask        = 1ull<<28 /* hg2cc */;
2310     info.flags              = 0;
2311     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2312     info.group_index        = 17;
2313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2314     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2315     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2316     info.func               = __cvmx_error_display;
2317     info.user_info          = (long)
2318         "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
2319         "    Set when either CRC8 error detected or when\n"
2320         "    a Control Character is found in the message\n"
2321         "    bytes after the K.SOM\n"
2322         "    NOTE: HG2CC has higher priority than HG2FLD\n"
2323         "          i.e. a HiGig2 message that results in HG2CC\n"
2324         "          getting set, will never set HG2FLD.\n";
2325     fail |= cvmx_error_add(&info);
2326
2327     /* CVMX_GMXX_RXX_INT_REG(2,1) */
2328     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2329     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2330     info.status_mask        = 1ull<<1 /* carext */;
2331     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2332     info.enable_mask        = 1ull<<1 /* carext */;
2333     info.flags              = 0;
2334     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2335     info.group_index        = 18;
2336     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2337     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2338     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2339     info.func               = __cvmx_error_display;
2340     info.user_info          = (long)
2341         "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
2342         "    (SGMII/1000Base-X only)\n";
2343     fail |= cvmx_error_add(&info);
2344
2345     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2346     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2347     info.status_mask        = 1ull<<8 /* skperr */;
2348     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2349     info.enable_mask        = 1ull<<8 /* skperr */;
2350     info.flags              = 0;
2351     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2352     info.group_index        = 18;
2353     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2354     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2355     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2356     info.func               = __cvmx_error_display;
2357     info.user_info          = (long)
2358         "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
2359     fail |= cvmx_error_add(&info);
2360
2361     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2362     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2363     info.status_mask        = 1ull<<10 /* ovrerr */;
2364     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2365     info.enable_mask        = 1ull<<10 /* ovrerr */;
2366     info.flags              = 0;
2367     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2368     info.group_index        = 18;
2369     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2370     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2371     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2372     info.func               = __cvmx_error_display;
2373     info.user_info          = (long)
2374         "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2375         "    This interrupt should never assert\n"
2376         "    (SGMII/1000Base-X only)\n";
2377     fail |= cvmx_error_add(&info);
2378
2379     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2380     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2381     info.status_mask        = 1ull<<20 /* loc_fault */;
2382     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2383     info.enable_mask        = 1ull<<20 /* loc_fault */;
2384     info.flags              = 0;
2385     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2386     info.group_index        = 18;
2387     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2388     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2389     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2390     info.func               = __cvmx_error_display;
2391     info.user_info          = (long)
2392         "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
2393         "    (XAUI Mode only)\n";
2394     fail |= cvmx_error_add(&info);
2395
2396     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2397     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2398     info.status_mask        = 1ull<<21 /* rem_fault */;
2399     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2400     info.enable_mask        = 1ull<<21 /* rem_fault */;
2401     info.flags              = 0;
2402     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2403     info.group_index        = 18;
2404     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2405     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2406     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2407     info.func               = __cvmx_error_display;
2408     info.user_info          = (long)
2409         "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
2410         "    (XAUI Mode only)\n";
2411     fail |= cvmx_error_add(&info);
2412
2413     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2414     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2415     info.status_mask        = 1ull<<22 /* bad_seq */;
2416     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2417     info.enable_mask        = 1ull<<22 /* bad_seq */;
2418     info.flags              = 0;
2419     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2420     info.group_index        = 18;
2421     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2422     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2423     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2424     info.func               = __cvmx_error_display;
2425     info.user_info          = (long)
2426         "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
2427         "    (XAUI Mode only)\n";
2428     fail |= cvmx_error_add(&info);
2429
2430     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2431     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2432     info.status_mask        = 1ull<<23 /* bad_term */;
2433     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2434     info.enable_mask        = 1ull<<23 /* bad_term */;
2435     info.flags              = 0;
2436     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2437     info.group_index        = 18;
2438     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2439     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2440     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2441     info.func               = __cvmx_error_display;
2442     info.user_info          = (long)
2443         "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
2444         "    than /T/.  The error propagation control\n"
2445         "    character /E/ will be included as part of the\n"
2446         "    frame and does not cause a frame termination.\n"
2447         "    (XAUI Mode only)\n";
2448     fail |= cvmx_error_add(&info);
2449
2450     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2451     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2452     info.status_mask        = 1ull<<24 /* unsop */;
2453     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2454     info.enable_mask        = 1ull<<24 /* unsop */;
2455     info.flags              = 0;
2456     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2457     info.group_index        = 18;
2458     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2459     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2460     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2461     info.func               = __cvmx_error_display;
2462     info.user_info          = (long)
2463         "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
2464         "    (XAUI Mode only)\n";
2465     fail |= cvmx_error_add(&info);
2466
2467     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2468     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2469     info.status_mask        = 1ull<<25 /* uneop */;
2470     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2471     info.enable_mask        = 1ull<<25 /* uneop */;
2472     info.flags              = 0;
2473     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2474     info.group_index        = 18;
2475     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2476     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2477     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2478     info.func               = __cvmx_error_display;
2479     info.user_info          = (long)
2480         "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
2481         "    (XAUI Mode only)\n";
2482     fail |= cvmx_error_add(&info);
2483
2484     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2485     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2486     info.status_mask        = 1ull<<26 /* undat */;
2487     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2488     info.enable_mask        = 1ull<<26 /* undat */;
2489     info.flags              = 0;
2490     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2491     info.group_index        = 18;
2492     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2493     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2494     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2495     info.func               = __cvmx_error_display;
2496     info.user_info          = (long)
2497         "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
2498         "    (XAUI Mode only)\n";
2499     fail |= cvmx_error_add(&info);
2500
2501     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2502     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2503     info.status_mask        = 1ull<<27 /* hg2fld */;
2504     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2505     info.enable_mask        = 1ull<<27 /* hg2fld */;
2506     info.flags              = 0;
2507     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2508     info.group_index        = 18;
2509     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2510     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2511     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2512     info.func               = __cvmx_error_display;
2513     info.user_info          = (long)
2514         "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
2515         "    1) MSG_TYPE field not 6'b00_0000\n"
2516         "       i.e. it is not a FLOW CONTROL message, which\n"
2517         "       is the only defined type for HiGig2\n"
2518         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
2519         "       which is the only defined type for HiGig2\n"
2520         "    3) FC_OBJECT field is neither 4'b0000 for\n"
2521         "       Physical Link nor 4'b0010 for Logical Link.\n"
2522         "       Those are the only two defined types in HiGig2\n";
2523     fail |= cvmx_error_add(&info);
2524
2525     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2526     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2527     info.status_mask        = 1ull<<28 /* hg2cc */;
2528     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2529     info.enable_mask        = 1ull<<28 /* hg2cc */;
2530     info.flags              = 0;
2531     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2532     info.group_index        = 18;
2533     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2534     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2535     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2536     info.func               = __cvmx_error_display;
2537     info.user_info          = (long)
2538         "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
2539         "    Set when either CRC8 error detected or when\n"
2540         "    a Control Character is found in the message\n"
2541         "    bytes after the K.SOM\n"
2542         "    NOTE: HG2CC has higher priority than HG2FLD\n"
2543         "          i.e. a HiGig2 message that results in HG2CC\n"
2544         "          getting set, will never set HG2FLD.\n";
2545     fail |= cvmx_error_add(&info);
2546
2547     /* CVMX_GMXX_RXX_INT_REG(3,1) */
2548     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2549     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2550     info.status_mask        = 1ull<<1 /* carext */;
2551     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2552     info.enable_mask        = 1ull<<1 /* carext */;
2553     info.flags              = 0;
2554     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2555     info.group_index        = 19;
2556     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2557     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2558     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2559     info.func               = __cvmx_error_display;
2560     info.user_info          = (long)
2561         "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
2562         "    (SGMII/1000Base-X only)\n";
2563     fail |= cvmx_error_add(&info);
2564
2565     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2566     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2567     info.status_mask        = 1ull<<8 /* skperr */;
2568     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2569     info.enable_mask        = 1ull<<8 /* skperr */;
2570     info.flags              = 0;
2571     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2572     info.group_index        = 19;
2573     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2574     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2575     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2576     info.func               = __cvmx_error_display;
2577     info.user_info          = (long)
2578         "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
2579     fail |= cvmx_error_add(&info);
2580
2581     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2582     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2583     info.status_mask        = 1ull<<10 /* ovrerr */;
2584     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2585     info.enable_mask        = 1ull<<10 /* ovrerr */;
2586     info.flags              = 0;
2587     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2588     info.group_index        = 19;
2589     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2590     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2591     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2592     info.func               = __cvmx_error_display;
2593     info.user_info          = (long)
2594         "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2595         "    This interrupt should never assert\n"
2596         "    (SGMII/1000Base-X only)\n";
2597     fail |= cvmx_error_add(&info);
2598
2599     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2600     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2601     info.status_mask        = 1ull<<20 /* loc_fault */;
2602     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2603     info.enable_mask        = 1ull<<20 /* loc_fault */;
2604     info.flags              = 0;
2605     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2606     info.group_index        = 19;
2607     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2608     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2609     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2610     info.func               = __cvmx_error_display;
2611     info.user_info          = (long)
2612         "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
2613         "    (XAUI Mode only)\n";
2614     fail |= cvmx_error_add(&info);
2615
2616     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2617     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2618     info.status_mask        = 1ull<<21 /* rem_fault */;
2619     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2620     info.enable_mask        = 1ull<<21 /* rem_fault */;
2621     info.flags              = 0;
2622     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2623     info.group_index        = 19;
2624     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2625     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2626     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2627     info.func               = __cvmx_error_display;
2628     info.user_info          = (long)
2629         "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
2630         "    (XAUI Mode only)\n";
2631     fail |= cvmx_error_add(&info);
2632
2633     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2634     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2635     info.status_mask        = 1ull<<22 /* bad_seq */;
2636     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2637     info.enable_mask        = 1ull<<22 /* bad_seq */;
2638     info.flags              = 0;
2639     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2640     info.group_index        = 19;
2641     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2642     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2643     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2644     info.func               = __cvmx_error_display;
2645     info.user_info          = (long)
2646         "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
2647         "    (XAUI Mode only)\n";
2648     fail |= cvmx_error_add(&info);
2649
2650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2651     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2652     info.status_mask        = 1ull<<23 /* bad_term */;
2653     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2654     info.enable_mask        = 1ull<<23 /* bad_term */;
2655     info.flags              = 0;
2656     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2657     info.group_index        = 19;
2658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2659     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2660     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2661     info.func               = __cvmx_error_display;
2662     info.user_info          = (long)
2663         "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
2664         "    than /T/.  The error propagation control\n"
2665         "    character /E/ will be included as part of the\n"
2666         "    frame and does not cause a frame termination.\n"
2667         "    (XAUI Mode only)\n";
2668     fail |= cvmx_error_add(&info);
2669
2670     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2671     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2672     info.status_mask        = 1ull<<24 /* unsop */;
2673     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2674     info.enable_mask        = 1ull<<24 /* unsop */;
2675     info.flags              = 0;
2676     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2677     info.group_index        = 19;
2678     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2679     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2680     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2681     info.func               = __cvmx_error_display;
2682     info.user_info          = (long)
2683         "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
2684         "    (XAUI Mode only)\n";
2685     fail |= cvmx_error_add(&info);
2686
2687     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2688     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2689     info.status_mask        = 1ull<<25 /* uneop */;
2690     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2691     info.enable_mask        = 1ull<<25 /* uneop */;
2692     info.flags              = 0;
2693     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2694     info.group_index        = 19;
2695     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2696     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2697     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2698     info.func               = __cvmx_error_display;
2699     info.user_info          = (long)
2700         "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
2701         "    (XAUI Mode only)\n";
2702     fail |= cvmx_error_add(&info);
2703
2704     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2705     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2706     info.status_mask        = 1ull<<26 /* undat */;
2707     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2708     info.enable_mask        = 1ull<<26 /* undat */;
2709     info.flags              = 0;
2710     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2711     info.group_index        = 19;
2712     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2713     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2714     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2715     info.func               = __cvmx_error_display;
2716     info.user_info          = (long)
2717         "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
2718         "    (XAUI Mode only)\n";
2719     fail |= cvmx_error_add(&info);
2720
2721     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2722     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2723     info.status_mask        = 1ull<<27 /* hg2fld */;
2724     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2725     info.enable_mask        = 1ull<<27 /* hg2fld */;
2726     info.flags              = 0;
2727     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2728     info.group_index        = 19;
2729     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2730     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2731     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2732     info.func               = __cvmx_error_display;
2733     info.user_info          = (long)
2734         "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
2735         "    1) MSG_TYPE field not 6'b00_0000\n"
2736         "       i.e. it is not a FLOW CONTROL message, which\n"
2737         "       is the only defined type for HiGig2\n"
2738         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
2739         "       which is the only defined type for HiGig2\n"
2740         "    3) FC_OBJECT field is neither 4'b0000 for\n"
2741         "       Physical Link nor 4'b0010 for Logical Link.\n"
2742         "       Those are the only two defined types in HiGig2\n";
2743     fail |= cvmx_error_add(&info);
2744
2745     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2746     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2747     info.status_mask        = 1ull<<28 /* hg2cc */;
2748     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2749     info.enable_mask        = 1ull<<28 /* hg2cc */;
2750     info.flags              = 0;
2751     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2752     info.group_index        = 19;
2753     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2754     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2755     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2756     info.func               = __cvmx_error_display;
2757     info.user_info          = (long)
2758         "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
2759         "    Set when either CRC8 error detected or when\n"
2760         "    a Control Character is found in the message\n"
2761         "    bytes after the K.SOM\n"
2762         "    NOTE: HG2CC has higher priority than HG2FLD\n"
2763         "          i.e. a HiGig2 message that results in HG2CC\n"
2764         "          getting set, will never set HG2FLD.\n";
2765     fail |= cvmx_error_add(&info);
2766
2767     /* CVMX_GMXX_TX_INT_REG(1) */
2768     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2769     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2770     info.status_mask        = 1ull<<0 /* pko_nxa */;
2771     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2772     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2773     info.flags              = 0;
2774     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2775     info.group_index        = 16;
2776     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2777     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2778     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2779     info.func               = __cvmx_error_display;
2780     info.user_info          = (long)
2781         "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2782     fail |= cvmx_error_add(&info);
2783
2784     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2785     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2786     info.status_mask        = 0xfull<<2 /* undflw */;
2787     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2788     info.enable_mask        = 0xfull<<2 /* undflw */;
2789     info.flags              = 0;
2790     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2791     info.group_index        = 16;
2792     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2793     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2794     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2795     info.func               = __cvmx_error_display;
2796     info.user_info          = (long)
2797         "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
2798     fail |= cvmx_error_add(&info);
2799
2800     /* CVMX_IPD_INT_SUM */
2801     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2802     info.status_addr        = CVMX_IPD_INT_SUM;
2803     info.status_mask        = 1ull<<0 /* prc_par0 */;
2804     info.enable_addr        = CVMX_IPD_INT_ENB;
2805     info.enable_mask        = 1ull<<0 /* prc_par0 */;
2806     info.flags              = 0;
2807     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2808     info.group_index        = 0;
2809     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2810     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2811     info.parent.status_mask = 1ull<<9 /* ipd */;
2812     info.func               = __cvmx_error_display;
2813     info.user_info          = (long)
2814         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2815         "    [31:0] of the PBM memory.\n";
2816     fail |= cvmx_error_add(&info);
2817
2818     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2819     info.status_addr        = CVMX_IPD_INT_SUM;
2820     info.status_mask        = 1ull<<1 /* prc_par1 */;
2821     info.enable_addr        = CVMX_IPD_INT_ENB;
2822     info.enable_mask        = 1ull<<1 /* prc_par1 */;
2823     info.flags              = 0;
2824     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2825     info.group_index        = 0;
2826     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2827     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2828     info.parent.status_mask = 1ull<<9 /* ipd */;
2829     info.func               = __cvmx_error_display;
2830     info.user_info          = (long)
2831         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2832         "    [63:32] of the PBM memory.\n";
2833     fail |= cvmx_error_add(&info);
2834
2835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2836     info.status_addr        = CVMX_IPD_INT_SUM;
2837     info.status_mask        = 1ull<<2 /* prc_par2 */;
2838     info.enable_addr        = CVMX_IPD_INT_ENB;
2839     info.enable_mask        = 1ull<<2 /* prc_par2 */;
2840     info.flags              = 0;
2841     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2842     info.group_index        = 0;
2843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2844     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2845     info.parent.status_mask = 1ull<<9 /* ipd */;
2846     info.func               = __cvmx_error_display;
2847     info.user_info          = (long)
2848         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2849         "    [95:64] of the PBM memory.\n";
2850     fail |= cvmx_error_add(&info);
2851
2852     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2853     info.status_addr        = CVMX_IPD_INT_SUM;
2854     info.status_mask        = 1ull<<3 /* prc_par3 */;
2855     info.enable_addr        = CVMX_IPD_INT_ENB;
2856     info.enable_mask        = 1ull<<3 /* prc_par3 */;
2857     info.flags              = 0;
2858     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2859     info.group_index        = 0;
2860     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2861     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2862     info.parent.status_mask = 1ull<<9 /* ipd */;
2863     info.func               = __cvmx_error_display;
2864     info.user_info          = (long)
2865         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2866         "    [127:96] of the PBM memory.\n";
2867     fail |= cvmx_error_add(&info);
2868
2869     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2870     info.status_addr        = CVMX_IPD_INT_SUM;
2871     info.status_mask        = 1ull<<4 /* bp_sub */;
2872     info.enable_addr        = CVMX_IPD_INT_ENB;
2873     info.enable_mask        = 1ull<<4 /* bp_sub */;
2874     info.flags              = 0;
2875     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2876     info.group_index        = 0;
2877     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2878     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2879     info.parent.status_mask = 1ull<<9 /* ipd */;
2880     info.func               = __cvmx_error_display;
2881     info.user_info          = (long)
2882         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2883         "    supplied illegal value.\n";
2884     fail |= cvmx_error_add(&info);
2885
2886     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2887     info.status_addr        = CVMX_IPD_INT_SUM;
2888     info.status_mask        = 1ull<<5 /* dc_ovr */;
2889     info.enable_addr        = CVMX_IPD_INT_ENB;
2890     info.enable_mask        = 1ull<<5 /* dc_ovr */;
2891     info.flags              = 0;
2892     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2893     info.group_index        = 0;
2894     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2895     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2896     info.parent.status_mask = 1ull<<9 /* ipd */;
2897     info.func               = __cvmx_error_display;
2898     info.user_info          = (long)
2899         "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
2900     fail |= cvmx_error_add(&info);
2901
2902     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2903     info.status_addr        = CVMX_IPD_INT_SUM;
2904     info.status_mask        = 1ull<<6 /* cc_ovr */;
2905     info.enable_addr        = CVMX_IPD_INT_ENB;
2906     info.enable_mask        = 1ull<<6 /* cc_ovr */;
2907     info.flags              = 0;
2908     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2909     info.group_index        = 0;
2910     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2911     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2912     info.parent.status_mask = 1ull<<9 /* ipd */;
2913     info.func               = __cvmx_error_display;
2914     info.user_info          = (long)
2915         "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
2916     fail |= cvmx_error_add(&info);
2917
2918     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2919     info.status_addr        = CVMX_IPD_INT_SUM;
2920     info.status_mask        = 1ull<<7 /* c_coll */;
2921     info.enable_addr        = CVMX_IPD_INT_ENB;
2922     info.enable_mask        = 1ull<<7 /* c_coll */;
2923     info.flags              = 0;
2924     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2925     info.group_index        = 0;
2926     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2927     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2928     info.parent.status_mask = 1ull<<9 /* ipd */;
2929     info.func               = __cvmx_error_display;
2930     info.user_info          = (long)
2931         "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
2932         "    collides.\n";
2933     fail |= cvmx_error_add(&info);
2934
2935     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2936     info.status_addr        = CVMX_IPD_INT_SUM;
2937     info.status_mask        = 1ull<<8 /* d_coll */;
2938     info.enable_addr        = CVMX_IPD_INT_ENB;
2939     info.enable_mask        = 1ull<<8 /* d_coll */;
2940     info.flags              = 0;
2941     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2942     info.group_index        = 0;
2943     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2944     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2945     info.parent.status_mask = 1ull<<9 /* ipd */;
2946     info.func               = __cvmx_error_display;
2947     info.user_info          = (long)
2948         "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
2949         "    collides.\n";
2950     fail |= cvmx_error_add(&info);
2951
2952     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2953     info.status_addr        = CVMX_IPD_INT_SUM;
2954     info.status_mask        = 1ull<<9 /* bc_ovr */;
2955     info.enable_addr        = CVMX_IPD_INT_ENB;
2956     info.enable_mask        = 1ull<<9 /* bc_ovr */;
2957     info.flags              = 0;
2958     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2959     info.group_index        = 0;
2960     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2961     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2962     info.parent.status_mask = 1ull<<9 /* ipd */;
2963     info.func               = __cvmx_error_display;
2964     info.user_info          = (long)
2965         "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
2966     fail |= cvmx_error_add(&info);
2967
2968     /* CVMX_TIM_REG_ERROR */
2969     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2970     info.status_addr        = CVMX_TIM_REG_ERROR;
2971     info.status_mask        = 0xffffull<<0 /* mask */;
2972     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
2973     info.enable_mask        = 0xffffull<<0 /* mask */;
2974     info.flags              = 0;
2975     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2976     info.group_index        = 0;
2977     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2978     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2979     info.parent.status_mask = 1ull<<11 /* tim */;
2980     info.func               = __cvmx_error_display;
2981     info.user_info          = (long)
2982         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2983     fail |= cvmx_error_add(&info);
2984
2985     /* CVMX_PKO_REG_ERROR */
2986     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2987     info.status_addr        = CVMX_PKO_REG_ERROR;
2988     info.status_mask        = 1ull<<0 /* parity */;
2989     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2990     info.enable_mask        = 1ull<<0 /* parity */;
2991     info.flags              = 0;
2992     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2993     info.group_index        = 0;
2994     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2995     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2996     info.parent.status_mask = 1ull<<10 /* pko */;
2997     info.func               = __cvmx_error_display;
2998     info.user_info          = (long)
2999         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
3000     fail |= cvmx_error_add(&info);
3001
3002     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3003     info.status_addr        = CVMX_PKO_REG_ERROR;
3004     info.status_mask        = 1ull<<1 /* doorbell */;
3005     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3006     info.enable_mask        = 1ull<<1 /* doorbell */;
3007     info.flags              = 0;
3008     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3009     info.group_index        = 0;
3010     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3011     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3012     info.parent.status_mask = 1ull<<10 /* pko */;
3013     info.func               = __cvmx_error_display;
3014     info.user_info          = (long)
3015         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
3016     fail |= cvmx_error_add(&info);
3017
3018     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3019     info.status_addr        = CVMX_PKO_REG_ERROR;
3020     info.status_mask        = 1ull<<2 /* currzero */;
3021     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3022     info.enable_mask        = 1ull<<2 /* currzero */;
3023     info.flags              = 0;
3024     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3025     info.group_index        = 0;
3026     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3027     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3028     info.parent.status_mask = 1ull<<10 /* pko */;
3029     info.func               = __cvmx_error_display;
3030     info.user_info          = (long)
3031         "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
3032     fail |= cvmx_error_add(&info);
3033
3034     /* CVMX_POW_ECC_ERR */
3035     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3036     info.status_addr        = CVMX_POW_ECC_ERR;
3037     info.status_mask        = 1ull<<0 /* sbe */;
3038     info.enable_addr        = CVMX_POW_ECC_ERR;
3039     info.enable_mask        = 1ull<<2 /* sbe_ie */;
3040     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
3041     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3042     info.group_index        = 0;
3043     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3044     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3045     info.parent.status_mask = 1ull<<12 /* pow */;
3046     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
3047     info.user_info          = (long)
3048         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
3049     fail |= cvmx_error_add(&info);
3050
3051     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3052     info.status_addr        = CVMX_POW_ECC_ERR;
3053     info.status_mask        = 1ull<<1 /* dbe */;
3054     info.enable_addr        = CVMX_POW_ECC_ERR;
3055     info.enable_mask        = 1ull<<3 /* dbe_ie */;
3056     info.flags              = 0;
3057     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3058     info.group_index        = 0;
3059     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3060     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3061     info.parent.status_mask = 1ull<<12 /* pow */;
3062     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
3063     info.user_info          = (long)
3064         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
3065     fail |= cvmx_error_add(&info);
3066
3067     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3068     info.status_addr        = CVMX_POW_ECC_ERR;
3069     info.status_mask        = 1ull<<12 /* rpe */;
3070     info.enable_addr        = CVMX_POW_ECC_ERR;
3071     info.enable_mask        = 1ull<<13 /* rpe_ie */;
3072     info.flags              = 0;
3073     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3074     info.group_index        = 0;
3075     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3076     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3077     info.parent.status_mask = 1ull<<12 /* pow */;
3078     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
3079     info.user_info          = (long)
3080         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
3081     fail |= cvmx_error_add(&info);
3082
3083     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3084     info.status_addr        = CVMX_POW_ECC_ERR;
3085     info.status_mask        = 0x1fffull<<16 /* iop */;
3086     info.enable_addr        = CVMX_POW_ECC_ERR;
3087     info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
3088     info.flags              = 0;
3089     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3090     info.group_index        = 0;
3091     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3092     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3093     info.parent.status_mask = 1ull<<12 /* pow */;
3094     info.func               = __cvmx_error_handle_pow_ecc_err_iop;
3095     info.user_info          = (long)
3096         "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
3097     fail |= cvmx_error_add(&info);
3098
3099     /* CVMX_PEXP_NPEI_INT_SUM */
3100     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3101     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3102     info.status_mask        = 1ull<<59 /* c0_ldwn */;
3103     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3104     info.enable_mask        = 1ull<<59 /* c0_ldwn */;
3105     info.flags              = 0;
3106     info.group              = CVMX_ERROR_GROUP_PCI;
3107     info.group_index        = 0;
3108     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3109     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3110     info.parent.status_mask = 1ull<<3 /* npei */;
3111     info.func               = __cvmx_error_display;
3112     info.user_info          = (long)
3113         "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
3114     fail |= cvmx_error_add(&info);
3115
3116     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3117     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3118     info.status_mask        = 1ull<<21 /* c0_se */;
3119     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3120     info.enable_mask        = 1ull<<21 /* c0_se */;
3121     info.flags              = 0;
3122     info.group              = CVMX_ERROR_GROUP_PCI;
3123     info.group_index        = 0;
3124     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3125     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3126     info.parent.status_mask = 1ull<<3 /* npei */;
3127     info.func               = __cvmx_error_display;
3128     info.user_info          = (long)
3129         "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
3130         "    Pcie Core 0. (cfg_sys_err_rc)\n";
3131     fail |= cvmx_error_add(&info);
3132
3133     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3134     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3135     info.status_mask        = 1ull<<38 /* c0_un_b0 */;
3136     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3137     info.enable_mask        = 1ull<<38 /* c0_un_b0 */;
3138     info.flags              = 0;
3139     info.group              = CVMX_ERROR_GROUP_PCI;
3140     info.group_index        = 0;
3141     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3142     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3143     info.parent.status_mask = 1ull<<3 /* npei */;
3144     info.func               = __cvmx_error_display;
3145     info.user_info          = (long)
3146         "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
3147         "    Core 0.\n";
3148     fail |= cvmx_error_add(&info);
3149
3150     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3151     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3152     info.status_mask        = 1ull<<39 /* c0_un_b1 */;
3153     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3154     info.enable_mask        = 1ull<<39 /* c0_un_b1 */;
3155     info.flags              = 0;
3156     info.group              = CVMX_ERROR_GROUP_PCI;
3157     info.group_index        = 0;
3158     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3159     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3160     info.parent.status_mask = 1ull<<3 /* npei */;
3161     info.func               = __cvmx_error_display;
3162     info.user_info          = (long)
3163         "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
3164         "    Core 0.\n";
3165     fail |= cvmx_error_add(&info);
3166
3167     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3168     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3169     info.status_mask        = 1ull<<40 /* c0_un_b2 */;
3170     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3171     info.enable_mask        = 1ull<<40 /* c0_un_b2 */;
3172     info.flags              = 0;
3173     info.group              = CVMX_ERROR_GROUP_PCI;
3174     info.group_index        = 0;
3175     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3176     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3177     info.parent.status_mask = 1ull<<3 /* npei */;
3178     info.func               = __cvmx_error_display;
3179     info.user_info          = (long)
3180         "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
3181         "    Core 0.\n";
3182     fail |= cvmx_error_add(&info);
3183
3184     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3185     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3186     info.status_mask        = 1ull<<42 /* c0_un_bx */;
3187     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3188     info.enable_mask        = 1ull<<42 /* c0_un_bx */;
3189     info.flags              = 0;
3190     info.group              = CVMX_ERROR_GROUP_PCI;
3191     info.group_index        = 0;
3192     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3193     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3194     info.parent.status_mask = 1ull<<3 /* npei */;
3195     info.func               = __cvmx_error_display;
3196     info.user_info          = (long)
3197         "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
3198         "    Core 0.\n";
3199     fail |= cvmx_error_add(&info);
3200
3201     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3202     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3203     info.status_mask        = 1ull<<53 /* c0_un_wf */;
3204     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3205     info.enable_mask        = 1ull<<53 /* c0_un_wf */;
3206     info.flags              = 0;
3207     info.group              = CVMX_ERROR_GROUP_PCI;
3208     info.group_index        = 0;
3209     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3210     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3211     info.parent.status_mask = 1ull<<3 /* npei */;
3212     info.func               = __cvmx_error_display;
3213     info.user_info          = (long)
3214         "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
3215         "    register. Core0.\n";
3216     fail |= cvmx_error_add(&info);
3217
3218     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3219     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3220     info.status_mask        = 1ull<<41 /* c0_un_wi */;
3221     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3222     info.enable_mask        = 1ull<<41 /* c0_un_wi */;
3223     info.flags              = 0;
3224     info.group              = CVMX_ERROR_GROUP_PCI;
3225     info.group_index        = 0;
3226     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3227     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3228     info.parent.status_mask = 1ull<<3 /* npei */;
3229     info.func               = __cvmx_error_display;
3230     info.user_info          = (long)
3231         "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
3232         "    Core 0.\n";
3233     fail |= cvmx_error_add(&info);
3234
3235     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3236     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3237     info.status_mask        = 1ull<<33 /* c0_up_b0 */;
3238     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3239     info.enable_mask        = 1ull<<33 /* c0_up_b0 */;
3240     info.flags              = 0;
3241     info.group              = CVMX_ERROR_GROUP_PCI;
3242     info.group_index        = 0;
3243     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3244     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3245     info.parent.status_mask = 1ull<<3 /* npei */;
3246     info.func               = __cvmx_error_display;
3247     info.user_info          = (long)
3248         "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
3249         "    Core 0.\n";
3250     fail |= cvmx_error_add(&info);
3251
3252     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3253     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3254     info.status_mask        = 1ull<<34 /* c0_up_b1 */;
3255     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3256     info.enable_mask        = 1ull<<34 /* c0_up_b1 */;
3257     info.flags              = 0;
3258     info.group              = CVMX_ERROR_GROUP_PCI;
3259     info.group_index        = 0;
3260     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3261     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3262     info.parent.status_mask = 1ull<<3 /* npei */;
3263     info.func               = __cvmx_error_display;
3264     info.user_info          = (long)
3265         "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
3266         "    Core 0.\n";
3267     fail |= cvmx_error_add(&info);
3268
3269     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3270     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3271     info.status_mask        = 1ull<<35 /* c0_up_b2 */;
3272     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3273     info.enable_mask        = 1ull<<35 /* c0_up_b2 */;
3274     info.flags              = 0;
3275     info.group              = CVMX_ERROR_GROUP_PCI;
3276     info.group_index        = 0;
3277     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3278     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3279     info.parent.status_mask = 1ull<<3 /* npei */;
3280     info.func               = __cvmx_error_display;
3281     info.user_info          = (long)
3282         "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3283         "    Core 0.\n";
3284     fail |= cvmx_error_add(&info);
3285
3286     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3287     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3288     info.status_mask        = 1ull<<37 /* c0_up_bx */;
3289     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3290     info.enable_mask        = 1ull<<37 /* c0_up_bx */;
3291     info.flags              = 0;
3292     info.group              = CVMX_ERROR_GROUP_PCI;
3293     info.group_index        = 0;
3294     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3295     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3296     info.parent.status_mask = 1ull<<3 /* npei */;
3297     info.func               = __cvmx_error_display;
3298     info.user_info          = (long)
3299         "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3300         "    Core 0.\n";
3301     fail |= cvmx_error_add(&info);
3302
3303     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3304     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3305     info.status_mask        = 1ull<<55 /* c0_up_wf */;
3306     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3307     info.enable_mask        = 1ull<<55 /* c0_up_wf */;
3308     info.flags              = 0;
3309     info.group              = CVMX_ERROR_GROUP_PCI;
3310     info.group_index        = 0;
3311     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3312     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3313     info.parent.status_mask = 1ull<<3 /* npei */;
3314     info.func               = __cvmx_error_display;
3315     info.user_info          = (long)
3316         "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3317         "    register. Core0.\n";
3318     fail |= cvmx_error_add(&info);
3319
3320     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3321     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3322     info.status_mask        = 1ull<<36 /* c0_up_wi */;
3323     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3324     info.enable_mask        = 1ull<<36 /* c0_up_wi */;
3325     info.flags              = 0;
3326     info.group              = CVMX_ERROR_GROUP_PCI;
3327     info.group_index        = 0;
3328     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3329     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3330     info.parent.status_mask = 1ull<<3 /* npei */;
3331     info.func               = __cvmx_error_display;
3332     info.user_info          = (long)
3333         "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3334         "    Core 0.\n";
3335     fail |= cvmx_error_add(&info);
3336
3337     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3338     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3339     info.status_mask        = 1ull<<23 /* c0_wake */;
3340     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3341     info.enable_mask        = 1ull<<23 /* c0_wake */;
3342     info.flags              = 0;
3343     info.group              = CVMX_ERROR_GROUP_PCI;
3344     info.group_index        = 0;
3345     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3346     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3347     info.parent.status_mask = 1ull<<3 /* npei */;
3348     info.func               = __cvmx_error_display;
3349     info.user_info          = (long)
3350         "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
3351         "    Pcie Core 0. (wake_n)\n"
3352         "    Octeon will never generate this interrupt.\n";
3353     fail |= cvmx_error_add(&info);
3354
3355     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3356     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3357     info.status_mask        = 1ull<<22 /* crs0_dr */;
3358     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3359     info.enable_mask        = 1ull<<22 /* crs0_dr */;
3360     info.flags              = 0;
3361     info.group              = CVMX_ERROR_GROUP_PCI;
3362     info.group_index        = 0;
3363     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3364     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3365     info.parent.status_mask = 1ull<<3 /* npei */;
3366     info.func               = __cvmx_error_display;
3367     info.user_info          = (long)
3368         "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
3369     fail |= cvmx_error_add(&info);
3370
3371     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3372     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3373     info.status_mask        = 1ull<<20 /* crs0_er */;
3374     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3375     info.enable_mask        = 1ull<<20 /* crs0_er */;
3376     info.flags              = 0;
3377     info.group              = CVMX_ERROR_GROUP_PCI;
3378     info.group_index        = 0;
3379     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3380     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3381     info.parent.status_mask = 1ull<<3 /* npei */;
3382     info.func               = __cvmx_error_display;
3383     info.user_info          = (long)
3384         "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
3385     fail |= cvmx_error_add(&info);
3386
3387     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3388     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3389     info.status_mask        = 1ull<<60 /* c1_ldwn */;
3390     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3391     info.enable_mask        = 1ull<<60 /* c1_ldwn */;
3392     info.flags              = 0;
3393     info.group              = CVMX_ERROR_GROUP_PCI;
3394     info.group_index        = 1;
3395     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3396     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3397     info.parent.status_mask = 1ull<<3 /* npei */;
3398     info.func               = __cvmx_error_display;
3399     info.user_info          = (long)
3400         "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
3401     fail |= cvmx_error_add(&info);
3402
3403     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3404     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3405     info.status_mask        = 1ull<<28 /* c1_se */;
3406     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3407     info.enable_mask        = 1ull<<28 /* c1_se */;
3408     info.flags              = 0;
3409     info.group              = CVMX_ERROR_GROUP_PCI;
3410     info.group_index        = 1;
3411     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3412     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3413     info.parent.status_mask = 1ull<<3 /* npei */;
3414     info.func               = __cvmx_error_display;
3415     info.user_info          = (long)
3416         "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
3417         "    Pcie Core 1. (cfg_sys_err_rc)\n";
3418     fail |= cvmx_error_add(&info);
3419
3420     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3421     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3422     info.status_mask        = 1ull<<48 /* c1_un_b0 */;
3423     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3424     info.enable_mask        = 1ull<<48 /* c1_un_b0 */;
3425     info.flags              = 0;
3426     info.group              = CVMX_ERROR_GROUP_PCI;
3427     info.group_index        = 1;
3428     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3429     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3430     info.parent.status_mask = 1ull<<3 /* npei */;
3431     info.func               = __cvmx_error_display;
3432     info.user_info          = (long)
3433         "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
3434         "    Core 1.\n";
3435     fail |= cvmx_error_add(&info);
3436
3437     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3438     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3439     info.status_mask        = 1ull<<49 /* c1_un_b1 */;
3440     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3441     info.enable_mask        = 1ull<<49 /* c1_un_b1 */;
3442     info.flags              = 0;
3443     info.group              = CVMX_ERROR_GROUP_PCI;
3444     info.group_index        = 1;
3445     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3446     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3447     info.parent.status_mask = 1ull<<3 /* npei */;
3448     info.func               = __cvmx_error_display;
3449     info.user_info          = (long)
3450         "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
3451         "    Core 1.\n";
3452     fail |= cvmx_error_add(&info);
3453
3454     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3455     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3456     info.status_mask        = 1ull<<50 /* c1_un_b2 */;
3457     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3458     info.enable_mask        = 1ull<<50 /* c1_un_b2 */;
3459     info.flags              = 0;
3460     info.group              = CVMX_ERROR_GROUP_PCI;
3461     info.group_index        = 1;
3462     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3463     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3464     info.parent.status_mask = 1ull<<3 /* npei */;
3465     info.func               = __cvmx_error_display;
3466     info.user_info          = (long)
3467         "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
3468         "    Core 1.\n";
3469     fail |= cvmx_error_add(&info);
3470
3471     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3472     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3473     info.status_mask        = 1ull<<52 /* c1_un_bx */;
3474     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3475     info.enable_mask        = 1ull<<52 /* c1_un_bx */;
3476     info.flags              = 0;
3477     info.group              = CVMX_ERROR_GROUP_PCI;
3478     info.group_index        = 1;
3479     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3480     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3481     info.parent.status_mask = 1ull<<3 /* npei */;
3482     info.func               = __cvmx_error_display;
3483     info.user_info          = (long)
3484         "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
3485         "    Core 1.\n";
3486     fail |= cvmx_error_add(&info);
3487
3488     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3489     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3490     info.status_mask        = 1ull<<54 /* c1_un_wf */;
3491     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3492     info.enable_mask        = 1ull<<54 /* c1_un_wf */;
3493     info.flags              = 0;
3494     info.group              = CVMX_ERROR_GROUP_PCI;
3495     info.group_index        = 1;
3496     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3497     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3498     info.parent.status_mask = 1ull<<3 /* npei */;
3499     info.func               = __cvmx_error_display;
3500     info.user_info          = (long)
3501         "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
3502         "    register. Core1.\n";
3503     fail |= cvmx_error_add(&info);
3504
3505     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3506     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3507     info.status_mask        = 1ull<<51 /* c1_un_wi */;
3508     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3509     info.enable_mask        = 1ull<<51 /* c1_un_wi */;
3510     info.flags              = 0;
3511     info.group              = CVMX_ERROR_GROUP_PCI;
3512     info.group_index        = 1;
3513     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3514     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3515     info.parent.status_mask = 1ull<<3 /* npei */;
3516     info.func               = __cvmx_error_display;
3517     info.user_info          = (long)
3518         "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
3519         "    Core 1.\n";
3520     fail |= cvmx_error_add(&info);
3521
3522     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3523     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3524     info.status_mask        = 1ull<<43 /* c1_up_b0 */;
3525     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3526     info.enable_mask        = 1ull<<43 /* c1_up_b0 */;
3527     info.flags              = 0;
3528     info.group              = CVMX_ERROR_GROUP_PCI;
3529     info.group_index        = 1;
3530     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3531     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3532     info.parent.status_mask = 1ull<<3 /* npei */;
3533     info.func               = __cvmx_error_display;
3534     info.user_info          = (long)
3535         "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
3536         "    Core 1.\n";
3537     fail |= cvmx_error_add(&info);
3538
3539     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3540     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3541     info.status_mask        = 1ull<<44 /* c1_up_b1 */;
3542     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3543     info.enable_mask        = 1ull<<44 /* c1_up_b1 */;
3544     info.flags              = 0;
3545     info.group              = CVMX_ERROR_GROUP_PCI;
3546     info.group_index        = 1;
3547     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3548     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3549     info.parent.status_mask = 1ull<<3 /* npei */;
3550     info.func               = __cvmx_error_display;
3551     info.user_info          = (long)
3552         "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n"
3553         "    Core 1.\n";
3554     fail |= cvmx_error_add(&info);
3555
3556     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3557     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3558     info.status_mask        = 1ull<<45 /* c1_up_b2 */;
3559     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3560     info.enable_mask        = 1ull<<45 /* c1_up_b2 */;
3561     info.flags              = 0;
3562     info.group              = CVMX_ERROR_GROUP_PCI;
3563     info.group_index        = 1;
3564     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3565     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3566     info.parent.status_mask = 1ull<<3 /* npei */;
3567     info.func               = __cvmx_error_display;
3568     info.user_info          = (long)
3569         "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3570         "    Core 1.\n";
3571     fail |= cvmx_error_add(&info);
3572
3573     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3574     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3575     info.status_mask        = 1ull<<47 /* c1_up_bx */;
3576     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3577     info.enable_mask        = 1ull<<47 /* c1_up_bx */;
3578     info.flags              = 0;
3579     info.group              = CVMX_ERROR_GROUP_PCI;
3580     info.group_index        = 1;
3581     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3582     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3583     info.parent.status_mask = 1ull<<3 /* npei */;
3584     info.func               = __cvmx_error_display;
3585     info.user_info          = (long)
3586         "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3587         "    Core 1.\n";
3588     fail |= cvmx_error_add(&info);
3589
3590     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3591     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3592     info.status_mask        = 1ull<<56 /* c1_up_wf */;
3593     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3594     info.enable_mask        = 1ull<<56 /* c1_up_wf */;
3595     info.flags              = 0;
3596     info.group              = CVMX_ERROR_GROUP_PCI;
3597     info.group_index        = 1;
3598     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3599     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3600     info.parent.status_mask = 1ull<<3 /* npei */;
3601     info.func               = __cvmx_error_display;
3602     info.user_info          = (long)
3603         "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3604         "    register. Core1.\n";
3605     fail |= cvmx_error_add(&info);
3606
3607     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3608     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3609     info.status_mask        = 1ull<<46 /* c1_up_wi */;
3610     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3611     info.enable_mask        = 1ull<<46 /* c1_up_wi */;
3612     info.flags              = 0;
3613     info.group              = CVMX_ERROR_GROUP_PCI;
3614     info.group_index        = 1;
3615     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3616     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3617     info.parent.status_mask = 1ull<<3 /* npei */;
3618     info.func               = __cvmx_error_display;
3619     info.user_info          = (long)
3620         "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3621         "    Core 1.\n";
3622     fail |= cvmx_error_add(&info);
3623
3624     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3625     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3626     info.status_mask        = 1ull<<30 /* c1_wake */;
3627     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3628     info.enable_mask        = 1ull<<30 /* c1_wake */;
3629     info.flags              = 0;
3630     info.group              = CVMX_ERROR_GROUP_PCI;
3631     info.group_index        = 1;
3632     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3633     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3634     info.parent.status_mask = 1ull<<3 /* npei */;
3635     info.func               = __cvmx_error_display;
3636     info.user_info          = (long)
3637         "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
3638         "    Pcie Core 1. (wake_n)\n"
3639         "    Octeon will never generate this interrupt.\n";
3640     fail |= cvmx_error_add(&info);
3641
3642     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3643     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3644     info.status_mask        = 1ull<<29 /* crs1_dr */;
3645     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3646     info.enable_mask        = 1ull<<29 /* crs1_dr */;
3647     info.flags              = 0;
3648     info.group              = CVMX_ERROR_GROUP_PCI;
3649     info.group_index        = 1;
3650     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3651     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3652     info.parent.status_mask = 1ull<<3 /* npei */;
3653     info.func               = __cvmx_error_display;
3654     info.user_info          = (long)
3655         "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
3656     fail |= cvmx_error_add(&info);
3657
3658     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3659     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3660     info.status_mask        = 1ull<<27 /* crs1_er */;
3661     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3662     info.enable_mask        = 1ull<<27 /* crs1_er */;
3663     info.flags              = 0;
3664     info.group              = CVMX_ERROR_GROUP_PCI;
3665     info.group_index        = 1;
3666     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3667     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3668     info.parent.status_mask = 1ull<<3 /* npei */;
3669     info.func               = __cvmx_error_display;
3670     info.user_info          = (long)
3671         "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
3672     fail |= cvmx_error_add(&info);
3673
3674     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3675     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3676     info.status_mask        = 1ull<<2 /* bar0_to */;
3677     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3678     info.enable_mask        = 1ull<<2 /* bar0_to */;
3679     info.flags              = 0;
3680     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3681     info.group_index        = 0;
3682     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3683     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3684     info.parent.status_mask = 1ull<<3 /* npei */;
3685     info.func               = __cvmx_error_display;
3686     info.user_info          = (long)
3687         "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
3688         "    read-data/commit in 0xffff core clocks.\n";
3689     fail |= cvmx_error_add(&info);
3690
3691     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3692     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3693     info.status_mask        = 1ull<<4 /* dma0dbo */;
3694     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3695     info.enable_mask        = 1ull<<4 /* dma0dbo */;
3696     info.flags              = 0;
3697     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3698     info.group_index        = 0;
3699     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3700     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3701     info.parent.status_mask = 1ull<<3 /* npei */;
3702     info.func               = __cvmx_error_display;
3703     info.user_info          = (long)
3704         "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
3705         "    Bit[32] of the doorbell count was set.\n";
3706     fail |= cvmx_error_add(&info);
3707
3708     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3709     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3710     info.status_mask        = 1ull<<5 /* dma1dbo */;
3711     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3712     info.enable_mask        = 1ull<<5 /* dma1dbo */;
3713     info.flags              = 0;
3714     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3715     info.group_index        = 0;
3716     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3717     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3718     info.parent.status_mask = 1ull<<3 /* npei */;
3719     info.func               = __cvmx_error_display;
3720     info.user_info          = (long)
3721         "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
3722         "    Bit[32] of the doorbell count was set.\n";
3723     fail |= cvmx_error_add(&info);
3724
3725     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3726     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3727     info.status_mask        = 1ull<<6 /* dma2dbo */;
3728     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3729     info.enable_mask        = 1ull<<6 /* dma2dbo */;
3730     info.flags              = 0;
3731     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3732     info.group_index        = 0;
3733     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3734     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3735     info.parent.status_mask = 1ull<<3 /* npei */;
3736     info.func               = __cvmx_error_display;
3737     info.user_info          = (long)
3738         "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
3739         "    Bit[32] of the doorbell count was set.\n";
3740     fail |= cvmx_error_add(&info);
3741
3742     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3743     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3744     info.status_mask        = 1ull<<7 /* dma3dbo */;
3745     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3746     info.enable_mask        = 1ull<<7 /* dma3dbo */;
3747     info.flags              = 0;
3748     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3749     info.group_index        = 0;
3750     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3751     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3752     info.parent.status_mask = 1ull<<3 /* npei */;
3753     info.func               = __cvmx_error_display;
3754     info.user_info          = (long)
3755         "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
3756         "    Bit[32] of the doorbell count was set.\n";
3757     fail |= cvmx_error_add(&info);
3758
3759     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3760     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3761     info.status_mask        = 1ull<<3 /* iob2big */;
3762     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3763     info.enable_mask        = 1ull<<3 /* iob2big */;
3764     info.flags              = 0;
3765     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3766     info.group_index        = 0;
3767     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3768     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3769     info.parent.status_mask = 1ull<<3 /* npei */;
3770     info.func               = __cvmx_error_display;
3771     info.user_info          = (long)
3772         "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
3773     fail |= cvmx_error_add(&info);
3774
3775     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3776     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3777     info.status_mask        = 1ull<<0 /* rml_rto */;
3778     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3779     info.enable_mask        = 1ull<<0 /* rml_rto */;
3780     info.flags              = 0;
3781     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3782     info.group_index        = 0;
3783     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3784     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3785     info.parent.status_mask = 1ull<<3 /* npei */;
3786     info.func               = __cvmx_error_display;
3787     info.user_info          = (long)
3788         "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
3789     fail |= cvmx_error_add(&info);
3790
3791     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3792     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3793     info.status_mask        = 1ull<<1 /* rml_wto */;
3794     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3795     info.enable_mask        = 1ull<<1 /* rml_wto */;
3796     info.flags              = 0;
3797     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3798     info.group_index        = 0;
3799     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3800     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3801     info.parent.status_mask = 1ull<<3 /* npei */;
3802     info.func               = __cvmx_error_display;
3803     info.user_info          = (long)
3804         "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
3805     fail |= cvmx_error_add(&info);
3806
3807     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3808     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3809     info.status_mask        = 1ull<<8 /* dma4dbo */;
3810     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
3811     info.enable_mask        = 1ull<<8 /* dma4dbo */;
3812     info.flags              = 0;
3813     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3814     info.group_index        = 0;
3815     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3816     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3817     info.parent.status_mask = 1ull<<3 /* npei */;
3818     info.func               = __cvmx_error_display;
3819     info.user_info          = (long)
3820         "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
3821         "    Bit[32] of the doorbell count was set.\n";
3822     fail |= cvmx_error_add(&info);
3823
3824     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3825     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
3826     info.status_mask        = 0;
3827     info.enable_addr        = 0;
3828     info.enable_mask        = 0;
3829     info.flags              = 0;
3830     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3831     info.group_index        = 0;
3832     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3833     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3834     info.parent.status_mask = 1ull<<3 /* npei */;
3835     info.func               = __cvmx_error_decode;
3836     info.user_info          = 0;
3837     fail |= cvmx_error_add(&info);
3838
3839     /* CVMX_PESCX_DBG_INFO(0) */
3840     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3841     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3842     info.status_mask        = 1ull<<0 /* spoison */;
3843     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3844     info.enable_mask        = 1ull<<0 /* spoison */;
3845     info.flags              = 0;
3846     info.group              = CVMX_ERROR_GROUP_PCI;
3847     info.group_index        = 0;
3848     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3849     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3850     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3851     info.func               = __cvmx_error_display;
3852     info.user_info          = (long)
3853         "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
3854         "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3855     fail |= cvmx_error_add(&info);
3856
3857     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3858     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3859     info.status_mask        = 1ull<<2 /* rtlplle */;
3860     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3861     info.enable_mask        = 1ull<<2 /* rtlplle */;
3862     info.flags              = 0;
3863     info.group              = CVMX_ERROR_GROUP_PCI;
3864     info.group_index        = 0;
3865     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3866     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3867     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3868     info.func               = __cvmx_error_display;
3869     info.user_info          = (long)
3870         "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
3871         "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3872     fail |= cvmx_error_add(&info);
3873
3874     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3875     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3876     info.status_mask        = 1ull<<3 /* recrce */;
3877     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3878     info.enable_mask        = 1ull<<3 /* recrce */;
3879     info.flags              = 0;
3880     info.group              = CVMX_ERROR_GROUP_PCI;
3881     info.group_index        = 0;
3882     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3883     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3884     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3885     info.func               = __cvmx_error_display;
3886     info.user_info          = (long)
3887         "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
3888         "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3889     fail |= cvmx_error_add(&info);
3890
3891     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3892     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3893     info.status_mask        = 1ull<<4 /* rpoison */;
3894     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3895     info.enable_mask        = 1ull<<4 /* rpoison */;
3896     info.flags              = 0;
3897     info.group              = CVMX_ERROR_GROUP_PCI;
3898     info.group_index        = 0;
3899     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3900     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3901     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3902     info.func               = __cvmx_error_display;
3903     info.user_info          = (long)
3904         "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
3905         "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3906     fail |= cvmx_error_add(&info);
3907
3908     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3909     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3910     info.status_mask        = 1ull<<5 /* rcemrc */;
3911     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3912     info.enable_mask        = 1ull<<5 /* rcemrc */;
3913     info.flags              = 0;
3914     info.group              = CVMX_ERROR_GROUP_PCI;
3915     info.group_index        = 0;
3916     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3917     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3918     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3919     info.func               = __cvmx_error_display;
3920     info.user_info          = (long)
3921         "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3922         "    pedc_radm_correctable_err\n";
3923     fail |= cvmx_error_add(&info);
3924
3925     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3926     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3927     info.status_mask        = 1ull<<6 /* rnfemrc */;
3928     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3929     info.enable_mask        = 1ull<<6 /* rnfemrc */;
3930     info.flags              = 0;
3931     info.group              = CVMX_ERROR_GROUP_PCI;
3932     info.group_index        = 0;
3933     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3934     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3935     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3936     info.func               = __cvmx_error_display;
3937     info.user_info          = (long)
3938         "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3939         "    pedc_radm_nonfatal_err\n";
3940     fail |= cvmx_error_add(&info);
3941
3942     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3943     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3944     info.status_mask        = 1ull<<7 /* rfemrc */;
3945     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3946     info.enable_mask        = 1ull<<7 /* rfemrc */;
3947     info.flags              = 0;
3948     info.group              = CVMX_ERROR_GROUP_PCI;
3949     info.group_index        = 0;
3950     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3951     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3952     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3953     info.func               = __cvmx_error_display;
3954     info.user_info          = (long)
3955         "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3956         "    pedc_radm_fatal_err\n"
3957         "    Bit set when a message with ERR_FATAL is set.\n";
3958     fail |= cvmx_error_add(&info);
3959
3960     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3961     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3962     info.status_mask        = 1ull<<8 /* rpmerc */;
3963     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3964     info.enable_mask        = 1ull<<8 /* rpmerc */;
3965     info.flags              = 0;
3966     info.group              = CVMX_ERROR_GROUP_PCI;
3967     info.group_index        = 0;
3968     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3969     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3970     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3971     info.func               = __cvmx_error_display;
3972     info.user_info          = (long)
3973         "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
3974         "    pedc_radm_pm_pme\n";
3975     fail |= cvmx_error_add(&info);
3976
3977     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3978     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3979     info.status_mask        = 1ull<<9 /* rptamrc */;
3980     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3981     info.enable_mask        = 1ull<<9 /* rptamrc */;
3982     info.flags              = 0;
3983     info.group              = CVMX_ERROR_GROUP_PCI;
3984     info.group_index        = 0;
3985     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3986     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3987     info.parent.status_mask = 1ull<<57 /* c0_exc */;
3988     info.func               = __cvmx_error_display;
3989     info.user_info          = (long)
3990         "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3991         "    (RC Mode only)\n"
3992         "    pedc_radm_pm_to_ack\n";
3993     fail |= cvmx_error_add(&info);
3994
3995     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3996     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
3997     info.status_mask        = 1ull<<10 /* rumep */;
3998     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
3999     info.enable_mask        = 1ull<<10 /* rumep */;
4000     info.flags              = 0;
4001     info.group              = CVMX_ERROR_GROUP_PCI;
4002     info.group_index        = 0;
4003     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4004     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4005     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4006     info.func               = __cvmx_error_display;
4007     info.user_info          = (long)
4008         "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
4009         "    pedc_radm_msg_unlock\n";
4010     fail |= cvmx_error_add(&info);
4011
4012     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4013     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4014     info.status_mask        = 1ull<<11 /* rvdm */;
4015     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4016     info.enable_mask        = 1ull<<11 /* rvdm */;
4017     info.flags              = 0;
4018     info.group              = CVMX_ERROR_GROUP_PCI;
4019     info.group_index        = 0;
4020     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4021     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4022     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4023     info.func               = __cvmx_error_display;
4024     info.user_info          = (long)
4025         "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
4026         "    pedc_radm_vendor_msg\n";
4027     fail |= cvmx_error_add(&info);
4028
4029     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4030     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4031     info.status_mask        = 1ull<<12 /* acto */;
4032     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4033     info.enable_mask        = 1ull<<12 /* acto */;
4034     info.flags              = 0;
4035     info.group              = CVMX_ERROR_GROUP_PCI;
4036     info.group_index        = 0;
4037     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4038     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4039     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4040     info.func               = __cvmx_error_display;
4041     info.user_info          = (long)
4042         "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
4043         "    pedc_radm_cpl_timeout\n";
4044     fail |= cvmx_error_add(&info);
4045
4046     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4047     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4048     info.status_mask        = 1ull<<13 /* rte */;
4049     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4050     info.enable_mask        = 1ull<<13 /* rte */;
4051     info.flags              = 0;
4052     info.group              = CVMX_ERROR_GROUP_PCI;
4053     info.group_index        = 0;
4054     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4055     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4056     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4057     info.func               = __cvmx_error_display;
4058     info.user_info          = (long)
4059         "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
4060         "    xdlh_replay_timeout_err\n"
4061         "    This bit is set when the REPLAY_TIMER expires in\n"
4062         "    the PCIE core. The probability of this bit being\n"
4063         "    set will increase with the traffic load.\n";
4064     fail |= cvmx_error_add(&info);
4065
4066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4067     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4068     info.status_mask        = 1ull<<14 /* mre */;
4069     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4070     info.enable_mask        = 1ull<<14 /* mre */;
4071     info.flags              = 0;
4072     info.group              = CVMX_ERROR_GROUP_PCI;
4073     info.group_index        = 0;
4074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4075     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4076     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4077     info.func               = __cvmx_error_display;
4078     info.user_info          = (long)
4079         "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
4080         "    xdlh_replay_num_rlover_err\n";
4081     fail |= cvmx_error_add(&info);
4082
4083     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4084     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4085     info.status_mask        = 1ull<<15 /* rdwdle */;
4086     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4087     info.enable_mask        = 1ull<<15 /* rdwdle */;
4088     info.flags              = 0;
4089     info.group              = CVMX_ERROR_GROUP_PCI;
4090     info.group_index        = 0;
4091     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4092     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4093     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4094     info.func               = __cvmx_error_display;
4095     info.user_info          = (long)
4096         "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
4097         "    rdlh_bad_dllp_err\n";
4098     fail |= cvmx_error_add(&info);
4099
4100     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4101     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4102     info.status_mask        = 1ull<<16 /* rtwdle */;
4103     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4104     info.enable_mask        = 1ull<<16 /* rtwdle */;
4105     info.flags              = 0;
4106     info.group              = CVMX_ERROR_GROUP_PCI;
4107     info.group_index        = 0;
4108     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4109     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4110     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4111     info.func               = __cvmx_error_display;
4112     info.user_info          = (long)
4113         "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
4114         "    rdlh_bad_tlp_err\n";
4115     fail |= cvmx_error_add(&info);
4116
4117     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4118     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4119     info.status_mask        = 1ull<<17 /* dpeoosd */;
4120     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4121     info.enable_mask        = 1ull<<17 /* dpeoosd */;
4122     info.flags              = 0;
4123     info.group              = CVMX_ERROR_GROUP_PCI;
4124     info.group_index        = 0;
4125     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4126     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4127     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4128     info.func               = __cvmx_error_display;
4129     info.user_info          = (long)
4130         "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
4131         "    rdlh_prot_err\n";
4132     fail |= cvmx_error_add(&info);
4133
4134     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4135     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4136     info.status_mask        = 1ull<<18 /* fcpvwt */;
4137     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4138     info.enable_mask        = 1ull<<18 /* fcpvwt */;
4139     info.flags              = 0;
4140     info.group              = CVMX_ERROR_GROUP_PCI;
4141     info.group_index        = 0;
4142     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4143     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4144     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4145     info.func               = __cvmx_error_display;
4146     info.user_info          = (long)
4147         "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
4148         "    rtlh_fc_prot_err\n";
4149     fail |= cvmx_error_add(&info);
4150
4151     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4152     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4153     info.status_mask        = 1ull<<19 /* rpe */;
4154     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4155     info.enable_mask        = 1ull<<19 /* rpe */;
4156     info.flags              = 0;
4157     info.group              = CVMX_ERROR_GROUP_PCI;
4158     info.group_index        = 0;
4159     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4160     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4161     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4162     info.func               = __cvmx_error_display;
4163     info.user_info          = (long)
4164         "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
4165         "    (RxStatus = 3b100) or disparity error\n"
4166         "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
4167         "    be asserted.\n"
4168         "    rmlh_rcvd_err\n";
4169     fail |= cvmx_error_add(&info);
4170
4171     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4172     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4173     info.status_mask        = 1ull<<20 /* fcuv */;
4174     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4175     info.enable_mask        = 1ull<<20 /* fcuv */;
4176     info.flags              = 0;
4177     info.group              = CVMX_ERROR_GROUP_PCI;
4178     info.group_index        = 0;
4179     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4180     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4181     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4182     info.func               = __cvmx_error_display;
4183     info.user_info          = (long)
4184         "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
4185         "    int_xadm_fc_prot_err\n";
4186     fail |= cvmx_error_add(&info);
4187
4188     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4189     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4190     info.status_mask        = 1ull<<21 /* rqo */;
4191     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4192     info.enable_mask        = 1ull<<21 /* rqo */;
4193     info.flags              = 0;
4194     info.group              = CVMX_ERROR_GROUP_PCI;
4195     info.group_index        = 0;
4196     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4197     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4198     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4199     info.func               = __cvmx_error_display;
4200     info.user_info          = (long)
4201         "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
4202         "    flow control advertisements are ignored\n"
4203         "    radm_qoverflow\n";
4204     fail |= cvmx_error_add(&info);
4205
4206     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4207     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4208     info.status_mask        = 1ull<<22 /* rauc */;
4209     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4210     info.enable_mask        = 1ull<<22 /* rauc */;
4211     info.flags              = 0;
4212     info.group              = CVMX_ERROR_GROUP_PCI;
4213     info.group_index        = 0;
4214     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4215     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4216     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4217     info.func               = __cvmx_error_display;
4218     info.user_info          = (long)
4219         "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
4220         "    radm_unexp_cpl_err\n";
4221     fail |= cvmx_error_add(&info);
4222
4223     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4224     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4225     info.status_mask        = 1ull<<23 /* racur */;
4226     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4227     info.enable_mask        = 1ull<<23 /* racur */;
4228     info.flags              = 0;
4229     info.group              = CVMX_ERROR_GROUP_PCI;
4230     info.group_index        = 0;
4231     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4232     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4233     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4234     info.func               = __cvmx_error_display;
4235     info.user_info          = (long)
4236         "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
4237         "    radm_rcvd_cpl_ur\n";
4238     fail |= cvmx_error_add(&info);
4239
4240     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4241     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4242     info.status_mask        = 1ull<<24 /* racca */;
4243     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4244     info.enable_mask        = 1ull<<24 /* racca */;
4245     info.flags              = 0;
4246     info.group              = CVMX_ERROR_GROUP_PCI;
4247     info.group_index        = 0;
4248     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4249     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4250     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4251     info.func               = __cvmx_error_display;
4252     info.user_info          = (long)
4253         "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
4254         "    radm_rcvd_cpl_ca\n";
4255     fail |= cvmx_error_add(&info);
4256
4257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4258     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4259     info.status_mask        = 1ull<<25 /* caar */;
4260     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4261     info.enable_mask        = 1ull<<25 /* caar */;
4262     info.flags              = 0;
4263     info.group              = CVMX_ERROR_GROUP_PCI;
4264     info.group_index        = 0;
4265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4266     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4267     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4268     info.func               = __cvmx_error_display;
4269     info.user_info          = (long)
4270         "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
4271         "    radm_rcvd_ca_req\n"
4272         "    This bit will never be set because Octeon does\n"
4273         "    not generate Completer Aborts.\n";
4274     fail |= cvmx_error_add(&info);
4275
4276     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4277     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4278     info.status_mask        = 1ull<<26 /* rarwdns */;
4279     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4280     info.enable_mask        = 1ull<<26 /* rarwdns */;
4281     info.flags              = 0;
4282     info.group              = CVMX_ERROR_GROUP_PCI;
4283     info.group_index        = 0;
4284     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4285     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4286     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4287     info.func               = __cvmx_error_display;
4288     info.user_info          = (long)
4289         "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
4290         "    radm_rcvd_ur_req\n";
4291     fail |= cvmx_error_add(&info);
4292
4293     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4294     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4295     info.status_mask        = 1ull<<27 /* ramtlp */;
4296     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4297     info.enable_mask        = 1ull<<27 /* ramtlp */;
4298     info.flags              = 0;
4299     info.group              = CVMX_ERROR_GROUP_PCI;
4300     info.group_index        = 0;
4301     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4302     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4303     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4304     info.func               = __cvmx_error_display;
4305     info.user_info          = (long)
4306         "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
4307         "    radm_mlf_tlp_err\n";
4308     fail |= cvmx_error_add(&info);
4309
4310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4311     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4312     info.status_mask        = 1ull<<28 /* racpp */;
4313     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4314     info.enable_mask        = 1ull<<28 /* racpp */;
4315     info.flags              = 0;
4316     info.group              = CVMX_ERROR_GROUP_PCI;
4317     info.group_index        = 0;
4318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4319     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4320     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4321     info.func               = __cvmx_error_display;
4322     info.user_info          = (long)
4323         "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
4324         "    radm_rcvd_cpl_poisoned\n";
4325     fail |= cvmx_error_add(&info);
4326
4327     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4328     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4329     info.status_mask        = 1ull<<29 /* rawwpp */;
4330     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4331     info.enable_mask        = 1ull<<29 /* rawwpp */;
4332     info.flags              = 0;
4333     info.group              = CVMX_ERROR_GROUP_PCI;
4334     info.group_index        = 0;
4335     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4336     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4337     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4338     info.func               = __cvmx_error_display;
4339     info.user_info          = (long)
4340         "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
4341         "    radm_rcvd_wreq_poisoned\n";
4342     fail |= cvmx_error_add(&info);
4343
4344     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4345     info.status_addr        = CVMX_PESCX_DBG_INFO(0);
4346     info.status_mask        = 1ull<<30 /* ecrc_e */;
4347     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
4348     info.enable_mask        = 1ull<<30 /* ecrc_e */;
4349     info.flags              = 0;
4350     info.group              = CVMX_ERROR_GROUP_PCI;
4351     info.group_index        = 0;
4352     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4353     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4354     info.parent.status_mask = 1ull<<57 /* c0_exc */;
4355     info.func               = __cvmx_error_display;
4356     info.user_info          = (long)
4357         "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
4358         "    radm_ecrc_err\n";
4359     fail |= cvmx_error_add(&info);
4360
4361     /* CVMX_PESCX_DBG_INFO(1) */
4362     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4363     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4364     info.status_mask        = 1ull<<0 /* spoison */;
4365     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4366     info.enable_mask        = 1ull<<0 /* spoison */;
4367     info.flags              = 0;
4368     info.group              = CVMX_ERROR_GROUP_PCI;
4369     info.group_index        = 1;
4370     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4371     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4372     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4373     info.func               = __cvmx_error_display;
4374     info.user_info          = (long)
4375         "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
4376         "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
4377     fail |= cvmx_error_add(&info);
4378
4379     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4380     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4381     info.status_mask        = 1ull<<2 /* rtlplle */;
4382     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4383     info.enable_mask        = 1ull<<2 /* rtlplle */;
4384     info.flags              = 0;
4385     info.group              = CVMX_ERROR_GROUP_PCI;
4386     info.group_index        = 1;
4387     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4388     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4389     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4390     info.func               = __cvmx_error_display;
4391     info.user_info          = (long)
4392         "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
4393         "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
4394     fail |= cvmx_error_add(&info);
4395
4396     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4397     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4398     info.status_mask        = 1ull<<3 /* recrce */;
4399     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4400     info.enable_mask        = 1ull<<3 /* recrce */;
4401     info.flags              = 0;
4402     info.group              = CVMX_ERROR_GROUP_PCI;
4403     info.group_index        = 1;
4404     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4405     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4406     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4407     info.func               = __cvmx_error_display;
4408     info.user_info          = (long)
4409         "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
4410         "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
4411     fail |= cvmx_error_add(&info);
4412
4413     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4414     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4415     info.status_mask        = 1ull<<4 /* rpoison */;
4416     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4417     info.enable_mask        = 1ull<<4 /* rpoison */;
4418     info.flags              = 0;
4419     info.group              = CVMX_ERROR_GROUP_PCI;
4420     info.group_index        = 1;
4421     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4422     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4423     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4424     info.func               = __cvmx_error_display;
4425     info.user_info          = (long)
4426         "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
4427         "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
4428     fail |= cvmx_error_add(&info);
4429
4430     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4431     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4432     info.status_mask        = 1ull<<5 /* rcemrc */;
4433     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4434     info.enable_mask        = 1ull<<5 /* rcemrc */;
4435     info.flags              = 0;
4436     info.group              = CVMX_ERROR_GROUP_PCI;
4437     info.group_index        = 1;
4438     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4439     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4440     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4441     info.func               = __cvmx_error_display;
4442     info.user_info          = (long)
4443         "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
4444         "    pedc_radm_correctable_err\n";
4445     fail |= cvmx_error_add(&info);
4446
4447     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4448     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4449     info.status_mask        = 1ull<<6 /* rnfemrc */;
4450     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4451     info.enable_mask        = 1ull<<6 /* rnfemrc */;
4452     info.flags              = 0;
4453     info.group              = CVMX_ERROR_GROUP_PCI;
4454     info.group_index        = 1;
4455     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4456     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4457     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4458     info.func               = __cvmx_error_display;
4459     info.user_info          = (long)
4460         "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
4461         "    pedc_radm_nonfatal_err\n";
4462     fail |= cvmx_error_add(&info);
4463
4464     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4465     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4466     info.status_mask        = 1ull<<7 /* rfemrc */;
4467     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4468     info.enable_mask        = 1ull<<7 /* rfemrc */;
4469     info.flags              = 0;
4470     info.group              = CVMX_ERROR_GROUP_PCI;
4471     info.group_index        = 1;
4472     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4473     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4474     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4475     info.func               = __cvmx_error_display;
4476     info.user_info          = (long)
4477         "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
4478         "    pedc_radm_fatal_err\n"
4479         "    Bit set when a message with ERR_FATAL is set.\n";
4480     fail |= cvmx_error_add(&info);
4481
4482     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4483     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4484     info.status_mask        = 1ull<<8 /* rpmerc */;
4485     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4486     info.enable_mask        = 1ull<<8 /* rpmerc */;
4487     info.flags              = 0;
4488     info.group              = CVMX_ERROR_GROUP_PCI;
4489     info.group_index        = 1;
4490     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4491     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4492     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4493     info.func               = __cvmx_error_display;
4494     info.user_info          = (long)
4495         "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
4496         "    pedc_radm_pm_pme\n";
4497     fail |= cvmx_error_add(&info);
4498
4499     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4500     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4501     info.status_mask        = 1ull<<9 /* rptamrc */;
4502     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4503     info.enable_mask        = 1ull<<9 /* rptamrc */;
4504     info.flags              = 0;
4505     info.group              = CVMX_ERROR_GROUP_PCI;
4506     info.group_index        = 1;
4507     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4508     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4509     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4510     info.func               = __cvmx_error_display;
4511     info.user_info          = (long)
4512         "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
4513         "    (RC Mode only)\n"
4514         "    pedc_radm_pm_to_ack\n";
4515     fail |= cvmx_error_add(&info);
4516
4517     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4518     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4519     info.status_mask        = 1ull<<10 /* rumep */;
4520     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4521     info.enable_mask        = 1ull<<10 /* rumep */;
4522     info.flags              = 0;
4523     info.group              = CVMX_ERROR_GROUP_PCI;
4524     info.group_index        = 1;
4525     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4526     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4527     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4528     info.func               = __cvmx_error_display;
4529     info.user_info          = (long)
4530         "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
4531         "    pedc_radm_msg_unlock\n";
4532     fail |= cvmx_error_add(&info);
4533
4534     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4535     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4536     info.status_mask        = 1ull<<11 /* rvdm */;
4537     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4538     info.enable_mask        = 1ull<<11 /* rvdm */;
4539     info.flags              = 0;
4540     info.group              = CVMX_ERROR_GROUP_PCI;
4541     info.group_index        = 1;
4542     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4543     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4544     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4545     info.func               = __cvmx_error_display;
4546     info.user_info          = (long)
4547         "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
4548         "    pedc_radm_vendor_msg\n";
4549     fail |= cvmx_error_add(&info);
4550
4551     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4552     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4553     info.status_mask        = 1ull<<12 /* acto */;
4554     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4555     info.enable_mask        = 1ull<<12 /* acto */;
4556     info.flags              = 0;
4557     info.group              = CVMX_ERROR_GROUP_PCI;
4558     info.group_index        = 1;
4559     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4560     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4561     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4562     info.func               = __cvmx_error_display;
4563     info.user_info          = (long)
4564         "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
4565         "    pedc_radm_cpl_timeout\n";
4566     fail |= cvmx_error_add(&info);
4567
4568     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4569     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4570     info.status_mask        = 1ull<<13 /* rte */;
4571     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4572     info.enable_mask        = 1ull<<13 /* rte */;
4573     info.flags              = 0;
4574     info.group              = CVMX_ERROR_GROUP_PCI;
4575     info.group_index        = 1;
4576     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4577     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4578     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4579     info.func               = __cvmx_error_display;
4580     info.user_info          = (long)
4581         "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
4582         "    xdlh_replay_timeout_err\n"
4583         "    This bit is set when the REPLAY_TIMER expires in\n"
4584         "    the PCIE core. The probability of this bit being\n"
4585         "    set will increase with the traffic load.\n";
4586     fail |= cvmx_error_add(&info);
4587
4588     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4589     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4590     info.status_mask        = 1ull<<14 /* mre */;
4591     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4592     info.enable_mask        = 1ull<<14 /* mre */;
4593     info.flags              = 0;
4594     info.group              = CVMX_ERROR_GROUP_PCI;
4595     info.group_index        = 1;
4596     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4597     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4598     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4599     info.func               = __cvmx_error_display;
4600     info.user_info          = (long)
4601         "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
4602         "    xdlh_replay_num_rlover_err\n";
4603     fail |= cvmx_error_add(&info);
4604
4605     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4606     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4607     info.status_mask        = 1ull<<15 /* rdwdle */;
4608     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4609     info.enable_mask        = 1ull<<15 /* rdwdle */;
4610     info.flags              = 0;
4611     info.group              = CVMX_ERROR_GROUP_PCI;
4612     info.group_index        = 1;
4613     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4614     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4615     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4616     info.func               = __cvmx_error_display;
4617     info.user_info          = (long)
4618         "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
4619         "    rdlh_bad_dllp_err\n";
4620     fail |= cvmx_error_add(&info);
4621
4622     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4623     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4624     info.status_mask        = 1ull<<16 /* rtwdle */;
4625     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4626     info.enable_mask        = 1ull<<16 /* rtwdle */;
4627     info.flags              = 0;
4628     info.group              = CVMX_ERROR_GROUP_PCI;
4629     info.group_index        = 1;
4630     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4631     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4632     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4633     info.func               = __cvmx_error_display;
4634     info.user_info          = (long)
4635         "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
4636         "    rdlh_bad_tlp_err\n";
4637     fail |= cvmx_error_add(&info);
4638
4639     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4640     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4641     info.status_mask        = 1ull<<17 /* dpeoosd */;
4642     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4643     info.enable_mask        = 1ull<<17 /* dpeoosd */;
4644     info.flags              = 0;
4645     info.group              = CVMX_ERROR_GROUP_PCI;
4646     info.group_index        = 1;
4647     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4648     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4649     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4650     info.func               = __cvmx_error_display;
4651     info.user_info          = (long)
4652         "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
4653         "    rdlh_prot_err\n";
4654     fail |= cvmx_error_add(&info);
4655
4656     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4657     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4658     info.status_mask        = 1ull<<18 /* fcpvwt */;
4659     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4660     info.enable_mask        = 1ull<<18 /* fcpvwt */;
4661     info.flags              = 0;
4662     info.group              = CVMX_ERROR_GROUP_PCI;
4663     info.group_index        = 1;
4664     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4665     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4666     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4667     info.func               = __cvmx_error_display;
4668     info.user_info          = (long)
4669         "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
4670         "    rtlh_fc_prot_err\n";
4671     fail |= cvmx_error_add(&info);
4672
4673     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4674     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4675     info.status_mask        = 1ull<<19 /* rpe */;
4676     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4677     info.enable_mask        = 1ull<<19 /* rpe */;
4678     info.flags              = 0;
4679     info.group              = CVMX_ERROR_GROUP_PCI;
4680     info.group_index        = 1;
4681     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4682     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4683     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4684     info.func               = __cvmx_error_display;
4685     info.user_info          = (long)
4686         "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
4687         "    (RxStatus = 3b100) or disparity error\n"
4688         "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
4689         "    be asserted.\n"
4690         "    rmlh_rcvd_err\n";
4691     fail |= cvmx_error_add(&info);
4692
4693     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4694     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4695     info.status_mask        = 1ull<<20 /* fcuv */;
4696     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4697     info.enable_mask        = 1ull<<20 /* fcuv */;
4698     info.flags              = 0;
4699     info.group              = CVMX_ERROR_GROUP_PCI;
4700     info.group_index        = 1;
4701     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4702     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4703     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4704     info.func               = __cvmx_error_display;
4705     info.user_info          = (long)
4706         "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
4707         "    int_xadm_fc_prot_err\n";
4708     fail |= cvmx_error_add(&info);
4709
4710     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4711     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4712     info.status_mask        = 1ull<<21 /* rqo */;
4713     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4714     info.enable_mask        = 1ull<<21 /* rqo */;
4715     info.flags              = 0;
4716     info.group              = CVMX_ERROR_GROUP_PCI;
4717     info.group_index        = 1;
4718     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4719     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4720     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4721     info.func               = __cvmx_error_display;
4722     info.user_info          = (long)
4723         "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
4724         "    flow control advertisements are ignored\n"
4725         "    radm_qoverflow\n";
4726     fail |= cvmx_error_add(&info);
4727
4728     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4729     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4730     info.status_mask        = 1ull<<22 /* rauc */;
4731     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4732     info.enable_mask        = 1ull<<22 /* rauc */;
4733     info.flags              = 0;
4734     info.group              = CVMX_ERROR_GROUP_PCI;
4735     info.group_index        = 1;
4736     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4737     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4738     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4739     info.func               = __cvmx_error_display;
4740     info.user_info          = (long)
4741         "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
4742         "    radm_unexp_cpl_err\n";
4743     fail |= cvmx_error_add(&info);
4744
4745     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4746     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4747     info.status_mask        = 1ull<<23 /* racur */;
4748     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4749     info.enable_mask        = 1ull<<23 /* racur */;
4750     info.flags              = 0;
4751     info.group              = CVMX_ERROR_GROUP_PCI;
4752     info.group_index        = 1;
4753     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4754     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4755     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4756     info.func               = __cvmx_error_display;
4757     info.user_info          = (long)
4758         "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
4759         "    radm_rcvd_cpl_ur\n";
4760     fail |= cvmx_error_add(&info);
4761
4762     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4763     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4764     info.status_mask        = 1ull<<24 /* racca */;
4765     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4766     info.enable_mask        = 1ull<<24 /* racca */;
4767     info.flags              = 0;
4768     info.group              = CVMX_ERROR_GROUP_PCI;
4769     info.group_index        = 1;
4770     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4771     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4772     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4773     info.func               = __cvmx_error_display;
4774     info.user_info          = (long)
4775         "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
4776         "    radm_rcvd_cpl_ca\n";
4777     fail |= cvmx_error_add(&info);
4778
4779     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4780     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4781     info.status_mask        = 1ull<<25 /* caar */;
4782     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4783     info.enable_mask        = 1ull<<25 /* caar */;
4784     info.flags              = 0;
4785     info.group              = CVMX_ERROR_GROUP_PCI;
4786     info.group_index        = 1;
4787     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4788     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4789     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4790     info.func               = __cvmx_error_display;
4791     info.user_info          = (long)
4792         "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
4793         "    radm_rcvd_ca_req\n"
4794         "    This bit will never be set because Octeon does\n"
4795         "    not generate Completer Aborts.\n";
4796     fail |= cvmx_error_add(&info);
4797
4798     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4799     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4800     info.status_mask        = 1ull<<26 /* rarwdns */;
4801     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4802     info.enable_mask        = 1ull<<26 /* rarwdns */;
4803     info.flags              = 0;
4804     info.group              = CVMX_ERROR_GROUP_PCI;
4805     info.group_index        = 1;
4806     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4807     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4808     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4809     info.func               = __cvmx_error_display;
4810     info.user_info          = (long)
4811         "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
4812         "    radm_rcvd_ur_req\n";
4813     fail |= cvmx_error_add(&info);
4814
4815     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4816     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4817     info.status_mask        = 1ull<<27 /* ramtlp */;
4818     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4819     info.enable_mask        = 1ull<<27 /* ramtlp */;
4820     info.flags              = 0;
4821     info.group              = CVMX_ERROR_GROUP_PCI;
4822     info.group_index        = 1;
4823     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4824     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4825     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4826     info.func               = __cvmx_error_display;
4827     info.user_info          = (long)
4828         "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
4829         "    radm_mlf_tlp_err\n";
4830     fail |= cvmx_error_add(&info);
4831
4832     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4833     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4834     info.status_mask        = 1ull<<28 /* racpp */;
4835     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4836     info.enable_mask        = 1ull<<28 /* racpp */;
4837     info.flags              = 0;
4838     info.group              = CVMX_ERROR_GROUP_PCI;
4839     info.group_index        = 1;
4840     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4841     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4842     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4843     info.func               = __cvmx_error_display;
4844     info.user_info          = (long)
4845         "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
4846         "    radm_rcvd_cpl_poisoned\n";
4847     fail |= cvmx_error_add(&info);
4848
4849     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4850     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4851     info.status_mask        = 1ull<<29 /* rawwpp */;
4852     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4853     info.enable_mask        = 1ull<<29 /* rawwpp */;
4854     info.flags              = 0;
4855     info.group              = CVMX_ERROR_GROUP_PCI;
4856     info.group_index        = 1;
4857     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4858     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4859     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4860     info.func               = __cvmx_error_display;
4861     info.user_info          = (long)
4862         "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
4863         "    radm_rcvd_wreq_poisoned\n";
4864     fail |= cvmx_error_add(&info);
4865
4866     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4867     info.status_addr        = CVMX_PESCX_DBG_INFO(1);
4868     info.status_mask        = 1ull<<30 /* ecrc_e */;
4869     info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
4870     info.enable_mask        = 1ull<<30 /* ecrc_e */;
4871     info.flags              = 0;
4872     info.group              = CVMX_ERROR_GROUP_PCI;
4873     info.group_index        = 1;
4874     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4875     info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4876     info.parent.status_mask = 1ull<<58 /* c1_exc */;
4877     info.func               = __cvmx_error_display;
4878     info.user_info          = (long)
4879         "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
4880         "    radm_ecrc_err\n";
4881     fail |= cvmx_error_add(&info);
4882
4883     /* CVMX_RAD_REG_ERROR */
4884     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4885     info.status_addr        = CVMX_RAD_REG_ERROR;
4886     info.status_mask        = 1ull<<0 /* doorbell */;
4887     info.enable_addr        = CVMX_RAD_REG_INT_MASK;
4888     info.enable_mask        = 1ull<<0 /* doorbell */;
4889     info.flags              = 0;
4890     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4891     info.group_index        = 0;
4892     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4893     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4894     info.parent.status_mask = 1ull<<14 /* rad */;
4895     info.func               = __cvmx_error_display;
4896     info.user_info          = (long)
4897         "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4898     fail |= cvmx_error_add(&info);
4899
4900     /* CVMX_LMCX_MEM_CFG0(1) */
4901     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4902     info.status_addr        = CVMX_LMCX_MEM_CFG0(1);
4903     info.status_mask        = 0xfull<<21 /* sec_err */;
4904     info.enable_addr        = CVMX_LMCX_MEM_CFG0(1);
4905     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
4906     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4907     info.group              = CVMX_ERROR_GROUP_LMC;
4908     info.group_index        = 1;
4909     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4910     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4911     info.parent.status_mask = 1ull<<29 /* lmc1 */;
4912     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
4913     info.user_info          = (long)
4914         "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4915         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4916         "    [0] corresponds to DQ[63:0]_c0_p0\n"
4917         "    [1] corresponds to DQ[63:0]_c0_p1\n"
4918         "    [2] corresponds to DQ[63:0]_c1_p0\n"
4919         "    [3] corresponds to DQ[63:0]_c1_p1\n"
4920         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
4921         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
4922         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
4923         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
4924         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
4925         "      where _cC_pP denotes cycle C and phase P\n"
4926         "    Write of 1 will clear the corresponding error bit\n";
4927     fail |= cvmx_error_add(&info);
4928
4929     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4930     info.status_addr        = CVMX_LMCX_MEM_CFG0(1);
4931     info.status_mask        = 0xfull<<25 /* ded_err */;
4932     info.enable_addr        = CVMX_LMCX_MEM_CFG0(1);
4933     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
4934     info.flags              = 0;
4935     info.group              = CVMX_ERROR_GROUP_LMC;
4936     info.group_index        = 1;
4937     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4938     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4939     info.parent.status_mask = 1ull<<29 /* lmc1 */;
4940     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
4941     info.user_info          = (long)
4942         "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4943         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4944         "    [0] corresponds to DQ[63:0]_c0_p0\n"
4945         "    [1] corresponds to DQ[63:0]_c0_p1\n"
4946         "    [2] corresponds to DQ[63:0]_c1_p0\n"
4947         "    [3] corresponds to DQ[63:0]_c1_p1\n"
4948         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
4949         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
4950         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
4951         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
4952         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
4953         "      where _cC_pP denotes cycle C and phase P\n"
4954         "    Write of 1 will clear the corresponding error bit\n";
4955     fail |= cvmx_error_add(&info);
4956
4957     /* CVMX_PCSX_INTX_REG(0,1) */
4958     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4959     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
4960     info.status_mask        = 1ull<<2 /* an_err */;
4961     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
4962     info.enable_mask        = 1ull<<2 /* an_err_en */;
4963     info.flags              = 0;
4964     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4965     info.group_index        = 16;
4966     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4967     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4968     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4969     info.func               = __cvmx_error_display;
4970     info.user_info          = (long)
4971         "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
4972     fail |= cvmx_error_add(&info);
4973
4974     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4975     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
4976     info.status_mask        = 1ull<<3 /* txfifu */;
4977     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
4978     info.enable_mask        = 1ull<<3 /* txfifu_en */;
4979     info.flags              = 0;
4980     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4981     info.group_index        = 16;
4982     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4983     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4984     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4985     info.func               = __cvmx_error_display;
4986     info.user_info          = (long)
4987         "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4988         "    condition\n";
4989     fail |= cvmx_error_add(&info);
4990
4991     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4992     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
4993     info.status_mask        = 1ull<<4 /* txfifo */;
4994     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
4995     info.enable_mask        = 1ull<<4 /* txfifo_en */;
4996     info.flags              = 0;
4997     info.group              = CVMX_ERROR_GROUP_ETHERNET;
4998     info.group_index        = 16;
4999     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5000     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5001     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5002     info.func               = __cvmx_error_display;
5003     info.user_info          = (long)
5004         "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5005         "    condition\n";
5006     fail |= cvmx_error_add(&info);
5007
5008     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5009     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
5010     info.status_mask        = 1ull<<5 /* txbad */;
5011     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
5012     info.enable_mask        = 1ull<<5 /* txbad_en */;
5013     info.flags              = 0;
5014     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5015     info.group_index        = 16;
5016     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5017     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5018     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5019     info.func               = __cvmx_error_display;
5020     info.user_info          = (long)
5021         "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5022         "    state. Should never be set during normal operation\n";
5023     fail |= cvmx_error_add(&info);
5024
5025     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5026     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
5027     info.status_mask        = 1ull<<7 /* rxbad */;
5028     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
5029     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5030     info.flags              = 0;
5031     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5032     info.group_index        = 16;
5033     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5034     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5035     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5036     info.func               = __cvmx_error_display;
5037     info.user_info          = (long)
5038         "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5039         "    state. Should never be set during normal operation\n";
5040     fail |= cvmx_error_add(&info);
5041
5042     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5043     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
5044     info.status_mask        = 1ull<<8 /* rxlock */;
5045     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
5046     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5047     info.flags              = 0;
5048     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5049     info.group_index        = 16;
5050     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5051     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5052     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5053     info.func               = __cvmx_error_display;
5054     info.user_info          = (long)
5055         "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5056         "    failure occurs\n"
5057         "    Cannot fire in loopback1 mode\n";
5058     fail |= cvmx_error_add(&info);
5059
5060     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5061     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
5062     info.status_mask        = 1ull<<9 /* an_bad */;
5063     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
5064     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5065     info.flags              = 0;
5066     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5067     info.group_index        = 16;
5068     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5069     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5070     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5071     info.func               = __cvmx_error_display;
5072     info.user_info          = (long)
5073         "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5074         "    state. Should never be set during normal operation\n";
5075     fail |= cvmx_error_add(&info);
5076
5077     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5078     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
5079     info.status_mask        = 1ull<<10 /* sync_bad */;
5080     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
5081     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5082     info.flags              = 0;
5083     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5084     info.group_index        = 16;
5085     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5086     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5087     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5088     info.func               = __cvmx_error_display;
5089     info.user_info          = (long)
5090         "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5091         "    state. Should never be set during normal operation\n";
5092     fail |= cvmx_error_add(&info);
5093
5094     /* CVMX_PCSX_INTX_REG(1,1) */
5095     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5096     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5097     info.status_mask        = 1ull<<2 /* an_err */;
5098     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5099     info.enable_mask        = 1ull<<2 /* an_err_en */;
5100     info.flags              = 0;
5101     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5102     info.group_index        = 17;
5103     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5104     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5105     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5106     info.func               = __cvmx_error_display;
5107     info.user_info          = (long)
5108         "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
5109     fail |= cvmx_error_add(&info);
5110
5111     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5112     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5113     info.status_mask        = 1ull<<3 /* txfifu */;
5114     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5115     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5116     info.flags              = 0;
5117     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5118     info.group_index        = 17;
5119     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5120     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5121     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5122     info.func               = __cvmx_error_display;
5123     info.user_info          = (long)
5124         "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5125         "    condition\n";
5126     fail |= cvmx_error_add(&info);
5127
5128     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5129     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5130     info.status_mask        = 1ull<<4 /* txfifo */;
5131     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5132     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5133     info.flags              = 0;
5134     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5135     info.group_index        = 17;
5136     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5137     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5138     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5139     info.func               = __cvmx_error_display;
5140     info.user_info          = (long)
5141         "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5142         "    condition\n";
5143     fail |= cvmx_error_add(&info);
5144
5145     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5146     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5147     info.status_mask        = 1ull<<5 /* txbad */;
5148     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5149     info.enable_mask        = 1ull<<5 /* txbad_en */;
5150     info.flags              = 0;
5151     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5152     info.group_index        = 17;
5153     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5154     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5155     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5156     info.func               = __cvmx_error_display;
5157     info.user_info          = (long)
5158         "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5159         "    state. Should never be set during normal operation\n";
5160     fail |= cvmx_error_add(&info);
5161
5162     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5163     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5164     info.status_mask        = 1ull<<7 /* rxbad */;
5165     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5166     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5167     info.flags              = 0;
5168     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5169     info.group_index        = 17;
5170     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5171     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5172     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5173     info.func               = __cvmx_error_display;
5174     info.user_info          = (long)
5175         "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5176         "    state. Should never be set during normal operation\n";
5177     fail |= cvmx_error_add(&info);
5178
5179     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5180     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5181     info.status_mask        = 1ull<<8 /* rxlock */;
5182     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5183     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5184     info.flags              = 0;
5185     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5186     info.group_index        = 17;
5187     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5188     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5189     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5190     info.func               = __cvmx_error_display;
5191     info.user_info          = (long)
5192         "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5193         "    failure occurs\n"
5194         "    Cannot fire in loopback1 mode\n";
5195     fail |= cvmx_error_add(&info);
5196
5197     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5198     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5199     info.status_mask        = 1ull<<9 /* an_bad */;
5200     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5201     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5202     info.flags              = 0;
5203     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5204     info.group_index        = 17;
5205     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5206     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5207     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5208     info.func               = __cvmx_error_display;
5209     info.user_info          = (long)
5210         "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5211         "    state. Should never be set during normal operation\n";
5212     fail |= cvmx_error_add(&info);
5213
5214     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5215     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
5216     info.status_mask        = 1ull<<10 /* sync_bad */;
5217     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
5218     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5219     info.flags              = 0;
5220     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5221     info.group_index        = 17;
5222     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5223     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5224     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5225     info.func               = __cvmx_error_display;
5226     info.user_info          = (long)
5227         "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5228         "    state. Should never be set during normal operation\n";
5229     fail |= cvmx_error_add(&info);
5230
5231     /* CVMX_PCSX_INTX_REG(2,1) */
5232     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5233     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5234     info.status_mask        = 1ull<<2 /* an_err */;
5235     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5236     info.enable_mask        = 1ull<<2 /* an_err_en */;
5237     info.flags              = 0;
5238     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5239     info.group_index        = 18;
5240     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5241     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5242     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5243     info.func               = __cvmx_error_display;
5244     info.user_info          = (long)
5245         "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
5246     fail |= cvmx_error_add(&info);
5247
5248     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5249     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5250     info.status_mask        = 1ull<<3 /* txfifu */;
5251     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5252     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5253     info.flags              = 0;
5254     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5255     info.group_index        = 18;
5256     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5257     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5258     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5259     info.func               = __cvmx_error_display;
5260     info.user_info          = (long)
5261         "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5262         "    condition\n";
5263     fail |= cvmx_error_add(&info);
5264
5265     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5266     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5267     info.status_mask        = 1ull<<4 /* txfifo */;
5268     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5269     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5270     info.flags              = 0;
5271     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5272     info.group_index        = 18;
5273     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5274     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5275     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5276     info.func               = __cvmx_error_display;
5277     info.user_info          = (long)
5278         "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5279         "    condition\n";
5280     fail |= cvmx_error_add(&info);
5281
5282     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5283     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5284     info.status_mask        = 1ull<<5 /* txbad */;
5285     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5286     info.enable_mask        = 1ull<<5 /* txbad_en */;
5287     info.flags              = 0;
5288     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5289     info.group_index        = 18;
5290     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5291     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5292     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5293     info.func               = __cvmx_error_display;
5294     info.user_info          = (long)
5295         "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5296         "    state. Should never be set during normal operation\n";
5297     fail |= cvmx_error_add(&info);
5298
5299     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5300     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5301     info.status_mask        = 1ull<<7 /* rxbad */;
5302     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5303     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5304     info.flags              = 0;
5305     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5306     info.group_index        = 18;
5307     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5308     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5309     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5310     info.func               = __cvmx_error_display;
5311     info.user_info          = (long)
5312         "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5313         "    state. Should never be set during normal operation\n";
5314     fail |= cvmx_error_add(&info);
5315
5316     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5317     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5318     info.status_mask        = 1ull<<8 /* rxlock */;
5319     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5320     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5321     info.flags              = 0;
5322     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5323     info.group_index        = 18;
5324     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5325     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5326     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5327     info.func               = __cvmx_error_display;
5328     info.user_info          = (long)
5329         "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5330         "    failure occurs\n"
5331         "    Cannot fire in loopback1 mode\n";
5332     fail |= cvmx_error_add(&info);
5333
5334     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5335     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5336     info.status_mask        = 1ull<<9 /* an_bad */;
5337     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5338     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5339     info.flags              = 0;
5340     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5341     info.group_index        = 18;
5342     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5343     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5344     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5345     info.func               = __cvmx_error_display;
5346     info.user_info          = (long)
5347         "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5348         "    state. Should never be set during normal operation\n";
5349     fail |= cvmx_error_add(&info);
5350
5351     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5352     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
5353     info.status_mask        = 1ull<<10 /* sync_bad */;
5354     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
5355     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5356     info.flags              = 0;
5357     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5358     info.group_index        = 18;
5359     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5360     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5361     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5362     info.func               = __cvmx_error_display;
5363     info.user_info          = (long)
5364         "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5365         "    state. Should never be set during normal operation\n";
5366     fail |= cvmx_error_add(&info);
5367
5368     /* CVMX_PCSX_INTX_REG(3,1) */
5369     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5370     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5371     info.status_mask        = 1ull<<2 /* an_err */;
5372     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5373     info.enable_mask        = 1ull<<2 /* an_err_en */;
5374     info.flags              = 0;
5375     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5376     info.group_index        = 19;
5377     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5378     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5379     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5380     info.func               = __cvmx_error_display;
5381     info.user_info          = (long)
5382         "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
5383     fail |= cvmx_error_add(&info);
5384
5385     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5386     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5387     info.status_mask        = 1ull<<3 /* txfifu */;
5388     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5389     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5390     info.flags              = 0;
5391     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5392     info.group_index        = 19;
5393     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5394     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5395     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5396     info.func               = __cvmx_error_display;
5397     info.user_info          = (long)
5398         "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5399         "    condition\n";
5400     fail |= cvmx_error_add(&info);
5401
5402     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5403     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5404     info.status_mask        = 1ull<<4 /* txfifo */;
5405     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5406     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5407     info.flags              = 0;
5408     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5409     info.group_index        = 19;
5410     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5411     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5412     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5413     info.func               = __cvmx_error_display;
5414     info.user_info          = (long)
5415         "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5416         "    condition\n";
5417     fail |= cvmx_error_add(&info);
5418
5419     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5420     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5421     info.status_mask        = 1ull<<5 /* txbad */;
5422     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5423     info.enable_mask        = 1ull<<5 /* txbad_en */;
5424     info.flags              = 0;
5425     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5426     info.group_index        = 19;
5427     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5428     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5429     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5430     info.func               = __cvmx_error_display;
5431     info.user_info          = (long)
5432         "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5433         "    state. Should never be set during normal operation\n";
5434     fail |= cvmx_error_add(&info);
5435
5436     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5437     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5438     info.status_mask        = 1ull<<7 /* rxbad */;
5439     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5440     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5441     info.flags              = 0;
5442     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5443     info.group_index        = 19;
5444     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5445     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5446     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5447     info.func               = __cvmx_error_display;
5448     info.user_info          = (long)
5449         "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5450         "    state. Should never be set during normal operation\n";
5451     fail |= cvmx_error_add(&info);
5452
5453     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5454     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5455     info.status_mask        = 1ull<<8 /* rxlock */;
5456     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5457     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5458     info.flags              = 0;
5459     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5460     info.group_index        = 19;
5461     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5462     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5463     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5464     info.func               = __cvmx_error_display;
5465     info.user_info          = (long)
5466         "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5467         "    failure occurs\n"
5468         "    Cannot fire in loopback1 mode\n";
5469     fail |= cvmx_error_add(&info);
5470
5471     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5472     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5473     info.status_mask        = 1ull<<9 /* an_bad */;
5474     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5475     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5476     info.flags              = 0;
5477     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5478     info.group_index        = 19;
5479     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5480     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5481     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5482     info.func               = __cvmx_error_display;
5483     info.user_info          = (long)
5484         "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5485         "    state. Should never be set during normal operation\n";
5486     fail |= cvmx_error_add(&info);
5487
5488     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5489     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
5490     info.status_mask        = 1ull<<10 /* sync_bad */;
5491     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
5492     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5493     info.flags              = 0;
5494     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5495     info.group_index        = 19;
5496     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5497     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5498     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5499     info.func               = __cvmx_error_display;
5500     info.user_info          = (long)
5501         "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5502         "    state. Should never be set during normal operation\n";
5503     fail |= cvmx_error_add(&info);
5504
5505     /* CVMX_PCSXX_INT_REG(1) */
5506     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5507     info.status_addr        = CVMX_PCSXX_INT_REG(1);
5508     info.status_mask        = 1ull<<0 /* txflt */;
5509     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
5510     info.enable_mask        = 1ull<<0 /* txflt_en */;
5511     info.flags              = 0;
5512     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5513     info.group_index        = 16;
5514     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5515     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5516     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5517     info.func               = __cvmx_error_display;
5518     info.user_info          = (long)
5519         "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
5520     fail |= cvmx_error_add(&info);
5521
5522     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5523     info.status_addr        = CVMX_PCSXX_INT_REG(1);
5524     info.status_mask        = 1ull<<1 /* rxbad */;
5525     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
5526     info.enable_mask        = 1ull<<1 /* rxbad_en */;
5527     info.flags              = 0;
5528     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5529     info.group_index        = 16;
5530     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5531     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5532     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5533     info.func               = __cvmx_error_display;
5534     info.user_info          = (long)
5535         "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
5536     fail |= cvmx_error_add(&info);
5537
5538     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5539     info.status_addr        = CVMX_PCSXX_INT_REG(1);
5540     info.status_mask        = 1ull<<2 /* rxsynbad */;
5541     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
5542     info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
5543     info.flags              = 0;
5544     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5545     info.group_index        = 16;
5546     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5547     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5548     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5549     info.func               = __cvmx_error_display;
5550     info.user_info          = (long)
5551         "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
5552         "    in one of the 4 xaui lanes\n";
5553     fail |= cvmx_error_add(&info);
5554
5555     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5556     info.status_addr        = CVMX_PCSXX_INT_REG(1);
5557     info.status_mask        = 1ull<<4 /* synlos */;
5558     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
5559     info.enable_mask        = 1ull<<4 /* synlos_en */;
5560     info.flags              = 0;
5561     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5562     info.group_index        = 16;
5563     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5564     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5565     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5566     info.func               = __cvmx_error_display;
5567     info.user_info          = (long)
5568         "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
5569     fail |= cvmx_error_add(&info);
5570
5571     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5572     info.status_addr        = CVMX_PCSXX_INT_REG(1);
5573     info.status_mask        = 1ull<<5 /* algnlos */;
5574     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
5575     info.enable_mask        = 1ull<<5 /* algnlos_en */;
5576     info.flags              = 0;
5577     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5578     info.group_index        = 16;
5579     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5580     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5581     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5582     info.func               = __cvmx_error_display;
5583     info.user_info          = (long)
5584         "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
5585     fail |= cvmx_error_add(&info);
5586
5587     /* CVMX_PCSX_INTX_REG(0,0) */
5588     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5589     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5590     info.status_mask        = 1ull<<2 /* an_err */;
5591     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5592     info.enable_mask        = 1ull<<2 /* an_err_en */;
5593     info.flags              = 0;
5594     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5595     info.group_index        = 0;
5596     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5597     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5598     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5599     info.func               = __cvmx_error_display;
5600     info.user_info          = (long)
5601         "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5602     fail |= cvmx_error_add(&info);
5603
5604     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5605     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5606     info.status_mask        = 1ull<<3 /* txfifu */;
5607     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5608     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5609     info.flags              = 0;
5610     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5611     info.group_index        = 0;
5612     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5613     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5614     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5615     info.func               = __cvmx_error_display;
5616     info.user_info          = (long)
5617         "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5618         "    condition\n";
5619     fail |= cvmx_error_add(&info);
5620
5621     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5622     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5623     info.status_mask        = 1ull<<4 /* txfifo */;
5624     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5625     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5626     info.flags              = 0;
5627     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5628     info.group_index        = 0;
5629     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5630     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5631     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5632     info.func               = __cvmx_error_display;
5633     info.user_info          = (long)
5634         "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5635         "    condition\n";
5636     fail |= cvmx_error_add(&info);
5637
5638     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5639     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5640     info.status_mask        = 1ull<<5 /* txbad */;
5641     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5642     info.enable_mask        = 1ull<<5 /* txbad_en */;
5643     info.flags              = 0;
5644     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5645     info.group_index        = 0;
5646     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5647     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5648     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5649     info.func               = __cvmx_error_display;
5650     info.user_info          = (long)
5651         "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5652         "    state. Should never be set during normal operation\n";
5653     fail |= cvmx_error_add(&info);
5654
5655     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5656     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5657     info.status_mask        = 1ull<<7 /* rxbad */;
5658     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5659     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5660     info.flags              = 0;
5661     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5662     info.group_index        = 0;
5663     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5664     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5665     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5666     info.func               = __cvmx_error_display;
5667     info.user_info          = (long)
5668         "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5669         "    state. Should never be set during normal operation\n";
5670     fail |= cvmx_error_add(&info);
5671
5672     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5673     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5674     info.status_mask        = 1ull<<8 /* rxlock */;
5675     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5676     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5677     info.flags              = 0;
5678     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5679     info.group_index        = 0;
5680     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5681     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5682     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5683     info.func               = __cvmx_error_display;
5684     info.user_info          = (long)
5685         "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5686         "    failure occurs\n"
5687         "    Cannot fire in loopback1 mode\n";
5688     fail |= cvmx_error_add(&info);
5689
5690     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5691     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5692     info.status_mask        = 1ull<<9 /* an_bad */;
5693     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5694     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5695     info.flags              = 0;
5696     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5697     info.group_index        = 0;
5698     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5699     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5700     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5701     info.func               = __cvmx_error_display;
5702     info.user_info          = (long)
5703         "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5704         "    state. Should never be set during normal operation\n";
5705     fail |= cvmx_error_add(&info);
5706
5707     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5708     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
5709     info.status_mask        = 1ull<<10 /* sync_bad */;
5710     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
5711     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5712     info.flags              = 0;
5713     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5714     info.group_index        = 0;
5715     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5716     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5717     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5718     info.func               = __cvmx_error_display;
5719     info.user_info          = (long)
5720         "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5721         "    state. Should never be set during normal operation\n";
5722     fail |= cvmx_error_add(&info);
5723
5724     /* CVMX_PCSX_INTX_REG(1,0) */
5725     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5726     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5727     info.status_mask        = 1ull<<2 /* an_err */;
5728     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5729     info.enable_mask        = 1ull<<2 /* an_err_en */;
5730     info.flags              = 0;
5731     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5732     info.group_index        = 1;
5733     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5734     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5735     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5736     info.func               = __cvmx_error_display;
5737     info.user_info          = (long)
5738         "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5739     fail |= cvmx_error_add(&info);
5740
5741     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5742     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5743     info.status_mask        = 1ull<<3 /* txfifu */;
5744     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5745     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5746     info.flags              = 0;
5747     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5748     info.group_index        = 1;
5749     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5750     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5751     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5752     info.func               = __cvmx_error_display;
5753     info.user_info          = (long)
5754         "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5755         "    condition\n";
5756     fail |= cvmx_error_add(&info);
5757
5758     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5759     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5760     info.status_mask        = 1ull<<4 /* txfifo */;
5761     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5762     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5763     info.flags              = 0;
5764     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5765     info.group_index        = 1;
5766     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5767     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5768     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5769     info.func               = __cvmx_error_display;
5770     info.user_info          = (long)
5771         "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5772         "    condition\n";
5773     fail |= cvmx_error_add(&info);
5774
5775     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5776     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5777     info.status_mask        = 1ull<<5 /* txbad */;
5778     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5779     info.enable_mask        = 1ull<<5 /* txbad_en */;
5780     info.flags              = 0;
5781     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5782     info.group_index        = 1;
5783     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5784     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5785     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5786     info.func               = __cvmx_error_display;
5787     info.user_info          = (long)
5788         "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5789         "    state. Should never be set during normal operation\n";
5790     fail |= cvmx_error_add(&info);
5791
5792     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5793     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5794     info.status_mask        = 1ull<<7 /* rxbad */;
5795     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5796     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5797     info.flags              = 0;
5798     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5799     info.group_index        = 1;
5800     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5801     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5802     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5803     info.func               = __cvmx_error_display;
5804     info.user_info          = (long)
5805         "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5806         "    state. Should never be set during normal operation\n";
5807     fail |= cvmx_error_add(&info);
5808
5809     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5810     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5811     info.status_mask        = 1ull<<8 /* rxlock */;
5812     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5813     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5814     info.flags              = 0;
5815     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5816     info.group_index        = 1;
5817     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5818     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5819     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5820     info.func               = __cvmx_error_display;
5821     info.user_info          = (long)
5822         "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5823         "    failure occurs\n"
5824         "    Cannot fire in loopback1 mode\n";
5825     fail |= cvmx_error_add(&info);
5826
5827     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5828     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5829     info.status_mask        = 1ull<<9 /* an_bad */;
5830     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5831     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5832     info.flags              = 0;
5833     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5834     info.group_index        = 1;
5835     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5836     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5837     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5838     info.func               = __cvmx_error_display;
5839     info.user_info          = (long)
5840         "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5841         "    state. Should never be set during normal operation\n";
5842     fail |= cvmx_error_add(&info);
5843
5844     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5845     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
5846     info.status_mask        = 1ull<<10 /* sync_bad */;
5847     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
5848     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5849     info.flags              = 0;
5850     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5851     info.group_index        = 1;
5852     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5853     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5854     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5855     info.func               = __cvmx_error_display;
5856     info.user_info          = (long)
5857         "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5858         "    state. Should never be set during normal operation\n";
5859     fail |= cvmx_error_add(&info);
5860
5861     /* CVMX_PCSX_INTX_REG(2,0) */
5862     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5863     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5864     info.status_mask        = 1ull<<2 /* an_err */;
5865     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5866     info.enable_mask        = 1ull<<2 /* an_err_en */;
5867     info.flags              = 0;
5868     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5869     info.group_index        = 2;
5870     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5871     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5872     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5873     info.func               = __cvmx_error_display;
5874     info.user_info          = (long)
5875         "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5876     fail |= cvmx_error_add(&info);
5877
5878     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5879     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5880     info.status_mask        = 1ull<<3 /* txfifu */;
5881     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5882     info.enable_mask        = 1ull<<3 /* txfifu_en */;
5883     info.flags              = 0;
5884     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5885     info.group_index        = 2;
5886     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5887     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5888     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5889     info.func               = __cvmx_error_display;
5890     info.user_info          = (long)
5891         "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5892         "    condition\n";
5893     fail |= cvmx_error_add(&info);
5894
5895     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5896     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5897     info.status_mask        = 1ull<<4 /* txfifo */;
5898     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5899     info.enable_mask        = 1ull<<4 /* txfifo_en */;
5900     info.flags              = 0;
5901     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5902     info.group_index        = 2;
5903     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5904     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5905     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5906     info.func               = __cvmx_error_display;
5907     info.user_info          = (long)
5908         "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5909         "    condition\n";
5910     fail |= cvmx_error_add(&info);
5911
5912     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5913     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5914     info.status_mask        = 1ull<<5 /* txbad */;
5915     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5916     info.enable_mask        = 1ull<<5 /* txbad_en */;
5917     info.flags              = 0;
5918     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5919     info.group_index        = 2;
5920     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5921     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5922     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5923     info.func               = __cvmx_error_display;
5924     info.user_info          = (long)
5925         "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5926         "    state. Should never be set during normal operation\n";
5927     fail |= cvmx_error_add(&info);
5928
5929     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5930     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5931     info.status_mask        = 1ull<<7 /* rxbad */;
5932     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5933     info.enable_mask        = 1ull<<7 /* rxbad_en */;
5934     info.flags              = 0;
5935     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5936     info.group_index        = 2;
5937     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5938     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5939     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5940     info.func               = __cvmx_error_display;
5941     info.user_info          = (long)
5942         "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
5943         "    state. Should never be set during normal operation\n";
5944     fail |= cvmx_error_add(&info);
5945
5946     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5947     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5948     info.status_mask        = 1ull<<8 /* rxlock */;
5949     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5950     info.enable_mask        = 1ull<<8 /* rxlock_en */;
5951     info.flags              = 0;
5952     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5953     info.group_index        = 2;
5954     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5955     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5956     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5957     info.func               = __cvmx_error_display;
5958     info.user_info          = (long)
5959         "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5960         "    failure occurs\n"
5961         "    Cannot fire in loopback1 mode\n";
5962     fail |= cvmx_error_add(&info);
5963
5964     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5965     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5966     info.status_mask        = 1ull<<9 /* an_bad */;
5967     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5968     info.enable_mask        = 1ull<<9 /* an_bad_en */;
5969     info.flags              = 0;
5970     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5971     info.group_index        = 2;
5972     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5973     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5974     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5975     info.func               = __cvmx_error_display;
5976     info.user_info          = (long)
5977         "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5978         "    state. Should never be set during normal operation\n";
5979     fail |= cvmx_error_add(&info);
5980
5981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5982     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
5983     info.status_mask        = 1ull<<10 /* sync_bad */;
5984     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
5985     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
5986     info.flags              = 0;
5987     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5988     info.group_index        = 2;
5989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5990     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5991     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5992     info.func               = __cvmx_error_display;
5993     info.user_info          = (long)
5994         "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5995         "    state. Should never be set during normal operation\n";
5996     fail |= cvmx_error_add(&info);
5997
5998     /* CVMX_PCSX_INTX_REG(3,0) */
5999     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6000     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6001     info.status_mask        = 1ull<<2 /* an_err */;
6002     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6003     info.enable_mask        = 1ull<<2 /* an_err_en */;
6004     info.flags              = 0;
6005     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6006     info.group_index        = 3;
6007     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6008     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6009     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6010     info.func               = __cvmx_error_display;
6011     info.user_info          = (long)
6012         "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
6013     fail |= cvmx_error_add(&info);
6014
6015     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6016     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6017     info.status_mask        = 1ull<<3 /* txfifu */;
6018     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6019     info.enable_mask        = 1ull<<3 /* txfifu_en */;
6020     info.flags              = 0;
6021     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6022     info.group_index        = 3;
6023     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6024     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6025     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6026     info.func               = __cvmx_error_display;
6027     info.user_info          = (long)
6028         "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
6029         "    condition\n";
6030     fail |= cvmx_error_add(&info);
6031
6032     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6033     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6034     info.status_mask        = 1ull<<4 /* txfifo */;
6035     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6036     info.enable_mask        = 1ull<<4 /* txfifo_en */;
6037     info.flags              = 0;
6038     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6039     info.group_index        = 3;
6040     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6041     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6042     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6043     info.func               = __cvmx_error_display;
6044     info.user_info          = (long)
6045         "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
6046         "    condition\n";
6047     fail |= cvmx_error_add(&info);
6048
6049     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6050     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6051     info.status_mask        = 1ull<<5 /* txbad */;
6052     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6053     info.enable_mask        = 1ull<<5 /* txbad_en */;
6054     info.flags              = 0;
6055     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6056     info.group_index        = 3;
6057     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6058     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6059     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6060     info.func               = __cvmx_error_display;
6061     info.user_info          = (long)
6062         "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
6063         "    state. Should never be set during normal operation\n";
6064     fail |= cvmx_error_add(&info);
6065
6066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6067     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6068     info.status_mask        = 1ull<<7 /* rxbad */;
6069     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6070     info.enable_mask        = 1ull<<7 /* rxbad_en */;
6071     info.flags              = 0;
6072     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6073     info.group_index        = 3;
6074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6075     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6076     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6077     info.func               = __cvmx_error_display;
6078     info.user_info          = (long)
6079         "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
6080         "    state. Should never be set during normal operation\n";
6081     fail |= cvmx_error_add(&info);
6082
6083     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6084     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6085     info.status_mask        = 1ull<<8 /* rxlock */;
6086     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6087     info.enable_mask        = 1ull<<8 /* rxlock_en */;
6088     info.flags              = 0;
6089     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6090     info.group_index        = 3;
6091     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6092     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6093     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6094     info.func               = __cvmx_error_display;
6095     info.user_info          = (long)
6096         "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
6097         "    failure occurs\n"
6098         "    Cannot fire in loopback1 mode\n";
6099     fail |= cvmx_error_add(&info);
6100
6101     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6102     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6103     info.status_mask        = 1ull<<9 /* an_bad */;
6104     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6105     info.enable_mask        = 1ull<<9 /* an_bad_en */;
6106     info.flags              = 0;
6107     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6108     info.group_index        = 3;
6109     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6110     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6111     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6112     info.func               = __cvmx_error_display;
6113     info.user_info          = (long)
6114         "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
6115         "    state. Should never be set during normal operation\n";
6116     fail |= cvmx_error_add(&info);
6117
6118     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6119     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
6120     info.status_mask        = 1ull<<10 /* sync_bad */;
6121     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
6122     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
6123     info.flags              = 0;
6124     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6125     info.group_index        = 3;
6126     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6127     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6128     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6129     info.func               = __cvmx_error_display;
6130     info.user_info          = (long)
6131         "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
6132         "    state. Should never be set during normal operation\n";
6133     fail |= cvmx_error_add(&info);
6134
6135     /* CVMX_PCSXX_INT_REG(0) */
6136     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6137     info.status_addr        = CVMX_PCSXX_INT_REG(0);
6138     info.status_mask        = 1ull<<0 /* txflt */;
6139     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
6140     info.enable_mask        = 1ull<<0 /* txflt_en */;
6141     info.flags              = 0;
6142     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6143     info.group_index        = 0;
6144     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6145     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6146     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6147     info.func               = __cvmx_error_display;
6148     info.user_info          = (long)
6149         "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
6150     fail |= cvmx_error_add(&info);
6151
6152     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6153     info.status_addr        = CVMX_PCSXX_INT_REG(0);
6154     info.status_mask        = 1ull<<1 /* rxbad */;
6155     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
6156     info.enable_mask        = 1ull<<1 /* rxbad_en */;
6157     info.flags              = 0;
6158     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6159     info.group_index        = 0;
6160     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6161     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6162     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6163     info.func               = __cvmx_error_display;
6164     info.user_info          = (long)
6165         "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
6166     fail |= cvmx_error_add(&info);
6167
6168     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6169     info.status_addr        = CVMX_PCSXX_INT_REG(0);
6170     info.status_mask        = 1ull<<2 /* rxsynbad */;
6171     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
6172     info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
6173     info.flags              = 0;
6174     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6175     info.group_index        = 0;
6176     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6177     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6178     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6179     info.func               = __cvmx_error_display;
6180     info.user_info          = (long)
6181         "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
6182         "    in one of the 4 xaui lanes\n";
6183     fail |= cvmx_error_add(&info);
6184
6185     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6186     info.status_addr        = CVMX_PCSXX_INT_REG(0);
6187     info.status_mask        = 1ull<<4 /* synlos */;
6188     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
6189     info.enable_mask        = 1ull<<4 /* synlos_en */;
6190     info.flags              = 0;
6191     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6192     info.group_index        = 0;
6193     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6194     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6195     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6196     info.func               = __cvmx_error_display;
6197     info.user_info          = (long)
6198         "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
6199     fail |= cvmx_error_add(&info);
6200
6201     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6202     info.status_addr        = CVMX_PCSXX_INT_REG(0);
6203     info.status_mask        = 1ull<<5 /* algnlos */;
6204     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
6205     info.enable_mask        = 1ull<<5 /* algnlos_en */;
6206     info.flags              = 0;
6207     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6208     info.group_index        = 0;
6209     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6210     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6211     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
6212     info.func               = __cvmx_error_display;
6213     info.user_info          = (long)
6214         "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
6215     fail |= cvmx_error_add(&info);
6216
6217     /* CVMX_KEY_INT_SUM */
6218     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6219     info.status_addr        = CVMX_KEY_INT_SUM;
6220     info.status_mask        = 1ull<<0 /* ked0_sbe */;
6221     info.enable_addr        = CVMX_KEY_INT_ENB;
6222     info.enable_mask        = 1ull<<0 /* ked0_sbe */;
6223     info.flags              = 0;
6224     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6225     info.group_index        = 0;
6226     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6227     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6228     info.parent.status_mask = 1ull<<4 /* key */;
6229     info.func               = __cvmx_error_display;
6230     info.user_info          = (long)
6231         "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
6232 ;
6233     fail |= cvmx_error_add(&info);
6234
6235     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6236     info.status_addr        = CVMX_KEY_INT_SUM;
6237     info.status_mask        = 1ull<<1 /* ked0_dbe */;
6238     info.enable_addr        = CVMX_KEY_INT_ENB;
6239     info.enable_mask        = 1ull<<1 /* ked0_dbe */;
6240     info.flags              = 0;
6241     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6242     info.group_index        = 0;
6243     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6244     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6245     info.parent.status_mask = 1ull<<4 /* key */;
6246     info.func               = __cvmx_error_display;
6247     info.user_info          = (long)
6248         "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
6249 ;
6250     fail |= cvmx_error_add(&info);
6251
6252     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6253     info.status_addr        = CVMX_KEY_INT_SUM;
6254     info.status_mask        = 1ull<<2 /* ked1_sbe */;
6255     info.enable_addr        = CVMX_KEY_INT_ENB;
6256     info.enable_mask        = 1ull<<2 /* ked1_sbe */;
6257     info.flags              = 0;
6258     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6259     info.group_index        = 0;
6260     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6261     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6262     info.parent.status_mask = 1ull<<4 /* key */;
6263     info.func               = __cvmx_error_display;
6264     info.user_info          = (long)
6265         "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
6266 ;
6267     fail |= cvmx_error_add(&info);
6268
6269     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6270     info.status_addr        = CVMX_KEY_INT_SUM;
6271     info.status_mask        = 1ull<<3 /* ked1_dbe */;
6272     info.enable_addr        = CVMX_KEY_INT_ENB;
6273     info.enable_mask        = 1ull<<3 /* ked1_dbe */;
6274     info.flags              = 0;
6275     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6276     info.group_index        = 0;
6277     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6278     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6279     info.parent.status_mask = 1ull<<4 /* key */;
6280     info.func               = __cvmx_error_display;
6281     info.user_info          = (long)
6282         "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
6283 ;
6284     fail |= cvmx_error_add(&info);
6285
6286     /* CVMX_MIO_BOOT_ERR */
6287     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6288     info.status_addr        = CVMX_MIO_BOOT_ERR;
6289     info.status_mask        = 1ull<<0 /* adr_err */;
6290     info.enable_addr        = CVMX_MIO_BOOT_INT;
6291     info.enable_mask        = 1ull<<0 /* adr_int */;
6292     info.flags              = 0;
6293     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6294     info.group_index        = 0;
6295     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6296     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6297     info.parent.status_mask = 1ull<<0 /* mio */;
6298     info.func               = __cvmx_error_display;
6299     info.user_info          = (long)
6300         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
6301     fail |= cvmx_error_add(&info);
6302
6303     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6304     info.status_addr        = CVMX_MIO_BOOT_ERR;
6305     info.status_mask        = 1ull<<1 /* wait_err */;
6306     info.enable_addr        = CVMX_MIO_BOOT_INT;
6307     info.enable_mask        = 1ull<<1 /* wait_int */;
6308     info.flags              = 0;
6309     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6310     info.group_index        = 0;
6311     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6312     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6313     info.parent.status_mask = 1ull<<0 /* mio */;
6314     info.func               = __cvmx_error_display;
6315     info.user_info          = (long)
6316         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
6317     fail |= cvmx_error_add(&info);
6318
6319     /* CVMX_PIP_INT_REG */
6320     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6321     info.status_addr        = CVMX_PIP_INT_REG;
6322     info.status_mask        = 1ull<<3 /* prtnxa */;
6323     info.enable_addr        = CVMX_PIP_INT_EN;
6324     info.enable_mask        = 1ull<<3 /* prtnxa */;
6325     info.flags              = 0;
6326     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6327     info.group_index        = 0;
6328     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6329     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6330     info.parent.status_mask = 1ull<<20 /* pip */;
6331     info.func               = __cvmx_error_display;
6332     info.user_info          = (long)
6333         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
6334     fail |= cvmx_error_add(&info);
6335
6336     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6337     info.status_addr        = CVMX_PIP_INT_REG;
6338     info.status_mask        = 1ull<<4 /* badtag */;
6339     info.enable_addr        = CVMX_PIP_INT_EN;
6340     info.enable_mask        = 1ull<<4 /* badtag */;
6341     info.flags              = 0;
6342     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6343     info.group_index        = 0;
6344     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6345     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6346     info.parent.status_mask = 1ull<<20 /* pip */;
6347     info.func               = __cvmx_error_display;
6348     info.user_info          = (long)
6349         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
6350     fail |= cvmx_error_add(&info);
6351
6352     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6353     info.status_addr        = CVMX_PIP_INT_REG;
6354     info.status_mask        = 1ull<<5 /* skprunt */;
6355     info.enable_addr        = CVMX_PIP_INT_EN;
6356     info.enable_mask        = 1ull<<5 /* skprunt */;
6357     info.flags              = 0;
6358     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6359     info.group_index        = 0;
6360     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6361     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6362     info.parent.status_mask = 1ull<<20 /* pip */;
6363     info.func               = __cvmx_error_display;
6364     info.user_info          = (long)
6365         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
6366         "    This interrupt can occur with received PARTIAL\n"
6367         "    packets that are truncated to SKIP bytes or\n"
6368         "    smaller.\n";
6369     fail |= cvmx_error_add(&info);
6370
6371     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6372     info.status_addr        = CVMX_PIP_INT_REG;
6373     info.status_mask        = 1ull<<6 /* todoovr */;
6374     info.enable_addr        = CVMX_PIP_INT_EN;
6375     info.enable_mask        = 1ull<<6 /* todoovr */;
6376     info.flags              = 0;
6377     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6378     info.group_index        = 0;
6379     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6380     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6381     info.parent.status_mask = 1ull<<20 /* pip */;
6382     info.func               = __cvmx_error_display;
6383     info.user_info          = (long)
6384         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
6385     fail |= cvmx_error_add(&info);
6386
6387     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6388     info.status_addr        = CVMX_PIP_INT_REG;
6389     info.status_mask        = 1ull<<7 /* feperr */;
6390     info.enable_addr        = CVMX_PIP_INT_EN;
6391     info.enable_mask        = 1ull<<7 /* feperr */;
6392     info.flags              = 0;
6393     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6394     info.group_index        = 0;
6395     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6396     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6397     info.parent.status_mask = 1ull<<20 /* pip */;
6398     info.func               = __cvmx_error_display;
6399     info.user_info          = (long)
6400         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
6401     fail |= cvmx_error_add(&info);
6402
6403     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6404     info.status_addr        = CVMX_PIP_INT_REG;
6405     info.status_mask        = 1ull<<8 /* beperr */;
6406     info.enable_addr        = CVMX_PIP_INT_EN;
6407     info.enable_mask        = 1ull<<8 /* beperr */;
6408     info.flags              = 0;
6409     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6410     info.group_index        = 0;
6411     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6412     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6413     info.parent.status_mask = 1ull<<20 /* pip */;
6414     info.func               = __cvmx_error_display;
6415     info.user_info          = (long)
6416         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
6417     fail |= cvmx_error_add(&info);
6418
6419     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6420     info.status_addr        = CVMX_PIP_INT_REG;
6421     info.status_mask        = 1ull<<12 /* punyerr */;
6422     info.enable_addr        = CVMX_PIP_INT_EN;
6423     info.enable_mask        = 1ull<<12 /* punyerr */;
6424     info.flags              = 0;
6425     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6426     info.group_index        = 0;
6427     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6428     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6429     info.parent.status_mask = 1ull<<20 /* pip */;
6430     info.func               = __cvmx_error_display;
6431     info.user_info          = (long)
6432         "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
6433         "    stripping in IPD is enable\n";
6434     fail |= cvmx_error_add(&info);
6435
6436     /* CVMX_FPA_INT_SUM */
6437     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6438     info.status_addr        = CVMX_FPA_INT_SUM;
6439     info.status_mask        = 1ull<<0 /* fed0_sbe */;
6440     info.enable_addr        = CVMX_FPA_INT_ENB;
6441     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
6442     info.flags              = 0;
6443     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6444     info.group_index        = 0;
6445     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6446     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6447     info.parent.status_mask = 1ull<<5 /* fpa */;
6448     info.func               = __cvmx_error_display;
6449     info.user_info          = (long)
6450         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
6451     fail |= cvmx_error_add(&info);
6452
6453     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6454     info.status_addr        = CVMX_FPA_INT_SUM;
6455     info.status_mask        = 1ull<<1 /* fed0_dbe */;
6456     info.enable_addr        = CVMX_FPA_INT_ENB;
6457     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
6458     info.flags              = 0;
6459     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6460     info.group_index        = 0;
6461     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6462     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6463     info.parent.status_mask = 1ull<<5 /* fpa */;
6464     info.func               = __cvmx_error_display;
6465     info.user_info          = (long)
6466         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
6467     fail |= cvmx_error_add(&info);
6468
6469     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6470     info.status_addr        = CVMX_FPA_INT_SUM;
6471     info.status_mask        = 1ull<<2 /* fed1_sbe */;
6472     info.enable_addr        = CVMX_FPA_INT_ENB;
6473     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
6474     info.flags              = 0;
6475     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6476     info.group_index        = 0;
6477     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6478     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6479     info.parent.status_mask = 1ull<<5 /* fpa */;
6480     info.func               = __cvmx_error_display;
6481     info.user_info          = (long)
6482         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
6483     fail |= cvmx_error_add(&info);
6484
6485     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6486     info.status_addr        = CVMX_FPA_INT_SUM;
6487     info.status_mask        = 1ull<<3 /* fed1_dbe */;
6488     info.enable_addr        = CVMX_FPA_INT_ENB;
6489     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
6490     info.flags              = 0;
6491     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6492     info.group_index        = 0;
6493     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6494     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6495     info.parent.status_mask = 1ull<<5 /* fpa */;
6496     info.func               = __cvmx_error_display;
6497     info.user_info          = (long)
6498         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
6499     fail |= cvmx_error_add(&info);
6500
6501     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6502     info.status_addr        = CVMX_FPA_INT_SUM;
6503     info.status_mask        = 1ull<<4 /* q0_und */;
6504     info.enable_addr        = CVMX_FPA_INT_ENB;
6505     info.enable_mask        = 1ull<<4 /* q0_und */;
6506     info.flags              = 0;
6507     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6508     info.group_index        = 0;
6509     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6510     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6511     info.parent.status_mask = 1ull<<5 /* fpa */;
6512     info.func               = __cvmx_error_display;
6513     info.user_info          = (long)
6514         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
6515         "    negative.\n";
6516     fail |= cvmx_error_add(&info);
6517
6518     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6519     info.status_addr        = CVMX_FPA_INT_SUM;
6520     info.status_mask        = 1ull<<5 /* q0_coff */;
6521     info.enable_addr        = CVMX_FPA_INT_ENB;
6522     info.enable_mask        = 1ull<<5 /* q0_coff */;
6523     info.flags              = 0;
6524     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6525     info.group_index        = 0;
6526     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6527     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6528     info.parent.status_mask = 1ull<<5 /* fpa */;
6529     info.func               = __cvmx_error_display;
6530     info.user_info          = (long)
6531         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
6532         "    the count available is greater than pointers\n"
6533         "    present in the FPA.\n";
6534     fail |= cvmx_error_add(&info);
6535
6536     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6537     info.status_addr        = CVMX_FPA_INT_SUM;
6538     info.status_mask        = 1ull<<6 /* q0_perr */;
6539     info.enable_addr        = CVMX_FPA_INT_ENB;
6540     info.enable_mask        = 1ull<<6 /* q0_perr */;
6541     info.flags              = 0;
6542     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6543     info.group_index        = 0;
6544     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6545     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6546     info.parent.status_mask = 1ull<<5 /* fpa */;
6547     info.func               = __cvmx_error_display;
6548     info.user_info          = (long)
6549         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
6550         "    the L2C does not have the FPA owner ship bit set.\n";
6551     fail |= cvmx_error_add(&info);
6552
6553     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6554     info.status_addr        = CVMX_FPA_INT_SUM;
6555     info.status_mask        = 1ull<<7 /* q1_und */;
6556     info.enable_addr        = CVMX_FPA_INT_ENB;
6557     info.enable_mask        = 1ull<<7 /* q1_und */;
6558     info.flags              = 0;
6559     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6560     info.group_index        = 0;
6561     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6562     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6563     info.parent.status_mask = 1ull<<5 /* fpa */;
6564     info.func               = __cvmx_error_display;
6565     info.user_info          = (long)
6566         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
6567         "    negative.\n";
6568     fail |= cvmx_error_add(&info);
6569
6570     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6571     info.status_addr        = CVMX_FPA_INT_SUM;
6572     info.status_mask        = 1ull<<8 /* q1_coff */;
6573     info.enable_addr        = CVMX_FPA_INT_ENB;
6574     info.enable_mask        = 1ull<<8 /* q1_coff */;
6575     info.flags              = 0;
6576     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6577     info.group_index        = 0;
6578     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6579     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6580     info.parent.status_mask = 1ull<<5 /* fpa */;
6581     info.func               = __cvmx_error_display;
6582     info.user_info          = (long)
6583         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
6584         "    the count available is greater than pointers\n"
6585         "    present in the FPA.\n";
6586     fail |= cvmx_error_add(&info);
6587
6588     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6589     info.status_addr        = CVMX_FPA_INT_SUM;
6590     info.status_mask        = 1ull<<9 /* q1_perr */;
6591     info.enable_addr        = CVMX_FPA_INT_ENB;
6592     info.enable_mask        = 1ull<<9 /* q1_perr */;
6593     info.flags              = 0;
6594     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6595     info.group_index        = 0;
6596     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6597     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6598     info.parent.status_mask = 1ull<<5 /* fpa */;
6599     info.func               = __cvmx_error_display;
6600     info.user_info          = (long)
6601         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
6602         "    the L2C does not have the FPA owner ship bit set.\n";
6603     fail |= cvmx_error_add(&info);
6604
6605     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6606     info.status_addr        = CVMX_FPA_INT_SUM;
6607     info.status_mask        = 1ull<<10 /* q2_und */;
6608     info.enable_addr        = CVMX_FPA_INT_ENB;
6609     info.enable_mask        = 1ull<<10 /* q2_und */;
6610     info.flags              = 0;
6611     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6612     info.group_index        = 0;
6613     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6614     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6615     info.parent.status_mask = 1ull<<5 /* fpa */;
6616     info.func               = __cvmx_error_display;
6617     info.user_info          = (long)
6618         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
6619         "    negative.\n";
6620     fail |= cvmx_error_add(&info);
6621
6622     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6623     info.status_addr        = CVMX_FPA_INT_SUM;
6624     info.status_mask        = 1ull<<11 /* q2_coff */;
6625     info.enable_addr        = CVMX_FPA_INT_ENB;
6626     info.enable_mask        = 1ull<<11 /* q2_coff */;
6627     info.flags              = 0;
6628     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6629     info.group_index        = 0;
6630     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6631     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6632     info.parent.status_mask = 1ull<<5 /* fpa */;
6633     info.func               = __cvmx_error_display;
6634     info.user_info          = (long)
6635         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
6636         "    the count available is greater than than pointers\n"
6637         "    present in the FPA.\n";
6638     fail |= cvmx_error_add(&info);
6639
6640     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6641     info.status_addr        = CVMX_FPA_INT_SUM;
6642     info.status_mask        = 1ull<<12 /* q2_perr */;
6643     info.enable_addr        = CVMX_FPA_INT_ENB;
6644     info.enable_mask        = 1ull<<12 /* q2_perr */;
6645     info.flags              = 0;
6646     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6647     info.group_index        = 0;
6648     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6649     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6650     info.parent.status_mask = 1ull<<5 /* fpa */;
6651     info.func               = __cvmx_error_display;
6652     info.user_info          = (long)
6653         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
6654         "    the L2C does not have the FPA owner ship bit set.\n";
6655     fail |= cvmx_error_add(&info);
6656
6657     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6658     info.status_addr        = CVMX_FPA_INT_SUM;
6659     info.status_mask        = 1ull<<13 /* q3_und */;
6660     info.enable_addr        = CVMX_FPA_INT_ENB;
6661     info.enable_mask        = 1ull<<13 /* q3_und */;
6662     info.flags              = 0;
6663     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6664     info.group_index        = 0;
6665     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6666     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6667     info.parent.status_mask = 1ull<<5 /* fpa */;
6668     info.func               = __cvmx_error_display;
6669     info.user_info          = (long)
6670         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
6671         "    negative.\n";
6672     fail |= cvmx_error_add(&info);
6673
6674     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6675     info.status_addr        = CVMX_FPA_INT_SUM;
6676     info.status_mask        = 1ull<<14 /* q3_coff */;
6677     info.enable_addr        = CVMX_FPA_INT_ENB;
6678     info.enable_mask        = 1ull<<14 /* q3_coff */;
6679     info.flags              = 0;
6680     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6681     info.group_index        = 0;
6682     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6683     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6684     info.parent.status_mask = 1ull<<5 /* fpa */;
6685     info.func               = __cvmx_error_display;
6686     info.user_info          = (long)
6687         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
6688         "    the count available is greater than than pointers\n"
6689         "    present in the FPA.\n";
6690     fail |= cvmx_error_add(&info);
6691
6692     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6693     info.status_addr        = CVMX_FPA_INT_SUM;
6694     info.status_mask        = 1ull<<15 /* q3_perr */;
6695     info.enable_addr        = CVMX_FPA_INT_ENB;
6696     info.enable_mask        = 1ull<<15 /* q3_perr */;
6697     info.flags              = 0;
6698     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6699     info.group_index        = 0;
6700     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6701     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6702     info.parent.status_mask = 1ull<<5 /* fpa */;
6703     info.func               = __cvmx_error_display;
6704     info.user_info          = (long)
6705         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
6706         "    the L2C does not have the FPA owner ship bit set.\n";
6707     fail |= cvmx_error_add(&info);
6708
6709     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6710     info.status_addr        = CVMX_FPA_INT_SUM;
6711     info.status_mask        = 1ull<<16 /* q4_und */;
6712     info.enable_addr        = CVMX_FPA_INT_ENB;
6713     info.enable_mask        = 1ull<<16 /* q4_und */;
6714     info.flags              = 0;
6715     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6716     info.group_index        = 0;
6717     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6718     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6719     info.parent.status_mask = 1ull<<5 /* fpa */;
6720     info.func               = __cvmx_error_display;
6721     info.user_info          = (long)
6722         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
6723         "    negative.\n";
6724     fail |= cvmx_error_add(&info);
6725
6726     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6727     info.status_addr        = CVMX_FPA_INT_SUM;
6728     info.status_mask        = 1ull<<17 /* q4_coff */;
6729     info.enable_addr        = CVMX_FPA_INT_ENB;
6730     info.enable_mask        = 1ull<<17 /* q4_coff */;
6731     info.flags              = 0;
6732     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6733     info.group_index        = 0;
6734     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6735     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6736     info.parent.status_mask = 1ull<<5 /* fpa */;
6737     info.func               = __cvmx_error_display;
6738     info.user_info          = (long)
6739         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
6740         "    the count available is greater than than pointers\n"
6741         "    present in the FPA.\n";
6742     fail |= cvmx_error_add(&info);
6743
6744     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6745     info.status_addr        = CVMX_FPA_INT_SUM;
6746     info.status_mask        = 1ull<<18 /* q4_perr */;
6747     info.enable_addr        = CVMX_FPA_INT_ENB;
6748     info.enable_mask        = 1ull<<18 /* q4_perr */;
6749     info.flags              = 0;
6750     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6751     info.group_index        = 0;
6752     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6753     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6754     info.parent.status_mask = 1ull<<5 /* fpa */;
6755     info.func               = __cvmx_error_display;
6756     info.user_info          = (long)
6757         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
6758         "    the L2C does not have the FPA owner ship bit set.\n";
6759     fail |= cvmx_error_add(&info);
6760
6761     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6762     info.status_addr        = CVMX_FPA_INT_SUM;
6763     info.status_mask        = 1ull<<19 /* q5_und */;
6764     info.enable_addr        = CVMX_FPA_INT_ENB;
6765     info.enable_mask        = 1ull<<19 /* q5_und */;
6766     info.flags              = 0;
6767     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6768     info.group_index        = 0;
6769     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6770     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6771     info.parent.status_mask = 1ull<<5 /* fpa */;
6772     info.func               = __cvmx_error_display;
6773     info.user_info          = (long)
6774         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
6775         "    negative.\n";
6776     fail |= cvmx_error_add(&info);
6777
6778     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6779     info.status_addr        = CVMX_FPA_INT_SUM;
6780     info.status_mask        = 1ull<<20 /* q5_coff */;
6781     info.enable_addr        = CVMX_FPA_INT_ENB;
6782     info.enable_mask        = 1ull<<20 /* q5_coff */;
6783     info.flags              = 0;
6784     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6785     info.group_index        = 0;
6786     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6787     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6788     info.parent.status_mask = 1ull<<5 /* fpa */;
6789     info.func               = __cvmx_error_display;
6790     info.user_info          = (long)
6791         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
6792         "    the count available is greater than than pointers\n"
6793         "    present in the FPA.\n";
6794     fail |= cvmx_error_add(&info);
6795
6796     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6797     info.status_addr        = CVMX_FPA_INT_SUM;
6798     info.status_mask        = 1ull<<21 /* q5_perr */;
6799     info.enable_addr        = CVMX_FPA_INT_ENB;
6800     info.enable_mask        = 1ull<<21 /* q5_perr */;
6801     info.flags              = 0;
6802     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6803     info.group_index        = 0;
6804     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6805     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6806     info.parent.status_mask = 1ull<<5 /* fpa */;
6807     info.func               = __cvmx_error_display;
6808     info.user_info          = (long)
6809         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
6810         "    the L2C does not have the FPA owner ship bit set.\n";
6811     fail |= cvmx_error_add(&info);
6812
6813     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6814     info.status_addr        = CVMX_FPA_INT_SUM;
6815     info.status_mask        = 1ull<<22 /* q6_und */;
6816     info.enable_addr        = CVMX_FPA_INT_ENB;
6817     info.enable_mask        = 1ull<<22 /* q6_und */;
6818     info.flags              = 0;
6819     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6820     info.group_index        = 0;
6821     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6822     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6823     info.parent.status_mask = 1ull<<5 /* fpa */;
6824     info.func               = __cvmx_error_display;
6825     info.user_info          = (long)
6826         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
6827         "    negative.\n";
6828     fail |= cvmx_error_add(&info);
6829
6830     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6831     info.status_addr        = CVMX_FPA_INT_SUM;
6832     info.status_mask        = 1ull<<23 /* q6_coff */;
6833     info.enable_addr        = CVMX_FPA_INT_ENB;
6834     info.enable_mask        = 1ull<<23 /* q6_coff */;
6835     info.flags              = 0;
6836     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6837     info.group_index        = 0;
6838     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6839     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6840     info.parent.status_mask = 1ull<<5 /* fpa */;
6841     info.func               = __cvmx_error_display;
6842     info.user_info          = (long)
6843         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
6844         "    the count available is greater than than pointers\n"
6845         "    present in the FPA.\n";
6846     fail |= cvmx_error_add(&info);
6847
6848     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6849     info.status_addr        = CVMX_FPA_INT_SUM;
6850     info.status_mask        = 1ull<<24 /* q6_perr */;
6851     info.enable_addr        = CVMX_FPA_INT_ENB;
6852     info.enable_mask        = 1ull<<24 /* q6_perr */;
6853     info.flags              = 0;
6854     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6855     info.group_index        = 0;
6856     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6857     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6858     info.parent.status_mask = 1ull<<5 /* fpa */;
6859     info.func               = __cvmx_error_display;
6860     info.user_info          = (long)
6861         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
6862         "    the L2C does not have the FPA owner ship bit set.\n";
6863     fail |= cvmx_error_add(&info);
6864
6865     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6866     info.status_addr        = CVMX_FPA_INT_SUM;
6867     info.status_mask        = 1ull<<25 /* q7_und */;
6868     info.enable_addr        = CVMX_FPA_INT_ENB;
6869     info.enable_mask        = 1ull<<25 /* q7_und */;
6870     info.flags              = 0;
6871     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6872     info.group_index        = 0;
6873     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6874     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6875     info.parent.status_mask = 1ull<<5 /* fpa */;
6876     info.func               = __cvmx_error_display;
6877     info.user_info          = (long)
6878         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
6879         "    negative.\n";
6880     fail |= cvmx_error_add(&info);
6881
6882     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6883     info.status_addr        = CVMX_FPA_INT_SUM;
6884     info.status_mask        = 1ull<<26 /* q7_coff */;
6885     info.enable_addr        = CVMX_FPA_INT_ENB;
6886     info.enable_mask        = 1ull<<26 /* q7_coff */;
6887     info.flags              = 0;
6888     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6889     info.group_index        = 0;
6890     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6891     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6892     info.parent.status_mask = 1ull<<5 /* fpa */;
6893     info.func               = __cvmx_error_display;
6894     info.user_info          = (long)
6895         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
6896         "    the count available is greater than than pointers\n"
6897         "    present in the FPA.\n";
6898     fail |= cvmx_error_add(&info);
6899
6900     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6901     info.status_addr        = CVMX_FPA_INT_SUM;
6902     info.status_mask        = 1ull<<27 /* q7_perr */;
6903     info.enable_addr        = CVMX_FPA_INT_ENB;
6904     info.enable_mask        = 1ull<<27 /* q7_perr */;
6905     info.flags              = 0;
6906     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6907     info.group_index        = 0;
6908     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6909     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6910     info.parent.status_mask = 1ull<<5 /* fpa */;
6911     info.func               = __cvmx_error_display;
6912     info.user_info          = (long)
6913         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
6914         "    the L2C does not have the FPA owner ship bit set.\n";
6915     fail |= cvmx_error_add(&info);
6916
6917     /* CVMX_LMCX_MEM_CFG0(0) */
6918     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6919     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
6920     info.status_mask        = 0xfull<<21 /* sec_err */;
6921     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
6922     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
6923     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
6924     info.group              = CVMX_ERROR_GROUP_LMC;
6925     info.group_index        = 0;
6926     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6927     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6928     info.parent.status_mask = 1ull<<17 /* lmc0 */;
6929     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
6930     info.user_info          = (long)
6931         "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
6932         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
6933         "    [0] corresponds to DQ[63:0]_c0_p0\n"
6934         "    [1] corresponds to DQ[63:0]_c0_p1\n"
6935         "    [2] corresponds to DQ[63:0]_c1_p0\n"
6936         "    [3] corresponds to DQ[63:0]_c1_p1\n"
6937         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
6938         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
6939         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
6940         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
6941         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
6942         "      where _cC_pP denotes cycle C and phase P\n"
6943         "    Write of 1 will clear the corresponding error bit\n";
6944     fail |= cvmx_error_add(&info);
6945
6946     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6947     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
6948     info.status_mask        = 0xfull<<25 /* ded_err */;
6949     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
6950     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
6951     info.flags              = 0;
6952     info.group              = CVMX_ERROR_GROUP_LMC;
6953     info.group_index        = 0;
6954     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6955     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6956     info.parent.status_mask = 1ull<<17 /* lmc0 */;
6957     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
6958     info.user_info          = (long)
6959         "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
6960         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
6961         "    [0] corresponds to DQ[63:0]_c0_p0\n"
6962         "    [1] corresponds to DQ[63:0]_c0_p1\n"
6963         "    [2] corresponds to DQ[63:0]_c1_p0\n"
6964         "    [3] corresponds to DQ[63:0]_c1_p1\n"
6965         "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
6966         "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
6967         "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
6968         "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
6969         "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
6970         "      where _cC_pP denotes cycle C and phase P\n"
6971         "    Write of 1 will clear the corresponding error bit\n";
6972     fail |= cvmx_error_add(&info);
6973
6974     /* CVMX_IOB_INT_SUM */
6975     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6976     info.status_addr        = CVMX_IOB_INT_SUM;
6977     info.status_mask        = 1ull<<0 /* np_sop */;
6978     info.enable_addr        = CVMX_IOB_INT_ENB;
6979     info.enable_mask        = 1ull<<0 /* np_sop */;
6980     info.flags              = 0;
6981     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6982     info.group_index        = 0;
6983     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6984     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6985     info.parent.status_mask = 1ull<<30 /* iob */;
6986     info.func               = __cvmx_error_display;
6987     info.user_info          = (long)
6988         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
6989         "    port for a non-passthrough packet.\n"
6990         "    The first detected error associated with bits [5:0]\n"
6991         "    of this register will only be set here. A new bit\n"
6992         "    can be set when the previous reported bit is cleared.\n";
6993     fail |= cvmx_error_add(&info);
6994
6995     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6996     info.status_addr        = CVMX_IOB_INT_SUM;
6997     info.status_mask        = 1ull<<1 /* np_eop */;
6998     info.enable_addr        = CVMX_IOB_INT_ENB;
6999     info.enable_mask        = 1ull<<1 /* np_eop */;
7000     info.flags              = 0;
7001     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7002     info.group_index        = 0;
7003     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7004     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7005     info.parent.status_mask = 1ull<<30 /* iob */;
7006     info.func               = __cvmx_error_display;
7007     info.user_info          = (long)
7008         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
7009         "    port for a non-passthrough packet.\n"
7010         "    The first detected error associated with bits [5:0]\n"
7011         "    of this register will only be set here. A new bit\n"
7012         "    can be set when the previous reported bit is cleared.\n";
7013     fail |= cvmx_error_add(&info);
7014
7015     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7016     info.status_addr        = CVMX_IOB_INT_SUM;
7017     info.status_mask        = 1ull<<2 /* p_sop */;
7018     info.enable_addr        = CVMX_IOB_INT_ENB;
7019     info.enable_mask        = 1ull<<2 /* p_sop */;
7020     info.flags              = 0;
7021     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7022     info.group_index        = 0;
7023     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7024     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7025     info.parent.status_mask = 1ull<<30 /* iob */;
7026     info.func               = __cvmx_error_display;
7027     info.user_info          = (long)
7028         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
7029         "    port for a passthrough packet.\n"
7030         "    The first detected error associated with bits [5:0]\n"
7031         "    of this register will only be set here. A new bit\n"
7032         "    can be set when the previous reported bit is cleared.\n";
7033     fail |= cvmx_error_add(&info);
7034
7035     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7036     info.status_addr        = CVMX_IOB_INT_SUM;
7037     info.status_mask        = 1ull<<3 /* p_eop */;
7038     info.enable_addr        = CVMX_IOB_INT_ENB;
7039     info.enable_mask        = 1ull<<3 /* p_eop */;
7040     info.flags              = 0;
7041     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7042     info.group_index        = 0;
7043     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7044     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7045     info.parent.status_mask = 1ull<<30 /* iob */;
7046     info.func               = __cvmx_error_display;
7047     info.user_info          = (long)
7048         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
7049         "    port for a passthrough packet.\n"
7050         "    The first detected error associated with bits [5:0]\n"
7051         "    of this register will only be set here. A new bit\n"
7052         "    can be set when the previous reported bit is cleared.\n";
7053     fail |= cvmx_error_add(&info);
7054
7055     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7056     info.status_addr        = CVMX_IOB_INT_SUM;
7057     info.status_mask        = 1ull<<4 /* np_dat */;
7058     info.enable_addr        = CVMX_IOB_INT_ENB;
7059     info.enable_mask        = 1ull<<4 /* np_dat */;
7060     info.flags              = 0;
7061     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7062     info.group_index        = 0;
7063     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7064     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7065     info.parent.status_mask = 1ull<<30 /* iob */;
7066     info.func               = __cvmx_error_display;
7067     info.user_info          = (long)
7068         "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
7069         "    port for a non-passthrough packet.\n"
7070         "    The first detected error associated with bits [5:0]\n"
7071         "    of this register will only be set here. A new bit\n"
7072         "    can be set when the previous reported bit is cleared.\n";
7073     fail |= cvmx_error_add(&info);
7074
7075     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7076     info.status_addr        = CVMX_IOB_INT_SUM;
7077     info.status_mask        = 1ull<<5 /* p_dat */;
7078     info.enable_addr        = CVMX_IOB_INT_ENB;
7079     info.enable_mask        = 1ull<<5 /* p_dat */;
7080     info.flags              = 0;
7081     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7082     info.group_index        = 0;
7083     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7084     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7085     info.parent.status_mask = 1ull<<30 /* iob */;
7086     info.func               = __cvmx_error_display;
7087     info.user_info          = (long)
7088         "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
7089         "    port for a passthrough packet.\n"
7090         "    The first detected error associated with bits [5:0]\n"
7091         "    of this register will only be set here. A new bit\n"
7092         "    can be set when the previous reported bit is cleared.\n";
7093     fail |= cvmx_error_add(&info);
7094
7095     /* CVMX_ZIP_ERROR */
7096     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7097     info.status_addr        = CVMX_ZIP_ERROR;
7098     info.status_mask        = 1ull<<0 /* doorbell */;
7099     info.enable_addr        = CVMX_ZIP_INT_MASK;
7100     info.enable_mask        = 1ull<<0 /* doorbell */;
7101     info.flags              = 0;
7102     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7103     info.group_index        = 0;
7104     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7105     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7106     info.parent.status_mask = 1ull<<7 /* zip */;
7107     info.func               = __cvmx_error_display;
7108     info.user_info          = (long)
7109         "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
7110     fail |= cvmx_error_add(&info);
7111
7112     /* CVMX_USBNX_INT_SUM(0) */
7113     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7114     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7115     info.status_mask        = 1ull<<0 /* pr_po_e */;
7116     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7117     info.enable_mask        = 1ull<<0 /* pr_po_e */;
7118     info.flags              = 0;
7119     info.group              = CVMX_ERROR_GROUP_USB;
7120     info.group_index        = 0;
7121     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7122     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7123     info.parent.status_mask = 1ull<<13 /* usb */;
7124     info.func               = __cvmx_error_display;
7125     info.user_info          = (long)
7126         "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
7127     fail |= cvmx_error_add(&info);
7128
7129     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7130     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7131     info.status_mask        = 1ull<<1 /* pr_pu_f */;
7132     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7133     info.enable_mask        = 1ull<<1 /* pr_pu_f */;
7134     info.flags              = 0;
7135     info.group              = CVMX_ERROR_GROUP_USB;
7136     info.group_index        = 0;
7137     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7138     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7139     info.parent.status_mask = 1ull<<13 /* usb */;
7140     info.func               = __cvmx_error_display;
7141     info.user_info          = (long)
7142         "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
7143     fail |= cvmx_error_add(&info);
7144
7145     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7146     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7147     info.status_mask        = 1ull<<2 /* nr_po_e */;
7148     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7149     info.enable_mask        = 1ull<<2 /* nr_po_e */;
7150     info.flags              = 0;
7151     info.group              = CVMX_ERROR_GROUP_USB;
7152     info.group_index        = 0;
7153     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7154     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7155     info.parent.status_mask = 1ull<<13 /* usb */;
7156     info.func               = __cvmx_error_display;
7157     info.user_info          = (long)
7158         "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
7159     fail |= cvmx_error_add(&info);
7160
7161     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7162     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7163     info.status_mask        = 1ull<<3 /* nr_pu_f */;
7164     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7165     info.enable_mask        = 1ull<<3 /* nr_pu_f */;
7166     info.flags              = 0;
7167     info.group              = CVMX_ERROR_GROUP_USB;
7168     info.group_index        = 0;
7169     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7170     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7171     info.parent.status_mask = 1ull<<13 /* usb */;
7172     info.func               = __cvmx_error_display;
7173     info.user_info          = (long)
7174         "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
7175     fail |= cvmx_error_add(&info);
7176
7177     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7178     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7179     info.status_mask        = 1ull<<4 /* lr_po_e */;
7180     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7181     info.enable_mask        = 1ull<<4 /* lr_po_e */;
7182     info.flags              = 0;
7183     info.group              = CVMX_ERROR_GROUP_USB;
7184     info.group_index        = 0;
7185     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7186     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7187     info.parent.status_mask = 1ull<<13 /* usb */;
7188     info.func               = __cvmx_error_display;
7189     info.user_info          = (long)
7190         "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
7191     fail |= cvmx_error_add(&info);
7192
7193     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7194     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7195     info.status_mask        = 1ull<<5 /* lr_pu_f */;
7196     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7197     info.enable_mask        = 1ull<<5 /* lr_pu_f */;
7198     info.flags              = 0;
7199     info.group              = CVMX_ERROR_GROUP_USB;
7200     info.group_index        = 0;
7201     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7202     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7203     info.parent.status_mask = 1ull<<13 /* usb */;
7204     info.func               = __cvmx_error_display;
7205     info.user_info          = (long)
7206         "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
7207     fail |= cvmx_error_add(&info);
7208
7209     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7210     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7211     info.status_mask        = 1ull<<6 /* pt_po_e */;
7212     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7213     info.enable_mask        = 1ull<<6 /* pt_po_e */;
7214     info.flags              = 0;
7215     info.group              = CVMX_ERROR_GROUP_USB;
7216     info.group_index        = 0;
7217     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7218     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7219     info.parent.status_mask = 1ull<<13 /* usb */;
7220     info.func               = __cvmx_error_display;
7221     info.user_info          = (long)
7222         "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
7223     fail |= cvmx_error_add(&info);
7224
7225     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7226     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7227     info.status_mask        = 1ull<<7 /* pt_pu_f */;
7228     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7229     info.enable_mask        = 1ull<<7 /* pt_pu_f */;
7230     info.flags              = 0;
7231     info.group              = CVMX_ERROR_GROUP_USB;
7232     info.group_index        = 0;
7233     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7234     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7235     info.parent.status_mask = 1ull<<13 /* usb */;
7236     info.func               = __cvmx_error_display;
7237     info.user_info          = (long)
7238         "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
7239     fail |= cvmx_error_add(&info);
7240
7241     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7242     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7243     info.status_mask        = 1ull<<8 /* nt_po_e */;
7244     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7245     info.enable_mask        = 1ull<<8 /* nt_po_e */;
7246     info.flags              = 0;
7247     info.group              = CVMX_ERROR_GROUP_USB;
7248     info.group_index        = 0;
7249     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7250     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7251     info.parent.status_mask = 1ull<<13 /* usb */;
7252     info.func               = __cvmx_error_display;
7253     info.user_info          = (long)
7254         "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
7255     fail |= cvmx_error_add(&info);
7256
7257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7258     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7259     info.status_mask        = 1ull<<9 /* nt_pu_f */;
7260     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7261     info.enable_mask        = 1ull<<9 /* nt_pu_f */;
7262     info.flags              = 0;
7263     info.group              = CVMX_ERROR_GROUP_USB;
7264     info.group_index        = 0;
7265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7266     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7267     info.parent.status_mask = 1ull<<13 /* usb */;
7268     info.func               = __cvmx_error_display;
7269     info.user_info          = (long)
7270         "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
7271     fail |= cvmx_error_add(&info);
7272
7273     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7274     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7275     info.status_mask        = 1ull<<10 /* lt_po_e */;
7276     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7277     info.enable_mask        = 1ull<<10 /* lt_po_e */;
7278     info.flags              = 0;
7279     info.group              = CVMX_ERROR_GROUP_USB;
7280     info.group_index        = 0;
7281     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7282     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7283     info.parent.status_mask = 1ull<<13 /* usb */;
7284     info.func               = __cvmx_error_display;
7285     info.user_info          = (long)
7286         "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
7287     fail |= cvmx_error_add(&info);
7288
7289     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7290     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7291     info.status_mask        = 1ull<<11 /* lt_pu_f */;
7292     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7293     info.enable_mask        = 1ull<<11 /* lt_pu_f */;
7294     info.flags              = 0;
7295     info.group              = CVMX_ERROR_GROUP_USB;
7296     info.group_index        = 0;
7297     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7298     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7299     info.parent.status_mask = 1ull<<13 /* usb */;
7300     info.func               = __cvmx_error_display;
7301     info.user_info          = (long)
7302         "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
7303     fail |= cvmx_error_add(&info);
7304
7305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7306     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7307     info.status_mask        = 1ull<<12 /* dcred_e */;
7308     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7309     info.enable_mask        = 1ull<<12 /* dcred_e */;
7310     info.flags              = 0;
7311     info.group              = CVMX_ERROR_GROUP_USB;
7312     info.group_index        = 0;
7313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7314     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7315     info.parent.status_mask = 1ull<<13 /* usb */;
7316     info.func               = __cvmx_error_display;
7317     info.user_info          = (long)
7318         "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
7319     fail |= cvmx_error_add(&info);
7320
7321     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7322     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7323     info.status_mask        = 1ull<<13 /* dcred_f */;
7324     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7325     info.enable_mask        = 1ull<<13 /* dcred_f */;
7326     info.flags              = 0;
7327     info.group              = CVMX_ERROR_GROUP_USB;
7328     info.group_index        = 0;
7329     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7330     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7331     info.parent.status_mask = 1ull<<13 /* usb */;
7332     info.func               = __cvmx_error_display;
7333     info.user_info          = (long)
7334         "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
7335     fail |= cvmx_error_add(&info);
7336
7337     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7338     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7339     info.status_mask        = 1ull<<14 /* l2c_s_e */;
7340     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7341     info.enable_mask        = 1ull<<14 /* l2c_s_e */;
7342     info.flags              = 0;
7343     info.group              = CVMX_ERROR_GROUP_USB;
7344     info.group_index        = 0;
7345     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7346     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7347     info.parent.status_mask = 1ull<<13 /* usb */;
7348     info.func               = __cvmx_error_display;
7349     info.user_info          = (long)
7350         "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
7351     fail |= cvmx_error_add(&info);
7352
7353     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7354     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7355     info.status_mask        = 1ull<<15 /* l2c_a_f */;
7356     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7357     info.enable_mask        = 1ull<<15 /* l2c_a_f */;
7358     info.flags              = 0;
7359     info.group              = CVMX_ERROR_GROUP_USB;
7360     info.group_index        = 0;
7361     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7362     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7363     info.parent.status_mask = 1ull<<13 /* usb */;
7364     info.func               = __cvmx_error_display;
7365     info.user_info          = (long)
7366         "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
7367     fail |= cvmx_error_add(&info);
7368
7369     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7370     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7371     info.status_mask        = 1ull<<16 /* lt_fi_e */;
7372     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7373     info.enable_mask        = 1ull<<16 /* l2_fi_e */;
7374     info.flags              = 0;
7375     info.group              = CVMX_ERROR_GROUP_USB;
7376     info.group_index        = 0;
7377     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7378     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7379     info.parent.status_mask = 1ull<<13 /* usb */;
7380     info.func               = __cvmx_error_display;
7381     info.user_info          = (long)
7382         "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
7383     fail |= cvmx_error_add(&info);
7384
7385     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7386     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7387     info.status_mask        = 1ull<<17 /* lt_fi_f */;
7388     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7389     info.enable_mask        = 1ull<<17 /* l2_fi_f */;
7390     info.flags              = 0;
7391     info.group              = CVMX_ERROR_GROUP_USB;
7392     info.group_index        = 0;
7393     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7394     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7395     info.parent.status_mask = 1ull<<13 /* usb */;
7396     info.func               = __cvmx_error_display;
7397     info.user_info          = (long)
7398         "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
7399     fail |= cvmx_error_add(&info);
7400
7401     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7402     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7403     info.status_mask        = 1ull<<18 /* rg_fi_e */;
7404     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7405     info.enable_mask        = 1ull<<18 /* rg_fi_e */;
7406     info.flags              = 0;
7407     info.group              = CVMX_ERROR_GROUP_USB;
7408     info.group_index        = 0;
7409     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7410     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7411     info.parent.status_mask = 1ull<<13 /* usb */;
7412     info.func               = __cvmx_error_display;
7413     info.user_info          = (long)
7414         "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
7415     fail |= cvmx_error_add(&info);
7416
7417     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7418     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7419     info.status_mask        = 1ull<<19 /* rg_fi_f */;
7420     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7421     info.enable_mask        = 1ull<<19 /* rg_fi_f */;
7422     info.flags              = 0;
7423     info.group              = CVMX_ERROR_GROUP_USB;
7424     info.group_index        = 0;
7425     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7426     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7427     info.parent.status_mask = 1ull<<13 /* usb */;
7428     info.func               = __cvmx_error_display;
7429     info.user_info          = (long)
7430         "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
7431     fail |= cvmx_error_add(&info);
7432
7433     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7434     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7435     info.status_mask        = 1ull<<20 /* rq_q2_f */;
7436     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7437     info.enable_mask        = 1ull<<20 /* rq_q2_f */;
7438     info.flags              = 0;
7439     info.group              = CVMX_ERROR_GROUP_USB;
7440     info.group_index        = 0;
7441     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7442     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7443     info.parent.status_mask = 1ull<<13 /* usb */;
7444     info.func               = __cvmx_error_display;
7445     info.user_info          = (long)
7446         "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
7447     fail |= cvmx_error_add(&info);
7448
7449     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7450     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7451     info.status_mask        = 1ull<<21 /* rq_q2_e */;
7452     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7453     info.enable_mask        = 1ull<<21 /* rq_q2_e */;
7454     info.flags              = 0;
7455     info.group              = CVMX_ERROR_GROUP_USB;
7456     info.group_index        = 0;
7457     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7458     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7459     info.parent.status_mask = 1ull<<13 /* usb */;
7460     info.func               = __cvmx_error_display;
7461     info.user_info          = (long)
7462         "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
7463     fail |= cvmx_error_add(&info);
7464
7465     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7466     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7467     info.status_mask        = 1ull<<22 /* rq_q3_f */;
7468     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7469     info.enable_mask        = 1ull<<22 /* rq_q3_f */;
7470     info.flags              = 0;
7471     info.group              = CVMX_ERROR_GROUP_USB;
7472     info.group_index        = 0;
7473     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7474     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7475     info.parent.status_mask = 1ull<<13 /* usb */;
7476     info.func               = __cvmx_error_display;
7477     info.user_info          = (long)
7478         "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
7479     fail |= cvmx_error_add(&info);
7480
7481     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7482     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7483     info.status_mask        = 1ull<<23 /* rq_q3_e */;
7484     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7485     info.enable_mask        = 1ull<<23 /* rq_q3_e */;
7486     info.flags              = 0;
7487     info.group              = CVMX_ERROR_GROUP_USB;
7488     info.group_index        = 0;
7489     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7490     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7491     info.parent.status_mask = 1ull<<13 /* usb */;
7492     info.func               = __cvmx_error_display;
7493     info.user_info          = (long)
7494         "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
7495     fail |= cvmx_error_add(&info);
7496
7497     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7498     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7499     info.status_mask        = 1ull<<24 /* uod_pe */;
7500     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7501     info.enable_mask        = 1ull<<24 /* uod_pe */;
7502     info.flags              = 0;
7503     info.group              = CVMX_ERROR_GROUP_USB;
7504     info.group_index        = 0;
7505     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7506     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7507     info.parent.status_mask = 1ull<<13 /* usb */;
7508     info.func               = __cvmx_error_display;
7509     info.user_info          = (long)
7510         "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
7511     fail |= cvmx_error_add(&info);
7512
7513     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7514     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7515     info.status_mask        = 1ull<<25 /* uod_pf */;
7516     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7517     info.enable_mask        = 1ull<<25 /* uod_pf */;
7518     info.flags              = 0;
7519     info.group              = CVMX_ERROR_GROUP_USB;
7520     info.group_index        = 0;
7521     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7522     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7523     info.parent.status_mask = 1ull<<13 /* usb */;
7524     info.func               = __cvmx_error_display;
7525     info.user_info          = (long)
7526         "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
7527     fail |= cvmx_error_add(&info);
7528
7529     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7530     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7531     info.status_mask        = 1ull<<32 /* ltl_f_pe */;
7532     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7533     info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
7534     info.flags              = 0;
7535     info.group              = CVMX_ERROR_GROUP_USB;
7536     info.group_index        = 0;
7537     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7538     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7539     info.parent.status_mask = 1ull<<13 /* usb */;
7540     info.func               = __cvmx_error_display;
7541     info.user_info          = (long)
7542         "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
7543     fail |= cvmx_error_add(&info);
7544
7545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7546     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7547     info.status_mask        = 1ull<<33 /* ltl_f_pf */;
7548     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7549     info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
7550     info.flags              = 0;
7551     info.group              = CVMX_ERROR_GROUP_USB;
7552     info.group_index        = 0;
7553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7554     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7555     info.parent.status_mask = 1ull<<13 /* usb */;
7556     info.func               = __cvmx_error_display;
7557     info.user_info          = (long)
7558         "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
7559     fail |= cvmx_error_add(&info);
7560
7561     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7562     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7563     info.status_mask        = 1ull<<34 /* nd4o_rpe */;
7564     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7565     info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
7566     info.flags              = 0;
7567     info.group              = CVMX_ERROR_GROUP_USB;
7568     info.group_index        = 0;
7569     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7570     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7571     info.parent.status_mask = 1ull<<13 /* usb */;
7572     info.func               = __cvmx_error_display;
7573     info.user_info          = (long)
7574         "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
7575     fail |= cvmx_error_add(&info);
7576
7577     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7578     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7579     info.status_mask        = 1ull<<35 /* nd4o_rpf */;
7580     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7581     info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
7582     info.flags              = 0;
7583     info.group              = CVMX_ERROR_GROUP_USB;
7584     info.group_index        = 0;
7585     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7586     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7587     info.parent.status_mask = 1ull<<13 /* usb */;
7588     info.func               = __cvmx_error_display;
7589     info.user_info          = (long)
7590         "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
7591     fail |= cvmx_error_add(&info);
7592
7593     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7594     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7595     info.status_mask        = 1ull<<36 /* nd4o_dpe */;
7596     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7597     info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
7598     info.flags              = 0;
7599     info.group              = CVMX_ERROR_GROUP_USB;
7600     info.group_index        = 0;
7601     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7602     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7603     info.parent.status_mask = 1ull<<13 /* usb */;
7604     info.func               = __cvmx_error_display;
7605     info.user_info          = (long)
7606         "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
7607     fail |= cvmx_error_add(&info);
7608
7609     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7610     info.status_addr        = CVMX_USBNX_INT_SUM(0);
7611     info.status_mask        = 1ull<<37 /* nd4o_dpf */;
7612     info.enable_addr        = CVMX_USBNX_INT_ENB(0);
7613     info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
7614     info.flags              = 0;
7615     info.group              = CVMX_ERROR_GROUP_USB;
7616     info.group_index        = 0;
7617     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7618     info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7619     info.parent.status_mask = 1ull<<13 /* usb */;
7620     info.func               = __cvmx_error_display;
7621     info.user_info          = (long)
7622         "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
7623     fail |= cvmx_error_add(&info);
7624
7625     return fail;
7626 }
7627