sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c

   1 /***********************license start***************
   2  * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
   3  * reserved.
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  37  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  38  ***********************license end**************************************/
  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn58xx.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN58XX</h2>
  51  * @dot
  52  * digraph cn58xx
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
  59  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  60  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
  61  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  62  *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
  63  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
  64  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
  65  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
  66  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
  67  *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
  68  *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
  69  *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
  70  *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
  71  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  72  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
  73  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  74  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
  75  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  76  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
  77  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  78  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
  79  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  80  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
  81  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
  82  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
  83  *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
  84  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
  85  *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  86  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
  87  *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  88  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
  89  *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  90  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
  91  *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
  92  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
  93  *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
  94  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
  95  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
  96  *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
  97  *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
  98  *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
  99  *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
 100  *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
 101  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
 102  *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
 103  *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
 104  *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
 105  *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
 106  *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
 107  *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
 108  *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
 109  *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
 110  *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
 111  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
 112  *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
 113  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
 114  *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
 115  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
 116  *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
 117  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
 118  *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
 119  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
 120  *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
 121  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
 122  *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
 123  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
 124  *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
 125  *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
 126  *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
 127  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
 128  *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
 129  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
 130  *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
 131  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 132  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 133  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 134  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
 135  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 136  *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
 137  *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
 138  *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
 139  *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
 140  *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
 141  *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
 142  *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
 143  *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
 144  * }
 145  * @enddot
 146  */
 147 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 148 #include <asm/octeon/cvmx.h>
 149 #include <asm/octeon/cvmx-error.h>
 150 #include <asm/octeon/cvmx-error-custom.h>
 151 #include <asm/octeon/cvmx-csr-typedefs.h>
 152 #else
 153 #include "cvmx.h"
 154 #include "cvmx-error.h"
 155 #include "cvmx-error-custom.h"
 156 #endif
 157
 158 int cvmx_error_initialize_cn58xx(void);
 159
 160 int cvmx_error_initialize_cn58xx(void)
 161 {
 162     cvmx_error_info_t info;
 163     int fail = 0;
 164
 165     /* CVMX_CIU_INTX_SUM0(0) */
 166     /* CVMX_CIU_INT_SUM1 */
 167     /* CVMX_NPI_RSL_INT_BLOCKS */
 168     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 169     info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
 170     info.status_mask        = 0;
 171     info.enable_addr        = 0;
 172     info.enable_mask        = 0;
 173     info.flags              = 0;
 174     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 175     info.group_index        = 0;
 176     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 177     info.parent.status_addr = 0;
 178     info.parent.status_mask = 0;
 179     info.func               = __cvmx_error_decode;
 180     info.user_info          = 0;
 181     fail |= cvmx_error_add(&info);
 182
 183     /* CVMX_L2D_ERR */
 184     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 185     info.status_addr        = CVMX_L2D_ERR;
 186     info.status_mask        = 1ull<<3 /* sec_err */;
 187     info.enable_addr        = CVMX_L2D_ERR;
 188     info.enable_mask        = 1ull<<1 /* sec_intena */;
 189     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 190     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 191     info.group_index        = 0;
 192     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 193     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 194     info.parent.status_mask = 1ull<<16 /* l2c */;
 195     info.func               = __cvmx_error_handle_l2d_err_sec_err;
 196     info.user_info          = (long)
 197         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
 198     fail |= cvmx_error_add(&info);
 199
 200     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 201     info.status_addr        = CVMX_L2D_ERR;
 202     info.status_mask        = 1ull<<4 /* ded_err */;
 203     info.enable_addr        = CVMX_L2D_ERR;
 204     info.enable_mask        = 1ull<<2 /* ded_intena */;
 205     info.flags              = 0;
 206     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 207     info.group_index        = 0;
 208     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 209     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 210     info.parent.status_mask = 1ull<<16 /* l2c */;
 211     info.func               = __cvmx_error_handle_l2d_err_ded_err;
 212     info.user_info          = (long)
 213         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
 214     fail |= cvmx_error_add(&info);
 215
 216     /* CVMX_L2T_ERR */
 217     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 218     info.status_addr        = CVMX_L2T_ERR;
 219     info.status_mask        = 1ull<<3 /* sec_err */;
 220     info.enable_addr        = CVMX_L2T_ERR;
 221     info.enable_mask        = 1ull<<1 /* sec_intena */;
 222     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
 223     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 224     info.group_index        = 0;
 225     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 226     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 227     info.parent.status_mask = 1ull<<16 /* l2c */;
 228     info.func               = __cvmx_error_handle_l2t_err_sec_err;
 229     info.user_info          = (long)
 230         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
 231         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 232         "    given index) are checked for single bit errors(SBEs).\n"
 233         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
 234         "    SBEs are auto corrected in HW and generate an\n"
 235         "    interrupt(if enabled).\n";
 236     fail |= cvmx_error_add(&info);
 237
 238     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 239     info.status_addr        = CVMX_L2T_ERR;
 240     info.status_mask        = 1ull<<4 /* ded_err */;
 241     info.enable_addr        = CVMX_L2T_ERR;
 242     info.enable_mask        = 1ull<<2 /* ded_intena */;
 243     info.flags              = 0;
 244     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 245     info.group_index        = 0;
 246     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 247     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 248     info.parent.status_mask = 1ull<<16 /* l2c */;
 249     info.func               = __cvmx_error_handle_l2t_err_ded_err;
 250     info.user_info          = (long)
 251         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
 252         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
 253         "    given index) are checked for double bit errors(DBEs).\n"
 254         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
 255         "    DBEs also generated an interrupt(if enabled).\n";
 256     fail |= cvmx_error_add(&info);
 257
 258     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 259     info.status_addr        = CVMX_L2T_ERR;
 260     info.status_mask        = 1ull<<24 /* lckerr */;
 261     info.enable_addr        = CVMX_L2T_ERR;
 262     info.enable_mask        = 1ull<<25 /* lck_intena */;
 263     info.flags              = 0;
 264     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 265     info.group_index        = 0;
 266     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 267     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 268     info.parent.status_mask = 1ull<<16 /* l2c */;
 269     info.func               = __cvmx_error_handle_l2t_err_lckerr;
 270     info.user_info          = (long)
 271         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
 272         "    the INDEX (which is ignored by HW - but reported to SW).\n"
 273         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
 274         "    successfully, however the address is NOT locked.\n"
 275         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
 276         "    into account. For example, if diagnostic PPx has\n"
 277         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
 278         "    been previously LOCKED, then an attempt to LOCK the\n"
 279         "    last available SET0 would result in a LCKERR. (This\n"
 280         "    is to ensure that at least 1 SET at each INDEX is\n"
 281         "    not LOCKED for general use by other PPs).\n";
 282     fail |= cvmx_error_add(&info);
 283
 284     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 285     info.status_addr        = CVMX_L2T_ERR;
 286     info.status_mask        = 1ull<<26 /* lckerr2 */;
 287     info.enable_addr        = CVMX_L2T_ERR;
 288     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
 289     info.flags              = 0;
 290     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 291     info.group_index        = 0;
 292     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 293     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 294     info.parent.status_mask = 1ull<<16 /* l2c */;
 295     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
 296     info.user_info          = (long)
 297         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
 298         "    could not find an available/unlocked set (for\n"
 299         "    replacement).\n"
 300         "    Most likely, this is a result of SW mixing SET\n"
 301         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
 302         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
 303         "    then a Rd/Wr Miss from PP#n will be unable\n"
 304         "    to determine a 'valid' replacement set (since LOCKED\n"
 305         "    addresses should NEVER be replaced).\n"
 306         "    If such an event occurs, the HW will select the smallest\n"
 307         "    available SET(specified by UMSK'x)' as the replacement\n"
 308         "    set, and the address is unlocked.\n";
 309     fail |= cvmx_error_add(&info);
 310
 311     /* CVMX_NPI_INT_SUM */
 312     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 313     info.status_addr        = CVMX_NPI_INT_SUM;
 314     info.status_mask        = 1ull<<0 /* rml_rto */;
 315     info.enable_addr        = CVMX_NPI_INT_ENB;
 316     info.enable_mask        = 1ull<<0 /* rml_rto */;
 317     info.flags              = 0;
 318     info.group              = CVMX_ERROR_GROUP_PCI;
 319     info.group_index        = 0;
 320     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 321     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 322     info.parent.status_mask = 1ull<<3 /* npi */;
 323     info.func               = __cvmx_error_display;
 324     info.user_info          = (long)
 325         "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
 326         "    back from a RSL after sending a read command to\n"
 327         "    a RSL.\n";
 328     fail |= cvmx_error_add(&info);
 329
 330     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 331     info.status_addr        = CVMX_NPI_INT_SUM;
 332     info.status_mask        = 1ull<<1 /* rml_wto */;
 333     info.enable_addr        = CVMX_NPI_INT_ENB;
 334     info.enable_mask        = 1ull<<1 /* rml_wto */;
 335     info.flags              = 0;
 336     info.group              = CVMX_ERROR_GROUP_PCI;
 337     info.group_index        = 0;
 338     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 339     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 340     info.parent.status_mask = 1ull<<3 /* npi */;
 341     info.func               = __cvmx_error_display;
 342     info.user_info          = (long)
 343         "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
 344         "    back from a RSL after sending a write command to\n"
 345         "    a RSL.\n";
 346     fail |= cvmx_error_add(&info);
 347
 348     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 349     info.status_addr        = CVMX_NPI_INT_SUM;
 350     info.status_mask        = 1ull<<3 /* po0_2sml */;
 351     info.enable_addr        = CVMX_NPI_INT_ENB;
 352     info.enable_mask        = 1ull<<3 /* po0_2sml */;
 353     info.flags              = 0;
 354     info.group              = CVMX_ERROR_GROUP_PCI;
 355     info.group_index        = 0;
 356     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 357     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 358     info.parent.status_mask = 1ull<<3 /* npi */;
 359     info.func               = __cvmx_error_display;
 360     info.user_info          = (long)
 361         "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
 362         "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
 363     fail |= cvmx_error_add(&info);
 364
 365     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 366     info.status_addr        = CVMX_NPI_INT_SUM;
 367     info.status_mask        = 1ull<<4 /* po1_2sml */;
 368     info.enable_addr        = CVMX_NPI_INT_ENB;
 369     info.enable_mask        = 1ull<<4 /* po1_2sml */;
 370     info.flags              = 0;
 371     info.group              = CVMX_ERROR_GROUP_PCI;
 372     info.group_index        = 0;
 373     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 374     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 375     info.parent.status_mask = 1ull<<3 /* npi */;
 376     info.func               = __cvmx_error_display;
 377     info.user_info          = (long)
 378         "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
 379         "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
 380     fail |= cvmx_error_add(&info);
 381
 382     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 383     info.status_addr        = CVMX_NPI_INT_SUM;
 384     info.status_mask        = 1ull<<5 /* po2_2sml */;
 385     info.enable_addr        = CVMX_NPI_INT_ENB;
 386     info.enable_mask        = 1ull<<5 /* po2_2sml */;
 387     info.flags              = 0;
 388     info.group              = CVMX_ERROR_GROUP_PCI;
 389     info.group_index        = 0;
 390     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 391     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 392     info.parent.status_mask = 1ull<<3 /* npi */;
 393     info.func               = __cvmx_error_display;
 394     info.user_info          = (long)
 395         "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
 396         "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
 397     fail |= cvmx_error_add(&info);
 398
 399     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 400     info.status_addr        = CVMX_NPI_INT_SUM;
 401     info.status_mask        = 1ull<<6 /* po3_2sml */;
 402     info.enable_addr        = CVMX_NPI_INT_ENB;
 403     info.enable_mask        = 1ull<<6 /* po3_2sml */;
 404     info.flags              = 0;
 405     info.group              = CVMX_ERROR_GROUP_PCI;
 406     info.group_index        = 0;
 407     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 408     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 409     info.parent.status_mask = 1ull<<3 /* npi */;
 410     info.func               = __cvmx_error_display;
 411     info.user_info          = (long)
 412         "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
 413         "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
 414     fail |= cvmx_error_add(&info);
 415
 416     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 417     info.status_addr        = CVMX_NPI_INT_SUM;
 418     info.status_mask        = 1ull<<7 /* i0_rtout */;
 419     info.enable_addr        = CVMX_NPI_INT_ENB;
 420     info.enable_mask        = 1ull<<7 /* i0_rtout */;
 421     info.flags              = 0;
 422     info.group              = CVMX_ERROR_GROUP_PCI;
 423     info.group_index        = 0;
 424     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 425     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 426     info.parent.status_mask = 1ull<<3 /* npi */;
 427     info.func               = __cvmx_error_display;
 428     info.user_info          = (long)
 429         "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 430         "    read instructions.\n";
 431     fail |= cvmx_error_add(&info);
 432
 433     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 434     info.status_addr        = CVMX_NPI_INT_SUM;
 435     info.status_mask        = 1ull<<8 /* i1_rtout */;
 436     info.enable_addr        = CVMX_NPI_INT_ENB;
 437     info.enable_mask        = 1ull<<8 /* i1_rtout */;
 438     info.flags              = 0;
 439     info.group              = CVMX_ERROR_GROUP_PCI;
 440     info.group_index        = 0;
 441     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 442     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 443     info.parent.status_mask = 1ull<<3 /* npi */;
 444     info.func               = __cvmx_error_display;
 445     info.user_info          = (long)
 446         "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 447         "    read instructions.\n";
 448     fail |= cvmx_error_add(&info);
 449
 450     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 451     info.status_addr        = CVMX_NPI_INT_SUM;
 452     info.status_mask        = 1ull<<9 /* i2_rtout */;
 453     info.enable_addr        = CVMX_NPI_INT_ENB;
 454     info.enable_mask        = 1ull<<9 /* i2_rtout */;
 455     info.flags              = 0;
 456     info.group              = CVMX_ERROR_GROUP_PCI;
 457     info.group_index        = 0;
 458     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 459     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 460     info.parent.status_mask = 1ull<<3 /* npi */;
 461     info.func               = __cvmx_error_display;
 462     info.user_info          = (long)
 463         "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
 464         "    read instructions.\n";
 465     fail |= cvmx_error_add(&info);
 466
 467     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 468     info.status_addr        = CVMX_NPI_INT_SUM;
 469     info.status_mask        = 1ull<<10 /* i3_rtout */;
 470     info.enable_addr        = CVMX_NPI_INT_ENB;
 471     info.enable_mask        = 1ull<<10 /* i3_rtout */;
 472     info.flags              = 0;
 473     info.group              = CVMX_ERROR_GROUP_PCI;
 474     info.group_index        = 0;
 475     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 476     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 477     info.parent.status_mask = 1ull<<3 /* npi */;
 478     info.func               = __cvmx_error_display;
 479     info.user_info          = (long)
 480         "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
 481         "    read instructions.\n";
 482     fail |= cvmx_error_add(&info);
 483
 484     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 485     info.status_addr        = CVMX_NPI_INT_SUM;
 486     info.status_mask        = 1ull<<11 /* i0_overf */;
 487     info.enable_addr        = CVMX_NPI_INT_ENB;
 488     info.enable_mask        = 1ull<<11 /* i0_overf */;
 489     info.flags              = 0;
 490     info.group              = CVMX_ERROR_GROUP_PCI;
 491     info.group_index        = 0;
 492     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 493     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 494     info.parent.status_mask = 1ull<<3 /* npi */;
 495     info.func               = __cvmx_error_display;
 496     info.user_info          = (long)
 497         "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
 498         "    doorbell count was set.\n";
 499     fail |= cvmx_error_add(&info);
 500
 501     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 502     info.status_addr        = CVMX_NPI_INT_SUM;
 503     info.status_mask        = 1ull<<12 /* i1_overf */;
 504     info.enable_addr        = CVMX_NPI_INT_ENB;
 505     info.enable_mask        = 1ull<<12 /* i1_overf */;
 506     info.flags              = 0;
 507     info.group              = CVMX_ERROR_GROUP_PCI;
 508     info.group_index        = 0;
 509     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 510     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 511     info.parent.status_mask = 1ull<<3 /* npi */;
 512     info.func               = __cvmx_error_display;
 513     info.user_info          = (long)
 514         "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
 515         "    doorbell count was set.\n";
 516     fail |= cvmx_error_add(&info);
 517
 518     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 519     info.status_addr        = CVMX_NPI_INT_SUM;
 520     info.status_mask        = 1ull<<13 /* i2_overf */;
 521     info.enable_addr        = CVMX_NPI_INT_ENB;
 522     info.enable_mask        = 1ull<<13 /* i2_overf */;
 523     info.flags              = 0;
 524     info.group              = CVMX_ERROR_GROUP_PCI;
 525     info.group_index        = 0;
 526     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 527     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 528     info.parent.status_mask = 1ull<<3 /* npi */;
 529     info.func               = __cvmx_error_display;
 530     info.user_info          = (long)
 531         "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
 532         "    doorbell count was set.\n";
 533     fail |= cvmx_error_add(&info);
 534
 535     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 536     info.status_addr        = CVMX_NPI_INT_SUM;
 537     info.status_mask        = 1ull<<14 /* i3_overf */;
 538     info.enable_addr        = CVMX_NPI_INT_ENB;
 539     info.enable_mask        = 1ull<<14 /* i3_overf */;
 540     info.flags              = 0;
 541     info.group              = CVMX_ERROR_GROUP_PCI;
 542     info.group_index        = 0;
 543     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 544     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 545     info.parent.status_mask = 1ull<<3 /* npi */;
 546     info.func               = __cvmx_error_display;
 547     info.user_info          = (long)
 548         "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
 549         "    doorbell count was set.\n";
 550     fail |= cvmx_error_add(&info);
 551
 552     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 553     info.status_addr        = CVMX_NPI_INT_SUM;
 554     info.status_mask        = 1ull<<15 /* p0_rtout */;
 555     info.enable_addr        = CVMX_NPI_INT_ENB;
 556     info.enable_mask        = 1ull<<15 /* p0_rtout */;
 557     info.flags              = 0;
 558     info.group              = CVMX_ERROR_GROUP_PCI;
 559     info.group_index        = 0;
 560     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 561     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 562     info.parent.status_mask = 1ull<<3 /* npi */;
 563     info.func               = __cvmx_error_display;
 564     info.user_info          = (long)
 565         "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 566         "    read packet data.\n";
 567     fail |= cvmx_error_add(&info);
 568
 569     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 570     info.status_addr        = CVMX_NPI_INT_SUM;
 571     info.status_mask        = 1ull<<16 /* p1_rtout */;
 572     info.enable_addr        = CVMX_NPI_INT_ENB;
 573     info.enable_mask        = 1ull<<16 /* p1_rtout */;
 574     info.flags              = 0;
 575     info.group              = CVMX_ERROR_GROUP_PCI;
 576     info.group_index        = 0;
 577     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 578     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 579     info.parent.status_mask = 1ull<<3 /* npi */;
 580     info.func               = __cvmx_error_display;
 581     info.user_info          = (long)
 582         "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 583         "    read packet data.\n";
 584     fail |= cvmx_error_add(&info);
 585
 586     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 587     info.status_addr        = CVMX_NPI_INT_SUM;
 588     info.status_mask        = 1ull<<17 /* p2_rtout */;
 589     info.enable_addr        = CVMX_NPI_INT_ENB;
 590     info.enable_mask        = 1ull<<17 /* p2_rtout */;
 591     info.flags              = 0;
 592     info.group              = CVMX_ERROR_GROUP_PCI;
 593     info.group_index        = 0;
 594     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 595     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 596     info.parent.status_mask = 1ull<<3 /* npi */;
 597     info.func               = __cvmx_error_display;
 598     info.user_info          = (long)
 599         "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
 600         "    read packet data.\n";
 601     fail |= cvmx_error_add(&info);
 602
 603     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 604     info.status_addr        = CVMX_NPI_INT_SUM;
 605     info.status_mask        = 1ull<<18 /* p3_rtout */;
 606     info.enable_addr        = CVMX_NPI_INT_ENB;
 607     info.enable_mask        = 1ull<<18 /* p3_rtout */;
 608     info.flags              = 0;
 609     info.group              = CVMX_ERROR_GROUP_PCI;
 610     info.group_index        = 0;
 611     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 612     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 613     info.parent.status_mask = 1ull<<3 /* npi */;
 614     info.func               = __cvmx_error_display;
 615     info.user_info          = (long)
 616         "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
 617         "    read packet data.\n";
 618     fail |= cvmx_error_add(&info);
 619
 620     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 621     info.status_addr        = CVMX_NPI_INT_SUM;
 622     info.status_mask        = 1ull<<19 /* p0_perr */;
 623     info.enable_addr        = CVMX_NPI_INT_ENB;
 624     info.enable_mask        = 1ull<<19 /* p0_perr */;
 625     info.flags              = 0;
 626     info.group              = CVMX_ERROR_GROUP_PCI;
 627     info.group_index        = 0;
 628     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 629     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 630     info.parent.status_mask = 1ull<<3 /* npi */;
 631     info.func               = __cvmx_error_display;
 632     info.user_info          = (long)
 633         "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
 634         "    data this bit may be set.\n";
 635     fail |= cvmx_error_add(&info);
 636
 637     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 638     info.status_addr        = CVMX_NPI_INT_SUM;
 639     info.status_mask        = 1ull<<20 /* p1_perr */;
 640     info.enable_addr        = CVMX_NPI_INT_ENB;
 641     info.enable_mask        = 1ull<<20 /* p1_perr */;
 642     info.flags              = 0;
 643     info.group              = CVMX_ERROR_GROUP_PCI;
 644     info.group_index        = 0;
 645     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 646     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 647     info.parent.status_mask = 1ull<<3 /* npi */;
 648     info.func               = __cvmx_error_display;
 649     info.user_info          = (long)
 650         "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
 651         "    data this bit may be set.\n";
 652     fail |= cvmx_error_add(&info);
 653
 654     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 655     info.status_addr        = CVMX_NPI_INT_SUM;
 656     info.status_mask        = 1ull<<21 /* p2_perr */;
 657     info.enable_addr        = CVMX_NPI_INT_ENB;
 658     info.enable_mask        = 1ull<<21 /* p2_perr */;
 659     info.flags              = 0;
 660     info.group              = CVMX_ERROR_GROUP_PCI;
 661     info.group_index        = 0;
 662     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 663     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 664     info.parent.status_mask = 1ull<<3 /* npi */;
 665     info.func               = __cvmx_error_display;
 666     info.user_info          = (long)
 667         "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
 668         "    data this bit may be set.\n";
 669     fail |= cvmx_error_add(&info);
 670
 671     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 672     info.status_addr        = CVMX_NPI_INT_SUM;
 673     info.status_mask        = 1ull<<22 /* p3_perr */;
 674     info.enable_addr        = CVMX_NPI_INT_ENB;
 675     info.enable_mask        = 1ull<<22 /* p3_perr */;
 676     info.flags              = 0;
 677     info.group              = CVMX_ERROR_GROUP_PCI;
 678     info.group_index        = 0;
 679     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 680     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 681     info.parent.status_mask = 1ull<<3 /* npi */;
 682     info.func               = __cvmx_error_display;
 683     info.user_info          = (long)
 684         "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
 685         "    data this bit may be set.\n";
 686     fail |= cvmx_error_add(&info);
 687
 688     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 689     info.status_addr        = CVMX_NPI_INT_SUM;
 690     info.status_mask        = 1ull<<23 /* g0_rtout */;
 691     info.enable_addr        = CVMX_NPI_INT_ENB;
 692     info.enable_mask        = 1ull<<23 /* g0_rtout */;
 693     info.flags              = 0;
 694     info.group              = CVMX_ERROR_GROUP_PCI;
 695     info.group_index        = 0;
 696     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 697     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 698     info.parent.status_mask = 1ull<<3 /* npi */;
 699     info.func               = __cvmx_error_display;
 700     info.user_info          = (long)
 701         "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
 702         "    read a gather list.\n";
 703     fail |= cvmx_error_add(&info);
 704
 705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 706     info.status_addr        = CVMX_NPI_INT_SUM;
 707     info.status_mask        = 1ull<<24 /* g1_rtout */;
 708     info.enable_addr        = CVMX_NPI_INT_ENB;
 709     info.enable_mask        = 1ull<<24 /* g1_rtout */;
 710     info.flags              = 0;
 711     info.group              = CVMX_ERROR_GROUP_PCI;
 712     info.group_index        = 0;
 713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 715     info.parent.status_mask = 1ull<<3 /* npi */;
 716     info.func               = __cvmx_error_display;
 717     info.user_info          = (long)
 718         "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
 719         "    read a gather list.\n";
 720     fail |= cvmx_error_add(&info);
 721
 722     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 723     info.status_addr        = CVMX_NPI_INT_SUM;
 724     info.status_mask        = 1ull<<25 /* g2_rtout */;
 725     info.enable_addr        = CVMX_NPI_INT_ENB;
 726     info.enable_mask        = 1ull<<25 /* g2_rtout */;
 727     info.flags              = 0;
 728     info.group              = CVMX_ERROR_GROUP_PCI;
 729     info.group_index        = 0;
 730     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 731     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 732     info.parent.status_mask = 1ull<<3 /* npi */;
 733     info.func               = __cvmx_error_display;
 734     info.user_info          = (long)
 735         "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
 736         "    read a gather list.\n";
 737     fail |= cvmx_error_add(&info);
 738
 739     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 740     info.status_addr        = CVMX_NPI_INT_SUM;
 741     info.status_mask        = 1ull<<26 /* g3_rtout */;
 742     info.enable_addr        = CVMX_NPI_INT_ENB;
 743     info.enable_mask        = 1ull<<26 /* g3_rtout */;
 744     info.flags              = 0;
 745     info.group              = CVMX_ERROR_GROUP_PCI;
 746     info.group_index        = 0;
 747     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 748     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 749     info.parent.status_mask = 1ull<<3 /* npi */;
 750     info.func               = __cvmx_error_display;
 751     info.user_info          = (long)
 752         "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
 753         "    read a gather list.\n";
 754     fail |= cvmx_error_add(&info);
 755
 756     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 757     info.status_addr        = CVMX_NPI_INT_SUM;
 758     info.status_mask        = 1ull<<27 /* p0_pperr */;
 759     info.enable_addr        = CVMX_NPI_INT_ENB;
 760     info.enable_mask        = 1ull<<27 /* p0_pperr */;
 761     info.flags              = 0;
 762     info.group              = CVMX_ERROR_GROUP_PCI;
 763     info.group_index        = 0;
 764     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 765     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 766     info.parent.status_mask = 1ull<<3 /* npi */;
 767     info.func               = __cvmx_error_display;
 768     info.user_info          = (long)
 769         "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
 770         "    pointer-pair, this bit may be set.\n";
 771     fail |= cvmx_error_add(&info);
 772
 773     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 774     info.status_addr        = CVMX_NPI_INT_SUM;
 775     info.status_mask        = 1ull<<28 /* p1_pperr */;
 776     info.enable_addr        = CVMX_NPI_INT_ENB;
 777     info.enable_mask        = 1ull<<28 /* p1_pperr */;
 778     info.flags              = 0;
 779     info.group              = CVMX_ERROR_GROUP_PCI;
 780     info.group_index        = 0;
 781     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 782     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 783     info.parent.status_mask = 1ull<<3 /* npi */;
 784     info.func               = __cvmx_error_display;
 785     info.user_info          = (long)
 786         "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
 787         "    pointer-pair, this bit may be set.\n";
 788     fail |= cvmx_error_add(&info);
 789
 790     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 791     info.status_addr        = CVMX_NPI_INT_SUM;
 792     info.status_mask        = 1ull<<29 /* p2_pperr */;
 793     info.enable_addr        = CVMX_NPI_INT_ENB;
 794     info.enable_mask        = 1ull<<29 /* p2_pperr */;
 795     info.flags              = 0;
 796     info.group              = CVMX_ERROR_GROUP_PCI;
 797     info.group_index        = 0;
 798     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 799     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 800     info.parent.status_mask = 1ull<<3 /* npi */;
 801     info.func               = __cvmx_error_display;
 802     info.user_info          = (long)
 803         "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
 804         "    pointer-pair, this bit may be set.\n";
 805     fail |= cvmx_error_add(&info);
 806
 807     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 808     info.status_addr        = CVMX_NPI_INT_SUM;
 809     info.status_mask        = 1ull<<30 /* p3_pperr */;
 810     info.enable_addr        = CVMX_NPI_INT_ENB;
 811     info.enable_mask        = 1ull<<30 /* p3_pperr */;
 812     info.flags              = 0;
 813     info.group              = CVMX_ERROR_GROUP_PCI;
 814     info.group_index        = 0;
 815     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 816     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 817     info.parent.status_mask = 1ull<<3 /* npi */;
 818     info.func               = __cvmx_error_display;
 819     info.user_info          = (long)
 820         "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
 821         "    pointer-pair, this bit may be set.\n";
 822     fail |= cvmx_error_add(&info);
 823
 824     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 825     info.status_addr        = CVMX_NPI_INT_SUM;
 826     info.status_mask        = 1ull<<31 /* p0_ptout */;
 827     info.enable_addr        = CVMX_NPI_INT_ENB;
 828     info.enable_mask        = 1ull<<31 /* p0_ptout */;
 829     info.flags              = 0;
 830     info.group              = CVMX_ERROR_GROUP_PCI;
 831     info.group_index        = 0;
 832     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 833     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 834     info.parent.status_mask = 1ull<<3 /* npi */;
 835     info.func               = __cvmx_error_display;
 836     info.user_info          = (long)
 837         "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
 838         "    pair.\n";
 839     fail |= cvmx_error_add(&info);
 840
 841     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 842     info.status_addr        = CVMX_NPI_INT_SUM;
 843     info.status_mask        = 1ull<<32 /* p1_ptout */;
 844     info.enable_addr        = CVMX_NPI_INT_ENB;
 845     info.enable_mask        = 1ull<<32 /* p1_ptout */;
 846     info.flags              = 0;
 847     info.group              = CVMX_ERROR_GROUP_PCI;
 848     info.group_index        = 0;
 849     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 850     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 851     info.parent.status_mask = 1ull<<3 /* npi */;
 852     info.func               = __cvmx_error_display;
 853     info.user_info          = (long)
 854         "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
 855         "    pair.\n";
 856     fail |= cvmx_error_add(&info);
 857
 858     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 859     info.status_addr        = CVMX_NPI_INT_SUM;
 860     info.status_mask        = 1ull<<33 /* p2_ptout */;
 861     info.enable_addr        = CVMX_NPI_INT_ENB;
 862     info.enable_mask        = 1ull<<33 /* p2_ptout */;
 863     info.flags              = 0;
 864     info.group              = CVMX_ERROR_GROUP_PCI;
 865     info.group_index        = 0;
 866     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 867     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 868     info.parent.status_mask = 1ull<<3 /* npi */;
 869     info.func               = __cvmx_error_display;
 870     info.user_info          = (long)
 871         "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
 872         "    pair.\n";
 873     fail |= cvmx_error_add(&info);
 874
 875     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 876     info.status_addr        = CVMX_NPI_INT_SUM;
 877     info.status_mask        = 1ull<<34 /* p3_ptout */;
 878     info.enable_addr        = CVMX_NPI_INT_ENB;
 879     info.enable_mask        = 1ull<<34 /* p3_ptout */;
 880     info.flags              = 0;
 881     info.group              = CVMX_ERROR_GROUP_PCI;
 882     info.group_index        = 0;
 883     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 884     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 885     info.parent.status_mask = 1ull<<3 /* npi */;
 886     info.func               = __cvmx_error_display;
 887     info.user_info          = (long)
 888         "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
 889         "    pair.\n";
 890     fail |= cvmx_error_add(&info);
 891
 892     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 893     info.status_addr        = CVMX_NPI_INT_SUM;
 894     info.status_mask        = 1ull<<35 /* i0_pperr */;
 895     info.enable_addr        = CVMX_NPI_INT_ENB;
 896     info.enable_mask        = 1ull<<35 /* i0_pperr */;
 897     info.flags              = 0;
 898     info.group              = CVMX_ERROR_GROUP_PCI;
 899     info.group_index        = 0;
 900     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 901     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 902     info.parent.status_mask = 1ull<<3 /* npi */;
 903     info.func               = __cvmx_error_display;
 904     info.user_info          = (long)
 905         "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
 906         "    this bit may be set.\n";
 907     fail |= cvmx_error_add(&info);
 908
 909     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 910     info.status_addr        = CVMX_NPI_INT_SUM;
 911     info.status_mask        = 1ull<<36 /* i1_pperr */;
 912     info.enable_addr        = CVMX_NPI_INT_ENB;
 913     info.enable_mask        = 1ull<<36 /* i1_pperr */;
 914     info.flags              = 0;
 915     info.group              = CVMX_ERROR_GROUP_PCI;
 916     info.group_index        = 0;
 917     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 918     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 919     info.parent.status_mask = 1ull<<3 /* npi */;
 920     info.func               = __cvmx_error_display;
 921     info.user_info          = (long)
 922         "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
 923         "    this bit may be set.\n";
 924     fail |= cvmx_error_add(&info);
 925
 926     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 927     info.status_addr        = CVMX_NPI_INT_SUM;
 928     info.status_mask        = 1ull<<37 /* i2_pperr */;
 929     info.enable_addr        = CVMX_NPI_INT_ENB;
 930     info.enable_mask        = 1ull<<37 /* i2_pperr */;
 931     info.flags              = 0;
 932     info.group              = CVMX_ERROR_GROUP_PCI;
 933     info.group_index        = 0;
 934     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 935     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 936     info.parent.status_mask = 1ull<<3 /* npi */;
 937     info.func               = __cvmx_error_display;
 938     info.user_info          = (long)
 939         "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
 940         "    this bit may be set.\n";
 941     fail |= cvmx_error_add(&info);
 942
 943     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 944     info.status_addr        = CVMX_NPI_INT_SUM;
 945     info.status_mask        = 1ull<<38 /* i3_pperr */;
 946     info.enable_addr        = CVMX_NPI_INT_ENB;
 947     info.enable_mask        = 1ull<<38 /* i3_pperr */;
 948     info.flags              = 0;
 949     info.group              = CVMX_ERROR_GROUP_PCI;
 950     info.group_index        = 0;
 951     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 952     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 953     info.parent.status_mask = 1ull<<3 /* npi */;
 954     info.func               = __cvmx_error_display;
 955     info.user_info          = (long)
 956         "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
 957         "    this bit may be set.\n";
 958     fail |= cvmx_error_add(&info);
 959
 960     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 961     info.status_addr        = CVMX_NPI_INT_SUM;
 962     info.status_mask        = 1ull<<39 /* win_rto */;
 963     info.enable_addr        = CVMX_NPI_INT_ENB;
 964     info.enable_mask        = 1ull<<39 /* win_rto */;
 965     info.flags              = 0;
 966     info.group              = CVMX_ERROR_GROUP_PCI;
 967     info.group_index        = 0;
 968     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 969     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 970     info.parent.status_mask = 1ull<<3 /* npi */;
 971     info.func               = __cvmx_error_display;
 972     info.user_info          = (long)
 973         "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
 974     fail |= cvmx_error_add(&info);
 975
 976     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 977     info.status_addr        = CVMX_NPI_INT_SUM;
 978     info.status_mask        = 1ull<<40 /* p_dperr */;
 979     info.enable_addr        = CVMX_NPI_INT_ENB;
 980     info.enable_mask        = 1ull<<40 /* p_dperr */;
 981     info.flags              = 0;
 982     info.group              = CVMX_ERROR_GROUP_PCI;
 983     info.group_index        = 0;
 984     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 985     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
 986     info.parent.status_mask = 1ull<<3 /* npi */;
 987     info.func               = __cvmx_error_display;
 988     info.user_info          = (long)
 989         "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
 990         "    from the PCI this bit may be set.\n";
 991     fail |= cvmx_error_add(&info);
 992
 993     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 994     info.status_addr        = CVMX_NPI_INT_SUM;
 995     info.status_mask        = 1ull<<41 /* iobdma */;
 996     info.enable_addr        = CVMX_NPI_INT_ENB;
 997     info.enable_mask        = 1ull<<41 /* iobdma */;
 998     info.flags              = 0;
 999     info.group              = CVMX_ERROR_GROUP_PCI;
1000     info.group_index        = 0;
1001     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1002     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1003     info.parent.status_mask = 1ull<<3 /* npi */;
1004     info.func               = __cvmx_error_display;
1005     info.user_info          = (long)
1006         "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
1007     fail |= cvmx_error_add(&info);
1008
1009     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1010     info.status_addr        = CVMX_NPI_INT_SUM;
1011     info.status_mask        = 1ull<<42 /* fcr_s_e */;
1012     info.enable_addr        = CVMX_NPI_INT_ENB;
1013     info.enable_mask        = 1ull<<42 /* fcr_s_e */;
1014     info.flags              = 0;
1015     info.group              = CVMX_ERROR_GROUP_PCI;
1016     info.group_index        = 0;
1017     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1018     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1019     info.parent.status_mask = 1ull<<3 /* npi */;
1020     info.func               = __cvmx_error_display;
1021     info.user_info          = (long)
1022         "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
1023         "    PASS3 Field.\n";
1024     fail |= cvmx_error_add(&info);
1025
1026     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1027     info.status_addr        = CVMX_NPI_INT_SUM;
1028     info.status_mask        = 1ull<<43 /* fcr_a_f */;
1029     info.enable_addr        = CVMX_NPI_INT_ENB;
1030     info.enable_mask        = 1ull<<43 /* fcr_a_f */;
1031     info.flags              = 0;
1032     info.group              = CVMX_ERROR_GROUP_PCI;
1033     info.group_index        = 0;
1034     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1035     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1036     info.parent.status_mask = 1ull<<3 /* npi */;
1037     info.func               = __cvmx_error_display;
1038     info.user_info          = (long)
1039         "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
1040         "    PASS3 Field.\n";
1041     fail |= cvmx_error_add(&info);
1042
1043     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1044     info.status_addr        = CVMX_NPI_INT_SUM;
1045     info.status_mask        = 1ull<<44 /* pcr_s_e */;
1046     info.enable_addr        = CVMX_NPI_INT_ENB;
1047     info.enable_mask        = 1ull<<44 /* pcr_s_e */;
1048     info.flags              = 0;
1049     info.group              = CVMX_ERROR_GROUP_PCI;
1050     info.group_index        = 0;
1051     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1052     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1053     info.parent.status_mask = 1ull<<3 /* npi */;
1054     info.func               = __cvmx_error_display;
1055     info.user_info          = (long)
1056         "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
1057         "    PASS3 Field.\n";
1058     fail |= cvmx_error_add(&info);
1059
1060     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1061     info.status_addr        = CVMX_NPI_INT_SUM;
1062     info.status_mask        = 1ull<<45 /* pcr_a_f */;
1063     info.enable_addr        = CVMX_NPI_INT_ENB;
1064     info.enable_mask        = 1ull<<45 /* pcr_a_f */;
1065     info.flags              = 0;
1066     info.group              = CVMX_ERROR_GROUP_PCI;
1067     info.group_index        = 0;
1068     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1069     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1070     info.parent.status_mask = 1ull<<3 /* npi */;
1071     info.func               = __cvmx_error_display;
1072     info.user_info          = (long)
1073         "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
1074         "    PASS3 Field.\n";
1075     fail |= cvmx_error_add(&info);
1076
1077     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1078     info.status_addr        = CVMX_NPI_INT_SUM;
1079     info.status_mask        = 1ull<<46 /* q2_s_e */;
1080     info.enable_addr        = CVMX_NPI_INT_ENB;
1081     info.enable_mask        = 1ull<<46 /* q2_s_e */;
1082     info.flags              = 0;
1083     info.group              = CVMX_ERROR_GROUP_PCI;
1084     info.group_index        = 0;
1085     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1086     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1087     info.parent.status_mask = 1ull<<3 /* npi */;
1088     info.func               = __cvmx_error_display;
1089     info.user_info          = (long)
1090         "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
1091         "    PASS3 Field.\n";
1092     fail |= cvmx_error_add(&info);
1093
1094     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1095     info.status_addr        = CVMX_NPI_INT_SUM;
1096     info.status_mask        = 1ull<<47 /* q2_a_f */;
1097     info.enable_addr        = CVMX_NPI_INT_ENB;
1098     info.enable_mask        = 1ull<<47 /* q2_a_f */;
1099     info.flags              = 0;
1100     info.group              = CVMX_ERROR_GROUP_PCI;
1101     info.group_index        = 0;
1102     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1103     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1104     info.parent.status_mask = 1ull<<3 /* npi */;
1105     info.func               = __cvmx_error_display;
1106     info.user_info          = (long)
1107         "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
1108         "    PASS3 Field.\n";
1109     fail |= cvmx_error_add(&info);
1110
1111     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1112     info.status_addr        = CVMX_NPI_INT_SUM;
1113     info.status_mask        = 1ull<<48 /* q3_s_e */;
1114     info.enable_addr        = CVMX_NPI_INT_ENB;
1115     info.enable_mask        = 1ull<<48 /* q3_s_e */;
1116     info.flags              = 0;
1117     info.group              = CVMX_ERROR_GROUP_PCI;
1118     info.group_index        = 0;
1119     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1120     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1121     info.parent.status_mask = 1ull<<3 /* npi */;
1122     info.func               = __cvmx_error_display;
1123     info.user_info          = (long)
1124         "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
1125         "    PASS3 Field.\n";
1126     fail |= cvmx_error_add(&info);
1127
1128     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1129     info.status_addr        = CVMX_NPI_INT_SUM;
1130     info.status_mask        = 1ull<<49 /* q3_a_f */;
1131     info.enable_addr        = CVMX_NPI_INT_ENB;
1132     info.enable_mask        = 1ull<<49 /* q3_a_f */;
1133     info.flags              = 0;
1134     info.group              = CVMX_ERROR_GROUP_PCI;
1135     info.group_index        = 0;
1136     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1137     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1138     info.parent.status_mask = 1ull<<3 /* npi */;
1139     info.func               = __cvmx_error_display;
1140     info.user_info          = (long)
1141         "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
1142         "    PASS3 Field.\n";
1143     fail |= cvmx_error_add(&info);
1144
1145     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1146     info.status_addr        = CVMX_NPI_INT_SUM;
1147     info.status_mask        = 1ull<<50 /* com_s_e */;
1148     info.enable_addr        = CVMX_NPI_INT_ENB;
1149     info.enable_mask        = 1ull<<50 /* com_s_e */;
1150     info.flags              = 0;
1151     info.group              = CVMX_ERROR_GROUP_PCI;
1152     info.group_index        = 0;
1153     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1154     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1155     info.parent.status_mask = 1ull<<3 /* npi */;
1156     info.func               = __cvmx_error_display;
1157     info.user_info          = (long)
1158         "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
1159         "    PASS3 Field.\n";
1160     fail |= cvmx_error_add(&info);
1161
1162     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1163     info.status_addr        = CVMX_NPI_INT_SUM;
1164     info.status_mask        = 1ull<<51 /* com_a_f */;
1165     info.enable_addr        = CVMX_NPI_INT_ENB;
1166     info.enable_mask        = 1ull<<51 /* com_a_f */;
1167     info.flags              = 0;
1168     info.group              = CVMX_ERROR_GROUP_PCI;
1169     info.group_index        = 0;
1170     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1171     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1172     info.parent.status_mask = 1ull<<3 /* npi */;
1173     info.func               = __cvmx_error_display;
1174     info.user_info          = (long)
1175         "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
1176         "    PASS3 Field.\n";
1177     fail |= cvmx_error_add(&info);
1178
1179     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1180     info.status_addr        = CVMX_NPI_INT_SUM;
1181     info.status_mask        = 1ull<<52 /* pnc_s_e */;
1182     info.enable_addr        = CVMX_NPI_INT_ENB;
1183     info.enable_mask        = 1ull<<52 /* pnc_s_e */;
1184     info.flags              = 0;
1185     info.group              = CVMX_ERROR_GROUP_PCI;
1186     info.group_index        = 0;
1187     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1188     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1189     info.parent.status_mask = 1ull<<3 /* npi */;
1190     info.func               = __cvmx_error_display;
1191     info.user_info          = (long)
1192         "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
1193         "    PASS3 Field.\n";
1194     fail |= cvmx_error_add(&info);
1195
1196     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1197     info.status_addr        = CVMX_NPI_INT_SUM;
1198     info.status_mask        = 1ull<<53 /* pnc_a_f */;
1199     info.enable_addr        = CVMX_NPI_INT_ENB;
1200     info.enable_mask        = 1ull<<53 /* pnc_a_f */;
1201     info.flags              = 0;
1202     info.group              = CVMX_ERROR_GROUP_PCI;
1203     info.group_index        = 0;
1204     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1205     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1206     info.parent.status_mask = 1ull<<3 /* npi */;
1207     info.func               = __cvmx_error_display;
1208     info.user_info          = (long)
1209         "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
1210         "    PASS3 Field.\n";
1211     fail |= cvmx_error_add(&info);
1212
1213     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1214     info.status_addr        = CVMX_NPI_INT_SUM;
1215     info.status_mask        = 1ull<<54 /* rwx_s_e */;
1216     info.enable_addr        = CVMX_NPI_INT_ENB;
1217     info.enable_mask        = 1ull<<54 /* rwx_s_e */;
1218     info.flags              = 0;
1219     info.group              = CVMX_ERROR_GROUP_PCI;
1220     info.group_index        = 0;
1221     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1222     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1223     info.parent.status_mask = 1ull<<3 /* npi */;
1224     info.func               = __cvmx_error_display;
1225     info.user_info          = (long)
1226         "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
1227         "    PASS3 Field.\n";
1228     fail |= cvmx_error_add(&info);
1229
1230     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1231     info.status_addr        = CVMX_NPI_INT_SUM;
1232     info.status_mask        = 1ull<<55 /* rdx_s_e */;
1233     info.enable_addr        = CVMX_NPI_INT_ENB;
1234     info.enable_mask        = 1ull<<55 /* rdx_s_e */;
1235     info.flags              = 0;
1236     info.group              = CVMX_ERROR_GROUP_PCI;
1237     info.group_index        = 0;
1238     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1239     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1240     info.parent.status_mask = 1ull<<3 /* npi */;
1241     info.func               = __cvmx_error_display;
1242     info.user_info          = (long)
1243         "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
1244         "    PASS3 Field.\n";
1245     fail |= cvmx_error_add(&info);
1246
1247     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1248     info.status_addr        = CVMX_NPI_INT_SUM;
1249     info.status_mask        = 1ull<<56 /* pcf_p_e */;
1250     info.enable_addr        = CVMX_NPI_INT_ENB;
1251     info.enable_mask        = 1ull<<56 /* pcf_p_e */;
1252     info.flags              = 0;
1253     info.group              = CVMX_ERROR_GROUP_PCI;
1254     info.group_index        = 0;
1255     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1256     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1257     info.parent.status_mask = 1ull<<3 /* npi */;
1258     info.func               = __cvmx_error_display;
1259     info.user_info          = (long)
1260         "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
1261         "    PASS3 Field.\n";
1262     fail |= cvmx_error_add(&info);
1263
1264     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1265     info.status_addr        = CVMX_NPI_INT_SUM;
1266     info.status_mask        = 1ull<<57 /* pcf_p_f */;
1267     info.enable_addr        = CVMX_NPI_INT_ENB;
1268     info.enable_mask        = 1ull<<57 /* pcf_p_f */;
1269     info.flags              = 0;
1270     info.group              = CVMX_ERROR_GROUP_PCI;
1271     info.group_index        = 0;
1272     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1273     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1274     info.parent.status_mask = 1ull<<3 /* npi */;
1275     info.func               = __cvmx_error_display;
1276     info.user_info          = (long)
1277         "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
1278         "    PASS3 Field.\n";
1279     fail |= cvmx_error_add(&info);
1280
1281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1282     info.status_addr        = CVMX_NPI_INT_SUM;
1283     info.status_mask        = 1ull<<58 /* pdf_p_e */;
1284     info.enable_addr        = CVMX_NPI_INT_ENB;
1285     info.enable_mask        = 1ull<<58 /* pdf_p_e */;
1286     info.flags              = 0;
1287     info.group              = CVMX_ERROR_GROUP_PCI;
1288     info.group_index        = 0;
1289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1290     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1291     info.parent.status_mask = 1ull<<3 /* npi */;
1292     info.func               = __cvmx_error_display;
1293     info.user_info          = (long)
1294         "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
1295         "    PASS3 Field.\n";
1296     fail |= cvmx_error_add(&info);
1297
1298     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1299     info.status_addr        = CVMX_NPI_INT_SUM;
1300     info.status_mask        = 1ull<<59 /* pdf_p_f */;
1301     info.enable_addr        = CVMX_NPI_INT_ENB;
1302     info.enable_mask        = 1ull<<59 /* pdf_p_f */;
1303     info.flags              = 0;
1304     info.group              = CVMX_ERROR_GROUP_PCI;
1305     info.group_index        = 0;
1306     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1307     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1308     info.parent.status_mask = 1ull<<3 /* npi */;
1309     info.func               = __cvmx_error_display;
1310     info.user_info          = (long)
1311         "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
1312         "    PASS3 Field.\n";
1313     fail |= cvmx_error_add(&info);
1314
1315     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1316     info.status_addr        = CVMX_NPI_INT_SUM;
1317     info.status_mask        = 1ull<<60 /* q1_s_e */;
1318     info.enable_addr        = CVMX_NPI_INT_ENB;
1319     info.enable_mask        = 1ull<<60 /* q1_s_e */;
1320     info.flags              = 0;
1321     info.group              = CVMX_ERROR_GROUP_PCI;
1322     info.group_index        = 0;
1323     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1324     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1325     info.parent.status_mask = 1ull<<3 /* npi */;
1326     info.func               = __cvmx_error_display;
1327     info.user_info          = (long)
1328         "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
1329         "    PASS3 Field.\n";
1330     fail |= cvmx_error_add(&info);
1331
1332     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1333     info.status_addr        = CVMX_NPI_INT_SUM;
1334     info.status_mask        = 1ull<<61 /* q1_a_f */;
1335     info.enable_addr        = CVMX_NPI_INT_ENB;
1336     info.enable_mask        = 1ull<<61 /* q1_a_f */;
1337     info.flags              = 0;
1338     info.group              = CVMX_ERROR_GROUP_PCI;
1339     info.group_index        = 0;
1340     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1341     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1342     info.parent.status_mask = 1ull<<3 /* npi */;
1343     info.func               = __cvmx_error_display;
1344     info.user_info          = (long)
1345         "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
1346         "    PASS3 Field.\n";
1347     fail |= cvmx_error_add(&info);
1348
1349     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1350     info.status_addr        = CVMX_NPI_INT_SUM;
1351     info.status_mask        = 0;
1352     info.enable_addr        = 0;
1353     info.enable_mask        = 0;
1354     info.flags              = 0;
1355     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1356     info.group_index        = 0;
1357     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1358     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1359     info.parent.status_mask = 1ull<<3 /* npi */;
1360     info.func               = __cvmx_error_decode;
1361     info.user_info          = 0;
1362     fail |= cvmx_error_add(&info);
1363
1364     /* CVMX_NPI_PCI_INT_SUM2 */
1365     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1366     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1367     info.status_mask        = 1ull<<0 /* tr_wabt */;
1368     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1369     info.enable_mask        = 1ull<<0 /* rtr_wabt */;
1370     info.flags              = 0;
1371     info.group              = CVMX_ERROR_GROUP_PCI;
1372     info.group_index        = 0;
1373     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1374     info.parent.status_addr = CVMX_NPI_INT_SUM;
1375     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1376     info.func               = __cvmx_error_display;
1377     info.user_info          = (long)
1378         "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
1379     fail |= cvmx_error_add(&info);
1380
1381     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1382     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1383     info.status_mask        = 1ull<<1 /* mr_wabt */;
1384     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1385     info.enable_mask        = 1ull<<1 /* rmr_wabt */;
1386     info.flags              = 0;
1387     info.group              = CVMX_ERROR_GROUP_PCI;
1388     info.group_index        = 0;
1389     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1390     info.parent.status_addr = CVMX_NPI_INT_SUM;
1391     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1392     info.func               = __cvmx_error_display;
1393     info.user_info          = (long)
1394         "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
1395     fail |= cvmx_error_add(&info);
1396
1397     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1398     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1399     info.status_mask        = 1ull<<2 /* mr_wtto */;
1400     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1401     info.enable_mask        = 1ull<<2 /* rmr_wtto */;
1402     info.flags              = 0;
1403     info.group              = CVMX_ERROR_GROUP_PCI;
1404     info.group_index        = 0;
1405     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1406     info.parent.status_addr = CVMX_NPI_INT_SUM;
1407     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1408     info.func               = __cvmx_error_display;
1409     info.user_info          = (long)
1410         "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
1411     fail |= cvmx_error_add(&info);
1412
1413     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1414     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1415     info.status_mask        = 1ull<<3 /* tr_abt */;
1416     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1417     info.enable_mask        = 1ull<<3 /* rtr_abt */;
1418     info.flags              = 0;
1419     info.group              = CVMX_ERROR_GROUP_PCI;
1420     info.group_index        = 0;
1421     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1422     info.parent.status_addr = CVMX_NPI_INT_SUM;
1423     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1424     info.func               = __cvmx_error_display;
1425     info.user_info          = (long)
1426         "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
1427     fail |= cvmx_error_add(&info);
1428
1429     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1430     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1431     info.status_mask        = 1ull<<4 /* mr_abt */;
1432     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1433     info.enable_mask        = 1ull<<4 /* rmr_abt */;
1434     info.flags              = 0;
1435     info.group              = CVMX_ERROR_GROUP_PCI;
1436     info.group_index        = 0;
1437     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1438     info.parent.status_addr = CVMX_NPI_INT_SUM;
1439     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1440     info.func               = __cvmx_error_display;
1441     info.user_info          = (long)
1442         "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
1443     fail |= cvmx_error_add(&info);
1444
1445     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1446     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1447     info.status_mask        = 1ull<<5 /* mr_tto */;
1448     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1449     info.enable_mask        = 1ull<<5 /* rmr_tto */;
1450     info.flags              = 0;
1451     info.group              = CVMX_ERROR_GROUP_PCI;
1452     info.group_index        = 0;
1453     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1454     info.parent.status_addr = CVMX_NPI_INT_SUM;
1455     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1456     info.func               = __cvmx_error_display;
1457     info.user_info          = (long)
1458         "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
1459     fail |= cvmx_error_add(&info);
1460
1461     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1462     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1463     info.status_mask        = 1ull<<6 /* msi_per */;
1464     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1465     info.enable_mask        = 1ull<<6 /* rmsi_per */;
1466     info.flags              = 0;
1467     info.group              = CVMX_ERROR_GROUP_PCI;
1468     info.group_index        = 0;
1469     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1470     info.parent.status_addr = CVMX_NPI_INT_SUM;
1471     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1472     info.func               = __cvmx_error_display;
1473     info.user_info          = (long)
1474         "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
1475     fail |= cvmx_error_add(&info);
1476
1477     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1478     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1479     info.status_mask        = 1ull<<7 /* msi_tabt */;
1480     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1481     info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
1482     info.flags              = 0;
1483     info.group              = CVMX_ERROR_GROUP_PCI;
1484     info.group_index        = 0;
1485     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1486     info.parent.status_addr = CVMX_NPI_INT_SUM;
1487     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1488     info.func               = __cvmx_error_display;
1489     info.user_info          = (long)
1490         "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
1491     fail |= cvmx_error_add(&info);
1492
1493     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1494     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1495     info.status_mask        = 1ull<<8 /* msi_mabt */;
1496     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1497     info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
1498     info.flags              = 0;
1499     info.group              = CVMX_ERROR_GROUP_PCI;
1500     info.group_index        = 0;
1501     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1502     info.parent.status_addr = CVMX_NPI_INT_SUM;
1503     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1504     info.func               = __cvmx_error_display;
1505     info.user_info          = (long)
1506         "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
1507     fail |= cvmx_error_add(&info);
1508
1509     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1510     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1511     info.status_mask        = 1ull<<9 /* msc_msg */;
1512     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1513     info.enable_mask        = 1ull<<9 /* rmsc_msg */;
1514     info.flags              = 0;
1515     info.group              = CVMX_ERROR_GROUP_PCI;
1516     info.group_index        = 0;
1517     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1518     info.parent.status_addr = CVMX_NPI_INT_SUM;
1519     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1520     info.func               = __cvmx_error_display;
1521     info.user_info          = (long)
1522         "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
1523     fail |= cvmx_error_add(&info);
1524
1525     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1526     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1527     info.status_mask        = 1ull<<10 /* tsr_abt */;
1528     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1529     info.enable_mask        = 1ull<<10 /* rtsr_abt */;
1530     info.flags              = 0;
1531     info.group              = CVMX_ERROR_GROUP_PCI;
1532     info.group_index        = 0;
1533     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1534     info.parent.status_addr = CVMX_NPI_INT_SUM;
1535     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1536     info.func               = __cvmx_error_display;
1537     info.user_info          = (long)
1538         "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
1539     fail |= cvmx_error_add(&info);
1540
1541     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1542     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1543     info.status_mask        = 1ull<<11 /* serr */;
1544     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1545     info.enable_mask        = 1ull<<11 /* rserr */;
1546     info.flags              = 0;
1547     info.group              = CVMX_ERROR_GROUP_PCI;
1548     info.group_index        = 0;
1549     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1550     info.parent.status_addr = CVMX_NPI_INT_SUM;
1551     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1552     info.func               = __cvmx_error_display;
1553     info.user_info          = (long)
1554         "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
1555     fail |= cvmx_error_add(&info);
1556
1557     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1558     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1559     info.status_mask        = 1ull<<12 /* aperr */;
1560     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1561     info.enable_mask        = 1ull<<12 /* raperr */;
1562     info.flags              = 0;
1563     info.group              = CVMX_ERROR_GROUP_PCI;
1564     info.group_index        = 0;
1565     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1566     info.parent.status_addr = CVMX_NPI_INT_SUM;
1567     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1568     info.func               = __cvmx_error_display;
1569     info.user_info          = (long)
1570         "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
1571     fail |= cvmx_error_add(&info);
1572
1573     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1574     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1575     info.status_mask        = 1ull<<13 /* dperr */;
1576     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1577     info.enable_mask        = 1ull<<13 /* rdperr */;
1578     info.flags              = 0;
1579     info.group              = CVMX_ERROR_GROUP_PCI;
1580     info.group_index        = 0;
1581     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1582     info.parent.status_addr = CVMX_NPI_INT_SUM;
1583     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1584     info.func               = __cvmx_error_display;
1585     info.user_info          = (long)
1586         "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
1587     fail |= cvmx_error_add(&info);
1588
1589     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1590     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1591     info.status_mask        = 1ull<<14 /* ill_rwr */;
1592     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1593     info.enable_mask        = 1ull<<14 /* ill_rwr */;
1594     info.flags              = 0;
1595     info.group              = CVMX_ERROR_GROUP_PCI;
1596     info.group_index        = 0;
1597     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1598     info.parent.status_addr = CVMX_NPI_INT_SUM;
1599     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1600     info.func               = __cvmx_error_display;
1601     info.user_info          = (long)
1602         "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
1603     fail |= cvmx_error_add(&info);
1604
1605     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1606     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1607     info.status_mask        = 1ull<<15 /* ill_rrd */;
1608     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1609     info.enable_mask        = 1ull<<15 /* ill_rrd */;
1610     info.flags              = 0;
1611     info.group              = CVMX_ERROR_GROUP_PCI;
1612     info.group_index        = 0;
1613     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1614     info.parent.status_addr = CVMX_NPI_INT_SUM;
1615     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1616     info.func               = __cvmx_error_display;
1617     info.user_info          = (long)
1618         "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
1619     fail |= cvmx_error_add(&info);
1620
1621     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1622     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1623     info.status_mask        = 1ull<<31 /* win_wr */;
1624     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1625     info.enable_mask        = 1ull<<31 /* win_wr */;
1626     info.flags              = 0;
1627     info.group              = CVMX_ERROR_GROUP_PCI;
1628     info.group_index        = 0;
1629     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1630     info.parent.status_addr = CVMX_NPI_INT_SUM;
1631     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1632     info.func               = __cvmx_error_display;
1633     info.user_info          = (long)
1634         "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
1635         "    Read-Address Register took place.\n";
1636     fail |= cvmx_error_add(&info);
1637
1638     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1639     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1640     info.status_mask        = 1ull<<32 /* ill_wr */;
1641     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1642     info.enable_mask        = 1ull<<32 /* ill_wr */;
1643     info.flags              = 0;
1644     info.group              = CVMX_ERROR_GROUP_PCI;
1645     info.group_index        = 0;
1646     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1647     info.parent.status_addr = CVMX_NPI_INT_SUM;
1648     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1649     info.func               = __cvmx_error_display;
1650     info.user_info          = (long)
1651         "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
1652         "    when the mem area is disabled.\n";
1653     fail |= cvmx_error_add(&info);
1654
1655     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1656     info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
1657     info.status_mask        = 1ull<<33 /* ill_rd */;
1658     info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
1659     info.enable_mask        = 1ull<<33 /* ill_rd */;
1660     info.flags              = 0;
1661     info.group              = CVMX_ERROR_GROUP_PCI;
1662     info.group_index        = 0;
1663     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1664     info.parent.status_addr = CVMX_NPI_INT_SUM;
1665     info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1666     info.func               = __cvmx_error_display;
1667     info.user_info          = (long)
1668         "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
1669         "    when the mem area is disabled.\n";
1670     fail |= cvmx_error_add(&info);
1671
1672     /* CVMX_GMXX_BAD_REG(0) */
1673     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1674     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1675     info.status_mask        = 1ull<<0 /* out_col */;
1676     info.enable_addr        = 0;
1677     info.enable_mask        = 0;
1678     info.flags              = 0;
1679     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1680     info.group_index        = 0;
1681     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1682     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1683     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1684     info.func               = __cvmx_error_display;
1685     info.user_info          = (long)
1686         "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
1687     fail |= cvmx_error_add(&info);
1688
1689     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1690     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1691     info.status_mask        = 1ull<<1 /* ncb_ovr */;
1692     info.enable_addr        = 0;
1693     info.enable_mask        = 0;
1694     info.flags              = 0;
1695     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1696     info.group_index        = 0;
1697     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1698     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1699     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1700     info.func               = __cvmx_error_display;
1701     info.user_info          = (long)
1702         "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
1703     fail |= cvmx_error_add(&info);
1704
1705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1706     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1707     info.status_mask        = 0xffffull<<2 /* out_ovr */;
1708     info.enable_addr        = 0;
1709     info.enable_mask        = 0;
1710     info.flags              = 0;
1711     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1712     info.group_index        = 0;
1713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1715     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1716     info.func               = __cvmx_error_display;
1717     info.user_info          = (long)
1718         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1719     fail |= cvmx_error_add(&info);
1720
1721     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1722     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1723     info.status_mask        = 0xfull<<22 /* loststat */;
1724     info.enable_addr        = 0;
1725     info.enable_mask        = 0;
1726     info.flags              = 0;
1727     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1728     info.group_index        = 0;
1729     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1730     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1731     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1732     info.func               = __cvmx_error_display;
1733     info.user_info          = (long)
1734         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
1735         "    TX Stats are corrupted\n";
1736     fail |= cvmx_error_add(&info);
1737
1738     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1739     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1740     info.status_mask        = 1ull<<26 /* statovr */;
1741     info.enable_addr        = 0;
1742     info.enable_mask        = 0;
1743     info.flags              = 0;
1744     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1745     info.group_index        = 0;
1746     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1747     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1748     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1749     info.func               = __cvmx_error_display;
1750     info.user_info          = (long)
1751         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
1752     fail |= cvmx_error_add(&info);
1753
1754     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1755     info.status_addr        = CVMX_GMXX_BAD_REG(0);
1756     info.status_mask        = 0xfull<<27 /* inb_nxa */;
1757     info.enable_addr        = 0;
1758     info.enable_mask        = 0;
1759     info.flags              = 0;
1760     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1761     info.group_index        = 0;
1762     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1763     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1764     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1765     info.func               = __cvmx_error_display;
1766     info.user_info          = (long)
1767         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1768     fail |= cvmx_error_add(&info);
1769
1770     /* CVMX_GMXX_RXX_INT_REG(0,0) */
1771     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1772     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1773     info.status_mask        = 1ull<<1 /* carext */;
1774     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1775     info.enable_mask        = 1ull<<1 /* carext */;
1776     info.flags              = 0;
1777     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1778     info.group_index        = 0;
1779     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1780     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1781     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1782     info.func               = __cvmx_error_display;
1783     info.user_info          = (long)
1784         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
1785     fail |= cvmx_error_add(&info);
1786
1787     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1788     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1789     info.status_mask        = 1ull<<2 /* maxerr */;
1790     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1791     info.enable_mask        = 1ull<<2 /* maxerr */;
1792     info.flags              = 0;
1793     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1794     info.group_index        = 0;
1795     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1796     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1797     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1798     info.func               = __cvmx_error_display;
1799     info.user_info          = (long)
1800         "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
1801     fail |= cvmx_error_add(&info);
1802
1803     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1804     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1805     info.status_mask        = 1ull<<5 /* alnerr */;
1806     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1807     info.enable_mask        = 1ull<<5 /* alnerr */;
1808     info.flags              = 0;
1809     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1810     info.group_index        = 0;
1811     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1812     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1813     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1814     info.func               = __cvmx_error_display;
1815     info.user_info          = (long)
1816         "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
1817     fail |= cvmx_error_add(&info);
1818
1819     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1820     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1821     info.status_mask        = 1ull<<6 /* lenerr */;
1822     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1823     info.enable_mask        = 1ull<<6 /* lenerr */;
1824     info.flags              = 0;
1825     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1826     info.group_index        = 0;
1827     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1828     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1829     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1830     info.func               = __cvmx_error_display;
1831     info.user_info          = (long)
1832         "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
1833     fail |= cvmx_error_add(&info);
1834
1835     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1836     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1837     info.status_mask        = 1ull<<8 /* skperr */;
1838     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1839     info.enable_mask        = 1ull<<8 /* skperr */;
1840     info.flags              = 0;
1841     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1842     info.group_index        = 0;
1843     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1844     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1845     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1846     info.func               = __cvmx_error_display;
1847     info.user_info          = (long)
1848         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
1849     fail |= cvmx_error_add(&info);
1850
1851     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1852     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1853     info.status_mask        = 1ull<<9 /* niberr */;
1854     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1855     info.enable_mask        = 1ull<<9 /* niberr */;
1856     info.flags              = 0;
1857     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1858     info.group_index        = 0;
1859     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1860     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1861     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1862     info.func               = __cvmx_error_display;
1863     info.user_info          = (long)
1864         "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1865     fail |= cvmx_error_add(&info);
1866
1867     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1868     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
1869     info.status_mask        = 1ull<<10 /* ovrerr */;
1870     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
1871     info.enable_mask        = 1ull<<10 /* ovrerr */;
1872     info.flags              = 0;
1873     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1874     info.group_index        = 0;
1875     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1876     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1877     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1878     info.func               = __cvmx_error_display;
1879     info.user_info          = (long)
1880         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1881         "    This interrupt should never assert\n";
1882     fail |= cvmx_error_add(&info);
1883
1884     /* CVMX_GMXX_RXX_INT_REG(1,0) */
1885     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1886     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1887     info.status_mask        = 1ull<<1 /* carext */;
1888     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1889     info.enable_mask        = 1ull<<1 /* carext */;
1890     info.flags              = 0;
1891     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1892     info.group_index        = 1;
1893     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1894     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1895     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1896     info.func               = __cvmx_error_display;
1897     info.user_info          = (long)
1898         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
1899     fail |= cvmx_error_add(&info);
1900
1901     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1902     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1903     info.status_mask        = 1ull<<2 /* maxerr */;
1904     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1905     info.enable_mask        = 1ull<<2 /* maxerr */;
1906     info.flags              = 0;
1907     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1908     info.group_index        = 1;
1909     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1910     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1911     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1912     info.func               = __cvmx_error_display;
1913     info.user_info          = (long)
1914         "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
1915     fail |= cvmx_error_add(&info);
1916
1917     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1918     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1919     info.status_mask        = 1ull<<5 /* alnerr */;
1920     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1921     info.enable_mask        = 1ull<<5 /* alnerr */;
1922     info.flags              = 0;
1923     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1924     info.group_index        = 1;
1925     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1926     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1927     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1928     info.func               = __cvmx_error_display;
1929     info.user_info          = (long)
1930         "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
1931     fail |= cvmx_error_add(&info);
1932
1933     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1934     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1935     info.status_mask        = 1ull<<6 /* lenerr */;
1936     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1937     info.enable_mask        = 1ull<<6 /* lenerr */;
1938     info.flags              = 0;
1939     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1940     info.group_index        = 1;
1941     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1942     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1943     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1944     info.func               = __cvmx_error_display;
1945     info.user_info          = (long)
1946         "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
1947     fail |= cvmx_error_add(&info);
1948
1949     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1950     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1951     info.status_mask        = 1ull<<8 /* skperr */;
1952     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1953     info.enable_mask        = 1ull<<8 /* skperr */;
1954     info.flags              = 0;
1955     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1956     info.group_index        = 1;
1957     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1958     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1959     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1960     info.func               = __cvmx_error_display;
1961     info.user_info          = (long)
1962         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1963     fail |= cvmx_error_add(&info);
1964
1965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1966     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1967     info.status_mask        = 1ull<<9 /* niberr */;
1968     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1969     info.enable_mask        = 1ull<<9 /* niberr */;
1970     info.flags              = 0;
1971     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1972     info.group_index        = 1;
1973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1974     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1975     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1976     info.func               = __cvmx_error_display;
1977     info.user_info          = (long)
1978         "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
1979     fail |= cvmx_error_add(&info);
1980
1981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1982     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
1983     info.status_mask        = 1ull<<10 /* ovrerr */;
1984     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
1985     info.enable_mask        = 1ull<<10 /* ovrerr */;
1986     info.flags              = 0;
1987     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1988     info.group_index        = 1;
1989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1990     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1991     info.parent.status_mask = 1ull<<1 /* gmx0 */;
1992     info.func               = __cvmx_error_display;
1993     info.user_info          = (long)
1994         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1995         "    This interrupt should never assert\n";
1996     fail |= cvmx_error_add(&info);
1997
1998     /* CVMX_GMXX_RXX_INT_REG(2,0) */
1999     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2000     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2001     info.status_mask        = 1ull<<1 /* carext */;
2002     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2003     info.enable_mask        = 1ull<<1 /* carext */;
2004     info.flags              = 0;
2005     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2006     info.group_index        = 2;
2007     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2008     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2009     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2010     info.func               = __cvmx_error_display;
2011     info.user_info          = (long)
2012         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
2013     fail |= cvmx_error_add(&info);
2014
2015     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2016     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2017     info.status_mask        = 1ull<<2 /* maxerr */;
2018     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2019     info.enable_mask        = 1ull<<2 /* maxerr */;
2020     info.flags              = 0;
2021     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2022     info.group_index        = 2;
2023     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2024     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2025     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2026     info.func               = __cvmx_error_display;
2027     info.user_info          = (long)
2028         "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
2029     fail |= cvmx_error_add(&info);
2030
2031     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2032     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2033     info.status_mask        = 1ull<<5 /* alnerr */;
2034     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2035     info.enable_mask        = 1ull<<5 /* alnerr */;
2036     info.flags              = 0;
2037     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2038     info.group_index        = 2;
2039     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2040     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2041     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2042     info.func               = __cvmx_error_display;
2043     info.user_info          = (long)
2044         "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
2045     fail |= cvmx_error_add(&info);
2046
2047     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2048     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2049     info.status_mask        = 1ull<<6 /* lenerr */;
2050     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2051     info.enable_mask        = 1ull<<6 /* lenerr */;
2052     info.flags              = 0;
2053     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2054     info.group_index        = 2;
2055     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2056     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2057     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2058     info.func               = __cvmx_error_display;
2059     info.user_info          = (long)
2060         "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
2061     fail |= cvmx_error_add(&info);
2062
2063     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2064     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2065     info.status_mask        = 1ull<<8 /* skperr */;
2066     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2067     info.enable_mask        = 1ull<<8 /* skperr */;
2068     info.flags              = 0;
2069     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2070     info.group_index        = 2;
2071     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2072     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2073     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2074     info.func               = __cvmx_error_display;
2075     info.user_info          = (long)
2076         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
2077     fail |= cvmx_error_add(&info);
2078
2079     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2080     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2081     info.status_mask        = 1ull<<9 /* niberr */;
2082     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2083     info.enable_mask        = 1ull<<9 /* niberr */;
2084     info.flags              = 0;
2085     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2086     info.group_index        = 2;
2087     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2088     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2089     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2090     info.func               = __cvmx_error_display;
2091     info.user_info          = (long)
2092         "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2093     fail |= cvmx_error_add(&info);
2094
2095     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2096     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
2097     info.status_mask        = 1ull<<10 /* ovrerr */;
2098     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
2099     info.enable_mask        = 1ull<<10 /* ovrerr */;
2100     info.flags              = 0;
2101     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2102     info.group_index        = 2;
2103     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2104     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2105     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2106     info.func               = __cvmx_error_display;
2107     info.user_info          = (long)
2108         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2109         "    This interrupt should never assert\n";
2110     fail |= cvmx_error_add(&info);
2111
2112     /* CVMX_GMXX_RXX_INT_REG(3,0) */
2113     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2114     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2115     info.status_mask        = 1ull<<1 /* carext */;
2116     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2117     info.enable_mask        = 1ull<<1 /* carext */;
2118     info.flags              = 0;
2119     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2120     info.group_index        = 3;
2121     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2122     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2123     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2124     info.func               = __cvmx_error_display;
2125     info.user_info          = (long)
2126         "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
2127     fail |= cvmx_error_add(&info);
2128
2129     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2130     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2131     info.status_mask        = 1ull<<2 /* maxerr */;
2132     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2133     info.enable_mask        = 1ull<<2 /* maxerr */;
2134     info.flags              = 0;
2135     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2136     info.group_index        = 3;
2137     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2138     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2139     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2140     info.func               = __cvmx_error_display;
2141     info.user_info          = (long)
2142         "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
2143     fail |= cvmx_error_add(&info);
2144
2145     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2146     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2147     info.status_mask        = 1ull<<5 /* alnerr */;
2148     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2149     info.enable_mask        = 1ull<<5 /* alnerr */;
2150     info.flags              = 0;
2151     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2152     info.group_index        = 3;
2153     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2154     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2155     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2156     info.func               = __cvmx_error_display;
2157     info.user_info          = (long)
2158         "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
2159     fail |= cvmx_error_add(&info);
2160
2161     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2162     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2163     info.status_mask        = 1ull<<6 /* lenerr */;
2164     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2165     info.enable_mask        = 1ull<<6 /* lenerr */;
2166     info.flags              = 0;
2167     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2168     info.group_index        = 3;
2169     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2170     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2171     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2172     info.func               = __cvmx_error_display;
2173     info.user_info          = (long)
2174         "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
2175     fail |= cvmx_error_add(&info);
2176
2177     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2178     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2179     info.status_mask        = 1ull<<8 /* skperr */;
2180     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2181     info.enable_mask        = 1ull<<8 /* skperr */;
2182     info.flags              = 0;
2183     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2184     info.group_index        = 3;
2185     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2186     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2187     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2188     info.func               = __cvmx_error_display;
2189     info.user_info          = (long)
2190         "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
2191     fail |= cvmx_error_add(&info);
2192
2193     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2194     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2195     info.status_mask        = 1ull<<9 /* niberr */;
2196     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2197     info.enable_mask        = 1ull<<9 /* niberr */;
2198     info.flags              = 0;
2199     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2200     info.group_index        = 3;
2201     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2202     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2203     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2204     info.func               = __cvmx_error_display;
2205     info.user_info          = (long)
2206         "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2207     fail |= cvmx_error_add(&info);
2208
2209     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2210     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
2211     info.status_mask        = 1ull<<10 /* ovrerr */;
2212     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
2213     info.enable_mask        = 1ull<<10 /* ovrerr */;
2214     info.flags              = 0;
2215     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2216     info.group_index        = 3;
2217     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2218     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2219     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2220     info.func               = __cvmx_error_display;
2221     info.user_info          = (long)
2222         "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2223         "    This interrupt should never assert\n";
2224     fail |= cvmx_error_add(&info);
2225
2226     /* CVMX_GMXX_TX_INT_REG(0) */
2227     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2228     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2229     info.status_mask        = 1ull<<0 /* pko_nxa */;
2230     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2231     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2232     info.flags              = 0;
2233     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2234     info.group_index        = 0;
2235     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2236     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2237     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2238     info.func               = __cvmx_error_display;
2239     info.user_info          = (long)
2240         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2241     fail |= cvmx_error_add(&info);
2242
2243     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2244     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2245     info.status_mask        = 1ull<<1 /* ncb_nxa */;
2246     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2247     info.enable_mask        = 1ull<<1 /* ncb_nxa */;
2248     info.flags              = 0;
2249     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2250     info.group_index        = 0;
2251     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2252     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2253     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2254     info.func               = __cvmx_error_display;
2255     info.user_info          = (long)
2256         "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
2257     fail |= cvmx_error_add(&info);
2258
2259     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2260     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
2261     info.status_mask        = 0xfull<<2 /* undflw */;
2262     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
2263     info.enable_mask        = 0xfull<<2 /* undflw */;
2264     info.flags              = 0;
2265     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2266     info.group_index        = 0;
2267     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2268     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2269     info.parent.status_mask = 1ull<<1 /* gmx0 */;
2270     info.func               = __cvmx_error_display;
2271     info.user_info          = (long)
2272         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
2273     fail |= cvmx_error_add(&info);
2274
2275     /* CVMX_GMXX_BAD_REG(1) */
2276     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2277     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2278     info.status_mask        = 1ull<<0 /* out_col */;
2279     info.enable_addr        = 0;
2280     info.enable_mask        = 0;
2281     info.flags              = 0;
2282     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2283     info.group_index        = 16;
2284     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2285     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2286     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2287     info.func               = __cvmx_error_display;
2288     info.user_info          = (long)
2289         "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
2290     fail |= cvmx_error_add(&info);
2291
2292     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2293     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2294     info.status_mask        = 1ull<<1 /* ncb_ovr */;
2295     info.enable_addr        = 0;
2296     info.enable_mask        = 0;
2297     info.flags              = 0;
2298     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2299     info.group_index        = 16;
2300     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2301     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2302     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2303     info.func               = __cvmx_error_display;
2304     info.user_info          = (long)
2305         "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
2306     fail |= cvmx_error_add(&info);
2307
2308     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2309     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2310     info.status_mask        = 0xffffull<<2 /* out_ovr */;
2311     info.enable_addr        = 0;
2312     info.enable_mask        = 0;
2313     info.flags              = 0;
2314     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2315     info.group_index        = 16;
2316     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2317     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2318     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2319     info.func               = __cvmx_error_display;
2320     info.user_info          = (long)
2321         "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
2322     fail |= cvmx_error_add(&info);
2323
2324     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2325     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2326     info.status_mask        = 0xfull<<22 /* loststat */;
2327     info.enable_addr        = 0;
2328     info.enable_mask        = 0;
2329     info.flags              = 0;
2330     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2331     info.group_index        = 16;
2332     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2333     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2334     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2335     info.func               = __cvmx_error_display;
2336     info.user_info          = (long)
2337         "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
2338         "    TX Stats are corrupted\n";
2339     fail |= cvmx_error_add(&info);
2340
2341     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2342     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2343     info.status_mask        = 1ull<<26 /* statovr */;
2344     info.enable_addr        = 0;
2345     info.enable_mask        = 0;
2346     info.flags              = 0;
2347     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2348     info.group_index        = 16;
2349     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2350     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2351     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2352     info.func               = __cvmx_error_display;
2353     info.user_info          = (long)
2354         "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
2355     fail |= cvmx_error_add(&info);
2356
2357     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2358     info.status_addr        = CVMX_GMXX_BAD_REG(1);
2359     info.status_mask        = 0xfull<<27 /* inb_nxa */;
2360     info.enable_addr        = 0;
2361     info.enable_mask        = 0;
2362     info.flags              = 0;
2363     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2364     info.group_index        = 16;
2365     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2366     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2367     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2368     info.func               = __cvmx_error_display;
2369     info.user_info          = (long)
2370         "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
2371     fail |= cvmx_error_add(&info);
2372
2373     /* CVMX_GMXX_RXX_INT_REG(0,1) */
2374     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2375     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2376     info.status_mask        = 1ull<<1 /* carext */;
2377     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2378     info.enable_mask        = 1ull<<1 /* carext */;
2379     info.flags              = 0;
2380     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2381     info.group_index        = 16;
2382     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2383     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2384     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2385     info.func               = __cvmx_error_display;
2386     info.user_info          = (long)
2387         "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
2388     fail |= cvmx_error_add(&info);
2389
2390     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2391     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2392     info.status_mask        = 1ull<<2 /* maxerr */;
2393     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2394     info.enable_mask        = 1ull<<2 /* maxerr */;
2395     info.flags              = 0;
2396     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2397     info.group_index        = 16;
2398     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2399     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2400     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2401     info.func               = __cvmx_error_display;
2402     info.user_info          = (long)
2403         "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
2404     fail |= cvmx_error_add(&info);
2405
2406     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2407     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2408     info.status_mask        = 1ull<<5 /* alnerr */;
2409     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2410     info.enable_mask        = 1ull<<5 /* alnerr */;
2411     info.flags              = 0;
2412     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2413     info.group_index        = 16;
2414     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2415     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2416     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2417     info.func               = __cvmx_error_display;
2418     info.user_info          = (long)
2419         "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
2420     fail |= cvmx_error_add(&info);
2421
2422     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2423     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2424     info.status_mask        = 1ull<<6 /* lenerr */;
2425     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2426     info.enable_mask        = 1ull<<6 /* lenerr */;
2427     info.flags              = 0;
2428     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2429     info.group_index        = 16;
2430     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2431     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2432     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2433     info.func               = __cvmx_error_display;
2434     info.user_info          = (long)
2435         "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
2436     fail |= cvmx_error_add(&info);
2437
2438     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2439     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2440     info.status_mask        = 1ull<<8 /* skperr */;
2441     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2442     info.enable_mask        = 1ull<<8 /* skperr */;
2443     info.flags              = 0;
2444     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2445     info.group_index        = 16;
2446     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2447     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2448     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2449     info.func               = __cvmx_error_display;
2450     info.user_info          = (long)
2451         "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
2452     fail |= cvmx_error_add(&info);
2453
2454     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2455     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2456     info.status_mask        = 1ull<<9 /* niberr */;
2457     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2458     info.enable_mask        = 1ull<<9 /* niberr */;
2459     info.flags              = 0;
2460     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2461     info.group_index        = 16;
2462     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2463     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2464     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2465     info.func               = __cvmx_error_display;
2466     info.user_info          = (long)
2467         "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2468     fail |= cvmx_error_add(&info);
2469
2470     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2471     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
2472     info.status_mask        = 1ull<<10 /* ovrerr */;
2473     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
2474     info.enable_mask        = 1ull<<10 /* ovrerr */;
2475     info.flags              = 0;
2476     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2477     info.group_index        = 16;
2478     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2479     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2480     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2481     info.func               = __cvmx_error_display;
2482     info.user_info          = (long)
2483         "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2484         "    This interrupt should never assert\n";
2485     fail |= cvmx_error_add(&info);
2486
2487     /* CVMX_GMXX_RXX_INT_REG(1,1) */
2488     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2489     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2490     info.status_mask        = 1ull<<1 /* carext */;
2491     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2492     info.enable_mask        = 1ull<<1 /* carext */;
2493     info.flags              = 0;
2494     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2495     info.group_index        = 17;
2496     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2497     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2498     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2499     info.func               = __cvmx_error_display;
2500     info.user_info          = (long)
2501         "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
2502     fail |= cvmx_error_add(&info);
2503
2504     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2505     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2506     info.status_mask        = 1ull<<2 /* maxerr */;
2507     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2508     info.enable_mask        = 1ull<<2 /* maxerr */;
2509     info.flags              = 0;
2510     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2511     info.group_index        = 17;
2512     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2513     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2514     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2515     info.func               = __cvmx_error_display;
2516     info.user_info          = (long)
2517         "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
2518     fail |= cvmx_error_add(&info);
2519
2520     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2521     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2522     info.status_mask        = 1ull<<5 /* alnerr */;
2523     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2524     info.enable_mask        = 1ull<<5 /* alnerr */;
2525     info.flags              = 0;
2526     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2527     info.group_index        = 17;
2528     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2529     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2530     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2531     info.func               = __cvmx_error_display;
2532     info.user_info          = (long)
2533         "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
2534     fail |= cvmx_error_add(&info);
2535
2536     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2537     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2538     info.status_mask        = 1ull<<6 /* lenerr */;
2539     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2540     info.enable_mask        = 1ull<<6 /* lenerr */;
2541     info.flags              = 0;
2542     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2543     info.group_index        = 17;
2544     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2545     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2546     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2547     info.func               = __cvmx_error_display;
2548     info.user_info          = (long)
2549         "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
2550     fail |= cvmx_error_add(&info);
2551
2552     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2553     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2554     info.status_mask        = 1ull<<8 /* skperr */;
2555     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2556     info.enable_mask        = 1ull<<8 /* skperr */;
2557     info.flags              = 0;
2558     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2559     info.group_index        = 17;
2560     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2561     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2562     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2563     info.func               = __cvmx_error_display;
2564     info.user_info          = (long)
2565         "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
2566     fail |= cvmx_error_add(&info);
2567
2568     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2569     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2570     info.status_mask        = 1ull<<9 /* niberr */;
2571     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2572     info.enable_mask        = 1ull<<9 /* niberr */;
2573     info.flags              = 0;
2574     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2575     info.group_index        = 17;
2576     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2577     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2578     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2579     info.func               = __cvmx_error_display;
2580     info.user_info          = (long)
2581         "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2582     fail |= cvmx_error_add(&info);
2583
2584     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2585     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
2586     info.status_mask        = 1ull<<10 /* ovrerr */;
2587     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
2588     info.enable_mask        = 1ull<<10 /* ovrerr */;
2589     info.flags              = 0;
2590     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2591     info.group_index        = 17;
2592     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2593     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2594     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2595     info.func               = __cvmx_error_display;
2596     info.user_info          = (long)
2597         "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2598         "    This interrupt should never assert\n";
2599     fail |= cvmx_error_add(&info);
2600
2601     /* CVMX_GMXX_RXX_INT_REG(2,1) */
2602     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2603     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2604     info.status_mask        = 1ull<<1 /* carext */;
2605     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2606     info.enable_mask        = 1ull<<1 /* carext */;
2607     info.flags              = 0;
2608     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2609     info.group_index        = 18;
2610     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2611     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2612     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2613     info.func               = __cvmx_error_display;
2614     info.user_info          = (long)
2615         "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
2616     fail |= cvmx_error_add(&info);
2617
2618     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2619     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2620     info.status_mask        = 1ull<<2 /* maxerr */;
2621     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2622     info.enable_mask        = 1ull<<2 /* maxerr */;
2623     info.flags              = 0;
2624     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2625     info.group_index        = 18;
2626     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2627     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2628     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2629     info.func               = __cvmx_error_display;
2630     info.user_info          = (long)
2631         "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
2632     fail |= cvmx_error_add(&info);
2633
2634     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2635     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2636     info.status_mask        = 1ull<<5 /* alnerr */;
2637     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2638     info.enable_mask        = 1ull<<5 /* alnerr */;
2639     info.flags              = 0;
2640     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2641     info.group_index        = 18;
2642     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2643     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2644     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2645     info.func               = __cvmx_error_display;
2646     info.user_info          = (long)
2647         "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
2648     fail |= cvmx_error_add(&info);
2649
2650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2651     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2652     info.status_mask        = 1ull<<6 /* lenerr */;
2653     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2654     info.enable_mask        = 1ull<<6 /* lenerr */;
2655     info.flags              = 0;
2656     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2657     info.group_index        = 18;
2658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2659     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2660     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2661     info.func               = __cvmx_error_display;
2662     info.user_info          = (long)
2663         "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
2664     fail |= cvmx_error_add(&info);
2665
2666     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2667     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2668     info.status_mask        = 1ull<<8 /* skperr */;
2669     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2670     info.enable_mask        = 1ull<<8 /* skperr */;
2671     info.flags              = 0;
2672     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2673     info.group_index        = 18;
2674     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2675     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2676     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2677     info.func               = __cvmx_error_display;
2678     info.user_info          = (long)
2679         "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
2680     fail |= cvmx_error_add(&info);
2681
2682     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2683     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2684     info.status_mask        = 1ull<<9 /* niberr */;
2685     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2686     info.enable_mask        = 1ull<<9 /* niberr */;
2687     info.flags              = 0;
2688     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2689     info.group_index        = 18;
2690     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2691     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2692     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2693     info.func               = __cvmx_error_display;
2694     info.user_info          = (long)
2695         "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2696     fail |= cvmx_error_add(&info);
2697
2698     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2699     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
2700     info.status_mask        = 1ull<<10 /* ovrerr */;
2701     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
2702     info.enable_mask        = 1ull<<10 /* ovrerr */;
2703     info.flags              = 0;
2704     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2705     info.group_index        = 18;
2706     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2707     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2708     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2709     info.func               = __cvmx_error_display;
2710     info.user_info          = (long)
2711         "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2712         "    This interrupt should never assert\n";
2713     fail |= cvmx_error_add(&info);
2714
2715     /* CVMX_GMXX_RXX_INT_REG(3,1) */
2716     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2717     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2718     info.status_mask        = 1ull<<1 /* carext */;
2719     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2720     info.enable_mask        = 1ull<<1 /* carext */;
2721     info.flags              = 0;
2722     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2723     info.group_index        = 19;
2724     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2725     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2726     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2727     info.func               = __cvmx_error_display;
2728     info.user_info          = (long)
2729         "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
2730     fail |= cvmx_error_add(&info);
2731
2732     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2733     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2734     info.status_mask        = 1ull<<2 /* maxerr */;
2735     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2736     info.enable_mask        = 1ull<<2 /* maxerr */;
2737     info.flags              = 0;
2738     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2739     info.group_index        = 19;
2740     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2741     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2742     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2743     info.func               = __cvmx_error_display;
2744     info.user_info          = (long)
2745         "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
2746     fail |= cvmx_error_add(&info);
2747
2748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2749     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2750     info.status_mask        = 1ull<<5 /* alnerr */;
2751     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2752     info.enable_mask        = 1ull<<5 /* alnerr */;
2753     info.flags              = 0;
2754     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2755     info.group_index        = 19;
2756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2757     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2758     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2759     info.func               = __cvmx_error_display;
2760     info.user_info          = (long)
2761         "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
2762     fail |= cvmx_error_add(&info);
2763
2764     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2765     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2766     info.status_mask        = 1ull<<6 /* lenerr */;
2767     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2768     info.enable_mask        = 1ull<<6 /* lenerr */;
2769     info.flags              = 0;
2770     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2771     info.group_index        = 19;
2772     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2773     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2774     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2775     info.func               = __cvmx_error_display;
2776     info.user_info          = (long)
2777         "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
2778     fail |= cvmx_error_add(&info);
2779
2780     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2781     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2782     info.status_mask        = 1ull<<8 /* skperr */;
2783     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2784     info.enable_mask        = 1ull<<8 /* skperr */;
2785     info.flags              = 0;
2786     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2787     info.group_index        = 19;
2788     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2789     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2790     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2791     info.func               = __cvmx_error_display;
2792     info.user_info          = (long)
2793         "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
2794     fail |= cvmx_error_add(&info);
2795
2796     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2797     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2798     info.status_mask        = 1ull<<9 /* niberr */;
2799     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2800     info.enable_mask        = 1ull<<9 /* niberr */;
2801     info.flags              = 0;
2802     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2803     info.group_index        = 19;
2804     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2805     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2806     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2807     info.func               = __cvmx_error_display;
2808     info.user_info          = (long)
2809         "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2810     fail |= cvmx_error_add(&info);
2811
2812     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2813     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
2814     info.status_mask        = 1ull<<10 /* ovrerr */;
2815     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
2816     info.enable_mask        = 1ull<<10 /* ovrerr */;
2817     info.flags              = 0;
2818     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2819     info.group_index        = 19;
2820     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2821     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2822     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2823     info.func               = __cvmx_error_display;
2824     info.user_info          = (long)
2825         "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2826         "    This interrupt should never assert\n";
2827     fail |= cvmx_error_add(&info);
2828
2829     /* CVMX_GMXX_TX_INT_REG(1) */
2830     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2831     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2832     info.status_mask        = 1ull<<0 /* pko_nxa */;
2833     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2834     info.enable_mask        = 1ull<<0 /* pko_nxa */;
2835     info.flags              = 0;
2836     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2837     info.group_index        = 16;
2838     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2839     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2840     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2841     info.func               = __cvmx_error_display;
2842     info.user_info          = (long)
2843         "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2844     fail |= cvmx_error_add(&info);
2845
2846     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2847     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2848     info.status_mask        = 1ull<<1 /* ncb_nxa */;
2849     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2850     info.enable_mask        = 1ull<<1 /* ncb_nxa */;
2851     info.flags              = 0;
2852     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2853     info.group_index        = 16;
2854     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2855     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2856     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2857     info.func               = __cvmx_error_display;
2858     info.user_info          = (long)
2859         "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
2860     fail |= cvmx_error_add(&info);
2861
2862     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2863     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
2864     info.status_mask        = 0xfull<<2 /* undflw */;
2865     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
2866     info.enable_mask        = 0xfull<<2 /* undflw */;
2867     info.flags              = 0;
2868     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2869     info.group_index        = 16;
2870     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2871     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2872     info.parent.status_mask = 1ull<<2 /* gmx1 */;
2873     info.func               = __cvmx_error_display;
2874     info.user_info          = (long)
2875         "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
2876     fail |= cvmx_error_add(&info);
2877
2878     /* CVMX_IPD_INT_SUM */
2879     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2880     info.status_addr        = CVMX_IPD_INT_SUM;
2881     info.status_mask        = 1ull<<0 /* prc_par0 */;
2882     info.enable_addr        = CVMX_IPD_INT_ENB;
2883     info.enable_mask        = 1ull<<0 /* prc_par0 */;
2884     info.flags              = 0;
2885     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2886     info.group_index        = 0;
2887     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2888     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2889     info.parent.status_mask = 1ull<<9 /* ipd */;
2890     info.func               = __cvmx_error_display;
2891     info.user_info          = (long)
2892         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2893         "    [31:0] of the PBM memory.\n";
2894     fail |= cvmx_error_add(&info);
2895
2896     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2897     info.status_addr        = CVMX_IPD_INT_SUM;
2898     info.status_mask        = 1ull<<1 /* prc_par1 */;
2899     info.enable_addr        = CVMX_IPD_INT_ENB;
2900     info.enable_mask        = 1ull<<1 /* prc_par1 */;
2901     info.flags              = 0;
2902     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2903     info.group_index        = 0;
2904     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2905     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2906     info.parent.status_mask = 1ull<<9 /* ipd */;
2907     info.func               = __cvmx_error_display;
2908     info.user_info          = (long)
2909         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2910         "    [63:32] of the PBM memory.\n";
2911     fail |= cvmx_error_add(&info);
2912
2913     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2914     info.status_addr        = CVMX_IPD_INT_SUM;
2915     info.status_mask        = 1ull<<2 /* prc_par2 */;
2916     info.enable_addr        = CVMX_IPD_INT_ENB;
2917     info.enable_mask        = 1ull<<2 /* prc_par2 */;
2918     info.flags              = 0;
2919     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2920     info.group_index        = 0;
2921     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2922     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2923     info.parent.status_mask = 1ull<<9 /* ipd */;
2924     info.func               = __cvmx_error_display;
2925     info.user_info          = (long)
2926         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2927         "    [95:64] of the PBM memory.\n";
2928     fail |= cvmx_error_add(&info);
2929
2930     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2931     info.status_addr        = CVMX_IPD_INT_SUM;
2932     info.status_mask        = 1ull<<3 /* prc_par3 */;
2933     info.enable_addr        = CVMX_IPD_INT_ENB;
2934     info.enable_mask        = 1ull<<3 /* prc_par3 */;
2935     info.flags              = 0;
2936     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2937     info.group_index        = 0;
2938     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2939     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2940     info.parent.status_mask = 1ull<<9 /* ipd */;
2941     info.func               = __cvmx_error_display;
2942     info.user_info          = (long)
2943         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2944         "    [127:96] of the PBM memory.\n";
2945     fail |= cvmx_error_add(&info);
2946
2947     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2948     info.status_addr        = CVMX_IPD_INT_SUM;
2949     info.status_mask        = 1ull<<4 /* bp_sub */;
2950     info.enable_addr        = CVMX_IPD_INT_ENB;
2951     info.enable_mask        = 1ull<<4 /* bp_sub */;
2952     info.flags              = 0;
2953     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2954     info.group_index        = 0;
2955     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2956     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2957     info.parent.status_mask = 1ull<<9 /* ipd */;
2958     info.func               = __cvmx_error_display;
2959     info.user_info          = (long)
2960         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2961         "    supplied illegal value.\n";
2962     fail |= cvmx_error_add(&info);
2963
2964     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2965     info.status_addr        = CVMX_IPD_INT_SUM;
2966     info.status_mask        = 1ull<<5 /* dc_ovr */;
2967     info.enable_addr        = CVMX_IPD_INT_ENB;
2968     info.enable_mask        = 1ull<<5 /* dc_ovr */;
2969     info.flags              = 0;
2970     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2971     info.group_index        = 0;
2972     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2973     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2974     info.parent.status_mask = 1ull<<9 /* ipd */;
2975     info.func               = __cvmx_error_display;
2976     info.user_info          = (long)
2977         "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
2978         "    This is a PASS-3 Field.\n";
2979     fail |= cvmx_error_add(&info);
2980
2981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2982     info.status_addr        = CVMX_IPD_INT_SUM;
2983     info.status_mask        = 1ull<<6 /* cc_ovr */;
2984     info.enable_addr        = CVMX_IPD_INT_ENB;
2985     info.enable_mask        = 1ull<<6 /* cc_ovr */;
2986     info.flags              = 0;
2987     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2988     info.group_index        = 0;
2989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2990     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2991     info.parent.status_mask = 1ull<<9 /* ipd */;
2992     info.func               = __cvmx_error_display;
2993     info.user_info          = (long)
2994         "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
2995         "    This is a PASS-3 Field.\n";
2996     fail |= cvmx_error_add(&info);
2997
2998     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2999     info.status_addr        = CVMX_IPD_INT_SUM;
3000     info.status_mask        = 1ull<<7 /* c_coll */;
3001     info.enable_addr        = CVMX_IPD_INT_ENB;
3002     info.enable_mask        = 1ull<<7 /* c_coll */;
3003     info.flags              = 0;
3004     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3005     info.group_index        = 0;
3006     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3007     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3008     info.parent.status_mask = 1ull<<9 /* ipd */;
3009     info.func               = __cvmx_error_display;
3010     info.user_info          = (long)
3011         "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
3012         "    collides.\n"
3013         "    This is a PASS-3 Field.\n";
3014     fail |= cvmx_error_add(&info);
3015
3016     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3017     info.status_addr        = CVMX_IPD_INT_SUM;
3018     info.status_mask        = 1ull<<8 /* d_coll */;
3019     info.enable_addr        = CVMX_IPD_INT_ENB;
3020     info.enable_mask        = 1ull<<8 /* d_coll */;
3021     info.flags              = 0;
3022     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3023     info.group_index        = 0;
3024     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3025     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3026     info.parent.status_mask = 1ull<<9 /* ipd */;
3027     info.func               = __cvmx_error_display;
3028     info.user_info          = (long)
3029         "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
3030         "    collides.\n"
3031         "    This is a PASS-3 Field.\n";
3032     fail |= cvmx_error_add(&info);
3033
3034     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3035     info.status_addr        = CVMX_IPD_INT_SUM;
3036     info.status_mask        = 1ull<<9 /* bc_ovr */;
3037     info.enable_addr        = CVMX_IPD_INT_ENB;
3038     info.enable_mask        = 1ull<<9 /* bc_ovr */;
3039     info.flags              = 0;
3040     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3041     info.group_index        = 0;
3042     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3043     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3044     info.parent.status_mask = 1ull<<9 /* ipd */;
3045     info.func               = __cvmx_error_display;
3046     info.user_info          = (long)
3047         "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
3048         "    This is a PASS-3 Field.\n";
3049     fail |= cvmx_error_add(&info);
3050
3051     /* CVMX_SPXX_INT_REG(0) */
3052     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3053     info.status_addr        = CVMX_SPXX_INT_REG(0);
3054     info.status_mask        = 1ull<<0 /* prtnxa */;
3055     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3056     info.enable_mask        = 1ull<<0 /* prtnxa */;
3057     info.flags              = 0;
3058     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3059     info.group_index        = 0;
3060     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3061     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3062     info.parent.status_mask = 1ull<<18 /* spx0 */;
3063     info.func               = __cvmx_error_display;
3064     info.user_info          = (long)
3065         "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
3066     fail |= cvmx_error_add(&info);
3067
3068     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3069     info.status_addr        = CVMX_SPXX_INT_REG(0);
3070     info.status_mask        = 1ull<<1 /* abnorm */;
3071     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3072     info.enable_mask        = 1ull<<1 /* abnorm */;
3073     info.flags              = 0;
3074     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3075     info.group_index        = 0;
3076     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3077     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3078     info.parent.status_mask = 1ull<<18 /* spx0 */;
3079     info.func               = __cvmx_error_display;
3080     info.user_info          = (long)
3081         "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
3082     fail |= cvmx_error_add(&info);
3083
3084     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3085     info.status_addr        = CVMX_SPXX_INT_REG(0);
3086     info.status_mask        = 1ull<<4 /* spiovr */;
3087     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3088     info.enable_mask        = 1ull<<4 /* spiovr */;
3089     info.flags              = 0;
3090     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3091     info.group_index        = 0;
3092     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3093     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3094     info.parent.status_mask = 1ull<<18 /* spx0 */;
3095     info.func               = __cvmx_error_display;
3096     info.user_info          = (long)
3097         "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
3098     fail |= cvmx_error_add(&info);
3099
3100     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3101     info.status_addr        = CVMX_SPXX_INT_REG(0);
3102     info.status_mask        = 1ull<<5 /* clserr */;
3103     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3104     info.enable_mask        = 1ull<<5 /* clserr */;
3105     info.flags              = 0;
3106     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3107     info.group_index        = 0;
3108     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3109     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3110     info.parent.status_mask = 1ull<<18 /* spx0 */;
3111     info.func               = __cvmx_error_display;
3112     info.user_info          = (long)
3113         "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
3114     fail |= cvmx_error_add(&info);
3115
3116     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3117     info.status_addr        = CVMX_SPXX_INT_REG(0);
3118     info.status_mask        = 1ull<<6 /* drwnng */;
3119     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3120     info.enable_mask        = 1ull<<6 /* drwnng */;
3121     info.flags              = 0;
3122     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3123     info.group_index        = 0;
3124     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3125     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3126     info.parent.status_mask = 1ull<<18 /* spx0 */;
3127     info.func               = __cvmx_error_display;
3128     info.user_info          = (long)
3129         "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
3130     fail |= cvmx_error_add(&info);
3131
3132     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3133     info.status_addr        = CVMX_SPXX_INT_REG(0);
3134     info.status_mask        = 1ull<<7 /* rsverr */;
3135     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3136     info.enable_mask        = 1ull<<7 /* rsverr */;
3137     info.flags              = 0;
3138     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3139     info.group_index        = 0;
3140     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3141     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3142     info.parent.status_mask = 1ull<<18 /* spx0 */;
3143     info.func               = __cvmx_error_display;
3144     info.user_info          = (long)
3145         "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
3146     fail |= cvmx_error_add(&info);
3147
3148     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3149     info.status_addr        = CVMX_SPXX_INT_REG(0);
3150     info.status_mask        = 1ull<<8 /* tpaovr */;
3151     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3152     info.enable_mask        = 1ull<<8 /* tpaovr */;
3153     info.flags              = 0;
3154     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3155     info.group_index        = 0;
3156     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3157     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3158     info.parent.status_mask = 1ull<<18 /* spx0 */;
3159     info.func               = __cvmx_error_display;
3160     info.user_info          = (long)
3161         "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
3162     fail |= cvmx_error_add(&info);
3163
3164     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3165     info.status_addr        = CVMX_SPXX_INT_REG(0);
3166     info.status_mask        = 1ull<<9 /* diperr */;
3167     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3168     info.enable_mask        = 1ull<<9 /* diperr */;
3169     info.flags              = 0;
3170     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3171     info.group_index        = 0;
3172     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3173     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3174     info.parent.status_mask = 1ull<<18 /* spx0 */;
3175     info.func               = __cvmx_error_display;
3176     info.user_info          = (long)
3177         "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
3178     fail |= cvmx_error_add(&info);
3179
3180     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3181     info.status_addr        = CVMX_SPXX_INT_REG(0);
3182     info.status_mask        = 1ull<<10 /* syncerr */;
3183     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3184     info.enable_mask        = 1ull<<10 /* syncerr */;
3185     info.flags              = 0;
3186     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3187     info.group_index        = 0;
3188     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3189     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3190     info.parent.status_mask = 1ull<<18 /* spx0 */;
3191     info.func               = __cvmx_error_display;
3192     info.user_info          = (long)
3193         "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
3194         "    SPX_ERR_CTL[ERRCNT]\n";
3195     fail |= cvmx_error_add(&info);
3196
3197     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3198     info.status_addr        = CVMX_SPXX_INT_REG(0);
3199     info.status_mask        = 1ull<<11 /* calerr */;
3200     info.enable_addr        = CVMX_SPXX_INT_MSK(0);
3201     info.enable_mask        = 1ull<<11 /* calerr */;
3202     info.flags              = 0;
3203     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3204     info.group_index        = 0;
3205     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3206     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3207     info.parent.status_mask = 1ull<<18 /* spx0 */;
3208     info.func               = __cvmx_error_display;
3209     info.user_info          = (long)
3210         "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
3211     fail |= cvmx_error_add(&info);
3212
3213     /* CVMX_STXX_INT_REG(0) */
3214     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3215     info.status_addr        = CVMX_STXX_INT_REG(0);
3216     info.status_mask        = 1ull<<0 /* calpar0 */;
3217     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3218     info.enable_mask        = 1ull<<0 /* calpar0 */;
3219     info.flags              = 0;
3220     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3221     info.group_index        = 0;
3222     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3223     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3224     info.parent.status_mask = 1ull<<18 /* spx0 */;
3225     info.func               = __cvmx_error_display;
3226     info.user_info          = (long)
3227         "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
3228     fail |= cvmx_error_add(&info);
3229
3230     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3231     info.status_addr        = CVMX_STXX_INT_REG(0);
3232     info.status_mask        = 1ull<<1 /* calpar1 */;
3233     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3234     info.enable_mask        = 1ull<<1 /* calpar1 */;
3235     info.flags              = 0;
3236     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3237     info.group_index        = 0;
3238     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3239     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3240     info.parent.status_mask = 1ull<<18 /* spx0 */;
3241     info.func               = __cvmx_error_display;
3242     info.user_info          = (long)
3243         "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
3244     fail |= cvmx_error_add(&info);
3245
3246     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3247     info.status_addr        = CVMX_STXX_INT_REG(0);
3248     info.status_mask        = 1ull<<2 /* ovrbst */;
3249     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3250     info.enable_mask        = 1ull<<2 /* ovrbst */;
3251     info.flags              = 0;
3252     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3253     info.group_index        = 0;
3254     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3255     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3256     info.parent.status_mask = 1ull<<18 /* spx0 */;
3257     info.func               = __cvmx_error_display;
3258     info.user_info          = (long)
3259         "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
3260     fail |= cvmx_error_add(&info);
3261
3262     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3263     info.status_addr        = CVMX_STXX_INT_REG(0);
3264     info.status_mask        = 1ull<<3 /* datovr */;
3265     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3266     info.enable_mask        = 1ull<<3 /* datovr */;
3267     info.flags              = 0;
3268     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3269     info.group_index        = 0;
3270     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3271     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3272     info.parent.status_mask = 1ull<<18 /* spx0 */;
3273     info.func               = __cvmx_error_display;
3274     info.user_info          = (long)
3275         "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
3276     fail |= cvmx_error_add(&info);
3277
3278     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3279     info.status_addr        = CVMX_STXX_INT_REG(0);
3280     info.status_mask        = 1ull<<4 /* diperr */;
3281     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3282     info.enable_mask        = 1ull<<4 /* diperr */;
3283     info.flags              = 0;
3284     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3285     info.group_index        = 0;
3286     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3287     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3288     info.parent.status_mask = 1ull<<18 /* spx0 */;
3289     info.func               = __cvmx_error_display;
3290     info.user_info          = (long)
3291         "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
3292     fail |= cvmx_error_add(&info);
3293
3294     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3295     info.status_addr        = CVMX_STXX_INT_REG(0);
3296     info.status_mask        = 1ull<<5 /* nosync */;
3297     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3298     info.enable_mask        = 1ull<<5 /* nosync */;
3299     info.flags              = 0;
3300     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3301     info.group_index        = 0;
3302     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3303     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3304     info.parent.status_mask = 1ull<<18 /* spx0 */;
3305     info.func               = __cvmx_error_display;
3306     info.user_info          = (long)
3307         "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
3308     fail |= cvmx_error_add(&info);
3309
3310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3311     info.status_addr        = CVMX_STXX_INT_REG(0);
3312     info.status_mask        = 1ull<<6 /* unxfrm */;
3313     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3314     info.enable_mask        = 1ull<<6 /* unxfrm */;
3315     info.flags              = 0;
3316     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3317     info.group_index        = 0;
3318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3319     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3320     info.parent.status_mask = 1ull<<18 /* spx0 */;
3321     info.func               = __cvmx_error_display;
3322     info.user_info          = (long)
3323         "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
3324     fail |= cvmx_error_add(&info);
3325
3326     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3327     info.status_addr        = CVMX_STXX_INT_REG(0);
3328     info.status_mask        = 1ull<<7 /* frmerr */;
3329     info.enable_addr        = CVMX_STXX_INT_MSK(0);
3330     info.enable_mask        = 1ull<<7 /* frmerr */;
3331     info.flags              = 0;
3332     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3333     info.group_index        = 0;
3334     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3335     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3336     info.parent.status_mask = 1ull<<18 /* spx0 */;
3337     info.func               = __cvmx_error_display;
3338     info.user_info          = (long)
3339         "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
3340     fail |= cvmx_error_add(&info);
3341
3342     /* CVMX_POW_ECC_ERR */
3343     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3344     info.status_addr        = CVMX_POW_ECC_ERR;
3345     info.status_mask        = 1ull<<0 /* sbe */;
3346     info.enable_addr        = CVMX_POW_ECC_ERR;
3347     info.enable_mask        = 1ull<<2 /* sbe_ie */;
3348     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
3349     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3350     info.group_index        = 0;
3351     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3352     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3353     info.parent.status_mask = 1ull<<12 /* pow */;
3354     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
3355     info.user_info          = (long)
3356         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
3357     fail |= cvmx_error_add(&info);
3358
3359     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3360     info.status_addr        = CVMX_POW_ECC_ERR;
3361     info.status_mask        = 1ull<<1 /* dbe */;
3362     info.enable_addr        = CVMX_POW_ECC_ERR;
3363     info.enable_mask        = 1ull<<3 /* dbe_ie */;
3364     info.flags              = 0;
3365     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3366     info.group_index        = 0;
3367     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3368     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3369     info.parent.status_mask = 1ull<<12 /* pow */;
3370     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
3371     info.user_info          = (long)
3372         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
3373     fail |= cvmx_error_add(&info);
3374
3375     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3376     info.status_addr        = CVMX_POW_ECC_ERR;
3377     info.status_mask        = 1ull<<12 /* rpe */;
3378     info.enable_addr        = CVMX_POW_ECC_ERR;
3379     info.enable_mask        = 1ull<<13 /* rpe_ie */;
3380     info.flags              = 0;
3381     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3382     info.group_index        = 0;
3383     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3384     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3385     info.parent.status_mask = 1ull<<12 /* pow */;
3386     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
3387     info.user_info          = (long)
3388         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
3389     fail |= cvmx_error_add(&info);
3390
3391     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3392     info.status_addr        = CVMX_POW_ECC_ERR;
3393     info.status_mask        = 0x1fffull<<16 /* iop */;
3394     info.enable_addr        = CVMX_POW_ECC_ERR;
3395     info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
3396     info.flags              = 0;
3397     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3398     info.group_index        = 0;
3399     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3400     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3401     info.parent.status_mask = 1ull<<12 /* pow */;
3402     info.func               = __cvmx_error_handle_pow_ecc_err_iop;
3403     info.user_info          = (long)
3404         "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
3405     fail |= cvmx_error_add(&info);
3406
3407     /* CVMX_SPXX_INT_REG(1) */
3408     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3409     info.status_addr        = CVMX_SPXX_INT_REG(1);
3410     info.status_mask        = 1ull<<0 /* prtnxa */;
3411     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3412     info.enable_mask        = 1ull<<0 /* prtnxa */;
3413     info.flags              = 0;
3414     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3415     info.group_index        = 16;
3416     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3417     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3418     info.parent.status_mask = 1ull<<19 /* spx1 */;
3419     info.func               = __cvmx_error_display;
3420     info.user_info          = (long)
3421         "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
3422     fail |= cvmx_error_add(&info);
3423
3424     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3425     info.status_addr        = CVMX_SPXX_INT_REG(1);
3426     info.status_mask        = 1ull<<1 /* abnorm */;
3427     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3428     info.enable_mask        = 1ull<<1 /* abnorm */;
3429     info.flags              = 0;
3430     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3431     info.group_index        = 16;
3432     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3433     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3434     info.parent.status_mask = 1ull<<19 /* spx1 */;
3435     info.func               = __cvmx_error_display;
3436     info.user_info          = (long)
3437         "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
3438     fail |= cvmx_error_add(&info);
3439
3440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3441     info.status_addr        = CVMX_SPXX_INT_REG(1);
3442     info.status_mask        = 1ull<<4 /* spiovr */;
3443     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3444     info.enable_mask        = 1ull<<4 /* spiovr */;
3445     info.flags              = 0;
3446     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3447     info.group_index        = 16;
3448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3449     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3450     info.parent.status_mask = 1ull<<19 /* spx1 */;
3451     info.func               = __cvmx_error_display;
3452     info.user_info          = (long)
3453         "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
3454     fail |= cvmx_error_add(&info);
3455
3456     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3457     info.status_addr        = CVMX_SPXX_INT_REG(1);
3458     info.status_mask        = 1ull<<5 /* clserr */;
3459     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3460     info.enable_mask        = 1ull<<5 /* clserr */;
3461     info.flags              = 0;
3462     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3463     info.group_index        = 16;
3464     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3465     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3466     info.parent.status_mask = 1ull<<19 /* spx1 */;
3467     info.func               = __cvmx_error_display;
3468     info.user_info          = (long)
3469         "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
3470     fail |= cvmx_error_add(&info);
3471
3472     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3473     info.status_addr        = CVMX_SPXX_INT_REG(1);
3474     info.status_mask        = 1ull<<6 /* drwnng */;
3475     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3476     info.enable_mask        = 1ull<<6 /* drwnng */;
3477     info.flags              = 0;
3478     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3479     info.group_index        = 16;
3480     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3481     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3482     info.parent.status_mask = 1ull<<19 /* spx1 */;
3483     info.func               = __cvmx_error_display;
3484     info.user_info          = (long)
3485         "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
3486     fail |= cvmx_error_add(&info);
3487
3488     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3489     info.status_addr        = CVMX_SPXX_INT_REG(1);
3490     info.status_mask        = 1ull<<7 /* rsverr */;
3491     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3492     info.enable_mask        = 1ull<<7 /* rsverr */;
3493     info.flags              = 0;
3494     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3495     info.group_index        = 16;
3496     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3497     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3498     info.parent.status_mask = 1ull<<19 /* spx1 */;
3499     info.func               = __cvmx_error_display;
3500     info.user_info          = (long)
3501         "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
3502     fail |= cvmx_error_add(&info);
3503
3504     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3505     info.status_addr        = CVMX_SPXX_INT_REG(1);
3506     info.status_mask        = 1ull<<8 /* tpaovr */;
3507     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3508     info.enable_mask        = 1ull<<8 /* tpaovr */;
3509     info.flags              = 0;
3510     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3511     info.group_index        = 16;
3512     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3513     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3514     info.parent.status_mask = 1ull<<19 /* spx1 */;
3515     info.func               = __cvmx_error_display;
3516     info.user_info          = (long)
3517         "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
3518     fail |= cvmx_error_add(&info);
3519
3520     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3521     info.status_addr        = CVMX_SPXX_INT_REG(1);
3522     info.status_mask        = 1ull<<9 /* diperr */;
3523     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3524     info.enable_mask        = 1ull<<9 /* diperr */;
3525     info.flags              = 0;
3526     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3527     info.group_index        = 16;
3528     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3529     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3530     info.parent.status_mask = 1ull<<19 /* spx1 */;
3531     info.func               = __cvmx_error_display;
3532     info.user_info          = (long)
3533         "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
3534     fail |= cvmx_error_add(&info);
3535
3536     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3537     info.status_addr        = CVMX_SPXX_INT_REG(1);
3538     info.status_mask        = 1ull<<10 /* syncerr */;
3539     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3540     info.enable_mask        = 1ull<<10 /* syncerr */;
3541     info.flags              = 0;
3542     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3543     info.group_index        = 16;
3544     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3545     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3546     info.parent.status_mask = 1ull<<19 /* spx1 */;
3547     info.func               = __cvmx_error_display;
3548     info.user_info          = (long)
3549         "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
3550         "    SPX_ERR_CTL[ERRCNT]\n";
3551     fail |= cvmx_error_add(&info);
3552
3553     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3554     info.status_addr        = CVMX_SPXX_INT_REG(1);
3555     info.status_mask        = 1ull<<11 /* calerr */;
3556     info.enable_addr        = CVMX_SPXX_INT_MSK(1);
3557     info.enable_mask        = 1ull<<11 /* calerr */;
3558     info.flags              = 0;
3559     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3560     info.group_index        = 16;
3561     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3562     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3563     info.parent.status_mask = 1ull<<19 /* spx1 */;
3564     info.func               = __cvmx_error_display;
3565     info.user_info          = (long)
3566         "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
3567     fail |= cvmx_error_add(&info);
3568
3569     /* CVMX_STXX_INT_REG(1) */
3570     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3571     info.status_addr        = CVMX_STXX_INT_REG(1);
3572     info.status_mask        = 1ull<<0 /* calpar0 */;
3573     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3574     info.enable_mask        = 1ull<<0 /* calpar0 */;
3575     info.flags              = 0;
3576     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3577     info.group_index        = 16;
3578     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3579     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3580     info.parent.status_mask = 1ull<<19 /* spx1 */;
3581     info.func               = __cvmx_error_display;
3582     info.user_info          = (long)
3583         "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
3584     fail |= cvmx_error_add(&info);
3585
3586     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3587     info.status_addr        = CVMX_STXX_INT_REG(1);
3588     info.status_mask        = 1ull<<1 /* calpar1 */;
3589     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3590     info.enable_mask        = 1ull<<1 /* calpar1 */;
3591     info.flags              = 0;
3592     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3593     info.group_index        = 16;
3594     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3595     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3596     info.parent.status_mask = 1ull<<19 /* spx1 */;
3597     info.func               = __cvmx_error_display;
3598     info.user_info          = (long)
3599         "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
3600     fail |= cvmx_error_add(&info);
3601
3602     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3603     info.status_addr        = CVMX_STXX_INT_REG(1);
3604     info.status_mask        = 1ull<<2 /* ovrbst */;
3605     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3606     info.enable_mask        = 1ull<<2 /* ovrbst */;
3607     info.flags              = 0;
3608     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3609     info.group_index        = 16;
3610     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3611     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3612     info.parent.status_mask = 1ull<<19 /* spx1 */;
3613     info.func               = __cvmx_error_display;
3614     info.user_info          = (long)
3615         "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
3616     fail |= cvmx_error_add(&info);
3617
3618     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3619     info.status_addr        = CVMX_STXX_INT_REG(1);
3620     info.status_mask        = 1ull<<3 /* datovr */;
3621     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3622     info.enable_mask        = 1ull<<3 /* datovr */;
3623     info.flags              = 0;
3624     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3625     info.group_index        = 16;
3626     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3627     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3628     info.parent.status_mask = 1ull<<19 /* spx1 */;
3629     info.func               = __cvmx_error_display;
3630     info.user_info          = (long)
3631         "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
3632     fail |= cvmx_error_add(&info);
3633
3634     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3635     info.status_addr        = CVMX_STXX_INT_REG(1);
3636     info.status_mask        = 1ull<<4 /* diperr */;
3637     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3638     info.enable_mask        = 1ull<<4 /* diperr */;
3639     info.flags              = 0;
3640     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3641     info.group_index        = 16;
3642     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3643     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3644     info.parent.status_mask = 1ull<<19 /* spx1 */;
3645     info.func               = __cvmx_error_display;
3646     info.user_info          = (long)
3647         "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
3648     fail |= cvmx_error_add(&info);
3649
3650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3651     info.status_addr        = CVMX_STXX_INT_REG(1);
3652     info.status_mask        = 1ull<<5 /* nosync */;
3653     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3654     info.enable_mask        = 1ull<<5 /* nosync */;
3655     info.flags              = 0;
3656     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3657     info.group_index        = 16;
3658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3659     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3660     info.parent.status_mask = 1ull<<19 /* spx1 */;
3661     info.func               = __cvmx_error_display;
3662     info.user_info          = (long)
3663         "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
3664     fail |= cvmx_error_add(&info);
3665
3666     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3667     info.status_addr        = CVMX_STXX_INT_REG(1);
3668     info.status_mask        = 1ull<<6 /* unxfrm */;
3669     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3670     info.enable_mask        = 1ull<<6 /* unxfrm */;
3671     info.flags              = 0;
3672     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3673     info.group_index        = 16;
3674     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3675     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3676     info.parent.status_mask = 1ull<<19 /* spx1 */;
3677     info.func               = __cvmx_error_display;
3678     info.user_info          = (long)
3679         "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
3680     fail |= cvmx_error_add(&info);
3681
3682     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3683     info.status_addr        = CVMX_STXX_INT_REG(1);
3684     info.status_mask        = 1ull<<7 /* frmerr */;
3685     info.enable_addr        = CVMX_STXX_INT_MSK(1);
3686     info.enable_mask        = 1ull<<7 /* frmerr */;
3687     info.flags              = 0;
3688     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3689     info.group_index        = 16;
3690     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3691     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3692     info.parent.status_mask = 1ull<<19 /* spx1 */;
3693     info.func               = __cvmx_error_display;
3694     info.user_info          = (long)
3695         "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
3696     fail |= cvmx_error_add(&info);
3697
3698     /* CVMX_ASXX_INT_REG(0) */
3699     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3700     info.status_addr        = CVMX_ASXX_INT_REG(0);
3701     info.status_mask        = 0xfull<<8 /* txpsh */;
3702     info.enable_addr        = CVMX_ASXX_INT_EN(0);
3703     info.enable_mask        = 0xfull<<8 /* txpsh */;
3704     info.flags              = 0;
3705     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3706     info.group_index        = 0;
3707     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3708     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3709     info.parent.status_mask = 1ull<<22 /* asx0 */;
3710     info.func               = __cvmx_error_display;
3711     info.user_info          = (long)
3712         "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
3713     fail |= cvmx_error_add(&info);
3714
3715     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3716     info.status_addr        = CVMX_ASXX_INT_REG(0);
3717     info.status_mask        = 0xfull<<4 /* txpop */;
3718     info.enable_addr        = CVMX_ASXX_INT_EN(0);
3719     info.enable_mask        = 0xfull<<4 /* txpop */;
3720     info.flags              = 0;
3721     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3722     info.group_index        = 0;
3723     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3724     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3725     info.parent.status_mask = 1ull<<22 /* asx0 */;
3726     info.func               = __cvmx_error_display;
3727     info.user_info          = (long)
3728         "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
3729     fail |= cvmx_error_add(&info);
3730
3731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3732     info.status_addr        = CVMX_ASXX_INT_REG(0);
3733     info.status_mask        = 0xfull<<0 /* ovrflw */;
3734     info.enable_addr        = CVMX_ASXX_INT_EN(0);
3735     info.enable_mask        = 0xfull<<0 /* ovrflw */;
3736     info.flags              = 0;
3737     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3738     info.group_index        = 0;
3739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3740     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3741     info.parent.status_mask = 1ull<<22 /* asx0 */;
3742     info.func               = __cvmx_error_display;
3743     info.user_info          = (long)
3744         "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
3745     fail |= cvmx_error_add(&info);
3746
3747     /* CVMX_ASXX_INT_REG(1) */
3748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3749     info.status_addr        = CVMX_ASXX_INT_REG(1);
3750     info.status_mask        = 0xfull<<8 /* txpsh */;
3751     info.enable_addr        = CVMX_ASXX_INT_EN(1);
3752     info.enable_mask        = 0xfull<<8 /* txpsh */;
3753     info.flags              = 0;
3754     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3755     info.group_index        = 16;
3756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3757     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3758     info.parent.status_mask = 1ull<<23 /* asx1 */;
3759     info.func               = __cvmx_error_display;
3760     info.user_info          = (long)
3761         "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
3762     fail |= cvmx_error_add(&info);
3763
3764     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3765     info.status_addr        = CVMX_ASXX_INT_REG(1);
3766     info.status_mask        = 0xfull<<4 /* txpop */;
3767     info.enable_addr        = CVMX_ASXX_INT_EN(1);
3768     info.enable_mask        = 0xfull<<4 /* txpop */;
3769     info.flags              = 0;
3770     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3771     info.group_index        = 16;
3772     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3773     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3774     info.parent.status_mask = 1ull<<23 /* asx1 */;
3775     info.func               = __cvmx_error_display;
3776     info.user_info          = (long)
3777         "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
3778     fail |= cvmx_error_add(&info);
3779
3780     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3781     info.status_addr        = CVMX_ASXX_INT_REG(1);
3782     info.status_mask        = 0xfull<<0 /* ovrflw */;
3783     info.enable_addr        = CVMX_ASXX_INT_EN(1);
3784     info.enable_mask        = 0xfull<<0 /* ovrflw */;
3785     info.flags              = 0;
3786     info.group              = CVMX_ERROR_GROUP_ETHERNET;
3787     info.group_index        = 16;
3788     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3789     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3790     info.parent.status_mask = 1ull<<23 /* asx1 */;
3791     info.func               = __cvmx_error_display;
3792     info.user_info          = (long)
3793         "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
3794     fail |= cvmx_error_add(&info);
3795
3796     /* CVMX_PKO_REG_ERROR */
3797     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3798     info.status_addr        = CVMX_PKO_REG_ERROR;
3799     info.status_mask        = 1ull<<0 /* parity */;
3800     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3801     info.enable_mask        = 1ull<<0 /* parity */;
3802     info.flags              = 0;
3803     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3804     info.group_index        = 0;
3805     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3806     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3807     info.parent.status_mask = 1ull<<10 /* pko */;
3808     info.func               = __cvmx_error_display;
3809     info.user_info          = (long)
3810         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
3811     fail |= cvmx_error_add(&info);
3812
3813     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3814     info.status_addr        = CVMX_PKO_REG_ERROR;
3815     info.status_mask        = 1ull<<1 /* doorbell */;
3816     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3817     info.enable_mask        = 1ull<<1 /* doorbell */;
3818     info.flags              = 0;
3819     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3820     info.group_index        = 0;
3821     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3822     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3823     info.parent.status_mask = 1ull<<10 /* pko */;
3824     info.func               = __cvmx_error_display;
3825     info.user_info          = (long)
3826         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
3827     fail |= cvmx_error_add(&info);
3828
3829     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3830     info.status_addr        = CVMX_PKO_REG_ERROR;
3831     info.status_mask        = 1ull<<2 /* currzero */;
3832     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
3833     info.enable_mask        = 1ull<<2 /* currzero */;
3834     info.flags              = 0;
3835     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3836     info.group_index        = 0;
3837     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3838     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3839     info.parent.status_mask = 1ull<<10 /* pko */;
3840     info.func               = __cvmx_error_display;
3841     info.user_info          = (long)
3842         "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
3843     fail |= cvmx_error_add(&info);
3844
3845     /* CVMX_TIM_REG_ERROR */
3846     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3847     info.status_addr        = CVMX_TIM_REG_ERROR;
3848     info.status_mask        = 0xffffull<<0 /* mask */;
3849     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
3850     info.enable_mask        = 0xffffull<<0 /* mask */;
3851     info.flags              = 0;
3852     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3853     info.group_index        = 0;
3854     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3855     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3856     info.parent.status_mask = 1ull<<11 /* tim */;
3857     info.func               = __cvmx_error_display;
3858     info.user_info          = (long)
3859         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
3860     fail |= cvmx_error_add(&info);
3861
3862     /* CVMX_KEY_INT_SUM */
3863     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3864     info.status_addr        = CVMX_KEY_INT_SUM;
3865     info.status_mask        = 1ull<<0 /* ked0_sbe */;
3866     info.enable_addr        = CVMX_KEY_INT_ENB;
3867     info.enable_mask        = 1ull<<0 /* ked0_sbe */;
3868     info.flags              = 0;
3869     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3870     info.group_index        = 0;
3871     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3872     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3873     info.parent.status_mask = 1ull<<4 /* key */;
3874     info.func               = __cvmx_error_display;
3875     info.user_info          = (long)
3876         "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
3877 ;
3878     fail |= cvmx_error_add(&info);
3879
3880     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3881     info.status_addr        = CVMX_KEY_INT_SUM;
3882     info.status_mask        = 1ull<<1 /* ked0_dbe */;
3883     info.enable_addr        = CVMX_KEY_INT_ENB;
3884     info.enable_mask        = 1ull<<1 /* ked0_dbe */;
3885     info.flags              = 0;
3886     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3887     info.group_index        = 0;
3888     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3889     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3890     info.parent.status_mask = 1ull<<4 /* key */;
3891     info.func               = __cvmx_error_display;
3892     info.user_info          = (long)
3893         "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
3894 ;
3895     fail |= cvmx_error_add(&info);
3896
3897     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3898     info.status_addr        = CVMX_KEY_INT_SUM;
3899     info.status_mask        = 1ull<<2 /* ked1_sbe */;
3900     info.enable_addr        = CVMX_KEY_INT_ENB;
3901     info.enable_mask        = 1ull<<2 /* ked1_sbe */;
3902     info.flags              = 0;
3903     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3904     info.group_index        = 0;
3905     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3906     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3907     info.parent.status_mask = 1ull<<4 /* key */;
3908     info.func               = __cvmx_error_display;
3909     info.user_info          = (long)
3910         "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
3911 ;
3912     fail |= cvmx_error_add(&info);
3913
3914     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3915     info.status_addr        = CVMX_KEY_INT_SUM;
3916     info.status_mask        = 1ull<<3 /* ked1_dbe */;
3917     info.enable_addr        = CVMX_KEY_INT_ENB;
3918     info.enable_mask        = 1ull<<3 /* ked1_dbe */;
3919     info.flags              = 0;
3920     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3921     info.group_index        = 0;
3922     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3923     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3924     info.parent.status_mask = 1ull<<4 /* key */;
3925     info.func               = __cvmx_error_display;
3926     info.user_info          = (long)
3927         "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
3928 ;
3929     fail |= cvmx_error_add(&info);
3930
3931     /* CVMX_MIO_BOOT_ERR */
3932     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3933     info.status_addr        = CVMX_MIO_BOOT_ERR;
3934     info.status_mask        = 1ull<<0 /* adr_err */;
3935     info.enable_addr        = CVMX_MIO_BOOT_INT;
3936     info.enable_mask        = 1ull<<0 /* adr_int */;
3937     info.flags              = 0;
3938     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3939     info.group_index        = 0;
3940     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3941     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3942     info.parent.status_mask = 1ull<<0 /* mio */;
3943     info.func               = __cvmx_error_display;
3944     info.user_info          = (long)
3945         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
3946     fail |= cvmx_error_add(&info);
3947
3948     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3949     info.status_addr        = CVMX_MIO_BOOT_ERR;
3950     info.status_mask        = 1ull<<1 /* wait_err */;
3951     info.enable_addr        = CVMX_MIO_BOOT_INT;
3952     info.enable_mask        = 1ull<<1 /* wait_int */;
3953     info.flags              = 0;
3954     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3955     info.group_index        = 0;
3956     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3957     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3958     info.parent.status_mask = 1ull<<0 /* mio */;
3959     info.func               = __cvmx_error_display;
3960     info.user_info          = (long)
3961         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
3962     fail |= cvmx_error_add(&info);
3963
3964     /* CVMX_PIP_INT_REG */
3965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3966     info.status_addr        = CVMX_PIP_INT_REG;
3967     info.status_mask        = 1ull<<3 /* prtnxa */;
3968     info.enable_addr        = CVMX_PIP_INT_EN;
3969     info.enable_mask        = 1ull<<3 /* prtnxa */;
3970     info.flags              = 0;
3971     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3972     info.group_index        = 0;
3973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3974     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3975     info.parent.status_mask = 1ull<<20 /* pip */;
3976     info.func               = __cvmx_error_display;
3977     info.user_info          = (long)
3978         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
3979     fail |= cvmx_error_add(&info);
3980
3981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3982     info.status_addr        = CVMX_PIP_INT_REG;
3983     info.status_mask        = 1ull<<4 /* badtag */;
3984     info.enable_addr        = CVMX_PIP_INT_EN;
3985     info.enable_mask        = 1ull<<4 /* badtag */;
3986     info.flags              = 0;
3987     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3988     info.group_index        = 0;
3989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3990     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3991     info.parent.status_mask = 1ull<<20 /* pip */;
3992     info.func               = __cvmx_error_display;
3993     info.user_info          = (long)
3994         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
3995     fail |= cvmx_error_add(&info);
3996
3997     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3998     info.status_addr        = CVMX_PIP_INT_REG;
3999     info.status_mask        = 1ull<<5 /* skprunt */;
4000     info.enable_addr        = CVMX_PIP_INT_EN;
4001     info.enable_mask        = 1ull<<5 /* skprunt */;
4002     info.flags              = 0;
4003     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4004     info.group_index        = 0;
4005     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4006     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4007     info.parent.status_mask = 1ull<<20 /* pip */;
4008     info.func               = __cvmx_error_display;
4009     info.user_info          = (long)
4010         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
4011         "    This interrupt can occur with received PARTIAL\n"
4012         "    packets that are truncated to SKIP bytes or\n"
4013         "    smaller.\n";
4014     fail |= cvmx_error_add(&info);
4015
4016     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4017     info.status_addr        = CVMX_PIP_INT_REG;
4018     info.status_mask        = 1ull<<6 /* todoovr */;
4019     info.enable_addr        = CVMX_PIP_INT_EN;
4020     info.enable_mask        = 1ull<<6 /* todoovr */;
4021     info.flags              = 0;
4022     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4023     info.group_index        = 0;
4024     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4025     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4026     info.parent.status_mask = 1ull<<20 /* pip */;
4027     info.func               = __cvmx_error_display;
4028     info.user_info          = (long)
4029         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
4030     fail |= cvmx_error_add(&info);
4031
4032     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4033     info.status_addr        = CVMX_PIP_INT_REG;
4034     info.status_mask        = 1ull<<7 /* feperr */;
4035     info.enable_addr        = CVMX_PIP_INT_EN;
4036     info.enable_mask        = 1ull<<7 /* feperr */;
4037     info.flags              = 0;
4038     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4039     info.group_index        = 0;
4040     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4041     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4042     info.parent.status_mask = 1ull<<20 /* pip */;
4043     info.func               = __cvmx_error_display;
4044     info.user_info          = (long)
4045         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
4046     fail |= cvmx_error_add(&info);
4047
4048     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4049     info.status_addr        = CVMX_PIP_INT_REG;
4050     info.status_mask        = 1ull<<8 /* beperr */;
4051     info.enable_addr        = CVMX_PIP_INT_EN;
4052     info.enable_mask        = 1ull<<8 /* beperr */;
4053     info.flags              = 0;
4054     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4055     info.group_index        = 0;
4056     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4057     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4058     info.parent.status_mask = 1ull<<20 /* pip */;
4059     info.func               = __cvmx_error_display;
4060     info.user_info          = (long)
4061         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
4062     fail |= cvmx_error_add(&info);
4063
4064     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4065     info.status_addr        = CVMX_PIP_INT_REG;
4066     info.status_mask        = 1ull<<12 /* punyerr */;
4067     info.enable_addr        = CVMX_PIP_INT_EN;
4068     info.enable_mask        = 1ull<<12 /* punyerr */;
4069     info.flags              = 0;
4070     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4071     info.group_index        = 0;
4072     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4073     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4074     info.parent.status_mask = 1ull<<20 /* pip */;
4075     info.func               = __cvmx_error_display;
4076     info.user_info          = (long)
4077         "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
4078         "    stripping in IPD is enable\n";
4079     fail |= cvmx_error_add(&info);
4080
4081     /* CVMX_FPA_INT_SUM */
4082     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4083     info.status_addr        = CVMX_FPA_INT_SUM;
4084     info.status_mask        = 1ull<<0 /* fed0_sbe */;
4085     info.enable_addr        = CVMX_FPA_INT_ENB;
4086     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
4087     info.flags              = 0;
4088     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4089     info.group_index        = 0;
4090     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4091     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4092     info.parent.status_mask = 1ull<<5 /* fpa */;
4093     info.func               = __cvmx_error_display;
4094     info.user_info          = (long)
4095         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
4096     fail |= cvmx_error_add(&info);
4097
4098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4099     info.status_addr        = CVMX_FPA_INT_SUM;
4100     info.status_mask        = 1ull<<1 /* fed0_dbe */;
4101     info.enable_addr        = CVMX_FPA_INT_ENB;
4102     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
4103     info.flags              = 0;
4104     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4105     info.group_index        = 0;
4106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4107     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4108     info.parent.status_mask = 1ull<<5 /* fpa */;
4109     info.func               = __cvmx_error_display;
4110     info.user_info          = (long)
4111         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
4112     fail |= cvmx_error_add(&info);
4113
4114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4115     info.status_addr        = CVMX_FPA_INT_SUM;
4116     info.status_mask        = 1ull<<2 /* fed1_sbe */;
4117     info.enable_addr        = CVMX_FPA_INT_ENB;
4118     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
4119     info.flags              = 0;
4120     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4121     info.group_index        = 0;
4122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4123     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4124     info.parent.status_mask = 1ull<<5 /* fpa */;
4125     info.func               = __cvmx_error_display;
4126     info.user_info          = (long)
4127         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
4128     fail |= cvmx_error_add(&info);
4129
4130     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4131     info.status_addr        = CVMX_FPA_INT_SUM;
4132     info.status_mask        = 1ull<<3 /* fed1_dbe */;
4133     info.enable_addr        = CVMX_FPA_INT_ENB;
4134     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
4135     info.flags              = 0;
4136     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4137     info.group_index        = 0;
4138     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4139     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4140     info.parent.status_mask = 1ull<<5 /* fpa */;
4141     info.func               = __cvmx_error_display;
4142     info.user_info          = (long)
4143         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
4144     fail |= cvmx_error_add(&info);
4145
4146     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4147     info.status_addr        = CVMX_FPA_INT_SUM;
4148     info.status_mask        = 1ull<<4 /* q0_und */;
4149     info.enable_addr        = CVMX_FPA_INT_ENB;
4150     info.enable_mask        = 1ull<<4 /* q0_und */;
4151     info.flags              = 0;
4152     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4153     info.group_index        = 0;
4154     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4155     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4156     info.parent.status_mask = 1ull<<5 /* fpa */;
4157     info.func               = __cvmx_error_display;
4158     info.user_info          = (long)
4159         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
4160         "    negative.\n";
4161     fail |= cvmx_error_add(&info);
4162
4163     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4164     info.status_addr        = CVMX_FPA_INT_SUM;
4165     info.status_mask        = 1ull<<5 /* q0_coff */;
4166     info.enable_addr        = CVMX_FPA_INT_ENB;
4167     info.enable_mask        = 1ull<<5 /* q0_coff */;
4168     info.flags              = 0;
4169     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4170     info.group_index        = 0;
4171     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4172     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4173     info.parent.status_mask = 1ull<<5 /* fpa */;
4174     info.func               = __cvmx_error_display;
4175     info.user_info          = (long)
4176         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
4177         "    the count available is greater than pointers\n"
4178         "    present in the FPA.\n";
4179     fail |= cvmx_error_add(&info);
4180
4181     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4182     info.status_addr        = CVMX_FPA_INT_SUM;
4183     info.status_mask        = 1ull<<6 /* q0_perr */;
4184     info.enable_addr        = CVMX_FPA_INT_ENB;
4185     info.enable_mask        = 1ull<<6 /* q0_perr */;
4186     info.flags              = 0;
4187     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4188     info.group_index        = 0;
4189     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4190     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4191     info.parent.status_mask = 1ull<<5 /* fpa */;
4192     info.func               = __cvmx_error_display;
4193     info.user_info          = (long)
4194         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
4195         "    the L2C does not have the FPA owner ship bit set.\n";
4196     fail |= cvmx_error_add(&info);
4197
4198     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4199     info.status_addr        = CVMX_FPA_INT_SUM;
4200     info.status_mask        = 1ull<<7 /* q1_und */;
4201     info.enable_addr        = CVMX_FPA_INT_ENB;
4202     info.enable_mask        = 1ull<<7 /* q1_und */;
4203     info.flags              = 0;
4204     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4205     info.group_index        = 0;
4206     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4207     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4208     info.parent.status_mask = 1ull<<5 /* fpa */;
4209     info.func               = __cvmx_error_display;
4210     info.user_info          = (long)
4211         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
4212         "    negative.\n";
4213     fail |= cvmx_error_add(&info);
4214
4215     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4216     info.status_addr        = CVMX_FPA_INT_SUM;
4217     info.status_mask        = 1ull<<8 /* q1_coff */;
4218     info.enable_addr        = CVMX_FPA_INT_ENB;
4219     info.enable_mask        = 1ull<<8 /* q1_coff */;
4220     info.flags              = 0;
4221     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4222     info.group_index        = 0;
4223     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4224     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4225     info.parent.status_mask = 1ull<<5 /* fpa */;
4226     info.func               = __cvmx_error_display;
4227     info.user_info          = (long)
4228         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
4229         "    the count available is greater than pointers\n"
4230         "    present in the FPA.\n";
4231     fail |= cvmx_error_add(&info);
4232
4233     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4234     info.status_addr        = CVMX_FPA_INT_SUM;
4235     info.status_mask        = 1ull<<9 /* q1_perr */;
4236     info.enable_addr        = CVMX_FPA_INT_ENB;
4237     info.enable_mask        = 1ull<<9 /* q1_perr */;
4238     info.flags              = 0;
4239     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4240     info.group_index        = 0;
4241     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4242     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4243     info.parent.status_mask = 1ull<<5 /* fpa */;
4244     info.func               = __cvmx_error_display;
4245     info.user_info          = (long)
4246         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
4247         "    the L2C does not have the FPA owner ship bit set.\n";
4248     fail |= cvmx_error_add(&info);
4249
4250     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4251     info.status_addr        = CVMX_FPA_INT_SUM;
4252     info.status_mask        = 1ull<<10 /* q2_und */;
4253     info.enable_addr        = CVMX_FPA_INT_ENB;
4254     info.enable_mask        = 1ull<<10 /* q2_und */;
4255     info.flags              = 0;
4256     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4257     info.group_index        = 0;
4258     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4259     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4260     info.parent.status_mask = 1ull<<5 /* fpa */;
4261     info.func               = __cvmx_error_display;
4262     info.user_info          = (long)
4263         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
4264         "    negative.\n";
4265     fail |= cvmx_error_add(&info);
4266
4267     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4268     info.status_addr        = CVMX_FPA_INT_SUM;
4269     info.status_mask        = 1ull<<11 /* q2_coff */;
4270     info.enable_addr        = CVMX_FPA_INT_ENB;
4271     info.enable_mask        = 1ull<<11 /* q2_coff */;
4272     info.flags              = 0;
4273     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4274     info.group_index        = 0;
4275     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4276     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4277     info.parent.status_mask = 1ull<<5 /* fpa */;
4278     info.func               = __cvmx_error_display;
4279     info.user_info          = (long)
4280         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
4281         "    the count available is greater than than pointers\n"
4282         "    present in the FPA.\n";
4283     fail |= cvmx_error_add(&info);
4284
4285     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4286     info.status_addr        = CVMX_FPA_INT_SUM;
4287     info.status_mask        = 1ull<<12 /* q2_perr */;
4288     info.enable_addr        = CVMX_FPA_INT_ENB;
4289     info.enable_mask        = 1ull<<12 /* q2_perr */;
4290     info.flags              = 0;
4291     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4292     info.group_index        = 0;
4293     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4294     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4295     info.parent.status_mask = 1ull<<5 /* fpa */;
4296     info.func               = __cvmx_error_display;
4297     info.user_info          = (long)
4298         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
4299         "    the L2C does not have the FPA owner ship bit set.\n";
4300     fail |= cvmx_error_add(&info);
4301
4302     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4303     info.status_addr        = CVMX_FPA_INT_SUM;
4304     info.status_mask        = 1ull<<13 /* q3_und */;
4305     info.enable_addr        = CVMX_FPA_INT_ENB;
4306     info.enable_mask        = 1ull<<13 /* q3_und */;
4307     info.flags              = 0;
4308     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4309     info.group_index        = 0;
4310     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4311     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4312     info.parent.status_mask = 1ull<<5 /* fpa */;
4313     info.func               = __cvmx_error_display;
4314     info.user_info          = (long)
4315         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
4316         "    negative.\n";
4317     fail |= cvmx_error_add(&info);
4318
4319     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4320     info.status_addr        = CVMX_FPA_INT_SUM;
4321     info.status_mask        = 1ull<<14 /* q3_coff */;
4322     info.enable_addr        = CVMX_FPA_INT_ENB;
4323     info.enable_mask        = 1ull<<14 /* q3_coff */;
4324     info.flags              = 0;
4325     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4326     info.group_index        = 0;
4327     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4328     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4329     info.parent.status_mask = 1ull<<5 /* fpa */;
4330     info.func               = __cvmx_error_display;
4331     info.user_info          = (long)
4332         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
4333         "    the count available is greater than than pointers\n"
4334         "    present in the FPA.\n";
4335     fail |= cvmx_error_add(&info);
4336
4337     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4338     info.status_addr        = CVMX_FPA_INT_SUM;
4339     info.status_mask        = 1ull<<15 /* q3_perr */;
4340     info.enable_addr        = CVMX_FPA_INT_ENB;
4341     info.enable_mask        = 1ull<<15 /* q3_perr */;
4342     info.flags              = 0;
4343     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4344     info.group_index        = 0;
4345     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4346     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4347     info.parent.status_mask = 1ull<<5 /* fpa */;
4348     info.func               = __cvmx_error_display;
4349     info.user_info          = (long)
4350         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
4351         "    the L2C does not have the FPA owner ship bit set.\n";
4352     fail |= cvmx_error_add(&info);
4353
4354     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4355     info.status_addr        = CVMX_FPA_INT_SUM;
4356     info.status_mask        = 1ull<<16 /* q4_und */;
4357     info.enable_addr        = CVMX_FPA_INT_ENB;
4358     info.enable_mask        = 1ull<<16 /* q4_und */;
4359     info.flags              = 0;
4360     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4361     info.group_index        = 0;
4362     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4363     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4364     info.parent.status_mask = 1ull<<5 /* fpa */;
4365     info.func               = __cvmx_error_display;
4366     info.user_info          = (long)
4367         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
4368         "    negative.\n";
4369     fail |= cvmx_error_add(&info);
4370
4371     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4372     info.status_addr        = CVMX_FPA_INT_SUM;
4373     info.status_mask        = 1ull<<17 /* q4_coff */;
4374     info.enable_addr        = CVMX_FPA_INT_ENB;
4375     info.enable_mask        = 1ull<<17 /* q4_coff */;
4376     info.flags              = 0;
4377     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4378     info.group_index        = 0;
4379     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4380     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4381     info.parent.status_mask = 1ull<<5 /* fpa */;
4382     info.func               = __cvmx_error_display;
4383     info.user_info          = (long)
4384         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
4385         "    the count available is greater than than pointers\n"
4386         "    present in the FPA.\n";
4387     fail |= cvmx_error_add(&info);
4388
4389     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4390     info.status_addr        = CVMX_FPA_INT_SUM;
4391     info.status_mask        = 1ull<<18 /* q4_perr */;
4392     info.enable_addr        = CVMX_FPA_INT_ENB;
4393     info.enable_mask        = 1ull<<18 /* q4_perr */;
4394     info.flags              = 0;
4395     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4396     info.group_index        = 0;
4397     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4398     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4399     info.parent.status_mask = 1ull<<5 /* fpa */;
4400     info.func               = __cvmx_error_display;
4401     info.user_info          = (long)
4402         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
4403         "    the L2C does not have the FPA owner ship bit set.\n";
4404     fail |= cvmx_error_add(&info);
4405
4406     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4407     info.status_addr        = CVMX_FPA_INT_SUM;
4408     info.status_mask        = 1ull<<19 /* q5_und */;
4409     info.enable_addr        = CVMX_FPA_INT_ENB;
4410     info.enable_mask        = 1ull<<19 /* q5_und */;
4411     info.flags              = 0;
4412     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4413     info.group_index        = 0;
4414     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4415     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4416     info.parent.status_mask = 1ull<<5 /* fpa */;
4417     info.func               = __cvmx_error_display;
4418     info.user_info          = (long)
4419         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
4420         "    negative.\n";
4421     fail |= cvmx_error_add(&info);
4422
4423     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4424     info.status_addr        = CVMX_FPA_INT_SUM;
4425     info.status_mask        = 1ull<<20 /* q5_coff */;
4426     info.enable_addr        = CVMX_FPA_INT_ENB;
4427     info.enable_mask        = 1ull<<20 /* q5_coff */;
4428     info.flags              = 0;
4429     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4430     info.group_index        = 0;
4431     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4432     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4433     info.parent.status_mask = 1ull<<5 /* fpa */;
4434     info.func               = __cvmx_error_display;
4435     info.user_info          = (long)
4436         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
4437         "    the count available is greater than than pointers\n"
4438         "    present in the FPA.\n";
4439     fail |= cvmx_error_add(&info);
4440
4441     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4442     info.status_addr        = CVMX_FPA_INT_SUM;
4443     info.status_mask        = 1ull<<21 /* q5_perr */;
4444     info.enable_addr        = CVMX_FPA_INT_ENB;
4445     info.enable_mask        = 1ull<<21 /* q5_perr */;
4446     info.flags              = 0;
4447     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4448     info.group_index        = 0;
4449     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4450     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4451     info.parent.status_mask = 1ull<<5 /* fpa */;
4452     info.func               = __cvmx_error_display;
4453     info.user_info          = (long)
4454         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
4455         "    the L2C does not have the FPA owner ship bit set.\n";
4456     fail |= cvmx_error_add(&info);
4457
4458     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4459     info.status_addr        = CVMX_FPA_INT_SUM;
4460     info.status_mask        = 1ull<<22 /* q6_und */;
4461     info.enable_addr        = CVMX_FPA_INT_ENB;
4462     info.enable_mask        = 1ull<<22 /* q6_und */;
4463     info.flags              = 0;
4464     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4465     info.group_index        = 0;
4466     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4467     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4468     info.parent.status_mask = 1ull<<5 /* fpa */;
4469     info.func               = __cvmx_error_display;
4470     info.user_info          = (long)
4471         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
4472         "    negative.\n";
4473     fail |= cvmx_error_add(&info);
4474
4475     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4476     info.status_addr        = CVMX_FPA_INT_SUM;
4477     info.status_mask        = 1ull<<23 /* q6_coff */;
4478     info.enable_addr        = CVMX_FPA_INT_ENB;
4479     info.enable_mask        = 1ull<<23 /* q6_coff */;
4480     info.flags              = 0;
4481     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4482     info.group_index        = 0;
4483     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4484     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4485     info.parent.status_mask = 1ull<<5 /* fpa */;
4486     info.func               = __cvmx_error_display;
4487     info.user_info          = (long)
4488         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
4489         "    the count available is greater than than pointers\n"
4490         "    present in the FPA.\n";
4491     fail |= cvmx_error_add(&info);
4492
4493     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4494     info.status_addr        = CVMX_FPA_INT_SUM;
4495     info.status_mask        = 1ull<<24 /* q6_perr */;
4496     info.enable_addr        = CVMX_FPA_INT_ENB;
4497     info.enable_mask        = 1ull<<24 /* q6_perr */;
4498     info.flags              = 0;
4499     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4500     info.group_index        = 0;
4501     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4502     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4503     info.parent.status_mask = 1ull<<5 /* fpa */;
4504     info.func               = __cvmx_error_display;
4505     info.user_info          = (long)
4506         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
4507         "    the L2C does not have the FPA owner ship bit set.\n";
4508     fail |= cvmx_error_add(&info);
4509
4510     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4511     info.status_addr        = CVMX_FPA_INT_SUM;
4512     info.status_mask        = 1ull<<25 /* q7_und */;
4513     info.enable_addr        = CVMX_FPA_INT_ENB;
4514     info.enable_mask        = 1ull<<25 /* q7_und */;
4515     info.flags              = 0;
4516     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4517     info.group_index        = 0;
4518     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4519     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4520     info.parent.status_mask = 1ull<<5 /* fpa */;
4521     info.func               = __cvmx_error_display;
4522     info.user_info          = (long)
4523         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
4524         "    negative.\n";
4525     fail |= cvmx_error_add(&info);
4526
4527     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4528     info.status_addr        = CVMX_FPA_INT_SUM;
4529     info.status_mask        = 1ull<<26 /* q7_coff */;
4530     info.enable_addr        = CVMX_FPA_INT_ENB;
4531     info.enable_mask        = 1ull<<26 /* q7_coff */;
4532     info.flags              = 0;
4533     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4534     info.group_index        = 0;
4535     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4536     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4537     info.parent.status_mask = 1ull<<5 /* fpa */;
4538     info.func               = __cvmx_error_display;
4539     info.user_info          = (long)
4540         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
4541         "    the count available is greater than than pointers\n"
4542         "    present in the FPA.\n";
4543     fail |= cvmx_error_add(&info);
4544
4545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4546     info.status_addr        = CVMX_FPA_INT_SUM;
4547     info.status_mask        = 1ull<<27 /* q7_perr */;
4548     info.enable_addr        = CVMX_FPA_INT_ENB;
4549     info.enable_mask        = 1ull<<27 /* q7_perr */;
4550     info.flags              = 0;
4551     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4552     info.group_index        = 0;
4553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4554     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4555     info.parent.status_mask = 1ull<<5 /* fpa */;
4556     info.func               = __cvmx_error_display;
4557     info.user_info          = (long)
4558         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
4559         "    the L2C does not have the FPA owner ship bit set.\n";
4560     fail |= cvmx_error_add(&info);
4561
4562     /* CVMX_LMCX_MEM_CFG0(0) */
4563     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4564     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
4565     info.status_mask        = 0xfull<<21 /* sec_err */;
4566     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
4567     info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
4568     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4569     info.group              = CVMX_ERROR_GROUP_LMC;
4570     info.group_index        = 0;
4571     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4572     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4573     info.parent.status_mask = 1ull<<17 /* lmc */;
4574     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
4575     info.user_info          = (long)
4576         "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4577         "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
4578         "    [21] corresponds to DQ[63:0], Phase0\n"
4579         "    [22] corresponds to DQ[127:64], Phase0\n"
4580         "    [23] corresponds to DQ[63:0], Phase1\n"
4581         "    [24] corresponds to DQ[127:64], Phase1\n"
4582         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4583         "    [21] corresponds to DQ[63:0], Phase0, cycle0\n"
4584         "    [22] corresponds to DQ[63:0], Phase0, cycle1\n"
4585         "    [23] corresponds to DQ[63:0], Phase1, cycle0\n"
4586         "    [24] corresponds to DQ[63:0], Phase1, cycle1\n"
4587         "    Write of 1 will clear the corresponding error bit\n";
4588     fail |= cvmx_error_add(&info);
4589
4590     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4591     info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
4592     info.status_mask        = 0xfull<<25 /* ded_err */;
4593     info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
4594     info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
4595     info.flags              = 0;
4596     info.group              = CVMX_ERROR_GROUP_LMC;
4597     info.group_index        = 0;
4598     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4599     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4600     info.parent.status_mask = 1ull<<17 /* lmc */;
4601     info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
4602     info.user_info          = (long)
4603         "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4604         "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
4605         "    [25] corresponds to DQ[63:0], Phase0\n"
4606         "    [26] corresponds to DQ[127:64], Phase0\n"
4607         "    [27] corresponds to DQ[63:0], Phase1\n"
4608         "    [28] corresponds to DQ[127:64], Phase1\n"
4609         "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4610         "    [25] corresponds to DQ[63:0], Phase0, cycle0\n"
4611         "    [26] corresponds to DQ[63:0], Phase0, cycle1\n"
4612         "    [27] corresponds to DQ[63:0], Phase1, cycle0\n"
4613         "    [28] corresponds to DQ[63:0], Phase1, cycle1\n"
4614         "    Write of 1 will clear the corresponding error bit\n";
4615     fail |= cvmx_error_add(&info);
4616
4617     /* CVMX_DFA_ERR */
4618     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4619     info.status_addr        = CVMX_DFA_ERR;
4620     info.status_mask        = 1ull<<1 /* cp2sbe */;
4621     info.enable_addr        = 0;
4622     info.enable_mask        = 0;
4623     info.flags              = 0;
4624     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4625     info.group_index        = 0;
4626     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4627     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4628     info.parent.status_mask = 1ull<<6 /* dfa */;
4629     info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
4630     info.user_info          = (long)
4631         "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
4632         "    When set, a single bit error had been detected and\n"
4633         "    corrected for a PP-generated QW Mode read\n"
4634         "    transaction.\n"
4635         "    If the CP2DBE=0, then the CP2SYN contains the\n"
4636         "    failing syndrome (used during correction).\n"
4637         "    Refer to CP2ECCENA.\n"
4638         "    If the CP2SBINA had previously been enabled(set),\n"
4639         "    an interrupt will be posted. Software can clear\n"
4640         "    the interrupt by writing a 1 to this register bit.\n"
4641         "    See also: DFA_MEMFADR CSR which contains more data\n"
4642         "    about the memory address/control to help isolate\n"
4643         "    the failure.\n"
4644         "    NOTE: PP-generated LW Mode Read transactions\n"
4645         "    do not participate in ECC check/correct).\n";
4646     fail |= cvmx_error_add(&info);
4647
4648     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4649     info.status_addr        = CVMX_DFA_ERR;
4650     info.status_mask        = 1ull<<2 /* cp2dbe */;
4651     info.enable_addr        = 0;
4652     info.enable_mask        = 0;
4653     info.flags              = 0;
4654     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4655     info.group_index        = 0;
4656     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4657     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4658     info.parent.status_mask = 1ull<<6 /* dfa */;
4659     info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
4660     info.user_info          = (long)
4661         "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
4662         "    When set, a double bit error had been detected\n"
4663         "    for a PP-generated QW Mode read transaction.\n"
4664         "    The CP2SYN contains the failing syndrome.\n"
4665         "     NOTE: PP-generated LW Mode Read transactions\n"
4666         "    do not participate in ECC check/correct).\n"
4667         "    Refer to CP2ECCENA.\n"
4668         "    If the CP2DBINA had previously been enabled(set),\n"
4669         "    an interrupt will be posted. Software can clear\n"
4670         "    the interrupt by writing a 1 to this register bit.\n"
4671         "    See also: DFA_MEMFADR CSR which contains more data\n"
4672         "    about the memory address/control to help isolate\n"
4673         "    the failure.\n";
4674     fail |= cvmx_error_add(&info);
4675
4676     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4677     info.status_addr        = CVMX_DFA_ERR;
4678     info.status_mask        = 1ull<<14 /* dtesbe */;
4679     info.enable_addr        = 0;
4680     info.enable_mask        = 0;
4681     info.flags              = 0;
4682     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4683     info.group_index        = 0;
4684     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4685     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4686     info.parent.status_mask = 1ull<<6 /* dfa */;
4687     info.func               = __cvmx_error_handle_dfa_err_dtesbe;
4688     info.user_info          = (long)
4689         "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
4690         "    When set, a single bit error had been detected and\n"
4691         "    corrected for a DTE-generated 36b SIMPLE Mode read\n"
4692         "    transaction.\n"
4693         "    If the DTEDBE=0, then the DTESYN contains the\n"
4694         "    failing syndrome (used during correction).\n"
4695         "    NOTE: DTE-generated 18b SIMPLE Mode Read\n"
4696         "    transactions do not participate in ECC check/correct).\n"
4697         "    If the DTESBINA had previously been enabled(set),\n"
4698         "    an interrupt will be posted. Software can clear\n"
4699         "    the interrupt by writing a 1 to this register bit.\n"
4700         "    See also: DFA_MEMFADR CSR which contains more data\n"
4701         "    about the memory address/control to help isolate\n"
4702         "    the failure.\n";
4703     fail |= cvmx_error_add(&info);
4704
4705     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4706     info.status_addr        = CVMX_DFA_ERR;
4707     info.status_mask        = 1ull<<15 /* dtedbe */;
4708     info.enable_addr        = 0;
4709     info.enable_mask        = 0;
4710     info.flags              = 0;
4711     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4712     info.group_index        = 0;
4713     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4714     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4715     info.parent.status_mask = 1ull<<6 /* dfa */;
4716     info.func               = __cvmx_error_handle_dfa_err_dtedbe;
4717     info.user_info          = (long)
4718         "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
4719         "    When set, a double bit error had been detected\n"
4720         "    for a DTE-generated 36b SIMPLE Mode read transaction.\n"
4721         "    The DTESYN contains the failing syndrome.\n"
4722         "    If the DTEDBINA had previously been enabled(set),\n"
4723         "    an interrupt will be posted. Software can clear\n"
4724         "    the interrupt by writing a 1 to this register bit.\n"
4725         "    See also: DFA_MEMFADR CSR which contains more data\n"
4726         "    about the memory address/control to help isolate\n"
4727         "    the failure.\n"
4728         "    NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
4729         "    do not participate in ECC check/correct).\n";
4730     fail |= cvmx_error_add(&info);
4731
4732     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4733     info.status_addr        = CVMX_DFA_ERR;
4734     info.status_mask        = 1ull<<26 /* dteperr */;
4735     info.enable_addr        = 0;
4736     info.enable_mask        = 0;
4737     info.flags              = 0;
4738     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4739     info.group_index        = 0;
4740     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4741     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4742     info.parent.status_mask = 1ull<<6 /* dfa */;
4743     info.func               = __cvmx_error_handle_dfa_err_dteperr;
4744     info.user_info          = (long)
4745         "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
4746         "    When set, all DTE-generated 18b SIMPLE Mode read\n"
4747         "    transactions which encounter a parity error (across\n"
4748         "    the 17b of data) are reported.\n";
4749     fail |= cvmx_error_add(&info);
4750
4751     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4752     info.status_addr        = CVMX_DFA_ERR;
4753     info.status_mask        = 1ull<<29 /* cp2perr */;
4754     info.enable_addr        = 0;
4755     info.enable_mask        = 0;
4756     info.flags              = 0;
4757     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4758     info.group_index        = 0;
4759     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4760     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4761     info.parent.status_mask = 1ull<<6 /* dfa */;
4762     info.func               = __cvmx_error_handle_dfa_err_cp2perr;
4763     info.user_info          = (long)
4764         "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
4765         "    When set, a parity error had been detected for a\n"
4766         "    PP-generated LW Mode read transaction.\n"
4767         "    If the CP2PINA had previously been enabled(set),\n"
4768         "    an interrupt will be posted. Software can clear\n"
4769         "    the interrupt by writing a 1 to this register bit.\n"
4770         "    See also: DFA_MEMFADR CSR which contains more data\n"
4771         "    about the memory address/control to help isolate\n"
4772         "    the failure.\n";
4773     fail |= cvmx_error_add(&info);
4774
4775     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4776     info.status_addr        = CVMX_DFA_ERR;
4777     info.status_mask        = 1ull<<31 /* dblovf */;
4778     info.enable_addr        = 0;
4779     info.enable_mask        = 0;
4780     info.flags              = 0;
4781     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4782     info.group_index        = 0;
4783     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4784     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4785     info.parent.status_mask = 1ull<<6 /* dfa */;
4786     info.func               = __cvmx_error_handle_dfa_err_dblovf;
4787     info.user_info          = (long)
4788         "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
4789         "    When set, the 20b accumulated doorbell register\n"
4790         "    had overflowed (SW wrote too many doorbell requests).\n"
4791         "    If the DBLINA had previously been enabled(set),\n"
4792         "    an interrupt will be posted. Software can clear\n"
4793         "    the interrupt by writing a 1 to this register bit.\n"
4794         "    NOTE: Detection of a Doorbell Register overflow\n"
4795         "    is a catastrophic error which may leave the DFA\n"
4796         "    HW in an unrecoverable state.\n";
4797     fail |= cvmx_error_add(&info);
4798
4799     /* CVMX_IOB_INT_SUM */
4800     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4801     info.status_addr        = CVMX_IOB_INT_SUM;
4802     info.status_mask        = 1ull<<0 /* np_sop */;
4803     info.enable_addr        = CVMX_IOB_INT_ENB;
4804     info.enable_mask        = 1ull<<0 /* np_sop */;
4805     info.flags              = 0;
4806     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4807     info.group_index        = 0;
4808     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4809     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4810     info.parent.status_mask = 1ull<<30 /* iob */;
4811     info.func               = __cvmx_error_display;
4812     info.user_info          = (long)
4813         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
4814         "    port for a non-passthrough packet.\n"
4815         "    The first detected error associated with bits [5:0]\n"
4816         "    of this register will only be set here. A new bit\n"
4817         "    can be set when the previous reported bit is cleared.\n";
4818     fail |= cvmx_error_add(&info);
4819
4820     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4821     info.status_addr        = CVMX_IOB_INT_SUM;
4822     info.status_mask        = 1ull<<1 /* np_eop */;
4823     info.enable_addr        = CVMX_IOB_INT_ENB;
4824     info.enable_mask        = 1ull<<1 /* np_eop */;
4825     info.flags              = 0;
4826     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4827     info.group_index        = 0;
4828     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4829     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4830     info.parent.status_mask = 1ull<<30 /* iob */;
4831     info.func               = __cvmx_error_display;
4832     info.user_info          = (long)
4833         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
4834         "    port for a non-passthrough packet.\n"
4835         "    The first detected error associated with bits [5:0]\n"
4836         "    of this register will only be set here. A new bit\n"
4837         "    can be set when the previous reported bit is cleared.\n";
4838     fail |= cvmx_error_add(&info);
4839
4840     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4841     info.status_addr        = CVMX_IOB_INT_SUM;
4842     info.status_mask        = 1ull<<2 /* p_sop */;
4843     info.enable_addr        = CVMX_IOB_INT_ENB;
4844     info.enable_mask        = 1ull<<2 /* p_sop */;
4845     info.flags              = 0;
4846     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4847     info.group_index        = 0;
4848     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4849     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4850     info.parent.status_mask = 1ull<<30 /* iob */;
4851     info.func               = __cvmx_error_display;
4852     info.user_info          = (long)
4853         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
4854         "    port for a passthrough packet.\n"
4855         "    The first detected error associated with bits [5:0]\n"
4856         "    of this register will only be set here. A new bit\n"
4857         "    can be set when the previous reported bit is cleared.\n";
4858     fail |= cvmx_error_add(&info);
4859
4860     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4861     info.status_addr        = CVMX_IOB_INT_SUM;
4862     info.status_mask        = 1ull<<3 /* p_eop */;
4863     info.enable_addr        = CVMX_IOB_INT_ENB;
4864     info.enable_mask        = 1ull<<3 /* p_eop */;
4865     info.flags              = 0;
4866     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4867     info.group_index        = 0;
4868     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4869     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4870     info.parent.status_mask = 1ull<<30 /* iob */;
4871     info.func               = __cvmx_error_display;
4872     info.user_info          = (long)
4873         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
4874         "    port for a passthrough packet.\n"
4875         "    The first detected error associated with bits [5:0]\n"
4876         "    of this register will only be set here. A new bit\n"
4877         "    can be set when the previous reported bit is cleared.\n";
4878     fail |= cvmx_error_add(&info);
4879
4880     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4881     info.status_addr        = CVMX_IOB_INT_SUM;
4882     info.status_mask        = 1ull<<4 /* np_dat */;
4883     info.enable_addr        = CVMX_IOB_INT_ENB;
4884     info.enable_mask        = 1ull<<4 /* np_dat */;
4885     info.flags              = 0;
4886     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4887     info.group_index        = 0;
4888     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4889     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4890     info.parent.status_mask = 1ull<<30 /* iob */;
4891     info.func               = __cvmx_error_display;
4892     info.user_info          = (long)
4893         "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
4894         "    port for a non-passthrough packet.\n"
4895         "    The first detected error associated with bits [5:0]\n"
4896         "    of this register will only be set here. A new bit\n"
4897         "    can be set when the previous reported bit is cleared.\n";
4898     fail |= cvmx_error_add(&info);
4899
4900     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4901     info.status_addr        = CVMX_IOB_INT_SUM;
4902     info.status_mask        = 1ull<<5 /* p_dat */;
4903     info.enable_addr        = CVMX_IOB_INT_ENB;
4904     info.enable_mask        = 1ull<<5 /* p_dat */;
4905     info.flags              = 0;
4906     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4907     info.group_index        = 0;
4908     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4909     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4910     info.parent.status_mask = 1ull<<30 /* iob */;
4911     info.func               = __cvmx_error_display;
4912     info.user_info          = (long)
4913         "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
4914         "    port for a passthrough packet.\n"
4915         "    The first detected error associated with bits [5:0]\n"
4916         "    of this register will only be set here. A new bit\n"
4917         "    can be set when the previous reported bit is cleared.\n";
4918     fail |= cvmx_error_add(&info);
4919
4920     /* CVMX_ZIP_ERROR */
4921     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4922     info.status_addr        = CVMX_ZIP_ERROR;
4923     info.status_mask        = 1ull<<0 /* doorbell */;
4924     info.enable_addr        = CVMX_ZIP_INT_MASK;
4925     info.enable_mask        = 1ull<<0 /* doorbell */;
4926     info.flags              = 0;
4927     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4928     info.group_index        = 0;
4929     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4930     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
4931     info.parent.status_mask = 1ull<<7 /* zip */;
4932     info.func               = __cvmx_error_display;
4933     info.user_info          = (long)
4934         "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4935     fail |= cvmx_error_add(&info);
4936
4937     return fail;
4938 }
4939