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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_L2T_TYPEDEFS_H__
53 #define __CVMX_L2T_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
57 static inline uint64_t CVMX_L2T_ERR_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
60 cvmx_warn("CVMX_L2T_ERR not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180080000008ull);
64 #define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
70 * L2T_ERR = L2 Tag Errors
72 * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable
79 #if __BYTE_ORDER == __BIG_ENDIAN
80 uint64_t reserved_29_63 : 35;
81 uint64_t fadru : 1; /**< Failing L2 Tag Upper Address Bit (Index[10])
82 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
83 the FADRU contains the upper(MSB bit) cacheline index
84 into the L2 Tag Store. */
85 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
86 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
87 could not find an available/unlocked set (for
89 Most likely, this is a result of SW mixing SET
90 PARTITIONING with ADDRESS LOCKING. If SW allows
91 another PP to LOCKDOWN all SETs available to PP#n,
92 then a Rd/Wr Miss from PP#n will be unable
93 to determine a 'valid' replacement set (since LOCKED
94 addresses should NEVER be replaced).
95 If such an event occurs, the HW will select the smallest
96 available SET(specified by UMSK'x)' as the replacement
97 set, and the address is unlocked. */
98 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
99 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
100 the INDEX (which is ignored by HW - but reported to SW).
101 The LDD(L1 load-miss) for the LOCK operation is completed
102 successfully, however the address is NOT locked.
103 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
104 into account. For example, if diagnostic PPx has
105 UMSKx defined to only use SETs [1:0], and SET1 had
106 been previously LOCKED, then an attempt to LOCK the
107 last available SET0 would result in a LCKERR. (This
108 is to ensure that at least 1 SET at each INDEX is
109 not LOCKED for general use by other PPs). */
110 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
111 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
112 (FSYN != 0), the FSET specifies the failing hit-set.
113 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
114 is specified by the L2C_DBG[SET]. */
115 uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index)
116 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
117 the FADR contains the lower 10bit cacheline index
118 into the L2 Tag Store. */
119 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
120 the contents of this register contain the 6-bit
121 syndrome for the hit set only.
122 If (FSYN = 0), the SBE or DBE reported was for one of
123 the "non-hit" sets at the failing index(FADR).
124 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
125 is specified by the L2C_DBG[SET].
126 If (FSYN != 0), the SBE or DBE reported was for the
127 hit set at the failing index(FADR) and failing
129 SW NOTE: To determine which "non-hit" set was in error,
130 SW can use the L2C_DBG[L2T] debug feature to explicitly
131 read the other sets at the failing index(FADR). When
132 (FSYN !=0), then the FSET contains the failing hit-set.
133 NOTE: A DED Error will always overwrite a SEC Error
134 SYNDROME and FADR). */
135 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
136 During every L2 Tag Probe, all 8 sets Tag's (at a
137 given index) are checked for double bit errors(DBEs).
138 This bit is set if ANY of the 8 sets contains a DBE.
139 DBEs also generated an interrupt(if enabled). */
140 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
141 During every L2 Tag Probe, all 8 sets Tag's (at a
142 given index) are checked for single bit errors(SBEs).
143 This bit is set if ANY of the 8 sets contains an SBE.
144 SBEs are auto corrected in HW and generate an
145 interrupt(if enabled). */
146 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
147 Enable bit. When set, allows interrupts to be
148 reported on double bit (uncorrectable) errors from
149 the L2 Tag Arrays. */
150 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
151 Enable bit. When set, allows interrupts to be
152 reported on single bit (correctable) errors from
153 the L2 Tag Arrays. */
154 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
155 When set, enables 6-bit SEC/DED codeword for 19-bit
156 L2 Tag Arrays [V,D,L,TAG[33:18]] */
158 uint64_t ecc_ena : 1;
159 uint64_t sec_intena : 1;
160 uint64_t ded_intena : 1;
161 uint64_t sec_err : 1;
162 uint64_t ded_err : 1;
167 uint64_t lck_intena : 1;
168 uint64_t lckerr2 : 1;
169 uint64_t lck_intena2 : 1;
171 uint64_t reserved_29_63 : 35;
174 struct cvmx_l2t_err_cn30xx
176 #if __BYTE_ORDER == __BIG_ENDIAN
177 uint64_t reserved_28_63 : 36;
178 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
179 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
180 could not find an available/unlocked set (for
182 Most likely, this is a result of SW mixing SET
183 PARTITIONING with ADDRESS LOCKING. If SW allows
184 another PP to LOCKDOWN all SETs available to PP#n,
185 then a Rd/Wr Miss from PP#n will be unable
186 to determine a 'valid' replacement set (since LOCKED
187 addresses should NEVER be replaced).
188 If such an event occurs, the HW will select the smallest
189 available SET(specified by UMSK'x)' as the replacement
190 set, and the address is unlocked. */
191 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
192 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
193 the INDEX (which is ignored by HW - but reported to SW).
194 The LDD(L1 load-miss) for the LOCK operation is
195 completed successfully, however the address is NOT
197 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
198 into account. For example, if diagnostic PPx has
199 UMSKx defined to only use SETs [1:0], and SET1 had
200 been previously LOCKED, then an attempt to LOCK the
201 last available SET0 would result in a LCKERR. (This
202 is to ensure that at least 1 SET at each INDEX is
203 not LOCKED for general use by other PPs). */
204 uint64_t reserved_23_23 : 1;
205 uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4)
206 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
207 (FSYN != 0), the FSET specifies the failing hit-set.
208 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
209 is specified by the L2C_DBG[SET]. */
210 uint64_t reserved_19_20 : 2;
211 uint64_t fadr : 8; /**< Failing L2 Tag Store Index (8-bit)
212 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
213 the FADR contains the 8bit cacheline index into the
215 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
216 the contents of this register contain the 6-bit
217 syndrome for the hit set only.
218 If (FSYN = 0), the SBE or DBE reported was for one of
219 the "non-hit" sets at the failing index(FADR).
220 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
221 is specified by the L2C_DBG[SET].
222 If (FSYN != 0), the SBE or DBE reported was for the
223 hit set at the failing index(FADR) and failing
225 SW NOTE: To determine which "non-hit" set was in error,
226 SW can use the L2C_DBG[L2T] debug feature to explicitly
227 read the other sets at the failing index(FADR). When
228 (FSYN !=0), then the FSET contains the failing hit-set.
229 NOTE: A DED Error will always overwrite a SEC Error
230 SYNDROME and FADR). */
231 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
232 During every L2 Tag Probe, all 8 sets Tag's (at a
233 given index) are checked for double bit errors(DBEs).
234 This bit is set if ANY of the 8 sets contains a DBE.
235 DBEs also generated an interrupt(if enabled). */
236 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
237 During every L2 Tag Probe, all 8 sets Tag's (at a
238 given index) are checked for single bit errors(SBEs).
239 This bit is set if ANY of the 8 sets contains an SBE.
240 SBEs are auto corrected in HW and generate an
241 interrupt(if enabled). */
242 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
243 Enable bit. When set, allows interrupts to be
244 reported on double bit (uncorrectable) errors from
245 the L2 Tag Arrays. */
246 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
247 Enable bit. When set, allows interrupts to be
248 reported on single bit (correctable) errors from
249 the L2 Tag Arrays. */
250 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
251 When set, enables 6-bit SEC/DED codeword for 22-bit
252 L2 Tag Arrays [V,D,L,TAG[33:15]] */
254 uint64_t ecc_ena : 1;
255 uint64_t sec_intena : 1;
256 uint64_t ded_intena : 1;
257 uint64_t sec_err : 1;
258 uint64_t ded_err : 1;
261 uint64_t reserved_19_20 : 2;
263 uint64_t reserved_23_23 : 1;
265 uint64_t lck_intena : 1;
266 uint64_t lckerr2 : 1;
267 uint64_t lck_intena2 : 1;
268 uint64_t reserved_28_63 : 36;
271 struct cvmx_l2t_err_cn31xx
273 #if __BYTE_ORDER == __BIG_ENDIAN
274 uint64_t reserved_28_63 : 36;
275 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
276 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
277 could not find an available/unlocked set (for
279 Most likely, this is a result of SW mixing SET
280 PARTITIONING with ADDRESS LOCKING. If SW allows
281 another PP to LOCKDOWN all SETs available to PP#n,
282 then a Rd/Wr Miss from PP#n will be unable
283 to determine a 'valid' replacement set (since LOCKED
284 addresses should NEVER be replaced).
285 If such an event occurs, the HW will select the smallest
286 available SET(specified by UMSK'x)' as the replacement
287 set, and the address is unlocked. */
288 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
289 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
290 the INDEX (which is ignored by HW - but reported to SW).
291 The LDD(L1 load-miss) for the LOCK operation is completed
292 successfully, however the address is NOT locked.
293 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
294 into account. For example, if diagnostic PPx has
295 UMSKx defined to only use SETs [1:0], and SET1 had
296 been previously LOCKED, then an attempt to LOCK the
297 last available SET0 would result in a LCKERR. (This
298 is to ensure that at least 1 SET at each INDEX is
299 not LOCKED for general use by other PPs). */
300 uint64_t reserved_23_23 : 1;
301 uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4)
302 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
303 (FSYN != 0), the FSET specifies the failing hit-set.
304 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
305 is specified by the L2C_DBG[SET]. */
306 uint64_t reserved_20_20 : 1;
307 uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index)
308 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
309 the FADR contains the 9-bit cacheline index into the
311 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
312 the contents of this register contain the 6-bit
313 syndrome for the hit set only.
314 If (FSYN = 0), the SBE or DBE reported was for one of
315 the "non-hit" sets at the failing index(FADR).
316 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
317 is specified by the L2C_DBG[SET].
318 If (FSYN != 0), the SBE or DBE reported was for the
319 hit set at the failing index(FADR) and failing
321 SW NOTE: To determine which "non-hit" set was in error,
322 SW can use the L2C_DBG[L2T] debug feature to explicitly
323 read the other sets at the failing index(FADR). When
324 (FSYN !=0), then the FSET contains the failing hit-set.
325 NOTE: A DED Error will always overwrite a SEC Error
326 SYNDROME and FADR). */
327 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
328 During every L2 Tag Probe, all 8 sets Tag's (at a
329 given index) are checked for double bit errors(DBEs).
330 This bit is set if ANY of the 8 sets contains a DBE.
331 DBEs also generated an interrupt(if enabled). */
332 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
333 During every L2 Tag Probe, all 8 sets Tag's (at a
334 given index) are checked for single bit errors(SBEs).
335 This bit is set if ANY of the 8 sets contains an SBE.
336 SBEs are auto corrected in HW and generate an
337 interrupt(if enabled). */
338 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
339 Enable bit. When set, allows interrupts to be
340 reported on double bit (uncorrectable) errors from
341 the L2 Tag Arrays. */
342 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
343 Enable bit. When set, allows interrupts to be
344 reported on single bit (correctable) errors from
345 the L2 Tag Arrays. */
346 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
347 When set, enables 6-bit SEC/DED codeword for 21-bit
348 L2 Tag Arrays [V,D,L,TAG[33:16]] */
350 uint64_t ecc_ena : 1;
351 uint64_t sec_intena : 1;
352 uint64_t ded_intena : 1;
353 uint64_t sec_err : 1;
354 uint64_t ded_err : 1;
357 uint64_t reserved_20_20 : 1;
359 uint64_t reserved_23_23 : 1;
361 uint64_t lck_intena : 1;
362 uint64_t lckerr2 : 1;
363 uint64_t lck_intena2 : 1;
364 uint64_t reserved_28_63 : 36;
367 struct cvmx_l2t_err_cn38xx
369 #if __BYTE_ORDER == __BIG_ENDIAN
370 uint64_t reserved_28_63 : 36;
371 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
372 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
373 could not find an available/unlocked set (for
375 Most likely, this is a result of SW mixing SET
376 PARTITIONING with ADDRESS LOCKING. If SW allows
377 another PP to LOCKDOWN all SETs available to PP#n,
378 then a Rd/Wr Miss from PP#n will be unable
379 to determine a 'valid' replacement set (since LOCKED
380 addresses should NEVER be replaced).
381 If such an event occurs, the HW will select the smallest
382 available SET(specified by UMSK'x)' as the replacement
383 set, and the address is unlocked. */
384 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
385 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
386 the INDEX (which is ignored by HW - but reported to SW).
387 The LDD(L1 load-miss) for the LOCK operation is completed
388 successfully, however the address is NOT locked.
389 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
390 into account. For example, if diagnostic PPx has
391 UMSKx defined to only use SETs [1:0], and SET1 had
392 been previously LOCKED, then an attempt to LOCK the
393 last available SET0 would result in a LCKERR. (This
394 is to ensure that at least 1 SET at each INDEX is
395 not LOCKED for general use by other PPs). */
396 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
397 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
398 (FSYN != 0), the FSET specifies the failing hit-set.
399 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
400 is specified by the L2C_DBG[SET]. */
401 uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index)
402 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
403 the FADR contains the 10bit cacheline index into the
405 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
406 the contents of this register contain the 6-bit
407 syndrome for the hit set only.
408 If (FSYN = 0), the SBE or DBE reported was for one of
409 the "non-hit" sets at the failing index(FADR).
410 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
411 is specified by the L2C_DBG[SET].
412 If (FSYN != 0), the SBE or DBE reported was for the
413 hit set at the failing index(FADR) and failing
415 SW NOTE: To determine which "non-hit" set was in error,
416 SW can use the L2C_DBG[L2T] debug feature to explicitly
417 read the other sets at the failing index(FADR). When
418 (FSYN !=0), then the FSET contains the failing hit-set.
419 NOTE: A DED Error will always overwrite a SEC Error
420 SYNDROME and FADR). */
421 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
422 During every L2 Tag Probe, all 8 sets Tag's (at a
423 given index) are checked for double bit errors(DBEs).
424 This bit is set if ANY of the 8 sets contains a DBE.
425 DBEs also generated an interrupt(if enabled). */
426 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
427 During every L2 Tag Probe, all 8 sets Tag's (at a
428 given index) are checked for single bit errors(SBEs).
429 This bit is set if ANY of the 8 sets contains an SBE.
430 SBEs are auto corrected in HW and generate an
431 interrupt(if enabled). */
432 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
433 Enable bit. When set, allows interrupts to be
434 reported on double bit (uncorrectable) errors from
435 the L2 Tag Arrays. */
436 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
437 Enable bit. When set, allows interrupts to be
438 reported on single bit (correctable) errors from
439 the L2 Tag Arrays. */
440 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
441 When set, enables 6-bit SEC/DED codeword for 20-bit
442 L2 Tag Arrays [V,D,L,TAG[33:17]] */
444 uint64_t ecc_ena : 1;
445 uint64_t sec_intena : 1;
446 uint64_t ded_intena : 1;
447 uint64_t sec_err : 1;
448 uint64_t ded_err : 1;
453 uint64_t lck_intena : 1;
454 uint64_t lckerr2 : 1;
455 uint64_t lck_intena2 : 1;
456 uint64_t reserved_28_63 : 36;
459 struct cvmx_l2t_err_cn38xx cn38xxp2;
460 struct cvmx_l2t_err_cn50xx
462 #if __BYTE_ORDER == __BIG_ENDIAN
463 uint64_t reserved_28_63 : 36;
464 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
465 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
466 could not find an available/unlocked set (for
468 Most likely, this is a result of SW mixing SET
469 PARTITIONING with ADDRESS LOCKING. If SW allows
470 another PP to LOCKDOWN all SETs available to PP#n,
471 then a Rd/Wr Miss from PP#n will be unable
472 to determine a 'valid' replacement set (since LOCKED
473 addresses should NEVER be replaced).
474 If such an event occurs, the HW will select the smallest
475 available SET(specified by UMSK'x)' as the replacement
476 set, and the address is unlocked. */
477 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
478 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
479 the INDEX (which is ignored by HW - but reported to SW).
480 The LDD(L1 load-miss) for the LOCK operation is completed
481 successfully, however the address is NOT locked.
482 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
483 into account. For example, if diagnostic PPx has
484 UMSKx defined to only use SETs [1:0], and SET1 had
485 been previously LOCKED, then an attempt to LOCK the
486 last available SET0 would result in a LCKERR. (This
487 is to ensure that at least 1 SET at each INDEX is
488 not LOCKED for general use by other PPs). */
489 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
490 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
491 (FSYN != 0), the FSET specifies the failing hit-set.
492 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
493 is specified by the L2C_DBG[SET]. */
494 uint64_t reserved_18_20 : 3;
495 uint64_t fadr : 7; /**< Failing L2 Tag Address (7-bit Index)
496 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
497 the FADR contains the lower 7bit cacheline index
498 into the L2 Tag Store. */
499 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
500 the contents of this register contain the 6-bit
501 syndrome for the hit set only.
502 If (FSYN = 0), the SBE or DBE reported was for one of
503 the "non-hit" sets at the failing index(FADR).
504 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
505 is specified by the L2C_DBG[SET].
506 If (FSYN != 0), the SBE or DBE reported was for the
507 hit set at the failing index(FADR) and failing
509 SW NOTE: To determine which "non-hit" set was in error,
510 SW can use the L2C_DBG[L2T] debug feature to explicitly
511 read the other sets at the failing index(FADR). When
512 (FSYN !=0), then the FSET contains the failing hit-set.
513 NOTE: A DED Error will always overwrite a SEC Error
514 SYNDROME and FADR). */
515 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
516 During every L2 Tag Probe, all 8 sets Tag's (at a
517 given index) are checked for double bit errors(DBEs).
518 This bit is set if ANY of the 8 sets contains a DBE.
519 DBEs also generated an interrupt(if enabled). */
520 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
521 During every L2 Tag Probe, all 8 sets Tag's (at a
522 given index) are checked for single bit errors(SBEs).
523 This bit is set if ANY of the 8 sets contains an SBE.
524 SBEs are auto corrected in HW and generate an
525 interrupt(if enabled). */
526 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
527 Enable bit. When set, allows interrupts to be
528 reported on double bit (uncorrectable) errors from
529 the L2 Tag Arrays. */
530 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
531 Enable bit. When set, allows interrupts to be
532 reported on single bit (correctable) errors from
533 the L2 Tag Arrays. */
534 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
535 When set, enables 6-bit SEC/DED codeword for 23-bit
536 L2 Tag Arrays [V,D,L,TAG[33:14]] */
538 uint64_t ecc_ena : 1;
539 uint64_t sec_intena : 1;
540 uint64_t ded_intena : 1;
541 uint64_t sec_err : 1;
542 uint64_t ded_err : 1;
545 uint64_t reserved_18_20 : 3;
548 uint64_t lck_intena : 1;
549 uint64_t lckerr2 : 1;
550 uint64_t lck_intena2 : 1;
551 uint64_t reserved_28_63 : 36;
554 struct cvmx_l2t_err_cn52xx
556 #if __BYTE_ORDER == __BIG_ENDIAN
557 uint64_t reserved_28_63 : 36;
558 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
559 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
560 could not find an available/unlocked set (for
562 Most likely, this is a result of SW mixing SET
563 PARTITIONING with ADDRESS LOCKING. If SW allows
564 another PP to LOCKDOWN all SETs available to PP#n,
565 then a Rd/Wr Miss from PP#n will be unable
566 to determine a 'valid' replacement set (since LOCKED
567 addresses should NEVER be replaced).
568 If such an event occurs, the HW will select the smallest
569 available SET(specified by UMSK'x)' as the replacement
570 set, and the address is unlocked. */
571 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
572 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
573 the INDEX (which is ignored by HW - but reported to SW).
574 The LDD(L1 load-miss) for the LOCK operation is completed
575 successfully, however the address is NOT locked.
576 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
577 into account. For example, if diagnostic PPx has
578 UMSKx defined to only use SETs [1:0], and SET1 had
579 been previously LOCKED, then an attempt to LOCK the
580 last available SET0 would result in a LCKERR. (This
581 is to ensure that at least 1 SET at each INDEX is
582 not LOCKED for general use by other PPs). */
583 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
584 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
585 (FSYN != 0), the FSET specifies the failing hit-set.
586 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
587 is specified by the L2C_DBG[SET]. */
588 uint64_t reserved_20_20 : 1;
589 uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index)
590 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
591 the FADR contains the lower 9bit cacheline index
592 into the L2 Tag Store. */
593 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
594 the contents of this register contain the 6-bit
595 syndrome for the hit set only.
596 If (FSYN = 0), the SBE or DBE reported was for one of
597 the "non-hit" sets at the failing index(FADR).
598 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
599 is specified by the L2C_DBG[SET].
600 If (FSYN != 0), the SBE or DBE reported was for the
601 hit set at the failing index(FADR) and failing
603 SW NOTE: To determine which "non-hit" set was in error,
604 SW can use the L2C_DBG[L2T] debug feature to explicitly
605 read the other sets at the failing index(FADR). When
606 (FSYN !=0), then the FSET contains the failing hit-set.
607 NOTE: A DED Error will always overwrite a SEC Error
608 SYNDROME and FADR). */
609 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
610 During every L2 Tag Probe, all 8 sets Tag's (at a
611 given index) are checked for double bit errors(DBEs).
612 This bit is set if ANY of the 8 sets contains a DBE.
613 DBEs also generated an interrupt(if enabled). */
614 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
615 During every L2 Tag Probe, all 8 sets Tag's (at a
616 given index) are checked for single bit errors(SBEs).
617 This bit is set if ANY of the 8 sets contains an SBE.
618 SBEs are auto corrected in HW and generate an
619 interrupt(if enabled). */
620 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
621 Enable bit. When set, allows interrupts to be
622 reported on double bit (uncorrectable) errors from
623 the L2 Tag Arrays. */
624 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
625 Enable bit. When set, allows interrupts to be
626 reported on single bit (correctable) errors from
627 the L2 Tag Arrays. */
628 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
629 When set, enables 6-bit SEC/DED codeword for 21-bit
630 L2 Tag Arrays [V,D,L,TAG[33:16]] */
632 uint64_t ecc_ena : 1;
633 uint64_t sec_intena : 1;
634 uint64_t ded_intena : 1;
635 uint64_t sec_err : 1;
636 uint64_t ded_err : 1;
639 uint64_t reserved_20_20 : 1;
642 uint64_t lck_intena : 1;
643 uint64_t lckerr2 : 1;
644 uint64_t lck_intena2 : 1;
645 uint64_t reserved_28_63 : 36;
648 struct cvmx_l2t_err_cn52xx cn52xxp1;
649 struct cvmx_l2t_err_s cn56xx;
650 struct cvmx_l2t_err_s cn56xxp1;
651 struct cvmx_l2t_err_s cn58xx;
652 struct cvmx_l2t_err_s cn58xxp1;
654 typedef union cvmx_l2t_err cvmx_l2t_err_t;