1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_LED_TYPEDEFS_H__
53 #define __CVMX_LED_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
57 static inline uint64_t CVMX_LED_BLINK_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
60 cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
64 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
68 static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
71 cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
75 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
79 static inline uint64_t CVMX_LED_CYLON_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
82 cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
86 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
90 static inline uint64_t CVMX_LED_DBG_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
93 cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
97 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_LED_EN CVMX_LED_EN_FUNC()
101 static inline uint64_t CVMX_LED_EN_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
104 cvmx_warn("CVMX_LED_EN not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
108 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
112 static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
115 cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
119 #define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
123 static inline uint64_t CVMX_LED_PRT_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
126 cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
130 #define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
134 static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
137 cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
141 #define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
147 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
148 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
149 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
150 cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
151 return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8;
154 #define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
157 static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
160 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
162 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
163 cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
164 return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8;
167 #define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
169 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
170 static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
173 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
174 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
175 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
176 cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
177 return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8;
180 #define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
182 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
183 static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
186 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
187 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
188 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
189 cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
190 return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16;
193 #define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
195 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
196 static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
199 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
201 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
202 cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
203 return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16;
206 #define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
212 * LED_BLINK = LED Blink Rate (in led_clks)
218 struct cvmx_led_blink_s
220 #if __BYTE_ORDER == __BIG_ENDIAN
221 uint64_t reserved_8_63 : 56;
222 uint64_t rate : 8; /**< LED Blink rate in led_latch clks
226 uint64_t reserved_8_63 : 56;
229 struct cvmx_led_blink_s cn38xx;
230 struct cvmx_led_blink_s cn38xxp2;
231 struct cvmx_led_blink_s cn56xx;
232 struct cvmx_led_blink_s cn56xxp1;
233 struct cvmx_led_blink_s cn58xx;
234 struct cvmx_led_blink_s cn58xxp1;
236 typedef union cvmx_led_blink cvmx_led_blink_t;
241 * LED_CLK_PHASE = LED Clock Phase (in 64 eclks)
246 * Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each
247 * led_clk phase is 64 eclks, or 128ns. The led_clk period is 2*phase,
248 * or 256ns which is 3.9MHz. The default value of 4, yields an led_clk
249 * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
251 union cvmx_led_clk_phase
254 struct cvmx_led_clk_phase_s
256 #if __BYTE_ORDER == __BIG_ENDIAN
257 uint64_t reserved_7_63 : 57;
258 uint64_t phase : 7; /**< Number of 64 eclks in order to create the led_clk */
261 uint64_t reserved_7_63 : 57;
264 struct cvmx_led_clk_phase_s cn38xx;
265 struct cvmx_led_clk_phase_s cn38xxp2;
266 struct cvmx_led_clk_phase_s cn56xx;
267 struct cvmx_led_clk_phase_s cn56xxp1;
268 struct cvmx_led_clk_phase_s cn58xx;
269 struct cvmx_led_clk_phase_s cn58xxp1;
271 typedef union cvmx_led_clk_phase cvmx_led_clk_phase_t;
276 * LED_CYLON = LED CYLON Effect (should remain undocumented)
282 struct cvmx_led_cylon_s
284 #if __BYTE_ORDER == __BIG_ENDIAN
285 uint64_t reserved_16_63 : 48;
286 uint64_t rate : 16; /**< LED Cylon Effect when RATE!=0
287 Changes at RATE*LATCH period */
290 uint64_t reserved_16_63 : 48;
293 struct cvmx_led_cylon_s cn38xx;
294 struct cvmx_led_cylon_s cn38xxp2;
295 struct cvmx_led_cylon_s cn56xx;
296 struct cvmx_led_cylon_s cn56xxp1;
297 struct cvmx_led_cylon_s cn58xx;
298 struct cvmx_led_cylon_s cn58xxp1;
300 typedef union cvmx_led_cylon cvmx_led_cylon_t;
305 * LED_DBG = LED Debug Port information
311 struct cvmx_led_dbg_s
313 #if __BYTE_ORDER == __BIG_ENDIAN
314 uint64_t reserved_1_63 : 63;
315 uint64_t dbg_en : 1; /**< Add Debug Port Data to the LED shift chain
316 Debug Data is shifted out LSB to MSB */
319 uint64_t reserved_1_63 : 63;
322 struct cvmx_led_dbg_s cn38xx;
323 struct cvmx_led_dbg_s cn38xxp2;
324 struct cvmx_led_dbg_s cn56xx;
325 struct cvmx_led_dbg_s cn56xxp1;
326 struct cvmx_led_dbg_s cn58xx;
327 struct cvmx_led_dbg_s cn58xxp1;
329 typedef union cvmx_led_dbg cvmx_led_dbg_t;
334 * LED_EN = LED Interface Enable
338 * The LED interface is comprised of a shift chain with a parallel latch. LED
339 * data is shifted out on each fallingg edge of led_clk and then captured by
342 * The LED shift chain is comprised of the following...
345 * 6x8 - per port status
349 * for a total of 129 bits.
351 * UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out
352 * LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1],
353 * ... LED_UDD_DAT0[LED_UDD_CNT0].
355 * The per port status is also variable. Systems can control which ports send
356 * data (LED_PRT) as well as the status content (LED_PRT_FMT and
357 * LED_PRT_STATUS*). When multiple ports are enabled, they come out in lowest
358 * port to highest port (prt0, prt1, ...).
360 * The debug port data can also be added to the LED chain (LED_DBG). When
361 * enabled, the debug data shifts out LSB to MSB.
363 * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
371 #if __BYTE_ORDER == __BIG_ENDIAN
372 uint64_t reserved_1_63 : 63;
373 uint64_t en : 1; /**< Enable the LED interface shift-chain */
376 uint64_t reserved_1_63 : 63;
379 struct cvmx_led_en_s cn38xx;
380 struct cvmx_led_en_s cn38xxp2;
381 struct cvmx_led_en_s cn56xx;
382 struct cvmx_led_en_s cn56xxp1;
383 struct cvmx_led_en_s cn58xx;
384 struct cvmx_led_en_s cn58xxp1;
386 typedef union cvmx_led_en cvmx_led_en_t;
391 * LED_POLARITY = LED Polarity
394 union cvmx_led_polarity
397 struct cvmx_led_polarity_s
399 #if __BYTE_ORDER == __BIG_ENDIAN
400 uint64_t reserved_1_63 : 63;
401 uint64_t polarity : 1; /**< LED active polarity
403 1 = active LOW LED (invert led_dat) */
405 uint64_t polarity : 1;
406 uint64_t reserved_1_63 : 63;
409 struct cvmx_led_polarity_s cn38xx;
410 struct cvmx_led_polarity_s cn38xxp2;
411 struct cvmx_led_polarity_s cn56xx;
412 struct cvmx_led_polarity_s cn56xxp1;
413 struct cvmx_led_polarity_s cn58xx;
414 struct cvmx_led_polarity_s cn58xxp1;
416 typedef union cvmx_led_polarity cvmx_led_polarity_t;
421 * LED_PRT = LED Port status information
426 * the PRT vector enables information of the 8 RGMII ports connected to
427 * Octane. It does not reflect the actual programmed PHY addresses.
432 struct cvmx_led_prt_s
434 #if __BYTE_ORDER == __BIG_ENDIAN
435 uint64_t reserved_8_63 : 56;
436 uint64_t prt_en : 8; /**< Which ports are enabled to display status
437 PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
438 PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1
439 Only applies when interface is in RGMII mode
440 The status format is defined by LED_PRT_FMT */
443 uint64_t reserved_8_63 : 56;
446 struct cvmx_led_prt_s cn38xx;
447 struct cvmx_led_prt_s cn38xxp2;
448 struct cvmx_led_prt_s cn56xx;
449 struct cvmx_led_prt_s cn56xxp1;
450 struct cvmx_led_prt_s cn58xx;
451 struct cvmx_led_prt_s cn58xxp1;
453 typedef union cvmx_led_prt cvmx_led_prt_t;
458 * LED_PRT_FMT = LED Port Status Infomation Format
462 * TX: RGMII TX block is sending packet data or extends on the port
463 * RX: RGMII RX block has received non-idle cycle
465 * For short transfers, LEDs will remain on for at least one blink cycle
467 union cvmx_led_prt_fmt
470 struct cvmx_led_prt_fmt_s
472 #if __BYTE_ORDER == __BIG_ENDIAN
473 uint64_t reserved_4_63 : 60;
474 uint64_t format : 4; /**< Port Status Information for each enabled port in
475 LED_PRT. The formats are below
476 0x0: [ LED_PRT_STATUS[0] ]
477 0x1: [ LED_PRT_STATUS[1:0] ]
478 0x2: [ LED_PRT_STATUS[3:0] ]
479 0x3: [ LED_PRT_STATUS[5:0] ]
480 0x4: [ (RX|TX), LED_PRT_STATUS[0] ]
481 0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ]
482 0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ]
483 0x8: [ Tx, Rx, LED_PRT_STATUS[0] ]
484 0x9: [ Tx, Rx, LED_PRT_STATUS[1:0] ]
485 0xa: [ Tx, Rx, LED_PRT_STATUS[3:0] ] */
488 uint64_t reserved_4_63 : 60;
491 struct cvmx_led_prt_fmt_s cn38xx;
492 struct cvmx_led_prt_fmt_s cn38xxp2;
493 struct cvmx_led_prt_fmt_s cn56xx;
494 struct cvmx_led_prt_fmt_s cn56xxp1;
495 struct cvmx_led_prt_fmt_s cn58xx;
496 struct cvmx_led_prt_fmt_s cn58xxp1;
498 typedef union cvmx_led_prt_fmt cvmx_led_prt_fmt_t;
501 * cvmx_led_prt_status#
503 * LED_PRT_STATUS = LED Port Status information
506 union cvmx_led_prt_statusx
509 struct cvmx_led_prt_statusx_s
511 #if __BYTE_ORDER == __BIG_ENDIAN
512 uint64_t reserved_6_63 : 58;
513 uint64_t status : 6; /**< Bits that software can set to be added to the
514 LED shift chain - depending on LED_PRT_FMT
515 LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0
517 LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4
519 Only applies when interface is in RGMII mode */
522 uint64_t reserved_6_63 : 58;
525 struct cvmx_led_prt_statusx_s cn38xx;
526 struct cvmx_led_prt_statusx_s cn38xxp2;
527 struct cvmx_led_prt_statusx_s cn56xx;
528 struct cvmx_led_prt_statusx_s cn56xxp1;
529 struct cvmx_led_prt_statusx_s cn58xx;
530 struct cvmx_led_prt_statusx_s cn58xxp1;
532 typedef union cvmx_led_prt_statusx cvmx_led_prt_statusx_t;
537 * LED_UDD_CNT = LED UDD Counts
540 union cvmx_led_udd_cntx
543 struct cvmx_led_udd_cntx_s
545 #if __BYTE_ORDER == __BIG_ENDIAN
546 uint64_t reserved_6_63 : 58;
547 uint64_t cnt : 6; /**< Number of bits of user-defined data to include in
548 the LED shift chain. Legal values: 0-32. */
551 uint64_t reserved_6_63 : 58;
554 struct cvmx_led_udd_cntx_s cn38xx;
555 struct cvmx_led_udd_cntx_s cn38xxp2;
556 struct cvmx_led_udd_cntx_s cn56xx;
557 struct cvmx_led_udd_cntx_s cn56xxp1;
558 struct cvmx_led_udd_cntx_s cn58xx;
559 struct cvmx_led_udd_cntx_s cn58xxp1;
561 typedef union cvmx_led_udd_cntx cvmx_led_udd_cntx_t;
566 * LED_UDD_DAT = User defined data (header or trailer)
570 * Bits come out LSB to MSB on the shift chain. If LED_UDD_CNT is set to 4
571 * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
574 union cvmx_led_udd_datx
577 struct cvmx_led_udd_datx_s
579 #if __BYTE_ORDER == __BIG_ENDIAN
580 uint64_t reserved_32_63 : 32;
581 uint64_t dat : 32; /**< Header or trailer UDD data to be displayed on
582 the LED shift chain. Number of bits to include
583 is controled by LED_UDD_CNT */
586 uint64_t reserved_32_63 : 32;
589 struct cvmx_led_udd_datx_s cn38xx;
590 struct cvmx_led_udd_datx_s cn38xxp2;
591 struct cvmx_led_udd_datx_s cn56xx;
592 struct cvmx_led_udd_datx_s cn56xxp1;
593 struct cvmx_led_udd_datx_s cn58xx;
594 struct cvmx_led_udd_datx_s cn58xxp1;
596 typedef union cvmx_led_udd_datx cvmx_led_udd_datx_t;
599 * cvmx_led_udd_dat_clr#
601 * LED_UDD_DAT_CLR = User defined data (header or trailer)
604 union cvmx_led_udd_dat_clrx
607 struct cvmx_led_udd_dat_clrx_s
609 #if __BYTE_ORDER == __BIG_ENDIAN
610 uint64_t reserved_32_63 : 32;
611 uint64_t clr : 32; /**< Bitwise clear for the Header or trailer UDD data to
612 be displayed on the LED shift chain. */
615 uint64_t reserved_32_63 : 32;
618 struct cvmx_led_udd_dat_clrx_s cn38xx;
619 struct cvmx_led_udd_dat_clrx_s cn38xxp2;
620 struct cvmx_led_udd_dat_clrx_s cn56xx;
621 struct cvmx_led_udd_dat_clrx_s cn56xxp1;
622 struct cvmx_led_udd_dat_clrx_s cn58xx;
623 struct cvmx_led_udd_dat_clrx_s cn58xxp1;
625 typedef union cvmx_led_udd_dat_clrx cvmx_led_udd_dat_clrx_t;
628 * cvmx_led_udd_dat_set#
630 * LED_UDD_DAT_SET = User defined data (header or trailer)
633 union cvmx_led_udd_dat_setx
636 struct cvmx_led_udd_dat_setx_s
638 #if __BYTE_ORDER == __BIG_ENDIAN
639 uint64_t reserved_32_63 : 32;
640 uint64_t set : 32; /**< Bitwise set for the Header or trailer UDD data to
641 be displayed on the LED shift chain. */
644 uint64_t reserved_32_63 : 32;
647 struct cvmx_led_udd_dat_setx_s cn38xx;
648 struct cvmx_led_udd_dat_setx_s cn38xxp2;
649 struct cvmx_led_udd_dat_setx_s cn56xx;
650 struct cvmx_led_udd_dat_setx_s cn56xxp1;
651 struct cvmx_led_udd_dat_setx_s cn58xx;
652 struct cvmx_led_udd_dat_setx_s cn58xxp1;
654 typedef union cvmx_led_udd_dat_setx cvmx_led_udd_dat_setx_t;