sys/contrib/octeon-sdk/cvmx-mixx-defs.h

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  39
  40
  41 /**
  42  * cvmx-mixx-defs.h
  43  *
  44  * Configuration and status register (CSR) type definitions for
  45  * Octeon mixx.
  46  *
  47  * This file is auto generated. Do not edit.
  48  *
  49  * <hr>$Revision$<hr>
  50  *
  51  */
  52 #ifndef __CVMX_MIXX_TYPEDEFS_H__
  53 #define __CVMX_MIXX_TYPEDEFS_H__
  54
  55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  56 static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
  57 {
  58         if (!(
  59               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  60               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
  61               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
  62                 cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
  63         return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048;
  64 }
  65 #else
  66 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
  67 #endif
  68 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  69 static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
  70 {
  71         if (!(
  72               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  73               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
  74               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
  75                 cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
  76         return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048;
  77 }
  78 #else
  79 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
  80 #endif
  81 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  82 static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
  83 {
  84         if (!(
  85               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  86               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
  87               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
  88                 cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
  89         return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048;
  90 }
  91 #else
  92 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
  93 #endif
  94 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  95 static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
  96 {
  97         if (!(
  98               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  99               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 100               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 101                 cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
 102         return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048;
 103 }
 104 #else
 105 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
 106 #endif
 107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 108 static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
 109 {
 110         if (!(
 111               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 112               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 113               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 114                 cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
 115         return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048;
 116 }
 117 #else
 118 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
 119 #endif
 120 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 121 static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
 122 {
 123         if (!(
 124               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 125               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 126               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 127                 cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
 128         return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048;
 129 }
 130 #else
 131 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
 132 #endif
 133 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 134 static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
 135 {
 136         if (!(
 137               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 138               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 139               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 140                 cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
 141         return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048;
 142 }
 143 #else
 144 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
 145 #endif
 146 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 147 static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
 148 {
 149         if (!(
 150               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 151               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 152               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 153                 cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
 154         return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048;
 155 }
 156 #else
 157 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
 158 #endif
 159 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 160 static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
 161 {
 162         if (!(
 163               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 164               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 165               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 166                 cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
 167         return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048;
 168 }
 169 #else
 170 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
 171 #endif
 172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 173 static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
 174 {
 175         if (!(
 176               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 177               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 178               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 179                 cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
 180         return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048;
 181 }
 182 #else
 183 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
 184 #endif
 185 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 186 static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
 187 {
 188         if (!(
 189               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 190               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 191               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 192                 cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
 193         return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048;
 194 }
 195 #else
 196 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
 197 #endif
 198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 199 static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
 200 {
 201         if (!(
 202               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 203               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 204               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 205                 cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
 206         return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048;
 207 }
 208 #else
 209 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
 210 #endif
 211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 212 static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
 213 {
 214         if (!(
 215               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 216               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 217               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 218                 cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
 219         return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048;
 220 }
 221 #else
 222 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
 223 #endif
 224 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 225 static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
 226 {
 227         if (!(
 228               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 229                 cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset);
 230         return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048;
 231 }
 232 #else
 233 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
 234 #endif
 235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 236 static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
 237 {
 238         if (!(
 239               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
 240                 cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset);
 241         return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048;
 242 }
 243 #else
 244 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
 245 #endif
 246
 247 /**
 248  * cvmx_mix#_bist
 249  *
 250  * MIX_BIST = MIX BIST Register
 251  *
 252  * Description:
 253  *  NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO.
 254  */
 255 union cvmx_mixx_bist
 256 {
 257         uint64_t u64;
 258         struct cvmx_mixx_bist_s
 259         {
 260 #if __BYTE_ORDER == __BIG_ENDIAN
 261         uint64_t reserved_6_63                : 58;
 262         uint64_t opfdat                       : 1;  /**< Bist Results for AGO OPF Buffer RAM
 263                                                          - 0: GOOD (or bist in progress/never run)
 264                                                          - 1: BAD */
 265         uint64_t mrgdat                       : 1;  /**< Bist Results for AGI MRG Buffer RAM
 266                                                          - 0: GOOD (or bist in progress/never run)
 267                                                          - 1: BAD */
 268         uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
 269                                                          - 0: GOOD (or bist in progress/never run)
 270                                                          - 1: BAD */
 271         uint64_t ipfdat                       : 1;  /**< Bist Results for MIX Inbound Packet RAM
 272                                                          - 0: GOOD (or bist in progress/never run)
 273                                                          - 1: BAD */
 274         uint64_t irfdat                       : 1;  /**< Bist Results for MIX I-Ring Entry RAM
 275                                                          - 0: GOOD (or bist in progress/never run)
 276                                                          - 1: BAD */
 277         uint64_t orfdat                       : 1;  /**< Bist Results for MIX O-Ring Entry RAM
 278                                                          - 0: GOOD (or bist in progress/never run)
 279                                                          - 1: BAD */
 280 #else
 281         uint64_t orfdat                       : 1;
 282         uint64_t irfdat                       : 1;
 283         uint64_t ipfdat                       : 1;
 284         uint64_t mrqdat                       : 1;
 285         uint64_t mrgdat                       : 1;
 286         uint64_t opfdat                       : 1;
 287         uint64_t reserved_6_63                : 58;
 288 #endif
 289         } s;
 290         struct cvmx_mixx_bist_cn52xx
 291         {
 292 #if __BYTE_ORDER == __BIG_ENDIAN
 293         uint64_t reserved_4_63                : 60;
 294         uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
 295                                                          - 0: GOOD (or bist in progress/never run)
 296                                                          - 1: BAD */
 297         uint64_t ipfdat                       : 1;  /**< Bist Results for MIX Inbound Packet RAM
 298                                                          - 0: GOOD (or bist in progress/never run)
 299                                                          - 1: BAD */
 300         uint64_t irfdat                       : 1;  /**< Bist Results for MIX I-Ring Entry RAM
 301                                                          - 0: GOOD (or bist in progress/never run)
 302                                                          - 1: BAD */
 303         uint64_t orfdat                       : 1;  /**< Bist Results for MIX O-Ring Entry RAM
 304                                                          - 0: GOOD (or bist in progress/never run)
 305                                                          - 1: BAD */
 306 #else
 307         uint64_t orfdat                       : 1;
 308         uint64_t irfdat                       : 1;
 309         uint64_t ipfdat                       : 1;
 310         uint64_t mrqdat                       : 1;
 311         uint64_t reserved_4_63                : 60;
 312 #endif
 313         } cn52xx;
 314         struct cvmx_mixx_bist_cn52xx          cn52xxp1;
 315         struct cvmx_mixx_bist_cn52xx          cn56xx;
 316         struct cvmx_mixx_bist_cn52xx          cn56xxp1;
 317         struct cvmx_mixx_bist_s               cn63xx;
 318         struct cvmx_mixx_bist_s               cn63xxp1;
 319 };
 320 typedef union cvmx_mixx_bist cvmx_mixx_bist_t;
 321
 322 /**
 323  * cvmx_mix#_ctl
 324  *
 325  * MIX_CTL = MIX Control Register
 326  *
 327  * Description:
 328  *  NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO.
 329  *        To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO.
 330  */
 331 union cvmx_mixx_ctl
 332 {
 333         uint64_t u64;
 334         struct cvmx_mixx_ctl_s
 335         {
 336 #if __BYTE_ORDER == __BIG_ENDIAN
 337         uint64_t reserved_12_63               : 52;
 338         uint64_t ts_thresh                    : 4;  /**< TimeStamp Interrupt Threshold
 339                                                          When the \#of pending Timestamp interrupts (MIX_TSCTL[TSCNT]
 340                                                          is greater than MIX_CTL[TS_THRESH], then a programmable
 341                                                          TimeStamp Interrupt is issued (see MIX_INTR[TS]
 342                                                          MIX_INTENA[TSENA]).
 343                                                          SWNOTE: For o63, since the implementation only supports
 344                                                          4 oustanding timestamp interrupts, this field should
 345                                                          only be programmed from [0..3]. */
 346         uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
 347                                                          When enabled, the last 4 bytes(CRC) of the ingress packet
 348                                                          are not included in cumulative packet byte length.
 349                                                          In other words, the cumulative LEN field for all
 350                                                          I-Ring Buffer Entries associated with a given ingress
 351                                                          packet will be 4 bytes less (so that the final 4B HW CRC
 352                                                          packet data is not processed by software). */
 353         uint64_t busy                         : 1;  /**< MIX Busy Status bit
 354                                                          MIX will assert busy status any time there are:
 355                                                            1) L2/DRAM reads in-flight (NCB-arb to read
 356                                                               response)
 357                                                            2) L2/DRAM writes in-flight (NCB-arb to write
 358                                                               data is sent.
 359                                                            3) L2/DRAM write commits in-flight (NCB-arb to write
 360                                                               commit response).
 361                                                          NOTE: After MIX_CTL[EN]=0, the MIX will eventually
 362                                                          complete any "inflight" transactions, at which point the
 363                                                          BUSY will de-assert. */
 364         uint64_t en                           : 1;  /**< MIX Enable bit
 365                                                          When EN=0, MIX will no longer arbitrate for
 366                                                          any new L2/DRAM read/write requests on the NCB Bus.
 367                                                          MIX will complete any requests that are currently
 368                                                          pended for the NCB Bus. */
 369         uint64_t reset                        : 1;  /**< MIX Soft Reset
 370                                                           When SW writes a '1' to MIX_CTL[RESET], the
 371                                                           MII-MIX/AGL logic will execute a soft reset.
 372                                                           NOTE: During a soft reset, CSR accesses are not effected.
 373                                                           However, the values of the CSR fields will be effected by
 374                                                           soft reset (except MIX_CTL[RESET] itself).
 375                                                           NOTE: After power-on, the MII-AGL/MIX are held in reset
 376                                                           until the MIX_CTL[RESET] is written to zero.
 377                                                           The intended "soft reset" sequence is: (please also
 378                                                           refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
 379                                                              1) Write MIX_CTL[EN]=0
 380                                                                 [To prevent any NEW transactions from being started]
 381                                                              2) Wait for MIX_CTL[BUSY]=0
 382                                                                 [To indicate that all inflight transactions have
 383                                                                  completed]
 384                                                              3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
 385                                                                 and wait for the result.
 386                                                              4) Re-Initialize the MIX/AGL just as would be done
 387                                                                 for a hard reset.
 388                                                          NOTE: Once the MII has been soft-reset, please refer to HRM Section
 389                                                          12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL
 390                                                          re-initialization sequence. */
 391         uint64_t lendian                      : 1;  /**< Packet Little Endian Mode
 392                                                          (0: Big Endian Mode/1: Little Endian Mode)
 393                                                          When the mode is set, MIX will byte-swap packet data
 394                                                          loads/stores at the MIX/NCB boundary. */
 395         uint64_t nbtarb                       : 1;  /**< MIX CB-Request Arbitration Mode.
 396                                                          When set to zero, the arbiter is fixed priority with
 397                                                          the following priority scheme:
 398                                                              Highest Priority: I-Ring Packet Write Request
 399                                                                                O-Ring Packet Read Request
 400                                                                                I-Ring Entry Write Request
 401                                                                                I-Ring Entry Read Request
 402                                                                                O-Ring Entry Read Request
 403                                                          When set to one, the arbiter is round robin. */
 404         uint64_t mrq_hwm                      : 2;  /**< MIX CB-Request FIFO Programmable High Water Mark.
 405                                                          The MRQ contains 16 CB-Requests which are CSR Rd/Wr
 406                                                          Requests. If the MRQ backs up with "HWM" entries,
 407                                                          then new CB-Requests are 'stalled'.
 408                                                             [0]: HWM = 11
 409                                                             [1]: HWM = 10
 410                                                             [2]: HWM = 9
 411                                                             [3]: HWM = 8
 412                                                          NOTE: This must only be written at power-on/boot time. */
 413 #else
 414         uint64_t mrq_hwm                      : 2;
 415         uint64_t nbtarb                       : 1;
 416         uint64_t lendian                      : 1;
 417         uint64_t reset                        : 1;
 418         uint64_t en                           : 1;
 419         uint64_t busy                         : 1;
 420         uint64_t crc_strip                    : 1;
 421         uint64_t ts_thresh                    : 4;
 422         uint64_t reserved_12_63               : 52;
 423 #endif
 424         } s;
 425         struct cvmx_mixx_ctl_cn52xx
 426         {
 427 #if __BYTE_ORDER == __BIG_ENDIAN
 428         uint64_t reserved_8_63                : 56;
 429         uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
 430                                                          When enabled, the last 4 bytes(CRC) of the ingress packet
 431                                                          are not included in cumulative packet byte length.
 432                                                          In other words, the cumulative LEN field for all
 433                                                          I-Ring Buffer Entries associated with a given ingress
 434                                                          packet will be 4 bytes less (so that the final 4B HW CRC
 435                                                          packet data is not processed by software). */
 436         uint64_t busy                         : 1;  /**< MIX Busy Status bit
 437                                                          MIX will assert busy status any time there are:
 438                                                            1) L2/DRAM reads in-flight (NCB-arb to read
 439                                                               response)
 440                                                            2) L2/DRAM writes in-flight (NCB-arb to write
 441                                                               data is sent.
 442                                                            3) L2/DRAM write commits in-flight (NCB-arb to write
 443                                                               commit response).
 444                                                          NOTE: After MIX_CTL[EN]=0, the MIX will eventually
 445                                                          complete any "inflight" transactions, at which point the
 446                                                          BUSY will de-assert. */
 447         uint64_t en                           : 1;  /**< MIX Enable bit
 448                                                          When EN=0, MIX will no longer arbitrate for
 449                                                          any new L2/DRAM read/write requests on the NCB Bus.
 450                                                          MIX will complete any requests that are currently
 451                                                          pended for the NCB Bus. */
 452         uint64_t reset                        : 1;  /**< MIX Soft Reset
 453                                                           When SW writes a '1' to MIX_CTL[RESET], the
 454                                                           MII-MIX/AGL logic will execute a soft reset.
 455                                                           NOTE: During a soft reset, CSR accesses are not effected.
 456                                                           However, the values of the CSR fields will be effected by
 457                                                           soft reset (except MIX_CTL[RESET] itself).
 458                                                           NOTE: After power-on, the MII-AGL/MIX are held in reset
 459                                                           until the MIX_CTL[RESET] is written to zero.
 460                                                           The intended "soft reset" sequence is: (please also
 461                                                           refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
 462                                                              1) Write MIX_CTL[EN]=0
 463                                                                 [To prevent any NEW transactions from being started]
 464                                                              2) Wait for MIX_CTL[BUSY]=0
 465                                                                 [To indicate that all inflight transactions have
 466                                                                  completed]
 467                                                              3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
 468                                                                 and wait for the result.
 469                                                              4) Re-Initialize the MIX/AGL just as would be done
 470                                                                 for a hard reset.
 471                                                          NOTE: Once the MII has been soft-reset, please refer to HRM Section
 472                                                          12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL
 473                                                          re-initialization sequence. */
 474         uint64_t lendian                      : 1;  /**< Packet Little Endian Mode
 475                                                          (0: Big Endian Mode/1: Little Endian Mode)
 476                                                          When the mode is set, MIX will byte-swap packet data
 477                                                          loads/stores at the MIX/NCB boundary. */
 478         uint64_t nbtarb                       : 1;  /**< MIX CB-Request Arbitration Mode.
 479                                                          When set to zero, the arbiter is fixed priority with
 480                                                          the following priority scheme:
 481                                                              Highest Priority: I-Ring Packet Write Request
 482                                                                                O-Ring Packet Read Request
 483                                                                                I-Ring Entry Write Request
 484                                                                                I-Ring Entry Read Request
 485                                                                                O-Ring Entry Read Request
 486                                                          When set to one, the arbiter is round robin. */
 487         uint64_t mrq_hwm                      : 2;  /**< MIX CB-Request FIFO Programmable High Water Mark.
 488                                                          The MRQ contains 16 CB-Requests which are CSR Rd/Wr
 489                                                          Requests. If the MRQ backs up with "HWM" entries,
 490                                                          then new CB-Requests are 'stalled'.
 491                                                             [0]: HWM = 11
 492                                                             [1]: HWM = 10
 493                                                             [2]: HWM = 9
 494                                                             [3]: HWM = 8
 495                                                          NOTE: This must only be written at power-on/boot time. */
 496 #else
 497         uint64_t mrq_hwm                      : 2;
 498         uint64_t nbtarb                       : 1;
 499         uint64_t lendian                      : 1;
 500         uint64_t reset                        : 1;
 501         uint64_t en                           : 1;
 502         uint64_t busy                         : 1;
 503         uint64_t crc_strip                    : 1;
 504         uint64_t reserved_8_63                : 56;
 505 #endif
 506         } cn52xx;
 507         struct cvmx_mixx_ctl_cn52xx           cn52xxp1;
 508         struct cvmx_mixx_ctl_cn52xx           cn56xx;
 509         struct cvmx_mixx_ctl_cn52xx           cn56xxp1;
 510         struct cvmx_mixx_ctl_s                cn63xx;
 511         struct cvmx_mixx_ctl_s                cn63xxp1;
 512 };
 513 typedef union cvmx_mixx_ctl cvmx_mixx_ctl_t;
 514
 515 /**
 516  * cvmx_mix#_intena
 517  *
 518  * MIX_INTENA = MIX Local Interrupt Enable Mask Register
 519  *
 520  * Description:
 521  *  NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO.
 522  *        To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO.
 523  */
 524 union cvmx_mixx_intena
 525 {
 526         uint64_t u64;
 527         struct cvmx_mixx_intena_s
 528         {
 529 #if __BYTE_ORDER == __BIG_ENDIAN
 530         uint64_t reserved_8_63                : 56;
 531         uint64_t tsena                        : 1;  /**< TimeStamp Interrupt Enable
 532                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 533                                                          and this local interrupt mask bit is set, than an
 534                                                          interrupt is reported for an Outbound Ring with Timestamp
 535                                                          event (see: MIX_ISR[TS]). */
 536         uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected Enable
 537                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 538                                                          and this local interrupt mask bit is set, than an
 539                                                          interrupt is reported for an ORCNT underflow condition
 540                                                          MIX_ISR[ORUN]. */
 541         uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
 542                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 543                                                          and this local interrupt mask bit is set, than an
 544                                                          interrupt is reported for an IRCNT underflow condition
 545                                                          MIX_ISR[IRUN]. */
 546         uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
 547                                                          enable. If both the global interrupt mask bits
 548                                                          (CIU_INTx_EN*[MII]) and the local interrupt mask
 549                                                          bit(DATA_DRPENA) is set, than an interrupt is
 550                                                          reported for this event. */
 551         uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
 552                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 553                                                          and this local interrupt mask bit is set, than an
 554                                                          interrupt is reported for an Inbound Ring Threshold
 555                                                          Exceeded event(IRTHRESH). */
 556         uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
 557                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 558                                                          and this local interrupt mask bit is set, than an
 559                                                          interrupt is reported for an Outbound Ring Threshold
 560                                                          Exceeded event(ORTHRESH). */
 561         uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
 562                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 563                                                          and this local interrupt mask bit is set, than an
 564                                                          interrupt is reported for an Inbound Doorbell Overflow
 565                                                          event(IDBOVF). */
 566         uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
 567                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 568                                                          and this local interrupt mask bit is set, than an
 569                                                          interrupt is reported for an Outbound Doorbell Overflow
 570                                                          event(ODBOVF). */
 571 #else
 572         uint64_t ovfena                       : 1;
 573         uint64_t ivfena                       : 1;
 574         uint64_t othena                       : 1;
 575         uint64_t ithena                       : 1;
 576         uint64_t data_drpena                  : 1;
 577         uint64_t irunena                      : 1;
 578         uint64_t orunena                      : 1;
 579         uint64_t tsena                        : 1;
 580         uint64_t reserved_8_63                : 56;
 581 #endif
 582         } s;
 583         struct cvmx_mixx_intena_cn52xx
 584         {
 585 #if __BYTE_ORDER == __BIG_ENDIAN
 586         uint64_t reserved_7_63                : 57;
 587         uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected
 588                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 589                                                          and this local interrupt mask bit is set, than an
 590                                                          interrupt is reported for an ORCNT underflow condition
 591                                                          MIX_ISR[ORUN]. */
 592         uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
 593                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 594                                                          and this local interrupt mask bit is set, than an
 595                                                          interrupt is reported for an IRCNT underflow condition
 596                                                          MIX_ISR[IRUN]. */
 597         uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
 598                                                          enable. If both the global interrupt mask bits
 599                                                          (CIU_INTx_EN*[MII]) and the local interrupt mask
 600                                                          bit(DATA_DRPENA) is set, than an interrupt is
 601                                                          reported for this event. */
 602         uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
 603                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 604                                                          and this local interrupt mask bit is set, than an
 605                                                          interrupt is reported for an Inbound Ring Threshold
 606                                                          Exceeded event(IRTHRESH). */
 607         uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
 608                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 609                                                          and this local interrupt mask bit is set, than an
 610                                                          interrupt is reported for an Outbound Ring Threshold
 611                                                          Exceeded event(ORTHRESH). */
 612         uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
 613                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 614                                                          and this local interrupt mask bit is set, than an
 615                                                          interrupt is reported for an Inbound Doorbell Overflow
 616                                                          event(IDBOVF). */
 617         uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
 618                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 619                                                          and this local interrupt mask bit is set, than an
 620                                                          interrupt is reported for an Outbound Doorbell Overflow
 621                                                          event(ODBOVF). */
 622 #else
 623         uint64_t ovfena                       : 1;
 624         uint64_t ivfena                       : 1;
 625         uint64_t othena                       : 1;
 626         uint64_t ithena                       : 1;
 627         uint64_t data_drpena                  : 1;
 628         uint64_t irunena                      : 1;
 629         uint64_t orunena                      : 1;
 630         uint64_t reserved_7_63                : 57;
 631 #endif
 632         } cn52xx;
 633         struct cvmx_mixx_intena_cn52xx        cn52xxp1;
 634         struct cvmx_mixx_intena_cn52xx        cn56xx;
 635         struct cvmx_mixx_intena_cn52xx        cn56xxp1;
 636         struct cvmx_mixx_intena_s             cn63xx;
 637         struct cvmx_mixx_intena_s             cn63xxp1;
 638 };
 639 typedef union cvmx_mixx_intena cvmx_mixx_intena_t;
 640
 641 /**
 642  * cvmx_mix#_ircnt
 643  *
 644  * MIX_IRCNT = MIX I-Ring Pending Packet Counter
 645  *
 646  * Description:
 647  *  NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO.
 648  *        To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO.
 649  */
 650 union cvmx_mixx_ircnt
 651 {
 652         uint64_t u64;
 653         struct cvmx_mixx_ircnt_s
 654         {
 655 #if __BYTE_ORDER == __BIG_ENDIAN
 656         uint64_t reserved_20_63               : 44;
 657         uint64_t ircnt                        : 20; /**< Pending \# of I-Ring Packets.
 658                                                          Whenever HW writes a completion code of Done, Trunc,
 659                                                          CRCErr or Err, it increments the IRCNT (to indicate
 660                                                          to SW the \# of pending Input packets in system memory).
 661                                                          NOTE: The HW guarantees that the completion code write
 662                                                          is always visible in system memory BEFORE it increments
 663                                                          the IRCNT.
 664                                                          Reads of IRCNT return the current inbound packet count.
 665                                                          Writes of IRCNT decrement the count by the value
 666                                                          written.
 667                                                          This register is used to generate interrupts to alert
 668                                                          SW of pending inbound MIX packets in system memory.
 669                                                          NOTE: In the case of inbound packets that span multiple
 670                                                          I-Ring entries, SW must keep track of the \# of I-Ring Entries
 671                                                          associated with a given inbound packet to reclaim the
 672                                                          proper \# of I-Ring Entries for re-use. */
 673 #else
 674         uint64_t ircnt                        : 20;
 675         uint64_t reserved_20_63               : 44;
 676 #endif
 677         } s;
 678         struct cvmx_mixx_ircnt_s              cn52xx;
 679         struct cvmx_mixx_ircnt_s              cn52xxp1;
 680         struct cvmx_mixx_ircnt_s              cn56xx;
 681         struct cvmx_mixx_ircnt_s              cn56xxp1;
 682         struct cvmx_mixx_ircnt_s              cn63xx;
 683         struct cvmx_mixx_ircnt_s              cn63xxp1;
 684 };
 685 typedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t;
 686
 687 /**
 688  * cvmx_mix#_irhwm
 689  *
 690  * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register
 691  *
 692  * Description:
 693  *  NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO.
 694  *        To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO.
 695  */
 696 union cvmx_mixx_irhwm
 697 {
 698         uint64_t u64;
 699         struct cvmx_mixx_irhwm_s
 700         {
 701 #if __BYTE_ORDER == __BIG_ENDIAN
 702         uint64_t reserved_40_63               : 24;
 703         uint64_t ibplwm                       : 20; /**< I-Ring BackPressure Low Water Mark Threshold.
 704                                                          When the \#of available I-Ring Entries (IDBELL)
 705                                                          is less than IBPLWM, the AGL-MAC will:
 706                                                            a) In full-duplex mode: send periodic PAUSE packets.
 707                                                            b) In half-duplex mode: Force collisions.
 708                                                          This programmable mechanism is provided as a means
 709                                                          to backpressure input traffic 'early' enough (so
 710                                                          that packets are not 'dropped' by OCTEON). */
 711         uint64_t irhwm                        : 20; /**< I-Ring Entry High Water Mark Threshold.
 712                                                          Used to determine when the \# of Inbound packets
 713                                                          in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM
 714                                                          threshold.
 715                                                          NOTE: The power-on value of the CIU_INTx_EN*[MII]
 716                                                          interrupt enable bits is zero and must be enabled
 717                                                          to allow interrupts to be reported. */
 718 #else
 719         uint64_t irhwm                        : 20;
 720         uint64_t ibplwm                       : 20;
 721         uint64_t reserved_40_63               : 24;
 722 #endif
 723         } s;
 724         struct cvmx_mixx_irhwm_s              cn52xx;
 725         struct cvmx_mixx_irhwm_s              cn52xxp1;
 726         struct cvmx_mixx_irhwm_s              cn56xx;
 727         struct cvmx_mixx_irhwm_s              cn56xxp1;
 728         struct cvmx_mixx_irhwm_s              cn63xx;
 729         struct cvmx_mixx_irhwm_s              cn63xxp1;
 730 };
 731 typedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t;
 732
 733 /**
 734  * cvmx_mix#_iring1
 735  *
 736  * MIX_IRING1 = MIX Inbound Ring Register \#1
 737  *
 738  * Description:
 739  *  NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO.
 740  *        To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO.
 741  */
 742 union cvmx_mixx_iring1
 743 {
 744         uint64_t u64;
 745         struct cvmx_mixx_iring1_s
 746         {
 747 #if __BYTE_ORDER == __BIG_ENDIAN
 748         uint64_t reserved_60_63               : 4;
 749         uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
 750                                                          words). The ring can be as large as 1M entries.
 751                                                          NOTE: This CSR MUST BE setup written by SW poweron
 752                                                          (when IDBELL/IRCNT=0). */
 753         uint64_t ibase                        : 37; /**< Represents the 8B-aligned base address of the first
 754                                                          Inbound Ring entry in system memory.
 755                                                          NOTE: SW MUST ONLY write to this register during
 756                                                          power-on/boot code. */
 757         uint64_t reserved_0_2                 : 3;
 758 #else
 759         uint64_t reserved_0_2                 : 3;
 760         uint64_t ibase                        : 37;
 761         uint64_t isize                        : 20;
 762         uint64_t reserved_60_63               : 4;
 763 #endif
 764         } s;
 765         struct cvmx_mixx_iring1_cn52xx
 766         {
 767 #if __BYTE_ORDER == __BIG_ENDIAN
 768         uint64_t reserved_60_63               : 4;
 769         uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
 770                                                          words). The ring can be as large as 1M entries.
 771                                                          NOTE: This CSR MUST BE setup written by SW poweron
 772                                                          (when IDBELL/IRCNT=0). */
 773         uint64_t reserved_36_39               : 4;
 774         uint64_t ibase                        : 33; /**< Represents the 8B-aligned base address of the first
 775                                                          Inbound Ring entry in system memory.
 776                                                          NOTE: SW MUST ONLY write to this register during
 777                                                          power-on/boot code. */
 778         uint64_t reserved_0_2                 : 3;
 779 #else
 780         uint64_t reserved_0_2                 : 3;
 781         uint64_t ibase                        : 33;
 782         uint64_t reserved_36_39               : 4;
 783         uint64_t isize                        : 20;
 784         uint64_t reserved_60_63               : 4;
 785 #endif
 786         } cn52xx;
 787         struct cvmx_mixx_iring1_cn52xx        cn52xxp1;
 788         struct cvmx_mixx_iring1_cn52xx        cn56xx;
 789         struct cvmx_mixx_iring1_cn52xx        cn56xxp1;
 790         struct cvmx_mixx_iring1_s             cn63xx;
 791         struct cvmx_mixx_iring1_s             cn63xxp1;
 792 };
 793 typedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t;
 794
 795 /**
 796  * cvmx_mix#_iring2
 797  *
 798  * MIX_IRING2 = MIX Inbound Ring Register \#2
 799  *
 800  * Description:
 801  *  NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO.
 802  *        To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO.
 803  */
 804 union cvmx_mixx_iring2
 805 {
 806         uint64_t u64;
 807         struct cvmx_mixx_iring2_s
 808         {
 809 #if __BYTE_ORDER == __BIG_ENDIAN
 810         uint64_t reserved_52_63               : 12;
 811         uint64_t itlptr                       : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring
 812                                                          Entry that the HW will process next. After the HW
 813                                                          completes receiving an inbound packet, it increments
 814                                                          the I-Ring Tail Pointer. [NOTE: The I-Ring Tail
 815                                                          Pointer HW increment is always modulo ISIZE.
 816                                                          NOTE: This field is 'read-only' to SW. */
 817         uint64_t reserved_20_31               : 12;
 818         uint64_t idbell                       : 20; /**< Represents the cumulative total of pending
 819                                                          Inbound Ring Buffer Entries. Each I-Ring
 820                                                          Buffer Entry contains 1) an L2/DRAM byte pointer
 821                                                          along with a 2) a Byte Length.
 822                                                          After SW inserts a new entry into the I-Ring Buffer,
 823                                                          it "rings the doorbell for the inbound ring". When
 824                                                          the MIX HW receives the doorbell ring, it advances
 825                                                          the doorbell count for the I-Ring.
 826                                                          SW must never cause the doorbell count for the
 827                                                          I-Ring to exceed the size of the I-ring(ISIZE).
 828                                                          A read of the CSR indicates the current doorbell
 829                                                          count. */
 830 #else
 831         uint64_t idbell                       : 20;
 832         uint64_t reserved_20_31               : 12;
 833         uint64_t itlptr                       : 20;
 834         uint64_t reserved_52_63               : 12;
 835 #endif
 836         } s;
 837         struct cvmx_mixx_iring2_s             cn52xx;
 838         struct cvmx_mixx_iring2_s             cn52xxp1;
 839         struct cvmx_mixx_iring2_s             cn56xx;
 840         struct cvmx_mixx_iring2_s             cn56xxp1;
 841         struct cvmx_mixx_iring2_s             cn63xx;
 842         struct cvmx_mixx_iring2_s             cn63xxp1;
 843 };
 844 typedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t;
 845
 846 /**
 847  * cvmx_mix#_isr
 848  *
 849  * MIX_ISR = MIX Interrupt/Status Register
 850  *
 851  * Description:
 852  *  NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO.
 853  *        To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO.
 854  */
 855 union cvmx_mixx_isr
 856 {
 857         uint64_t u64;
 858         struct cvmx_mixx_isr_s
 859         {
 860 #if __BYTE_ORDER == __BIG_ENDIAN
 861         uint64_t reserved_8_63                : 56;
 862         uint64_t ts                           : 1;  /**< TimeStamp Interrupt
 863                                                          When the \#of pending Timestamp Interrupts (MIX_TSCTL[TSCNT])
 864                                                          is greater than the TimeStamp Interrupt Threshold
 865                                                          (MIX_CTL[TS_THRESH]) value this interrupt bit is set.
 866                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 867                                                          and this local interrupt mask bit is set, than an
 868                                                          interrupt is reported for an Outbound Ring with Timestamp
 869                                                          event (see: MIX_INTENA[TSENA]). */
 870         uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
 871                                                          If SW writes a larger value than what is currently
 872                                                          in the MIX_ORCNT[ORCNT], then HW will report the
 873                                                          underflow condition.
 874                                                          NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
 875                                                          NOTE: If an ORUN underflow condition is detected,
 876                                                          the integrity of the MIX/AGL HW state has
 877                                                          been compromised. To recover, SW must issue a
 878                                                          software reset sequence (see: MIX_CTL[RESET] */
 879         uint64_t irun                         : 1;  /**< IRCNT UnderFlow Detected
 880                                                          If SW writes a larger value than what is currently
 881                                                          in the MIX_IRCNT[IRCNT], then HW will report the
 882                                                          underflow condition.
 883                                                          NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
 884                                                          NOTE: If an IRUN underflow condition is detected,
 885                                                          the integrity of the MIX/AGL HW state has
 886                                                          been compromised. To recover, SW must issue a
 887                                                          software reset sequence (see: MIX_CTL[RESET] */
 888         uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
 889                                                          If this does occur, the DATA_DRP is set and the
 890                                                          CIU_INTx_SUM0,4[MII] bits are set.
 891                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 892                                                          and the local interrupt mask bit(DATA_DRPENA) is set, than an
 893                                                          interrupt is reported for this event. */
 894         uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
 895                                                          When the pending \#inbound packets in system
 896                                                          memory(IRCNT) has exceeded a programmable threshold
 897                                                          (IRHWM), then this bit is set. If this does occur,
 898                                                          the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
 899                                                          are set if ((MIX_ISR & MIX_INTENA) != 0)).
 900                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 901                                                          and the local interrupt mask bit(ITHENA) is set, than an
 902                                                          interrupt is reported for this event. */
 903         uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
 904                                                          When the pending \#outbound packets in system
 905                                                          memory(ORCNT) has exceeded a programmable threshold
 906                                                          (ORHWM), then this bit is set. If this does occur,
 907                                                          the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
 908                                                          are set if ((MIX_ISR & MIX_INTENA) != 0)).
 909                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 910                                                          and the local interrupt mask bit(OTHENA) is set, than an
 911                                                          interrupt is reported for this event. */
 912         uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
 913                                                          If SW attempts to write to the MIX_IRING2[IDBELL]
 914                                                          with a value greater than the remaining \#of
 915                                                          I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
 916                                                          the following occurs:
 917                                                          1) The  MIX_IRING2[IDBELL] write is IGNORED
 918                                                          2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
 919                                                             bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
 920                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 921                                                          and the local interrupt mask bit(IVFENA) is set, than an
 922                                                          interrupt is reported for this event.
 923                                                          SW should keep track of the \#I-Ring Entries in use
 924                                                          (ie: cumulative \# of IDBELL writes),  and ensure that
 925                                                          future IDBELL writes don't exceed the size of the
 926                                                          I-Ring Buffer (MIX_IRING2[ISIZE]).
 927                                                          SW must reclaim I-Ring Entries by keeping track of the
 928                                                          \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
 929                                                          NOTE: The MIX_IRCNT[IRCNT] register represents the
 930                                                          total \#packets(not IRing Entries) and SW must further
 931                                                          keep track of the \# of I-Ring Entries associated with
 932                                                          each packet as they are processed.
 933                                                          NOTE: There is no recovery from an IDBLOVF Interrupt.
 934                                                          If it occurs, it's an indication that SW has
 935                                                          overwritten the I-Ring buffer, and the only recourse
 936                                                          is a HW reset. */
 937         uint64_t odblovf                      : 1;  /**< Outbound DoorBell(ODBELL) Overflow Detected
 938                                                          If SW attempts to write to the MIX_ORING2[ODBELL]
 939                                                          with a value greater than the remaining \#of
 940                                                          O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
 941                                                          the following occurs:
 942                                                          1) The  MIX_ORING2[ODBELL] write is IGNORED
 943                                                          2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
 944                                                             bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
 945                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 946                                                          and the local interrupt mask bit(OVFENA) is set, than an
 947                                                          interrupt is reported for this event.
 948                                                          SW should keep track of the \#I-Ring Entries in use
 949                                                          (ie: cumulative \# of ODBELL writes),  and ensure that
 950                                                          future ODBELL writes don't exceed the size of the
 951                                                          O-Ring Buffer (MIX_ORING2[OSIZE]).
 952                                                          SW must reclaim O-Ring Entries by writing to the
 953                                                          MIX_ORCNT[ORCNT]. .
 954                                                          NOTE: There is no recovery from an ODBLOVF Interrupt.
 955                                                          If it occurs, it's an indication that SW has
 956                                                          overwritten the O-Ring buffer, and the only recourse
 957                                                          is a HW reset. */
 958 #else
 959         uint64_t odblovf                      : 1;
 960         uint64_t idblovf                      : 1;
 961         uint64_t orthresh                     : 1;
 962         uint64_t irthresh                     : 1;
 963         uint64_t data_drp                     : 1;
 964         uint64_t irun                         : 1;
 965         uint64_t orun                         : 1;
 966         uint64_t ts                           : 1;
 967         uint64_t reserved_8_63                : 56;
 968 #endif
 969         } s;
 970         struct cvmx_mixx_isr_cn52xx
 971         {
 972 #if __BYTE_ORDER == __BIG_ENDIAN
 973         uint64_t reserved_7_63                : 57;
 974         uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
 975                                                          If SW writes a larger value than what is currently
 976                                                          in the MIX_ORCNT[ORCNT], then HW will report the
 977                                                          underflow condition.
 978                                                          NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
 979                                                          NOTE: If an ORUN underflow condition is detected,
 980                                                          the integrity of the MIX/AGL HW state has
 981                                                          been compromised. To recover, SW must issue a
 982                                                          software reset sequence (see: MIX_CTL[RESET] */
 983         uint64_t irun                         : 1;  /**< IRCNT UnderFlow Detected
 984                                                          If SW writes a larger value than what is currently
 985                                                          in the MIX_IRCNT[IRCNT], then HW will report the
 986                                                          underflow condition.
 987                                                          NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
 988                                                          NOTE: If an IRUN underflow condition is detected,
 989                                                          the integrity of the MIX/AGL HW state has
 990                                                          been compromised. To recover, SW must issue a
 991                                                          software reset sequence (see: MIX_CTL[RESET] */
 992         uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
 993                                                          If this does occur, the DATA_DRP is set and the
 994                                                          CIU_INTx_SUM0,4[MII] bits are set.
 995                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 996                                                          and the local interrupt mask bit(DATA_DRPENA) is set, than an
 997                                                          interrupt is reported for this event. */
 998         uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
 999                                                          When the pending \#inbound packets in system
1000                                                          memory(IRCNT) has exceeded a programmable threshold
1001                                                          (IRHWM), then this bit is set. If this does occur,
1002                                                          the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
1003                                                          are set if ((MIX_ISR & MIX_INTENA) != 0)).
1004                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1005                                                          and the local interrupt mask bit(ITHENA) is set, than an
1006                                                          interrupt is reported for this event. */
1007         uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
1008                                                          When the pending \#outbound packets in system
1009                                                          memory(ORCNT) has exceeded a programmable threshold
1010                                                          (ORHWM), then this bit is set. If this does occur,
1011                                                          the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
1012                                                          are set if ((MIX_ISR & MIX_INTENA) != 0)).
1013                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1014                                                          and the local interrupt mask bit(OTHENA) is set, than an
1015                                                          interrupt is reported for this event. */
1016         uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
1017                                                          If SW attempts to write to the MIX_IRING2[IDBELL]
1018                                                          with a value greater than the remaining \#of
1019                                                          I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
1020                                                          the following occurs:
1021                                                          1) The  MIX_IRING2[IDBELL] write is IGNORED
1022                                                          2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
1023                                                             bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
1024                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1025                                                          and the local interrupt mask bit(IVFENA) is set, than an
1026                                                          interrupt is reported for this event.
1027                                                          SW should keep track of the \#I-Ring Entries in use
1028                                                          (ie: cumulative \# of IDBELL writes),  and ensure that
1029                                                          future IDBELL writes don't exceed the size of the
1030                                                          I-Ring Buffer (MIX_IRING2[ISIZE]).
1031                                                          SW must reclaim I-Ring Entries by keeping track of the
1032                                                          \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
1033                                                          NOTE: The MIX_IRCNT[IRCNT] register represents the
1034                                                          total \#packets(not IRing Entries) and SW must further
1035                                                          keep track of the \# of I-Ring Entries associated with
1036                                                          each packet as they are processed.
1037                                                          NOTE: There is no recovery from an IDBLOVF Interrupt.
1038                                                          If it occurs, it's an indication that SW has
1039                                                          overwritten the I-Ring buffer, and the only recourse
1040                                                          is a HW reset. */
1041         uint64_t odblovf                      : 1;  /**< Outbound DoorBell(ODBELL) Overflow Detected
1042                                                          If SW attempts to write to the MIX_ORING2[ODBELL]
1043                                                          with a value greater than the remaining \#of
1044                                                          O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
1045                                                          the following occurs:
1046                                                          1) The  MIX_ORING2[ODBELL] write is IGNORED
1047                                                          2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
1048                                                             bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
1049                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1050                                                          and the local interrupt mask bit(OVFENA) is set, than an
1051                                                          interrupt is reported for this event.
1052                                                          SW should keep track of the \#I-Ring Entries in use
1053                                                          (ie: cumulative \# of ODBELL writes),  and ensure that
1054                                                          future ODBELL writes don't exceed the size of the
1055                                                          O-Ring Buffer (MIX_ORING2[OSIZE]).
1056                                                          SW must reclaim O-Ring Entries by writing to the
1057                                                          MIX_ORCNT[ORCNT]. .
1058                                                          NOTE: There is no recovery from an ODBLOVF Interrupt.
1059                                                          If it occurs, it's an indication that SW has
1060                                                          overwritten the O-Ring buffer, and the only recourse
1061                                                          is a HW reset. */
1062 #else
1063         uint64_t odblovf                      : 1;
1064         uint64_t idblovf                      : 1;
1065         uint64_t orthresh                     : 1;
1066         uint64_t irthresh                     : 1;
1067         uint64_t data_drp                     : 1;
1068         uint64_t irun                         : 1;
1069         uint64_t orun                         : 1;
1070         uint64_t reserved_7_63                : 57;
1071 #endif
1072         } cn52xx;
1073         struct cvmx_mixx_isr_cn52xx           cn52xxp1;
1074         struct cvmx_mixx_isr_cn52xx           cn56xx;
1075         struct cvmx_mixx_isr_cn52xx           cn56xxp1;
1076         struct cvmx_mixx_isr_s                cn63xx;
1077         struct cvmx_mixx_isr_s                cn63xxp1;
1078 };
1079 typedef union cvmx_mixx_isr cvmx_mixx_isr_t;
1080
1081 /**
1082  * cvmx_mix#_orcnt
1083  *
1084  * MIX_ORCNT = MIX O-Ring Packets Sent Counter
1085  *
1086  * Description:
1087  *  NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO.
1088  *        To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO.
1089  */
1090 union cvmx_mixx_orcnt
1091 {
1092         uint64_t u64;
1093         struct cvmx_mixx_orcnt_s
1094         {
1095 #if __BYTE_ORDER == __BIG_ENDIAN
1096         uint64_t reserved_20_63               : 44;
1097         uint64_t orcnt                        : 20; /**< Pending \# of O-Ring Packets.
1098                                                          Whenever HW removes a packet from the O-Ring, it
1099                                                          increments the ORCNT (to indicate to SW the \# of
1100                                                          Output packets in system memory that can be reclaimed).
1101                                                          Reads of ORCNT return the current count.
1102                                                          Writes of ORCNT decrement the count by the value
1103                                                          written.
1104                                                          This register is used to generate interrupts to alert
1105                                                          SW of pending outbound MIX packets that have been
1106                                                          removed from system memory. (see MIX_ISR[ORTHRESH]
1107                                                          description for more details).
1108                                                          NOTE: For outbound packets, the \# of O-Ring Packets
1109                                                          is equal to the \# of O-Ring Entries. */
1110 #else
1111         uint64_t orcnt                        : 20;
1112         uint64_t reserved_20_63               : 44;
1113 #endif
1114         } s;
1115         struct cvmx_mixx_orcnt_s              cn52xx;
1116         struct cvmx_mixx_orcnt_s              cn52xxp1;
1117         struct cvmx_mixx_orcnt_s              cn56xx;
1118         struct cvmx_mixx_orcnt_s              cn56xxp1;
1119         struct cvmx_mixx_orcnt_s              cn63xx;
1120         struct cvmx_mixx_orcnt_s              cn63xxp1;
1121 };
1122 typedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t;
1123
1124 /**
1125  * cvmx_mix#_orhwm
1126  *
1127  * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register
1128  *
1129  * Description:
1130  *  NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO.
1131  *        To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO.
1132  */
1133 union cvmx_mixx_orhwm
1134 {
1135         uint64_t u64;
1136         struct cvmx_mixx_orhwm_s
1137         {
1138 #if __BYTE_ORDER == __BIG_ENDIAN
1139         uint64_t reserved_20_63               : 44;
1140         uint64_t orhwm                        : 20; /**< O-Ring Entry High Water Mark Threshold.
1141                                                          Used to determine when the \# of Outbound packets
1142                                                          in system memory that can be reclaimed
1143                                                          (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold.
1144                                                          NOTE: The power-on value of the CIU_INTx_EN*[MII]
1145                                                          interrupt enable bits is zero and must be enabled
1146                                                          to allow interrupts to be reported. */
1147 #else
1148         uint64_t orhwm                        : 20;
1149         uint64_t reserved_20_63               : 44;
1150 #endif
1151         } s;
1152         struct cvmx_mixx_orhwm_s              cn52xx;
1153         struct cvmx_mixx_orhwm_s              cn52xxp1;
1154         struct cvmx_mixx_orhwm_s              cn56xx;
1155         struct cvmx_mixx_orhwm_s              cn56xxp1;
1156         struct cvmx_mixx_orhwm_s              cn63xx;
1157         struct cvmx_mixx_orhwm_s              cn63xxp1;
1158 };
1159 typedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t;
1160
1161 /**
1162  * cvmx_mix#_oring1
1163  *
1164  * MIX_ORING1 = MIX Outbound Ring Register \#1
1165  *
1166  * Description:
1167  *  NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO.
1168  *        To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO.
1169  */
1170 union cvmx_mixx_oring1
1171 {
1172         uint64_t u64;
1173         struct cvmx_mixx_oring1_s
1174         {
1175 #if __BYTE_ORDER == __BIG_ENDIAN
1176         uint64_t reserved_60_63               : 4;
1177         uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
1178                                                          words). The ring can be as large as 1M entries.
1179                                                          NOTE: This CSR MUST BE setup written by SW poweron
1180                                                          (when ODBELL/ORCNT=0). */
1181         uint64_t obase                        : 37; /**< Represents the 8B-aligned base address of the first
1182                                                          Outbound Ring(O-Ring) Entry in system memory.
1183                                                          NOTE: SW MUST ONLY write to this register during
1184                                                          power-on/boot code. */
1185         uint64_t reserved_0_2                 : 3;
1186 #else
1187         uint64_t reserved_0_2                 : 3;
1188         uint64_t obase                        : 37;
1189         uint64_t osize                        : 20;
1190         uint64_t reserved_60_63               : 4;
1191 #endif
1192         } s;
1193         struct cvmx_mixx_oring1_cn52xx
1194         {
1195 #if __BYTE_ORDER == __BIG_ENDIAN
1196         uint64_t reserved_60_63               : 4;
1197         uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
1198                                                          words). The ring can be as large as 1M entries.
1199                                                          NOTE: This CSR MUST BE setup written by SW poweron
1200                                                          (when ODBELL/ORCNT=0). */
1201         uint64_t reserved_36_39               : 4;
1202         uint64_t obase                        : 33; /**< Represents the 8B-aligned base address of the first
1203                                                          Outbound Ring(O-Ring) Entry in system memory.
1204                                                          NOTE: SW MUST ONLY write to this register during
1205                                                          power-on/boot code. */
1206         uint64_t reserved_0_2                 : 3;
1207 #else
1208         uint64_t reserved_0_2                 : 3;
1209         uint64_t obase                        : 33;
1210         uint64_t reserved_36_39               : 4;
1211         uint64_t osize                        : 20;
1212         uint64_t reserved_60_63               : 4;
1213 #endif
1214         } cn52xx;
1215         struct cvmx_mixx_oring1_cn52xx        cn52xxp1;
1216         struct cvmx_mixx_oring1_cn52xx        cn56xx;
1217         struct cvmx_mixx_oring1_cn52xx        cn56xxp1;
1218         struct cvmx_mixx_oring1_s             cn63xx;
1219         struct cvmx_mixx_oring1_s             cn63xxp1;
1220 };
1221 typedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t;
1222
1223 /**
1224  * cvmx_mix#_oring2
1225  *
1226  * MIX_ORING2 = MIX Outbound Ring Register \#2
1227  *
1228  * Description:
1229  *  NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO.
1230  *        To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO.
1231  */
1232 union cvmx_mixx_oring2
1233 {
1234         uint64_t u64;
1235         struct cvmx_mixx_oring2_s
1236         {
1237 #if __BYTE_ORDER == __BIG_ENDIAN
1238         uint64_t reserved_52_63               : 12;
1239         uint64_t otlptr                       : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring
1240                                                          Entry that the HW will process next. After the HW
1241                                                          completes sending an outbound packet, it increments
1242                                                          the O-Ring Tail Pointer. [NOTE: The O-Ring Tail
1243                                                          Pointer HW increment is always modulo
1244                                                          MIX_ORING2[OSIZE].
1245                                                          NOTE: This field is 'read-only' to SW. */
1246         uint64_t reserved_20_31               : 12;
1247         uint64_t odbell                       : 20; /**< Represents the cumulative total of pending
1248                                                          Outbound Ring(O-Ring) Buffer Entries. Each O-Ring
1249                                                          Buffer Entry contains 1) an L2/DRAM byte pointer
1250                                                          along with a 2) a Byte Length.
1251                                                          After SW inserts new entries into the O-Ring Buffer,
1252                                                          it "rings the doorbell with the count of the newly
1253                                                          inserted entries". When the MIX HW receives the
1254                                                          doorbell ring, it increments the current doorbell
1255                                                          count by the CSR write value.
1256                                                          SW must never cause the doorbell count for the
1257                                                          O-Ring to exceed the size of the ring(OSIZE).
1258                                                          A read of the CSR indicates the current doorbell
1259                                                          count. */
1260 #else
1261         uint64_t odbell                       : 20;
1262         uint64_t reserved_20_31               : 12;
1263         uint64_t otlptr                       : 20;
1264         uint64_t reserved_52_63               : 12;
1265 #endif
1266         } s;
1267         struct cvmx_mixx_oring2_s             cn52xx;
1268         struct cvmx_mixx_oring2_s             cn52xxp1;
1269         struct cvmx_mixx_oring2_s             cn56xx;
1270         struct cvmx_mixx_oring2_s             cn56xxp1;
1271         struct cvmx_mixx_oring2_s             cn63xx;
1272         struct cvmx_mixx_oring2_s             cn63xxp1;
1273 };
1274 typedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t;
1275
1276 /**
1277  * cvmx_mix#_remcnt
1278  *
1279  * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only)
1280  *
1281  * Description:
1282  *  NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO.
1283  */
1284 union cvmx_mixx_remcnt
1285 {
1286         uint64_t u64;
1287         struct cvmx_mixx_remcnt_s
1288         {
1289 #if __BYTE_ORDER == __BIG_ENDIAN
1290         uint64_t reserved_52_63               : 12;
1291         uint64_t iremcnt                      : 20; /**< Remaining I-Ring Buffer Count
1292                                                          Reflects the \# of unused/remaining I-Ring Entries
1293                                                          that HW  currently detects in the I-Ring Buffer.
1294                                                          HW uses this value to detect I-Ring Doorbell overflows.
1295                                                          (see: MIX_ISR[IDBLOVF])
1296                                                          When SW writes the MIX_IRING1[ISIZE], the IREMCNT
1297                                                          is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only
1298                                                          be written at power-on, when it's known that there are
1299                                                          no I-Ring Entries currently in use by HW).
1300                                                          When SW writes to the IDBELL register, the IREMCNT
1301                                                          is decremented by the CSR write value.
1302                                                          When HW issues an IRing Write Request(onto NCB Bus),
1303                                                          the IREMCNT is incremented by 1. */
1304         uint64_t reserved_20_31               : 12;
1305         uint64_t oremcnt                      : 20; /**< Remaining O-Ring Buffer Count
1306                                                          Reflects the \# of unused/remaining O-Ring Entries
1307                                                          that HW  currently detects in the O-Ring Buffer.
1308                                                          HW uses this value to detect O-Ring Doorbell overflows.
1309                                                          (see: MIX_ISR[ODBLOVF])
1310                                                          When SW writes the MIX_IRING1[OSIZE], the OREMCNT
1311                                                          is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only
1312                                                          be written at power-on, when it's known that there are
1313                                                          no O-Ring Entries currently in use by HW).
1314                                                          When SW writes to the ODBELL register, the OREMCNT
1315                                                          is decremented by the CSR write value.
1316                                                          When SW writes to MIX_[OREMCNT], the OREMCNT is decremented
1317                                                          by the CSR write value. */
1318 #else
1319         uint64_t oremcnt                      : 20;
1320         uint64_t reserved_20_31               : 12;
1321         uint64_t iremcnt                      : 20;
1322         uint64_t reserved_52_63               : 12;
1323 #endif
1324         } s;
1325         struct cvmx_mixx_remcnt_s             cn52xx;
1326         struct cvmx_mixx_remcnt_s             cn52xxp1;
1327         struct cvmx_mixx_remcnt_s             cn56xx;
1328         struct cvmx_mixx_remcnt_s             cn56xxp1;
1329         struct cvmx_mixx_remcnt_s             cn63xx;
1330         struct cvmx_mixx_remcnt_s             cn63xxp1;
1331 };
1332 typedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t;
1333
1334 /**
1335  * cvmx_mix#_tsctl
1336  *
1337  * MIX_TSCTL = MIX TimeStamp Control Register
1338  *
1339  * Description:
1340  *  NOTE: To read the MIX_TSCTL register, a device would issue an IOBLD64 directed at the MIO.
1341  *
1342  * Notes:
1343  * SW can read the MIX_TSCTL register to determine the \#pending timestamp interrupts(TSCNT)
1344  * as well as the \#outstanding timestamp requests in flight(TSTOT), as well as the \#of available
1345  * timestamp entries (TSAVL) in the timestamp fifo.
1346  * A write to the MIX_TSCTL register will advance the MIX*_TSTAMP fifo head ptr by 1, and
1347  * also decrements the MIX*_TSCTL[TSCNT] and MIX*_TSCTL[TSTOT] pending count(s) by 1.
1348  * For example, if SW reads MIX*_TSCTL[TSCNT]=2 (2 pending timestamp interrupts), it would immediately
1349  * issue this sequence:
1350  *      1) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write
1351  *            [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1]
1352  *      2) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write
1353  *            [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1]
1354  *
1355  * SWNOTE: A MIX_TSCTL write when MIX_TSCTL[TSCNT]=0 (ie: TimeStamp Fifo empty), then the write is ignored.
1356  */
1357 union cvmx_mixx_tsctl
1358 {
1359         uint64_t u64;
1360         struct cvmx_mixx_tsctl_s
1361         {
1362 #if __BYTE_ORDER == __BIG_ENDIAN
1363         uint64_t reserved_21_63               : 43;
1364         uint64_t tsavl                        : 5;  /**< # of MIX TimeStamp Entries Available for use
1365                                                          For o63: TSAVL MAX=4 (implementation
1366                                                          depth of timestamp fifo)
1367                                                          TSAVL = [IMPLEMENTATION_DEPTH=4(MAX) - TSCNT] */
1368         uint64_t reserved_13_15               : 3;
1369         uint64_t tstot                        : 5;  /**< # of pending MIX TimeStamp Requests in-flight
1370                                                          For o63: TSTOT must never exceed MAX=4 (implementation
1371                                                          depth of timestamp fifo) */
1372         uint64_t reserved_5_7                 : 3;
1373         uint64_t tscnt                        : 5;  /**< # of pending MIX TimeStamp Interrupts
1374                                                          For o63: TSCNT must never exceed MAX=4 (implementation
1375                                                          depth of timestamp fifo) */
1376 #else
1377         uint64_t tscnt                        : 5;
1378         uint64_t reserved_5_7                 : 3;
1379         uint64_t tstot                        : 5;
1380         uint64_t reserved_13_15               : 3;
1381         uint64_t tsavl                        : 5;
1382         uint64_t reserved_21_63               : 43;
1383 #endif
1384         } s;
1385         struct cvmx_mixx_tsctl_s              cn63xx;
1386         struct cvmx_mixx_tsctl_s              cn63xxp1;
1387 };
1388 typedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t;
1389
1390 /**
1391  * cvmx_mix#_tstamp
1392  *
1393  * MIX_TSTAMP = MIX TimeStamp Register
1394  *
1395  * Description:
1396  *  NOTE: To read the MIX_TSTAMP register, a device would issue an IOBLD64 directed at the MIO.
1397  */
1398 union cvmx_mixx_tstamp
1399 {
1400         uint64_t u64;
1401         struct cvmx_mixx_tstamp_s
1402         {
1403 #if __BYTE_ORDER == __BIG_ENDIAN
1404         uint64_t tstamp                       : 64; /**< MIX TimeStamp Value
1405                                                           When SW sets up an ORING Entry with [47]=1(TSTAMP),
1406                                                           The packet is tagged with a specal SOP w/TSTAMP flag
1407                                                           as it is sent to the AGL.
1408                                                           Later the AGL will send "sample" strobe(s) to capture
1409                                                           a global 64bit timestamp value followed by a "commit"
1410                                                           strobe which writes the last sampled value into the
1411                                                           outbound Timestamp fifo (max depth=4) and increments
1412                                                           the MIX_TSCTL[TSCNT] register to indicate the total
1413                                                           \#of pending Timestamp interrupts.
1414                                                           If the \#pending Timestamp interrupts (MIX_TSCTL[TSCNT])
1415                                                           is greater than the MIX_CTL[TS_THRESH] value, then
1416                                                           a programmable interrupt is also triggered (see:
1417                                                           MIX_ISR[TS] MIX_INTENA[TSENA]).
1418                                                           SW will then read the MIX*_TSTAMP[TSTAMP]
1419                                                           register value, and MUST THEN write the MIX_TSCTL
1420                                                           register, which will decrement MIX_TSCTL[TSCNT] register,
1421                                                           to indicate that a single timestamp interrupt has
1422                                                           been serviced.
1423                                                           NOTE: The MIO-MIX HW tracks upto MAX=4 outstanding
1424                                                           timestamped outbound packets at a time. All subsequent
1425                                                           ORING Entries w/SOP-TSTAMP will be stalled until
1426                                                           SW can service the 4 outstanding interrupts.
1427                                                           SW can read the MIX_TSCTL register to determine the
1428                                                           \#pending timestamp interrupts(TSCNT) as well as the
1429                                                           \#outstanding timestamp requests in flight(TSTOT), as
1430                                                           well as the \#of available timestamp entries (TSAVL).
1431                                                          SW NOTE: A MIX_TSTAMP read when MIX_TSCTL[TSCNT]=0, will
1432                                                          result in a return value of all zeroes. SW should only
1433                                                          read this register when MIX_ISR[TS]=1 (or when
1434                                                          MIX_TSCTL[TSCNT] != 0) to retrieve the timestamp value
1435                                                          recorded by HW. If SW reads the TSTAMP when HW has not
1436                                                          recorded a valid timestamp, then an  all zeroes value is
1437                                                          returned. */
1438 #else
1439         uint64_t tstamp                       : 64;
1440 #endif
1441         } s;
1442         struct cvmx_mixx_tstamp_s             cn63xx;
1443         struct cvmx_mixx_tstamp_s             cn63xxp1;
1444 };
1445 typedef union cvmx_mixx_tstamp cvmx_mixx_tstamp_t;
1446
1447 #endif