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49 * Support library for the hardware Packet Output unit.
51 * <hr>$Revision: 49448 $<hr>
53 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
54 #include <asm/octeon/cvmx.h>
55 #include <asm/octeon/cvmx-config.h>
56 #include <asm/octeon/cvmx-pko.h>
57 #include <asm/octeon/cvmx-helper.h>
58 #include <asm/octeon/cvmx-clock.h>
60 #if !defined(__FreeBSD__) || !defined(_KERNEL)
61 #include "executive-config.h"
64 #include "cvmx-sysinfo.h"
65 #if !defined(__FreeBSD__) || !defined(_KERNEL)
66 #include "cvmx-config.h"
69 #include "cvmx-helper.h"
73 * Internal state of packet output
76 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
79 * Call before any other calls to initialize the packet
80 * output system. This does chip global config, and should only be
84 void cvmx_pko_initialize_global(void)
87 uint64_t priority = 8;
88 cvmx_pko_reg_cmd_buf_t config;
90 /* Set the size of the PKO command buffers to an odd number of 64bit
91 words. This allows the normal two word send to stay aligned and never
92 span a comamnd word buffer. */
94 config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
95 config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
97 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
99 for (i=0; i<CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
100 cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, &priority);
102 /* If we aren't using all of the queues optimize PKO's internal memory */
103 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
105 int num_interfaces = cvmx_helper_get_number_of_interfaces();
106 int last_port = cvmx_helper_get_last_ipd_port(num_interfaces-1);
107 int max_queues = cvmx_pko_get_base_queue(last_port) + cvmx_pko_get_num_queues(last_port);
108 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
110 if (max_queues <= 32)
111 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
112 else if (max_queues <= 64)
113 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
117 if (max_queues <= 64)
118 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
119 else if (max_queues <= 128)
120 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
126 * This function does per-core initialization required by the PKO routines.
127 * This must be called on all cores that will do packet output, and must
128 * be called after the FPA has been initialized and filled with pages.
130 * @return 0 on success
133 int cvmx_pko_initialize_local(void)
141 * Enables the packet output hardware. It must already be
144 void cvmx_pko_enable(void)
146 cvmx_pko_reg_flags_t flags;
148 flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
150 cvmx_dprintf("Warning: Enabling PKO when PKO already enabled.\n");
154 flags.s.store_be =1; /* always enable big endian for 3-word command. Does nothing for 2-word */
155 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
160 * Disables the packet output. Does not affect any configuration.
162 void cvmx_pko_disable(void)
164 cvmx_pko_reg_flags_t pko_reg_flags;
165 pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
166 pko_reg_flags.s.ena_pko = 0;
167 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
171 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
174 * Reset the packet output.
176 static void __cvmx_pko_reset(void)
178 cvmx_pko_reg_flags_t pko_reg_flags;
179 pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
180 pko_reg_flags.s.reset = 1;
181 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
186 * Shutdown and free resources required by packet output.
188 void cvmx_pko_shutdown(void)
190 cvmx_pko_mem_queue_ptrs_t config;
195 for (queue=0; queue<CVMX_PKO_MAX_OUTPUT_QUEUES; queue++)
200 config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
201 config.s.queue = queue & 0x7f;
202 config.s.qos_mask = 0;
203 config.s.buf_ptr = 0;
204 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
206 cvmx_pko_reg_queue_ptrs1_t config1;
208 config1.s.qid7 = queue >> 7;
209 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
211 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
212 cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
219 * Configure a output port and the associated queues for use.
221 * @param port Port to configure.
222 * @param base_queue First queue number to associate with this port.
223 * @param num_queues Number of queues to associate with this port
224 * @param priority Array of priority levels for each queue. Values are
225 * allowed to be 0-8. A value of 8 get 8 times the traffic
226 * of a value of 1. A value of 0 indicates that no rounds
227 * will be participated in. These priorities can be changed
228 * on the fly while the pko is enabled. A priority of 9
229 * indicates that static priority should be used. If static
230 * priority is used all queues with static priority must be
231 * contiguous starting at the base_queue, and lower numbered
232 * queues have higher priority than higher numbered queues.
233 * There must be num_queues elements in the array.
235 cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[])
237 cvmx_pko_status_t result_code;
239 cvmx_pko_mem_queue_ptrs_t config;
240 cvmx_pko_reg_queue_ptrs1_t config1;
241 int static_priority_base = -1;
242 int static_priority_end = -1;
245 if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID))
247 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", (unsigned long long)port);
248 return CVMX_PKO_INVALID_PORT;
251 if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES)
253 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", (unsigned long long)(base_queue + num_queues));
254 return CVMX_PKO_INVALID_QUEUE;
257 if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
259 /* Validate the static queue priority setup and set static_priority_base and static_priority_end
261 for (queue = 0; queue < num_queues; queue++)
263 /* Find first queue of static priority */
264 if (static_priority_base == -1 && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
265 static_priority_base = queue;
266 /* Find last queue of static priority */
267 if (static_priority_base != -1 && static_priority_end == -1 && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY && queue)
268 static_priority_end = queue - 1;
269 else if (static_priority_base != -1 && static_priority_end == -1 && queue == num_queues - 1)
270 static_priority_end = queue; /* all queues are static priority */
271 /* Check to make sure all static priority queues are contiguous. Also catches some cases of
272 ** static priorites not starting at queue 0. */
273 if (static_priority_end != -1 && (int)queue > static_priority_end && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
275 cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d\n", (int)queue, static_priority_end);
276 return CVMX_PKO_INVALID_PRIORITY;
279 if (static_priority_base > 0)
281 cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues don't start at base queue. sq: %d\n", static_priority_base);
282 return CVMX_PKO_INVALID_PRIORITY;
285 cvmx_dprintf("Port %d: Static priority queue base: %d, end: %d\n", port, static_priority_base, static_priority_end);
288 /* At this point, static_priority_base and static_priority_end are either both -1,
289 ** or are valid start/end queue numbers */
291 result_code = CVMX_PKO_SUCCESS;
294 cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
297 for (queue = 0; queue < num_queues; queue++)
299 uint64_t *buf_ptr = NULL;
302 config1.s.idx3 = queue >> 3;
303 config1.s.qid7 = (base_queue + queue) >> 7;
306 config.s.tail = queue == (num_queues - 1);
307 config.s.index = queue;
308 config.s.port = port;
309 config.s.queue = base_queue + queue;
311 config.s.static_p = static_priority_base >= 0;
312 config.s.static_q = (int)queue <= static_priority_end;
313 config.s.s_tail = (int)queue == static_priority_end;
314 /* Convert the priority into an enable bit field. Try to space the bits
315 out evenly so the packet don't get grouped up */
316 switch ((int)priority[queue])
318 case 0: config.s.qos_mask = 0x00; break;
319 case 1: config.s.qos_mask = 0x01; break;
320 case 2: config.s.qos_mask = 0x11; break;
321 case 3: config.s.qos_mask = 0x49; break;
322 case 4: config.s.qos_mask = 0x55; break;
323 case 5: config.s.qos_mask = 0x57; break;
324 case 6: config.s.qos_mask = 0x77; break;
325 case 7: config.s.qos_mask = 0x7f; break;
326 case 8: config.s.qos_mask = 0xff; break;
327 case CVMX_PKO_QUEUE_STATIC_PRIORITY:
328 config.s.qos_mask = 0xff;
331 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n", (unsigned long long)priority[queue]);
332 config.s.qos_mask = 0xff;
333 result_code = CVMX_PKO_INVALID_PRIORITY;
337 if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
339 cvmx_cmd_queue_result_t cmd_res = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO(base_queue + queue),
340 CVMX_PKO_MAX_QUEUE_DEPTH,
341 CVMX_FPA_OUTPUT_BUFFER_POOL,
342 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST*8);
343 if (cmd_res != CVMX_CMD_QUEUE_SUCCESS)
347 case CVMX_CMD_QUEUE_NO_MEMORY:
348 cvmx_dprintf("ERROR: cvmx_pko_config_port: Unable to allocate output buffer.\n");
349 return(CVMX_PKO_NO_MEMORY);
350 case CVMX_CMD_QUEUE_ALREADY_SETUP:
351 cvmx_dprintf("ERROR: cvmx_pko_config_port: Port already setup.\n");
352 return(CVMX_PKO_PORT_ALREADY_SETUP);
353 case CVMX_CMD_QUEUE_INVALID_PARAM:
355 cvmx_dprintf("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
356 return(CVMX_PKO_CMD_QUEUE_INIT_ERROR);
360 buf_ptr = (uint64_t*)cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO(base_queue + queue));
361 config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
364 config.s.buf_ptr = 0;
368 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
370 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
372 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
380 * Show map of ports -> queues for different cores.
382 void cvmx_pko_show_queue_map()
385 int pko_output_ports = 36;
387 cvmx_dprintf("port");
388 for(port=0; port<pko_output_ports; port++)
389 cvmx_dprintf("%3d ", port);
392 for(core=0; core<CVMX_MAX_CORES; core++)
394 cvmx_dprintf("\n%2d: ", core);
395 for(port=0; port<pko_output_ports; port++)
397 cvmx_dprintf("%3d ", cvmx_pko_get_base_queue_per_core(port, core));
406 * Rate limit a PKO port to a max packets/sec. This function is only
407 * supported on CN51XX and higher, excluding CN58XX.
409 * @param port Port to rate limit
410 * @param packets_s Maximum packet/sec
411 * @param burst Maximum number of packets to burst in a row before rate
414 * @return Zero on success, negative on failure
416 int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
418 cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
419 cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
421 pko_mem_port_rate0.u64 = 0;
422 pko_mem_port_rate0.s.pid = port;
423 pko_mem_port_rate0.s.rate_pkt = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / packets_s / 16;
424 /* No cost per word since we are limited by packets/sec, not bits/sec */
425 pko_mem_port_rate0.s.rate_word = 0;
427 pko_mem_port_rate1.u64 = 0;
428 pko_mem_port_rate1.s.pid = port;
429 pko_mem_port_rate1.s.rate_lim = ((uint64_t)pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
431 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
432 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
438 * Rate limit a PKO port to a max bits/sec. This function is only
439 * supported on CN51XX and higher, excluding CN58XX.
441 * @param port Port to rate limit
442 * @param bits_s PKO rate limit in bits/sec
443 * @param burst Maximum number of bits to burst before rate
446 * @return Zero on success, negative on failure
448 int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
450 cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
451 cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
452 uint64_t clock_rate = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
453 uint64_t tokens_per_bit = clock_rate*16 / bits_s;
455 pko_mem_port_rate0.u64 = 0;
456 pko_mem_port_rate0.s.pid = port;
457 /* Each packet has a 12 bytes of interframe gap, an 8 byte preamble, and a
458 4 byte CRC. These are not included in the per word count. Multiply
459 by 8 to covert to bits and divide by 256 for limit granularity */
460 pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
461 /* Each 8 byte word has 64bits */
462 pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
464 pko_mem_port_rate1.u64 = 0;
465 pko_mem_port_rate1.s.pid = port;
466 pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
468 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
469 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
473 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */