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44 * Interface to the hardware Packet Output unit.
46 * Starting with SDK 1.7.0, the PKO output functions now support
47 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
48 * function similarly to previous SDKs by using POW atomic tags
49 * to preserve ordering and exclusivity. As a new option, you
50 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
51 * memory based locking instead. This locking has the advantage
52 * of not affecting the tag state but doesn't preserve packet
53 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
54 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
55 * with hand tuned fast path code.
57 * Some of other SDK differences visible to the command command
59 * - PKO indexes are no longer stored in the FAU. A large
60 * percentage of the FAU register block used to be tied up
61 * maintaining PKO queue pointers. These are now stored in a
63 * - The PKO <b>use_locking</b> parameter can now have a global
64 * effect. Since all application use the same named block,
65 * queue locking correctly applies across all operating
66 * systems when using CVMX_PKO_LOCK_CMD_QUEUE.
67 * - PKO 3 word commands are now supported. Use
68 * cvmx_pko_send_packet_finish3().
70 * <hr>$Revision: 49448 $<hr>
74 #ifndef __CVMX_PKO_H__
75 #define __CVMX_PKO_H__
77 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
78 #include "cvmx-config.h"
79 #include "cvmx-pko-defs.h"
81 # ifndef CVMX_DONT_INCLUDE_CONFIG
82 # include "executive-config.h"
83 # ifdef CVMX_ENABLE_PKO_FUNCTIONS
84 # include "cvmx-config.h"
93 #include "cvmx-cmd-queue.h"
95 /* Adjust the command buffer size by 1 word so that in the case of using only
96 ** two word PKO commands no command words stradle buffers. The useful values
97 ** for this are 0 and 1. */
98 #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
104 #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
105 #define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 256 : 128)
106 #define CVMX_PKO_NUM_OUTPUT_PORTS ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 44 : 40)
107 #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 /* use this for queues that are not used */
108 #define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
109 #define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF
110 #define CVMX_PKO_MAX_QUEUE_DEPTH 0
115 CVMX_PKO_INVALID_PORT,
116 CVMX_PKO_INVALID_QUEUE,
117 CVMX_PKO_INVALID_PRIORITY,
119 CVMX_PKO_PORT_ALREADY_SETUP,
120 CVMX_PKO_CMD_QUEUE_INIT_ERROR
124 * This enumeration represents the differnet locking modes supported by PKO.
128 CVMX_PKO_LOCK_NONE = 0, /**< PKO doesn't do any locking. It is the responsibility
129 of the application to make sure that no other core is
130 accessing the same queue at the smae time */
131 CVMX_PKO_LOCK_ATOMIC_TAG = 1, /**< PKO performs an atomic tagswitch to insure exclusive
132 access to the output queue. This will maintain
133 packet ordering on output */
134 CVMX_PKO_LOCK_CMD_QUEUE = 2, /**< PKO uses the common command queue locks to insure
135 exclusive access to the output queue. This is a memory
136 based ll/sc. This is the most portable locking
145 } cvmx_pko_port_status_t;
148 * This structure defines the address to use on a packet enqueue
155 cvmx_mips_space_t mem_space : 2; /**< Must CVMX_IO_SEG */
156 uint64_t reserved :13; /**< Must be zero */
157 uint64_t is_io : 1; /**< Must be one */
158 uint64_t did : 8; /**< The ID of the device on the non-coherent bus */
159 uint64_t reserved2 : 4; /**< Must be zero */
160 uint64_t reserved3 :18; /**< Must be zero */
161 uint64_t port : 6; /**< The hardware likes to have the output port in addition to the output queue */
162 uint64_t queue : 9; /**< The output queue to send the packet to (0-127 are legal) */
163 uint64_t reserved4 : 3; /**< Must be zero */
165 } cvmx_pko_doorbell_address_t;
168 * Structure of the first packet output command word.
175 cvmx_fau_op_size_t size1 : 2; /**< The size of the reg1 operation - could be 8, 16, 32, or 64 bits */
176 cvmx_fau_op_size_t size0 : 2; /**< The size of the reg0 operation - could be 8, 16, 32, or 64 bits */
177 uint64_t subone1 : 1; /**< If set, subtract 1, if clear, subtract packet size */
178 uint64_t reg1 :11; /**< The register, subtract will be done if reg1 is non-zero */
179 uint64_t subone0 : 1; /**< If set, subtract 1, if clear, subtract packet size */
180 uint64_t reg0 :11; /**< The register, subtract will be done if reg0 is non-zero */
181 uint64_t le : 1; /**< When set, interpret segment pointer and segment bytes in little endian order */
182 uint64_t n2 : 1; /**< When set, packet data not allocated in L2 cache by PKO */
183 uint64_t wqp : 1; /**< If set and rsp is set, word3 contains a pointer to a work queue entry */
184 uint64_t rsp : 1; /**< If set, the hardware will send a response when done */
185 uint64_t gather : 1; /**< If set, the supplied pkt_ptr is really a pointer to a list of pkt_ptr's */
186 uint64_t ipoffp1 : 7; /**< If ipoffp1 is non zero, (ipoffp1-1) is the number of bytes to IP header,
187 and the hardware will calculate and insert the UDP/TCP checksum */
188 uint64_t ignore_i : 1; /**< If set, ignore the I bit (force to zero) from all pointer structures */
189 uint64_t dontfree : 1; /**< If clear, the hardware will attempt to free the buffers containing the packet */
190 uint64_t segs : 6; /**< The total number of segs in the packet, if gather set, also gather list length */
191 uint64_t total_bytes :16; /**< Including L2, but no trailing CRC */
193 } cvmx_pko_command_word0_t;
195 /* CSR typedefs have been moved to cvmx-pko-defs.h */
198 * Definition of internal state for Packet output processing
202 uint64_t * start_ptr; /**< ptr to start of buffer, offset kept in FAU reg */
203 } cvmx_pko_state_elem_t;
206 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
208 * Call before any other calls to initialize the packet
211 extern void cvmx_pko_initialize_global(void);
212 extern int cvmx_pko_initialize_local(void);
218 * Enables the packet output hardware. It must already be
221 extern void cvmx_pko_enable(void);
225 * Disables the packet output. Does not affect any configuration.
227 extern void cvmx_pko_disable(void);
231 * Shutdown and free resources required by packet output.
234 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
235 extern void cvmx_pko_shutdown(void);
239 * Configure a output port and the associated queues for use.
241 * @param port Port to configure.
242 * @param base_queue First queue number to associate with this port.
243 * @param num_queues Number of queues t oassociate with this port
244 * @param priority Array of priority levels for each queue. Values are
245 * allowed to be 1-8. A value of 8 get 8 times the traffic
246 * of a value of 1. There must be num_queues elements in the
249 extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[]);
253 * Ring the packet output doorbell. This tells the packet
254 * output hardware that "len" command words have been added
255 * to its pending list. This command includes the required
256 * CVMX_SYNCWS before the doorbell ring.
258 * @param port Port the packet is for
259 * @param queue Queue the packet is for
260 * @param len Length of the command in 64 bit words
262 static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, uint64_t len)
264 cvmx_pko_doorbell_address_t ptr;
267 ptr.s.mem_space = CVMX_IO_SEG;
268 ptr.s.did = CVMX_OCT_DID_PKT_SEND;
272 CVMX_SYNCWS; /* Need to make sure output queue data is in DRAM before doorbell write */
273 cvmx_write_io(ptr.u64, len);
278 * Prepare to send a packet. This may initiate a tag switch to
279 * get exclusive access to the output queue structure, and
280 * performs other prep work for the packet send operation.
282 * cvmx_pko_send_packet_finish() MUST be called after this function is called,
283 * and must be called with the same port/queue/use_locking arguments.
285 * The use_locking parameter allows the caller to use three
286 * possible locking modes.
287 * - CVMX_PKO_LOCK_NONE
288 * - PKO doesn't do any locking. It is the responsibility
289 * of the application to make sure that no other core
290 * is accessing the same queue at the smae time.
291 * - CVMX_PKO_LOCK_ATOMIC_TAG
292 * - PKO performs an atomic tagswitch to insure exclusive
293 * access to the output queue. This will maintain
294 * packet ordering on output.
295 * - CVMX_PKO_LOCK_CMD_QUEUE
296 * - PKO uses the common command queue locks to insure
297 * exclusive access to the output queue. This is a
298 * memory based ll/sc. This is the most portable
301 * NOTE: If atomic locking is used, the POW entry CANNOT be
302 * descheduled, as it does not contain a valid WQE pointer.
304 * @param port Port to send it on
305 * @param queue Queue to use
307 * CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
309 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
310 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, cvmx_pko_lock_t use_locking)
312 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
314 /* Must do a full switch here to handle all cases. We use a fake WQE pointer, as the POW does
315 ** not access this memory. The WQE pointer and group are only used if this work is descheduled,
316 ** which is not supported by the cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish combination.
317 ** Note that this is a special case in which these fake values can be used - this is not a general technique.
319 uint32_t tag = CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT | (CVMX_TAG_SUBGROUP_MASK & queue);
320 cvmx_pow_tag_sw_full((cvmx_wqe_t *)cvmx_phys_to_ptr(0x80), tag, CVMX_POW_TAG_TYPE_ATOMIC, 0);
326 * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
327 * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
328 * cvmx_pko_send_packet_finish().
330 * @param port Port to send it on
331 * @param queue Queue to use
333 * PKO HW command word
334 * @param packet Packet to send
336 * CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
338 * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
340 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, uint64_t queue,
341 cvmx_pko_command_word0_t pko_command,
342 cvmx_buf_ptr_t packet, cvmx_pko_lock_t use_locking)
344 cvmx_cmd_queue_result_t result;
345 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
346 cvmx_pow_tag_sw_wait();
347 result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
348 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
351 if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
353 cvmx_pko_doorbell(port, queue, 2);
354 return CVMX_PKO_SUCCESS;
356 else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
358 return CVMX_PKO_NO_MEMORY;
362 return CVMX_PKO_INVALID_QUEUE;
368 * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
369 * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
370 * cvmx_pko_send_packet_finish().
372 * @param port Port to send it on
373 * @param queue Queue to use
375 * PKO HW command word
376 * @param packet Packet to send
377 * @param addr Plysical address of a work queue entry or physical address to zero on complete.
379 * CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
381 * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
383 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t port, uint64_t queue,
384 cvmx_pko_command_word0_t pko_command,
385 cvmx_buf_ptr_t packet, uint64_t addr, cvmx_pko_lock_t use_locking)
387 cvmx_cmd_queue_result_t result;
388 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
389 cvmx_pow_tag_sw_wait();
390 result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
391 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
395 if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
397 cvmx_pko_doorbell(port, queue, 3);
398 return CVMX_PKO_SUCCESS;
400 else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
402 return CVMX_PKO_NO_MEMORY;
406 return CVMX_PKO_INVALID_QUEUE;
411 * Return the pko output queue associated with a port and a specific core.
412 * In normal mode (PKO lockless operation is disabled), the value returned
415 * @param port Port number
416 * @param core Core to get queue for
418 * @return Core-specific output queue
420 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
422 #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
423 #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
425 #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
426 #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
428 #ifndef CVMX_PKO_QUEUES_PER_PORT_SRIO0
429 /* We use two queues per port for SRIO0. Having two queues per
430 port with two ports gives us four queues, one for each mailbox */
431 #define CVMX_PKO_QUEUES_PER_PORT_SRIO0 2
433 #ifndef CVMX_PKO_QUEUES_PER_PORT_SRIO1
434 /* We use two queues per port for SRIO1. Having two queues per
435 port with two ports gives us four queues, one for each mailbox */
436 #define CVMX_PKO_QUEUES_PER_PORT_SRIO1 2
438 if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
439 return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
440 else if (port >=16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
441 return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
442 (port-16) * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
443 else if ((port >= 32) && (port < 36))
444 return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
445 CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
446 (port-32) * CVMX_PKO_QUEUES_PER_PORT_PCI;
447 else if ((port >= 36) && (port < 40))
448 return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
449 CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
450 4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
451 (port-36) * CVMX_PKO_QUEUES_PER_PORT_LOOP;
452 else if ((port >= 40) && (port < 42))
453 return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
454 CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
455 4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
456 4 * CVMX_PKO_QUEUES_PER_PORT_LOOP +
457 (port-40) * CVMX_PKO_QUEUES_PER_PORT_SRIO0;
458 else if ((port >= 42) && (port < 44))
459 return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
460 CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
461 4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
462 4 * CVMX_PKO_QUEUES_PER_PORT_LOOP +
463 2 * CVMX_PKO_QUEUES_PER_PORT_SRIO0 +
464 (port-42) * CVMX_PKO_QUEUES_PER_PORT_SRIO1;
466 /* Given the limit on the number of ports we can map to
467 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
468 * divided among all cores), the remaining unmapped ports
469 * are assigned an illegal queue number */
470 return CVMX_PKO_ILLEGAL_QUEUE;
474 * For a given port number, return the base pko output queue
477 * @param port Port number
478 * @return Base output queue
480 static inline int cvmx_pko_get_base_queue(int port)
482 return cvmx_pko_get_base_queue_per_core(port, 0);
486 * For a given port number, return the number of pko output queues.
488 * @param port Port number
489 * @return Number of output queues
491 static inline int cvmx_pko_get_num_queues(int port)
494 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
496 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
498 return CVMX_PKO_QUEUES_PER_PORT_PCI;
500 return CVMX_PKO_QUEUES_PER_PORT_LOOP;
502 return CVMX_PKO_QUEUES_PER_PORT_SRIO0;
504 return CVMX_PKO_QUEUES_PER_PORT_SRIO1;
510 * Get the status counters for a port.
512 * @param port_num Port number to get statistics for.
513 * @param clear Set to 1 to clear the counters after they are read
514 * @param status Where to put the results.
516 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pko_port_status_t *status)
518 cvmx_pko_reg_read_idx_t pko_reg_read_idx;
519 cvmx_pko_mem_count0_t pko_mem_count0;
520 cvmx_pko_mem_count1_t pko_mem_count1;
522 pko_reg_read_idx.u64 = 0;
523 pko_reg_read_idx.s.index = port_num;
524 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
526 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
527 status->packets = pko_mem_count0.s.count;
530 pko_mem_count0.s.count = port_num;
531 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
534 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
535 status->octets = pko_mem_count1.s.count;
538 pko_mem_count1.s.count = port_num;
539 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
542 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
544 cvmx_pko_mem_debug9_t debug9;
545 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
546 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
547 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
548 status->doorbell = debug9.cn38xx.doorbell;
552 cvmx_pko_mem_debug8_t debug8;
553 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
554 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
555 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
556 status->doorbell = debug8.cn58xx.doorbell;
562 * Rate limit a PKO port to a max packets/sec. This function is only
563 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
565 * @param port Port to rate limit
566 * @param packets_s Maximum packet/sec
567 * @param burst Maximum number of packets to burst in a row before rate
570 * @return Zero on success, negative on failure
572 extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
575 * Rate limit a PKO port to a max bits/sec. This function is only
576 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
578 * @param port Port to rate limit
579 * @param bits_s PKO rate limit in bits/sec
580 * @param burst Maximum number of bits to burst before rate
583 * @return Zero on success, negative on failure
585 extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
587 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */
593 #endif /* __CVMX_PKO_H__ */