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49 * Interface to the TWSI / I2C bus
51 * <hr>$Revision: 49448 $<hr>
54 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55 #include <linux/i2c.h>
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-twsi.h>
61 #include "cvmx-twsi.h"
62 #include "cvmx-csr-db.h"
65 //#define PRINT_TWSI_CONFIG
66 #ifdef PRINT_TWSI_CONFIG
67 #define twsi_printf printf
69 #define twsi_printf(...)
70 #define cvmx_csr_db_decode(...)
73 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
74 static struct i2c_adapter *__cvmx_twsix_get_adapter(int twsi_id)
76 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
78 wait_queue_head_t queue;
79 struct i2c_adapter adap;
83 resource_size_t twsi_phys;
84 void __iomem *twsi_base;
85 resource_size_t regsize;
89 struct i2c_adapter *adapter;
90 struct octeon_i2c *i2c;
92 adapter = i2c_get_adapter(0);
95 i2c = container_of(adapter, struct octeon_i2c, adap);
96 return &i2c[twsi_id].adap;
105 * Do a twsi read from a 7 bit device address using an (optional) internal address.
106 * Up to 8 bytes can be read at a time.
108 * @param twsi_id which Octeon TWSI bus to use
109 * @param dev_addr Device address (7 bit)
110 * @param internal_addr
111 * Internal address. Can be 0, 1 or 2 bytes in width
112 * @param num_bytes Number of data bytes to read
113 * @param ia_width_bytes
114 * Internal address size in bytes (0, 1, or 2)
115 * @param data Pointer argument where the read data is returned.
117 * @return read data returned in 'data' argument
118 * Number of bytes read on success
121 int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data)
123 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
124 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
125 struct i2c_adapter *adapter;
128 struct i2c_msg msg[2];
132 if (ia_width_bytes == 0)
133 return cvmx_twsix_read(twsi_id, dev_addr, num_bytes, data);
135 BUG_ON(ia_width_bytes > 2);
136 BUG_ON(num_bytes > 8 || num_bytes < 1);
138 adapter = __cvmx_twsix_get_adapter(twsi_id);
142 for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
143 addr_buf[j] = (u8)(internal_addr >> (i * 8));
145 msg[0].addr = dev_addr;
147 msg[0].len = ia_width_bytes;
148 msg[0].buf = addr_buf;
150 msg[1].addr = dev_addr;
151 msg[1].flags = I2C_M_RD;
152 msg[1].len = num_bytes;
153 msg[1].buf = data_buf;
155 i = i2c_transfer(adapter, msg, 2);
157 i2c_put_adapter(adapter);
161 for (i = 0; i < num_bytes; i++)
162 r = (r << 8) | data_buf[i];
169 BUG(); /* The I2C driver is not compiled in */
172 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
173 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
175 if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
182 sw_twsi_val.s.sovr = 1;
183 sw_twsi_val.s.size = num_bytes - 1;
184 sw_twsi_val.s.a = dev_addr;
186 if (ia_width_bytes > 0) {
187 sw_twsi_val.s.op = 1;
188 sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
189 sw_twsi_val.s.eop_ia = internal_addr & 0x7;
191 if (ia_width_bytes == 2) {
192 sw_twsi_val.s.eia = 1;
193 twsi_ext.s.ia = internal_addr >> 8;
194 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
197 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
198 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
199 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
201 twsi_printf("Results:\n");
202 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
203 if (!sw_twsi_val.s.r)
206 *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
208 twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
209 *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
216 * Read from a TWSI device (7 bit device address only) without generating any
217 * internal addresses.
218 * Read from 1-8 bytes and returns them in the data pointer.
220 * @param twsi_id TWSI interface on Octeon to use
221 * @param dev_addr TWSI device address (7 bit only)
222 * @param num_bytes number of bytes to read
223 * @param data Pointer to data read from TWSI device
225 * @return Number of bytes read on success
228 int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data)
230 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
231 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
232 struct i2c_adapter *adapter;
234 struct i2c_msg msg[1];
238 BUG_ON(num_bytes > 8 || num_bytes < 1);
240 adapter = __cvmx_twsix_get_adapter(twsi_id);
244 msg[0].addr = dev_addr;
245 msg[0].flags = I2C_M_RD;
246 msg[0].len = num_bytes;
247 msg[0].buf = data_buf;
249 i = i2c_transfer(adapter, msg, 1);
251 i2c_put_adapter(adapter);
255 for (i = 0; i < num_bytes; i++)
256 r = (r << 8) | data_buf[i];
263 BUG(); /* The I2C driver is not compiled in */
266 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
267 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
269 if (num_bytes > 8 || num_bytes < 1)
275 sw_twsi_val.s.a = dev_addr;
276 sw_twsi_val.s.sovr = 1;
277 sw_twsi_val.s.size = num_bytes - 1;
279 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
280 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
281 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
283 twsi_printf("Results:\n");
284 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
285 if (!sw_twsi_val.s.r)
288 *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
290 twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
291 *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
298 * Perform a twsi write operation to a 7 bit device address.
300 * Note that many eeprom devices have page restrictions regarding address boundaries
301 * that can be crossed in one write operation. This is device dependent, and this routine
302 * does nothing in this regard.
303 * This command does not generate any internal addressess.
305 * @param twsi_id Octeon TWSI interface to use
306 * @param dev_addr TWSI device address
307 * @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
308 * @param data Data to write
310 * @return 0 on success
313 int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data)
315 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
316 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
317 struct i2c_adapter *adapter;
319 struct i2c_msg msg[1];
322 BUG_ON(num_bytes > 8 || num_bytes < 1);
324 adapter = __cvmx_twsix_get_adapter(twsi_id);
328 for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
329 data_buf[j] = (u8)(data >> (i * 8));
331 msg[1].addr = dev_addr;
333 msg[1].len = num_bytes;
334 msg[1].buf = data_buf;
336 i = i2c_transfer(adapter, msg, 1);
338 i2c_put_adapter(adapter);
345 BUG(); /* The I2C driver is not compiled in */
348 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
350 if (num_bytes > 8 || num_bytes < 1)
355 sw_twsi_val.s.a = dev_addr;
356 sw_twsi_val.s.d = data & 0xffffffff;
357 sw_twsi_val.s.sovr = 1;
358 sw_twsi_val.s.size = num_bytes - 1;
360 /* Upper four bytes go into a separate register */
361 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
363 twsi_ext.s.d = data >> 32;
364 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
366 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
367 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
368 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
370 twsi_printf("Results:\n");
371 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
372 if (!sw_twsi_val.s.r)
380 * Write 1-8 bytes to a TWSI device using an internal address.
382 * @param twsi_id which TWSI interface on Octeon to use
383 * @param dev_addr TWSI device address (7 bit only)
384 * @param internal_addr
385 * TWSI internal address (0, 8, or 16 bits)
386 * @param num_bytes Number of bytes to write (1-8)
387 * @param ia_width_bytes
388 * internal address width, in bytes (0, 1, 2)
389 * @param data Data to write. Data is written MSB first on the twsi bus, and only the lower
390 * num_bytes bytes of the argument are valid. (If a 2 byte write is done, only
391 * the low 2 bytes of the argument is used.
393 * @return Number of bytes read on success,
396 int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
398 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
399 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
400 struct i2c_adapter *adapter;
403 struct i2c_msg msg[2];
406 if (ia_width_bytes == 0)
407 return cvmx_twsix_write(twsi_id, dev_addr, num_bytes, data);
409 BUG_ON(ia_width_bytes > 2);
410 BUG_ON(num_bytes > 8 || num_bytes < 1);
412 adapter = __cvmx_twsix_get_adapter(twsi_id);
417 for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
418 addr_buf[j] = (u8)(internal_addr >> (i * 8));
420 for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
421 data_buf[j] = (u8)(data >> (i * 8));
423 msg[0].addr = dev_addr;
425 msg[0].len = ia_width_bytes;
426 msg[0].buf = addr_buf;
428 msg[1].addr = dev_addr;
430 msg[1].len = num_bytes;
431 msg[1].buf = data_buf;
433 i = i2c_transfer(adapter, msg, 2);
435 i2c_put_adapter(adapter);
438 /* Poll until reads succeed, or polling times out */
442 if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
452 BUG(); /* The I2C driver is not compiled in */
455 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
456 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
459 if (num_bytes < 1 || num_bytes > 8 || ia_width_bytes < 0 || ia_width_bytes > 2)
466 sw_twsi_val.s.sovr = 1;
467 sw_twsi_val.s.size = num_bytes - 1;
468 sw_twsi_val.s.a = dev_addr;
469 sw_twsi_val.s.d = 0xFFFFFFFF & data;
471 if (ia_width_bytes > 0) {
472 sw_twsi_val.s.op = 1;
473 sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
474 sw_twsi_val.s.eop_ia = internal_addr & 0x7;
476 if (ia_width_bytes == 2) {
477 sw_twsi_val.s.eia = 1;
478 twsi_ext.s.ia = internal_addr >> 8;
481 twsi_ext.s.d = data >> 32;
483 twsi_printf("%s: twsi_id=%x, dev_addr=%x, internal_addr=%x\n\tnum_bytes=%d, ia_width_bytes=%d, data=%lx\n",
484 __FUNCTION__, twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
485 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
486 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
487 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
488 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
489 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
491 twsi_printf("Results:\n");
492 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
494 /* Poll until reads succeed, or polling times out */
498 if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)