1 /***********************license start***************
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7 * modification, are permitted provided that the following conditions are
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBNX_TYPEDEFS_H__
53 #define __CVMX_USBNX_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
64 cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
65 return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull;
68 #define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull)
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
71 static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
78 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
79 cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
80 return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull;
83 #define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull)
85 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
86 static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
93 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
94 cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
95 return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull;
98 #define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull)
100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
101 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
109 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull;
113 #define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
124 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id);
125 return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull;
128 #define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull)
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
131 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
139 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id);
140 return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull;
143 #define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull)
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
146 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
153 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
154 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id);
155 return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull;
158 #define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull)
160 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
161 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
169 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id);
170 return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull;
173 #define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull)
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
183 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
184 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id);
185 return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull;
188 #define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull)
190 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
191 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
198 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
199 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id);
200 return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull;
203 #define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull)
205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
206 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
214 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id);
215 return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull;
218 #define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull)
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
221 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
229 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id);
230 return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull;
233 #define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull)
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
236 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
243 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
244 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id);
245 return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull;
248 #define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull)
250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
251 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
258 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
259 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id);
260 return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull;
263 #define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull)
265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
266 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
274 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id);
275 return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull;
278 #define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull)
280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
281 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
289 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id);
290 return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull;
293 #define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull)
295 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
296 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
302 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
303 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
304 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id);
305 return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull;
308 #define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull)
310 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
311 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
319 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id);
320 return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull;
323 #define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull)
325 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
326 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
334 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id);
335 return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull;
338 #define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull)
340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
341 static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
348 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
349 cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id);
350 return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull;
353 #define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull)
355 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
356 static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
363 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
364 cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id);
365 return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull;
368 #define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull)
370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
371 static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
378 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
379 cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id);
380 return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull;
383 #define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull)
385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
386 static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
392 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
393 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
394 cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
395 return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull;
398 #define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull)
402 * cvmx_usbn#_bist_status
404 * USBN_BIST_STATUS = USBN's Control and Status
406 * Contain general control bits and status information for the USBN.
408 union cvmx_usbnx_bist_status
411 struct cvmx_usbnx_bist_status_s
413 #if __BYTE_ORDER == __BIG_ENDIAN
414 uint64_t reserved_7_63 : 57;
415 uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */
416 uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */
417 uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */
418 uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */
419 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */
420 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */
421 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */
423 uint64_t nof_bis : 1;
424 uint64_t nif_bis : 1;
425 uint64_t usbc_bis : 1;
426 uint64_t n2uf_bis : 1;
427 uint64_t e2hc_bis : 1;
428 uint64_t u2nf_bis : 1;
429 uint64_t u2nc_bis : 1;
430 uint64_t reserved_7_63 : 57;
433 struct cvmx_usbnx_bist_status_cn30xx
435 #if __BYTE_ORDER == __BIG_ENDIAN
436 uint64_t reserved_3_63 : 61;
437 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */
438 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */
439 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */
441 uint64_t nof_bis : 1;
442 uint64_t nif_bis : 1;
443 uint64_t usbc_bis : 1;
444 uint64_t reserved_3_63 : 61;
447 struct cvmx_usbnx_bist_status_cn30xx cn31xx;
448 struct cvmx_usbnx_bist_status_s cn50xx;
449 struct cvmx_usbnx_bist_status_s cn52xx;
450 struct cvmx_usbnx_bist_status_s cn52xxp1;
451 struct cvmx_usbnx_bist_status_s cn56xx;
452 struct cvmx_usbnx_bist_status_s cn56xxp1;
454 typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t;
459 * USBN_CLK_CTL = USBN's Clock Control
461 * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
463 union cvmx_usbnx_clk_ctl
466 struct cvmx_usbnx_clk_ctl_s
468 #if __BYTE_ORDER == __BIG_ENDIAN
469 uint64_t reserved_20_63 : 44;
470 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
472 Also see the field DIVIDE. DIVIDE2<1> must currently
473 be zero because it is not implemented, so the maximum
474 ratio of eclk/hclk is currently 16.
475 The actual divide number for hclk is:
476 (DIVIDE2 + 1) * (DIVIDE + 1) */
477 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
478 generate the hclk in the USB Subsystem is held
479 in reset. This bit must be set to '0' before
480 changing the value os DIVIDE in this register.
481 The reset to the HCLK_DIVIDERis also asserted
482 when core reset is asserted. */
483 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
484 '1' USB-PHY XO block is powered-down during
486 '0' USB-PHY XO block is powered-up during
488 The value of this field must be set while POR is
490 uint64_t reserved_14_15 : 2;
491 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
492 remain powered in Suspend Mode.
493 '1' The USB-PHY XO Bias, Bandgap and PLL are
494 powered down in suspend mode.
495 The value of this field must be set while POR is
497 uint64_t p_c_sel : 2; /**< Phy clock speed select.
498 Selects the reference clock / crystal frequency.
500 '10': 48 MHz (reserved when a crystal is used)
501 '01': 24 MHz (reserved when a crystal is used)
503 The value of this field must be set while POR is
505 NOTE: if a crystal is used as a reference clock,
506 this field must be set to 12 MHz. */
507 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
508 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
509 in the USBC, for normal operation this must be '0'. */
510 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
511 to '1' transition. */
512 uint64_t por : 1; /**< Power On Reset for the PHY.
513 Resets all the PHYS registers and state machines. */
514 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
515 '0' the hclk will not be generated. SEE DIVIDE
516 field of this register. */
517 uint64_t prst : 1; /**< When this field is '0' the reset associated with
518 the phy_clk functionality in the USB Subsystem is
519 help in reset. This bit should not be set to '1'
520 until the time it takes 6 clocks (hclk or phy_clk,
521 whichever is slower) has passed. Under normal
522 operation once this bit is set to '1' it should not
524 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
525 the hclk functioanlity in the USB Subsystem is
526 held in reset.This bit should not be set to '1'
527 until 12ms after phy_clk is stable. Under normal
528 operation, once this bit is set to '1' it should
529 not be set to '0'. */
530 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
531 is the eclk frequency divided by the value of
532 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
533 DIVIDE2 of this register.
534 The hclk frequency should be less than 125Mhz.
535 After writing a value to this field the SW should
536 read the field for the value written.
537 The ENABLE field of this register should not be set
538 until AFTER this field is set and then read. */
546 uint64_t sd_mode : 2;
547 uint64_t cdiv_byp : 1;
548 uint64_t p_c_sel : 2;
549 uint64_t p_com_on : 1;
550 uint64_t reserved_14_15 : 2;
552 uint64_t hclk_rst : 1;
553 uint64_t divide2 : 2;
554 uint64_t reserved_20_63 : 44;
557 struct cvmx_usbnx_clk_ctl_cn30xx
559 #if __BYTE_ORDER == __BIG_ENDIAN
560 uint64_t reserved_18_63 : 46;
561 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
562 generate the hclk in the USB Subsystem is held
563 in reset. This bit must be set to '0' before
564 changing the value os DIVIDE in this register.
565 The reset to the HCLK_DIVIDERis also asserted
566 when core reset is asserted. */
567 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
568 '1' USB-PHY XO block is powered-down during
570 '0' USB-PHY XO block is powered-up during
572 The value of this field must be set while POR is
574 uint64_t p_rclk : 1; /**< Phy refrence clock enable.
575 '1' The PHY PLL uses the XO block output as a
578 uint64_t p_xenbn : 1; /**< Phy external clock enable.
579 '1' The XO block uses the clock from a crystal.
580 '0' The XO block uses an external clock supplied
581 on the XO pin. USB_XI should be tied to
582 ground for this usage. */
583 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
584 remain powered in Suspend Mode.
585 '1' The USB-PHY XO Bias, Bandgap and PLL are
586 powered down in suspend mode.
587 The value of this field must be set while POR is
589 uint64_t p_c_sel : 2; /**< Phy clock speed select.
590 Selects the reference clock / crystal frequency.
595 The value of this field must be set while POR is
597 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
598 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
599 in the USBC, for normal operation this must be '0'. */
600 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
601 to '1' transition. */
602 uint64_t por : 1; /**< Power On Reset for the PHY.
603 Resets all the PHYS registers and state machines. */
604 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
605 '0' the hclk will not be generated. */
606 uint64_t prst : 1; /**< When this field is '0' the reset associated with
607 the phy_clk functionality in the USB Subsystem is
608 help in reset. This bit should not be set to '1'
609 until the time it takes 6 clocks (hclk or phy_clk,
610 whichever is slower) has passed. Under normal
611 operation once this bit is set to '1' it should not
613 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
614 the hclk functioanlity in the USB Subsystem is
615 held in reset.This bit should not be set to '1'
616 until 12ms after phy_clk is stable. Under normal
617 operation, once this bit is set to '1' it should
618 not be set to '0'. */
619 uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived
620 from the eclk. The eclk will be divided by the
621 value of this field +1 to determine the hclk
622 frequency. (Also see HRST of this register).
623 The hclk frequency must be less than 125 MHz. */
631 uint64_t sd_mode : 2;
632 uint64_t cdiv_byp : 1;
633 uint64_t p_c_sel : 2;
634 uint64_t p_com_on : 1;
635 uint64_t p_xenbn : 1;
638 uint64_t hclk_rst : 1;
639 uint64_t reserved_18_63 : 46;
642 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx;
643 struct cvmx_usbnx_clk_ctl_cn50xx
645 #if __BYTE_ORDER == __BIG_ENDIAN
646 uint64_t reserved_20_63 : 44;
647 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
649 Also see the field DIVIDE. DIVIDE2<1> must currently
650 be zero because it is not implemented, so the maximum
651 ratio of eclk/hclk is currently 16.
652 The actual divide number for hclk is:
653 (DIVIDE2 + 1) * (DIVIDE + 1) */
654 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
655 generate the hclk in the USB Subsystem is held
656 in reset. This bit must be set to '0' before
657 changing the value os DIVIDE in this register.
658 The reset to the HCLK_DIVIDERis also asserted
659 when core reset is asserted. */
660 uint64_t reserved_16_16 : 1;
661 uint64_t p_rtype : 2; /**< PHY reference clock type
662 '0' The USB-PHY uses a 12MHz crystal as a clock
663 source at the USB_XO and USB_XI pins
665 '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
666 at the USB_XO pin. USB_XI should be tied to
669 (bit 14 was P_XENBN on 3xxx)
670 (bit 15 was P_RCLK on 3xxx) */
671 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
672 remain powered in Suspend Mode.
673 '1' The USB-PHY XO Bias, Bandgap and PLL are
674 powered down in suspend mode.
675 The value of this field must be set while POR is
677 uint64_t p_c_sel : 2; /**< Phy clock speed select.
678 Selects the reference clock / crystal frequency.
680 '10': 48 MHz (reserved when a crystal is used)
681 '01': 24 MHz (reserved when a crystal is used)
683 The value of this field must be set while POR is
685 NOTE: if a crystal is used as a reference clock,
686 this field must be set to 12 MHz. */
687 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
688 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
689 in the USBC, for normal operation this must be '0'. */
690 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
691 to '1' transition. */
692 uint64_t por : 1; /**< Power On Reset for the PHY.
693 Resets all the PHYS registers and state machines. */
694 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
695 '0' the hclk will not be generated. SEE DIVIDE
696 field of this register. */
697 uint64_t prst : 1; /**< When this field is '0' the reset associated with
698 the phy_clk functionality in the USB Subsystem is
699 help in reset. This bit should not be set to '1'
700 until the time it takes 6 clocks (hclk or phy_clk,
701 whichever is slower) has passed. Under normal
702 operation once this bit is set to '1' it should not
704 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
705 the hclk functioanlity in the USB Subsystem is
706 held in reset.This bit should not be set to '1'
707 until 12ms after phy_clk is stable. Under normal
708 operation, once this bit is set to '1' it should
709 not be set to '0'. */
710 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
711 is the eclk frequency divided by the value of
712 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
713 DIVIDE2 of this register.
714 The hclk frequency should be less than 125Mhz.
715 After writing a value to this field the SW should
716 read the field for the value written.
717 The ENABLE field of this register should not be set
718 until AFTER this field is set and then read. */
726 uint64_t sd_mode : 2;
727 uint64_t cdiv_byp : 1;
728 uint64_t p_c_sel : 2;
729 uint64_t p_com_on : 1;
730 uint64_t p_rtype : 2;
731 uint64_t reserved_16_16 : 1;
732 uint64_t hclk_rst : 1;
733 uint64_t divide2 : 2;
734 uint64_t reserved_20_63 : 44;
737 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx;
738 struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1;
739 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx;
740 struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1;
742 typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
745 * cvmx_usbn#_ctl_status
747 * USBN_CTL_STATUS = USBN's Control And Status Register
749 * Contains general control and status information for the USBN block.
751 union cvmx_usbnx_ctl_status
754 struct cvmx_usbnx_ctl_status_s
756 #if __BYTE_ORDER == __BIG_ENDIAN
757 uint64_t reserved_6_63 : 58;
758 uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page
759 bit in the L2C store operation to the IOB. */
760 uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */
761 uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode.
762 For normal operation this bit should be '0'. */
763 uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB
764 for USB-CORE FIFO access to be inverted. Also data
765 writen to and read from the AHB will have it byte
766 order swapped. If the orginal order was A-B-C-D the
767 new byte order will be D-C-B-A. */
768 uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C.
770 OUT0: A-B-C-D-E-F-G-H
771 OUT1: H-G-F-E-D-C-B-A
772 OUT2: D-C-B-A-H-G-F-E
773 OUT3: E-F-G-H-A-B-C-D */
775 uint64_t l2c_emod : 2;
777 uint64_t dma_test : 1;
778 uint64_t dma_stt : 1;
779 uint64_t dma_0pag : 1;
780 uint64_t reserved_6_63 : 58;
783 struct cvmx_usbnx_ctl_status_s cn30xx;
784 struct cvmx_usbnx_ctl_status_s cn31xx;
785 struct cvmx_usbnx_ctl_status_s cn50xx;
786 struct cvmx_usbnx_ctl_status_s cn52xx;
787 struct cvmx_usbnx_ctl_status_s cn52xxp1;
788 struct cvmx_usbnx_ctl_status_s cn56xx;
789 struct cvmx_usbnx_ctl_status_s cn56xxp1;
791 typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t;
794 * cvmx_usbn#_dma0_inb_chn0
796 * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0
798 * Contains the starting address for use when USB0 writes to L2C via Channel0.
799 * Writing of this register sets the base address.
801 union cvmx_usbnx_dma0_inb_chn0
804 struct cvmx_usbnx_dma0_inb_chn0_s
806 #if __BYTE_ORDER == __BIG_ENDIAN
807 uint64_t reserved_36_63 : 28;
808 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
811 uint64_t reserved_36_63 : 28;
814 struct cvmx_usbnx_dma0_inb_chn0_s cn30xx;
815 struct cvmx_usbnx_dma0_inb_chn0_s cn31xx;
816 struct cvmx_usbnx_dma0_inb_chn0_s cn50xx;
817 struct cvmx_usbnx_dma0_inb_chn0_s cn52xx;
818 struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1;
819 struct cvmx_usbnx_dma0_inb_chn0_s cn56xx;
820 struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1;
822 typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t;
825 * cvmx_usbn#_dma0_inb_chn1
827 * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1
829 * Contains the starting address for use when USB0 writes to L2C via Channel1.
830 * Writing of this register sets the base address.
832 union cvmx_usbnx_dma0_inb_chn1
835 struct cvmx_usbnx_dma0_inb_chn1_s
837 #if __BYTE_ORDER == __BIG_ENDIAN
838 uint64_t reserved_36_63 : 28;
839 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
842 uint64_t reserved_36_63 : 28;
845 struct cvmx_usbnx_dma0_inb_chn1_s cn30xx;
846 struct cvmx_usbnx_dma0_inb_chn1_s cn31xx;
847 struct cvmx_usbnx_dma0_inb_chn1_s cn50xx;
848 struct cvmx_usbnx_dma0_inb_chn1_s cn52xx;
849 struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1;
850 struct cvmx_usbnx_dma0_inb_chn1_s cn56xx;
851 struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1;
853 typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t;
856 * cvmx_usbn#_dma0_inb_chn2
858 * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2
860 * Contains the starting address for use when USB0 writes to L2C via Channel2.
861 * Writing of this register sets the base address.
863 union cvmx_usbnx_dma0_inb_chn2
866 struct cvmx_usbnx_dma0_inb_chn2_s
868 #if __BYTE_ORDER == __BIG_ENDIAN
869 uint64_t reserved_36_63 : 28;
870 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
873 uint64_t reserved_36_63 : 28;
876 struct cvmx_usbnx_dma0_inb_chn2_s cn30xx;
877 struct cvmx_usbnx_dma0_inb_chn2_s cn31xx;
878 struct cvmx_usbnx_dma0_inb_chn2_s cn50xx;
879 struct cvmx_usbnx_dma0_inb_chn2_s cn52xx;
880 struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1;
881 struct cvmx_usbnx_dma0_inb_chn2_s cn56xx;
882 struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1;
884 typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t;
887 * cvmx_usbn#_dma0_inb_chn3
889 * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3
891 * Contains the starting address for use when USB0 writes to L2C via Channel3.
892 * Writing of this register sets the base address.
894 union cvmx_usbnx_dma0_inb_chn3
897 struct cvmx_usbnx_dma0_inb_chn3_s
899 #if __BYTE_ORDER == __BIG_ENDIAN
900 uint64_t reserved_36_63 : 28;
901 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
904 uint64_t reserved_36_63 : 28;
907 struct cvmx_usbnx_dma0_inb_chn3_s cn30xx;
908 struct cvmx_usbnx_dma0_inb_chn3_s cn31xx;
909 struct cvmx_usbnx_dma0_inb_chn3_s cn50xx;
910 struct cvmx_usbnx_dma0_inb_chn3_s cn52xx;
911 struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1;
912 struct cvmx_usbnx_dma0_inb_chn3_s cn56xx;
913 struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1;
915 typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t;
918 * cvmx_usbn#_dma0_inb_chn4
920 * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4
922 * Contains the starting address for use when USB0 writes to L2C via Channel4.
923 * Writing of this register sets the base address.
925 union cvmx_usbnx_dma0_inb_chn4
928 struct cvmx_usbnx_dma0_inb_chn4_s
930 #if __BYTE_ORDER == __BIG_ENDIAN
931 uint64_t reserved_36_63 : 28;
932 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
935 uint64_t reserved_36_63 : 28;
938 struct cvmx_usbnx_dma0_inb_chn4_s cn30xx;
939 struct cvmx_usbnx_dma0_inb_chn4_s cn31xx;
940 struct cvmx_usbnx_dma0_inb_chn4_s cn50xx;
941 struct cvmx_usbnx_dma0_inb_chn4_s cn52xx;
942 struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1;
943 struct cvmx_usbnx_dma0_inb_chn4_s cn56xx;
944 struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1;
946 typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t;
949 * cvmx_usbn#_dma0_inb_chn5
951 * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5
953 * Contains the starting address for use when USB0 writes to L2C via Channel5.
954 * Writing of this register sets the base address.
956 union cvmx_usbnx_dma0_inb_chn5
959 struct cvmx_usbnx_dma0_inb_chn5_s
961 #if __BYTE_ORDER == __BIG_ENDIAN
962 uint64_t reserved_36_63 : 28;
963 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
966 uint64_t reserved_36_63 : 28;
969 struct cvmx_usbnx_dma0_inb_chn5_s cn30xx;
970 struct cvmx_usbnx_dma0_inb_chn5_s cn31xx;
971 struct cvmx_usbnx_dma0_inb_chn5_s cn50xx;
972 struct cvmx_usbnx_dma0_inb_chn5_s cn52xx;
973 struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1;
974 struct cvmx_usbnx_dma0_inb_chn5_s cn56xx;
975 struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1;
977 typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t;
980 * cvmx_usbn#_dma0_inb_chn6
982 * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6
984 * Contains the starting address for use when USB0 writes to L2C via Channel6.
985 * Writing of this register sets the base address.
987 union cvmx_usbnx_dma0_inb_chn6
990 struct cvmx_usbnx_dma0_inb_chn6_s
992 #if __BYTE_ORDER == __BIG_ENDIAN
993 uint64_t reserved_36_63 : 28;
994 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
997 uint64_t reserved_36_63 : 28;
1000 struct cvmx_usbnx_dma0_inb_chn6_s cn30xx;
1001 struct cvmx_usbnx_dma0_inb_chn6_s cn31xx;
1002 struct cvmx_usbnx_dma0_inb_chn6_s cn50xx;
1003 struct cvmx_usbnx_dma0_inb_chn6_s cn52xx;
1004 struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1;
1005 struct cvmx_usbnx_dma0_inb_chn6_s cn56xx;
1006 struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1;
1008 typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t;
1011 * cvmx_usbn#_dma0_inb_chn7
1013 * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7
1015 * Contains the starting address for use when USB0 writes to L2C via Channel7.
1016 * Writing of this register sets the base address.
1018 union cvmx_usbnx_dma0_inb_chn7
1021 struct cvmx_usbnx_dma0_inb_chn7_s
1023 #if __BYTE_ORDER == __BIG_ENDIAN
1024 uint64_t reserved_36_63 : 28;
1025 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
1028 uint64_t reserved_36_63 : 28;
1031 struct cvmx_usbnx_dma0_inb_chn7_s cn30xx;
1032 struct cvmx_usbnx_dma0_inb_chn7_s cn31xx;
1033 struct cvmx_usbnx_dma0_inb_chn7_s cn50xx;
1034 struct cvmx_usbnx_dma0_inb_chn7_s cn52xx;
1035 struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1;
1036 struct cvmx_usbnx_dma0_inb_chn7_s cn56xx;
1037 struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1;
1039 typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t;
1042 * cvmx_usbn#_dma0_outb_chn0
1044 * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0
1046 * Contains the starting address for use when USB0 reads from L2C via Channel0.
1047 * Writing of this register sets the base address.
1049 union cvmx_usbnx_dma0_outb_chn0
1052 struct cvmx_usbnx_dma0_outb_chn0_s
1054 #if __BYTE_ORDER == __BIG_ENDIAN
1055 uint64_t reserved_36_63 : 28;
1056 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1059 uint64_t reserved_36_63 : 28;
1062 struct cvmx_usbnx_dma0_outb_chn0_s cn30xx;
1063 struct cvmx_usbnx_dma0_outb_chn0_s cn31xx;
1064 struct cvmx_usbnx_dma0_outb_chn0_s cn50xx;
1065 struct cvmx_usbnx_dma0_outb_chn0_s cn52xx;
1066 struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1;
1067 struct cvmx_usbnx_dma0_outb_chn0_s cn56xx;
1068 struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1;
1070 typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t;
1073 * cvmx_usbn#_dma0_outb_chn1
1075 * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1
1077 * Contains the starting address for use when USB0 reads from L2C via Channel1.
1078 * Writing of this register sets the base address.
1080 union cvmx_usbnx_dma0_outb_chn1
1083 struct cvmx_usbnx_dma0_outb_chn1_s
1085 #if __BYTE_ORDER == __BIG_ENDIAN
1086 uint64_t reserved_36_63 : 28;
1087 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1090 uint64_t reserved_36_63 : 28;
1093 struct cvmx_usbnx_dma0_outb_chn1_s cn30xx;
1094 struct cvmx_usbnx_dma0_outb_chn1_s cn31xx;
1095 struct cvmx_usbnx_dma0_outb_chn1_s cn50xx;
1096 struct cvmx_usbnx_dma0_outb_chn1_s cn52xx;
1097 struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1;
1098 struct cvmx_usbnx_dma0_outb_chn1_s cn56xx;
1099 struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1;
1101 typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t;
1104 * cvmx_usbn#_dma0_outb_chn2
1106 * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2
1108 * Contains the starting address for use when USB0 reads from L2C via Channel2.
1109 * Writing of this register sets the base address.
1111 union cvmx_usbnx_dma0_outb_chn2
1114 struct cvmx_usbnx_dma0_outb_chn2_s
1116 #if __BYTE_ORDER == __BIG_ENDIAN
1117 uint64_t reserved_36_63 : 28;
1118 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1121 uint64_t reserved_36_63 : 28;
1124 struct cvmx_usbnx_dma0_outb_chn2_s cn30xx;
1125 struct cvmx_usbnx_dma0_outb_chn2_s cn31xx;
1126 struct cvmx_usbnx_dma0_outb_chn2_s cn50xx;
1127 struct cvmx_usbnx_dma0_outb_chn2_s cn52xx;
1128 struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1;
1129 struct cvmx_usbnx_dma0_outb_chn2_s cn56xx;
1130 struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1;
1132 typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t;
1135 * cvmx_usbn#_dma0_outb_chn3
1137 * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3
1139 * Contains the starting address for use when USB0 reads from L2C via Channel3.
1140 * Writing of this register sets the base address.
1142 union cvmx_usbnx_dma0_outb_chn3
1145 struct cvmx_usbnx_dma0_outb_chn3_s
1147 #if __BYTE_ORDER == __BIG_ENDIAN
1148 uint64_t reserved_36_63 : 28;
1149 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1152 uint64_t reserved_36_63 : 28;
1155 struct cvmx_usbnx_dma0_outb_chn3_s cn30xx;
1156 struct cvmx_usbnx_dma0_outb_chn3_s cn31xx;
1157 struct cvmx_usbnx_dma0_outb_chn3_s cn50xx;
1158 struct cvmx_usbnx_dma0_outb_chn3_s cn52xx;
1159 struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1;
1160 struct cvmx_usbnx_dma0_outb_chn3_s cn56xx;
1161 struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1;
1163 typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t;
1166 * cvmx_usbn#_dma0_outb_chn4
1168 * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4
1170 * Contains the starting address for use when USB0 reads from L2C via Channel4.
1171 * Writing of this register sets the base address.
1173 union cvmx_usbnx_dma0_outb_chn4
1176 struct cvmx_usbnx_dma0_outb_chn4_s
1178 #if __BYTE_ORDER == __BIG_ENDIAN
1179 uint64_t reserved_36_63 : 28;
1180 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1183 uint64_t reserved_36_63 : 28;
1186 struct cvmx_usbnx_dma0_outb_chn4_s cn30xx;
1187 struct cvmx_usbnx_dma0_outb_chn4_s cn31xx;
1188 struct cvmx_usbnx_dma0_outb_chn4_s cn50xx;
1189 struct cvmx_usbnx_dma0_outb_chn4_s cn52xx;
1190 struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1;
1191 struct cvmx_usbnx_dma0_outb_chn4_s cn56xx;
1192 struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1;
1194 typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t;
1197 * cvmx_usbn#_dma0_outb_chn5
1199 * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5
1201 * Contains the starting address for use when USB0 reads from L2C via Channel5.
1202 * Writing of this register sets the base address.
1204 union cvmx_usbnx_dma0_outb_chn5
1207 struct cvmx_usbnx_dma0_outb_chn5_s
1209 #if __BYTE_ORDER == __BIG_ENDIAN
1210 uint64_t reserved_36_63 : 28;
1211 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1214 uint64_t reserved_36_63 : 28;
1217 struct cvmx_usbnx_dma0_outb_chn5_s cn30xx;
1218 struct cvmx_usbnx_dma0_outb_chn5_s cn31xx;
1219 struct cvmx_usbnx_dma0_outb_chn5_s cn50xx;
1220 struct cvmx_usbnx_dma0_outb_chn5_s cn52xx;
1221 struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1;
1222 struct cvmx_usbnx_dma0_outb_chn5_s cn56xx;
1223 struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1;
1225 typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t;
1228 * cvmx_usbn#_dma0_outb_chn6
1230 * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6
1232 * Contains the starting address for use when USB0 reads from L2C via Channel6.
1233 * Writing of this register sets the base address.
1235 union cvmx_usbnx_dma0_outb_chn6
1238 struct cvmx_usbnx_dma0_outb_chn6_s
1240 #if __BYTE_ORDER == __BIG_ENDIAN
1241 uint64_t reserved_36_63 : 28;
1242 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1245 uint64_t reserved_36_63 : 28;
1248 struct cvmx_usbnx_dma0_outb_chn6_s cn30xx;
1249 struct cvmx_usbnx_dma0_outb_chn6_s cn31xx;
1250 struct cvmx_usbnx_dma0_outb_chn6_s cn50xx;
1251 struct cvmx_usbnx_dma0_outb_chn6_s cn52xx;
1252 struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1;
1253 struct cvmx_usbnx_dma0_outb_chn6_s cn56xx;
1254 struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1;
1256 typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t;
1259 * cvmx_usbn#_dma0_outb_chn7
1261 * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7
1263 * Contains the starting address for use when USB0 reads from L2C via Channel7.
1264 * Writing of this register sets the base address.
1266 union cvmx_usbnx_dma0_outb_chn7
1269 struct cvmx_usbnx_dma0_outb_chn7_s
1271 #if __BYTE_ORDER == __BIG_ENDIAN
1272 uint64_t reserved_36_63 : 28;
1273 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1276 uint64_t reserved_36_63 : 28;
1279 struct cvmx_usbnx_dma0_outb_chn7_s cn30xx;
1280 struct cvmx_usbnx_dma0_outb_chn7_s cn31xx;
1281 struct cvmx_usbnx_dma0_outb_chn7_s cn50xx;
1282 struct cvmx_usbnx_dma0_outb_chn7_s cn52xx;
1283 struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1;
1284 struct cvmx_usbnx_dma0_outb_chn7_s cn56xx;
1285 struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1;
1287 typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t;
1290 * cvmx_usbn#_dma_test
1292 * USBN_DMA_TEST = USBN's DMA TestRegister
1294 * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
1296 union cvmx_usbnx_dma_test
1299 struct cvmx_usbnx_dma_test_s
1301 #if __BYTE_ORDER == __BIG_ENDIAN
1302 uint64_t reserved_40_63 : 24;
1303 uint64_t done : 1; /**< This field is set when a DMA completes. Writing a
1304 '1' to this field clears this bit. */
1305 uint64_t req : 1; /**< DMA Request. Writing a 1 to this register
1306 will cause a DMA request as specified in the other
1307 fields of this register to take place. This field
1308 will always read as '0'. */
1309 uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */
1310 uint64_t count : 11; /**< DMA Request Count. */
1311 uint64_t channel : 5; /**< DMA Channel/Enpoint. */
1312 uint64_t burst : 4; /**< DMA Burst Size. */
1315 uint64_t channel : 5;
1316 uint64_t count : 11;
1317 uint64_t f_addr : 18;
1320 uint64_t reserved_40_63 : 24;
1323 struct cvmx_usbnx_dma_test_s cn30xx;
1324 struct cvmx_usbnx_dma_test_s cn31xx;
1325 struct cvmx_usbnx_dma_test_s cn50xx;
1326 struct cvmx_usbnx_dma_test_s cn52xx;
1327 struct cvmx_usbnx_dma_test_s cn52xxp1;
1328 struct cvmx_usbnx_dma_test_s cn56xx;
1329 struct cvmx_usbnx_dma_test_s cn56xxp1;
1331 typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t;
1334 * cvmx_usbn#_int_enb
1336 * USBN_INT_ENB = USBN's Interrupt Enable
1338 * The USBN's interrupt enable register.
1340 union cvmx_usbnx_int_enb
1343 struct cvmx_usbnx_int_enb_s
1345 #if __BYTE_ORDER == __BIG_ENDIAN
1346 uint64_t reserved_38_63 : 26;
1347 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM
1348 register is asserted the USBN will assert an
1350 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM
1351 register is asserted the USBN will assert an
1353 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM
1354 register is asserted the USBN will assert an
1356 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM
1357 register is asserted the USBN will assert an
1359 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM
1360 register is asserted the USBN will assert an
1362 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM
1363 register is asserted the USBN will assert an
1365 uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM
1366 register is asserted the USBN will assert an
1368 uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM
1369 register is asserted the USBN will assert an
1371 uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM
1372 register is asserted the USBN will assert an
1374 uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM
1375 register is asserted the USBN will assert an
1377 uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM
1378 register is asserted the USBN will assert an
1380 uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM
1381 register is asserted the USBN will assert an
1383 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM
1384 register is asserted the USBN will assert an
1386 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM
1387 register is asserted the USBN will assert an
1389 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM
1390 register is asserted the USBN will assert an
1392 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM
1393 register is asserted the USBN will assert an
1395 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM
1396 register is asserted the USBN will assert an
1398 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM
1399 register is asserted the USBN will assert an
1401 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM
1402 register is asserted the USBN will assert an
1404 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM
1405 register is asserted the USBN will assert an
1407 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM
1408 register is asserted the USBN will assert an
1410 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM
1411 register is asserted the USBN will assert an
1413 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM
1414 register is asserted the USBN will assert an
1416 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM
1417 register is asserted the USBN will assert an
1419 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM
1420 register is asserted the USBN will assert an
1422 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM
1423 register is asserted the USBN will assert an
1425 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM
1426 register is asserted the USBN will assert an
1428 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM
1429 register is asserted the USBN will assert an
1431 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM
1432 register is asserted the USBN will assert an
1434 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM
1435 register is asserted the USBN will assert an
1437 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM
1438 register is asserted the USBN will assert an
1440 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM
1441 register is asserted the USBN will assert an
1443 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM
1444 register is asserted the USBN will assert an
1446 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM
1447 register is asserted the USBN will assert an
1449 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM
1450 register is asserted the USBN will assert an
1452 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM
1453 register is asserted the USBN will assert an
1455 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM
1456 register is asserted the USBN will assert an
1458 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM
1459 register is asserted the USBN will assert an
1462 uint64_t pr_po_e : 1;
1463 uint64_t pr_pu_f : 1;
1464 uint64_t nr_po_e : 1;
1465 uint64_t nr_pu_f : 1;
1466 uint64_t lr_po_e : 1;
1467 uint64_t lr_pu_f : 1;
1468 uint64_t pt_po_e : 1;
1469 uint64_t pt_pu_f : 1;
1470 uint64_t nt_po_e : 1;
1471 uint64_t nt_pu_f : 1;
1472 uint64_t lt_po_e : 1;
1473 uint64_t lt_pu_f : 1;
1474 uint64_t dcred_e : 1;
1475 uint64_t dcred_f : 1;
1476 uint64_t l2c_s_e : 1;
1477 uint64_t l2c_a_f : 1;
1478 uint64_t l2_fi_e : 1;
1479 uint64_t l2_fi_f : 1;
1480 uint64_t rg_fi_e : 1;
1481 uint64_t rg_fi_f : 1;
1482 uint64_t rq_q2_f : 1;
1483 uint64_t rq_q2_e : 1;
1484 uint64_t rq_q3_f : 1;
1485 uint64_t rq_q3_e : 1;
1486 uint64_t uod_pe : 1;
1487 uint64_t uod_pf : 1;
1488 uint64_t n2u_pf : 1;
1489 uint64_t n2u_pe : 1;
1490 uint64_t u2n_d_pe : 1;
1491 uint64_t u2n_d_pf : 1;
1492 uint64_t u2n_c_pf : 1;
1493 uint64_t u2n_c_pe : 1;
1494 uint64_t ltl_f_pe : 1;
1495 uint64_t ltl_f_pf : 1;
1496 uint64_t nd4o_rpe : 1;
1497 uint64_t nd4o_rpf : 1;
1498 uint64_t nd4o_dpe : 1;
1499 uint64_t nd4o_dpf : 1;
1500 uint64_t reserved_38_63 : 26;
1503 struct cvmx_usbnx_int_enb_s cn30xx;
1504 struct cvmx_usbnx_int_enb_s cn31xx;
1505 struct cvmx_usbnx_int_enb_cn50xx
1507 #if __BYTE_ORDER == __BIG_ENDIAN
1508 uint64_t reserved_38_63 : 26;
1509 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM
1510 register is asserted the USBN will assert an
1512 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM
1513 register is asserted the USBN will assert an
1515 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM
1516 register is asserted the USBN will assert an
1518 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM
1519 register is asserted the USBN will assert an
1521 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM
1522 register is asserted the USBN will assert an
1524 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM
1525 register is asserted the USBN will assert an
1527 uint64_t reserved_26_31 : 6;
1528 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM
1529 register is asserted the USBN will assert an
1531 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM
1532 register is asserted the USBN will assert an
1534 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM
1535 register is asserted the USBN will assert an
1537 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM
1538 register is asserted the USBN will assert an
1540 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM
1541 register is asserted the USBN will assert an
1543 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM
1544 register is asserted the USBN will assert an
1546 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM
1547 register is asserted the USBN will assert an
1549 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM
1550 register is asserted the USBN will assert an
1552 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM
1553 register is asserted the USBN will assert an
1555 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM
1556 register is asserted the USBN will assert an
1558 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM
1559 register is asserted the USBN will assert an
1561 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM
1562 register is asserted the USBN will assert an
1564 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM
1565 register is asserted the USBN will assert an
1567 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM
1568 register is asserted the USBN will assert an
1570 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM
1571 register is asserted the USBN will assert an
1573 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM
1574 register is asserted the USBN will assert an
1576 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM
1577 register is asserted the USBN will assert an
1579 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM
1580 register is asserted the USBN will assert an
1582 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM
1583 register is asserted the USBN will assert an
1585 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM
1586 register is asserted the USBN will assert an
1588 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM
1589 register is asserted the USBN will assert an
1591 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM
1592 register is asserted the USBN will assert an
1594 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM
1595 register is asserted the USBN will assert an
1597 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM
1598 register is asserted the USBN will assert an
1600 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM
1601 register is asserted the USBN will assert an
1603 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM
1604 register is asserted the USBN will assert an
1607 uint64_t pr_po_e : 1;
1608 uint64_t pr_pu_f : 1;
1609 uint64_t nr_po_e : 1;
1610 uint64_t nr_pu_f : 1;
1611 uint64_t lr_po_e : 1;
1612 uint64_t lr_pu_f : 1;
1613 uint64_t pt_po_e : 1;
1614 uint64_t pt_pu_f : 1;
1615 uint64_t nt_po_e : 1;
1616 uint64_t nt_pu_f : 1;
1617 uint64_t lt_po_e : 1;
1618 uint64_t lt_pu_f : 1;
1619 uint64_t dcred_e : 1;
1620 uint64_t dcred_f : 1;
1621 uint64_t l2c_s_e : 1;
1622 uint64_t l2c_a_f : 1;
1623 uint64_t l2_fi_e : 1;
1624 uint64_t l2_fi_f : 1;
1625 uint64_t rg_fi_e : 1;
1626 uint64_t rg_fi_f : 1;
1627 uint64_t rq_q2_f : 1;
1628 uint64_t rq_q2_e : 1;
1629 uint64_t rq_q3_f : 1;
1630 uint64_t rq_q3_e : 1;
1631 uint64_t uod_pe : 1;
1632 uint64_t uod_pf : 1;
1633 uint64_t reserved_26_31 : 6;
1634 uint64_t ltl_f_pe : 1;
1635 uint64_t ltl_f_pf : 1;
1636 uint64_t nd4o_rpe : 1;
1637 uint64_t nd4o_rpf : 1;
1638 uint64_t nd4o_dpe : 1;
1639 uint64_t nd4o_dpf : 1;
1640 uint64_t reserved_38_63 : 26;
1643 struct cvmx_usbnx_int_enb_cn50xx cn52xx;
1644 struct cvmx_usbnx_int_enb_cn50xx cn52xxp1;
1645 struct cvmx_usbnx_int_enb_cn50xx cn56xx;
1646 struct cvmx_usbnx_int_enb_cn50xx cn56xxp1;
1648 typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t;
1651 * cvmx_usbn#_int_sum
1653 * USBN_INT_SUM = USBN's Interrupt Summary Register
1655 * Contains the diffrent interrupt summary bits of the USBN.
1657 union cvmx_usbnx_int_sum
1660 struct cvmx_usbnx_int_sum_s
1662 #if __BYTE_ORDER == __BIG_ENDIAN
1663 uint64_t reserved_38_63 : 26;
1664 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */
1665 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */
1666 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */
1667 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */
1668 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */
1669 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */
1670 uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */
1671 uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */
1672 uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */
1673 uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */
1674 uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */
1675 uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */
1676 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */
1677 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */
1678 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1679 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1680 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1681 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1682 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */
1683 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */
1684 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */
1685 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */
1686 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */
1687 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */
1688 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */
1689 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */
1690 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */
1691 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */
1692 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */
1693 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */
1694 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */
1695 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */
1696 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */
1697 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */
1698 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */
1699 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */
1700 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */
1701 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */
1703 uint64_t pr_po_e : 1;
1704 uint64_t pr_pu_f : 1;
1705 uint64_t nr_po_e : 1;
1706 uint64_t nr_pu_f : 1;
1707 uint64_t lr_po_e : 1;
1708 uint64_t lr_pu_f : 1;
1709 uint64_t pt_po_e : 1;
1710 uint64_t pt_pu_f : 1;
1711 uint64_t nt_po_e : 1;
1712 uint64_t nt_pu_f : 1;
1713 uint64_t lt_po_e : 1;
1714 uint64_t lt_pu_f : 1;
1715 uint64_t dcred_e : 1;
1716 uint64_t dcred_f : 1;
1717 uint64_t l2c_s_e : 1;
1718 uint64_t l2c_a_f : 1;
1719 uint64_t lt_fi_e : 1;
1720 uint64_t lt_fi_f : 1;
1721 uint64_t rg_fi_e : 1;
1722 uint64_t rg_fi_f : 1;
1723 uint64_t rq_q2_f : 1;
1724 uint64_t rq_q2_e : 1;
1725 uint64_t rq_q3_f : 1;
1726 uint64_t rq_q3_e : 1;
1727 uint64_t uod_pe : 1;
1728 uint64_t uod_pf : 1;
1729 uint64_t n2u_pf : 1;
1730 uint64_t n2u_pe : 1;
1731 uint64_t u2n_d_pe : 1;
1732 uint64_t u2n_d_pf : 1;
1733 uint64_t u2n_c_pf : 1;
1734 uint64_t u2n_c_pe : 1;
1735 uint64_t ltl_f_pe : 1;
1736 uint64_t ltl_f_pf : 1;
1737 uint64_t nd4o_rpe : 1;
1738 uint64_t nd4o_rpf : 1;
1739 uint64_t nd4o_dpe : 1;
1740 uint64_t nd4o_dpf : 1;
1741 uint64_t reserved_38_63 : 26;
1744 struct cvmx_usbnx_int_sum_s cn30xx;
1745 struct cvmx_usbnx_int_sum_s cn31xx;
1746 struct cvmx_usbnx_int_sum_cn50xx
1748 #if __BYTE_ORDER == __BIG_ENDIAN
1749 uint64_t reserved_38_63 : 26;
1750 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */
1751 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */
1752 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */
1753 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */
1754 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */
1755 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */
1756 uint64_t reserved_26_31 : 6;
1757 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */
1758 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */
1759 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1760 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1761 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1762 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1763 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */
1764 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */
1765 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */
1766 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */
1767 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */
1768 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */
1769 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */
1770 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */
1771 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */
1772 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */
1773 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */
1774 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */
1775 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */
1776 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */
1777 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */
1778 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */
1779 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */
1780 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */
1781 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */
1782 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */
1784 uint64_t pr_po_e : 1;
1785 uint64_t pr_pu_f : 1;
1786 uint64_t nr_po_e : 1;
1787 uint64_t nr_pu_f : 1;
1788 uint64_t lr_po_e : 1;
1789 uint64_t lr_pu_f : 1;
1790 uint64_t pt_po_e : 1;
1791 uint64_t pt_pu_f : 1;
1792 uint64_t nt_po_e : 1;
1793 uint64_t nt_pu_f : 1;
1794 uint64_t lt_po_e : 1;
1795 uint64_t lt_pu_f : 1;
1796 uint64_t dcred_e : 1;
1797 uint64_t dcred_f : 1;
1798 uint64_t l2c_s_e : 1;
1799 uint64_t l2c_a_f : 1;
1800 uint64_t lt_fi_e : 1;
1801 uint64_t lt_fi_f : 1;
1802 uint64_t rg_fi_e : 1;
1803 uint64_t rg_fi_f : 1;
1804 uint64_t rq_q2_f : 1;
1805 uint64_t rq_q2_e : 1;
1806 uint64_t rq_q3_f : 1;
1807 uint64_t rq_q3_e : 1;
1808 uint64_t uod_pe : 1;
1809 uint64_t uod_pf : 1;
1810 uint64_t reserved_26_31 : 6;
1811 uint64_t ltl_f_pe : 1;
1812 uint64_t ltl_f_pf : 1;
1813 uint64_t nd4o_rpe : 1;
1814 uint64_t nd4o_rpf : 1;
1815 uint64_t nd4o_dpe : 1;
1816 uint64_t nd4o_dpf : 1;
1817 uint64_t reserved_38_63 : 26;
1820 struct cvmx_usbnx_int_sum_cn50xx cn52xx;
1821 struct cvmx_usbnx_int_sum_cn50xx cn52xxp1;
1822 struct cvmx_usbnx_int_sum_cn50xx cn56xx;
1823 struct cvmx_usbnx_int_sum_cn50xx cn56xxp1;
1825 typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t;
1828 * cvmx_usbn#_usbp_ctl_status
1830 * USBN_USBP_CTL_STATUS = USBP Control And Status Register
1832 * Contains general control and status information for the USBN block.
1834 union cvmx_usbnx_usbp_ctl_status
1837 struct cvmx_usbnx_usbp_ctl_status_s
1839 #if __BYTE_ORDER == __BIG_ENDIAN
1840 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
1841 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
1842 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
1843 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
1844 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
1845 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
1846 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
1847 uint64_t otgdisable : 1; /**< OTG Block Disable */
1848 uint64_t portreset : 1; /**< Per_Port Reset */
1849 uint64_t drvvbus : 1; /**< Drive VBUS */
1850 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
1851 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
1852 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
1853 uint64_t bist_done : 1; /**< PHY Bist Done.
1854 Asserted at the end of the PHY BIST sequence. */
1855 uint64_t bist_err : 1; /**< PHY Bist Error.
1856 Indicates an internal error was detected during
1857 the BIST sequence. */
1858 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1859 Presents either internaly generated signals or
1860 test register contents, based upon the value of
1861 test_data_out_sel. */
1862 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
1863 Normally should be set to zero.
1864 When customers have no intent to use USB PHY
1865 interface, they should:
1866 - still provide 3.3V to USB_VDD33, and
1867 - tie USB_REXT to 3.3V supply, and
1868 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
1869 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
1870 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1871 with byte-counts between packets. When set to 0
1872 the L2C DMA address is incremented to the next
1873 4-byte aligned address after adding byte-count. */
1874 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1875 set to '0' for operation. */
1876 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1877 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1878 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1879 This signal enables the pull-down resistance on
1880 the D+ line. '1' pull down-resistance is connected
1881 to D+/ '0' pull down resistance is not connected
1882 to D+. When an A/B device is acting as a host
1883 (downstream-facing port), dp_pulldown and
1884 dm_pulldown are enabled. This must not toggle
1885 during normal opeartion. */
1886 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1887 This signal enables the pull-down resistance on
1888 the D- line. '1' pull down-resistance is connected
1889 to D-. '0' pull down resistance is not connected
1890 to D-. When an A/B device is acting as a host
1891 (downstream-facing port), dp_pulldown and
1892 dm_pulldown are enabled. This must not toggle
1893 during normal opeartion. */
1894 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1895 USB is acting as device. This field needs to be
1896 set while the USB is in reset. */
1897 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
1898 Tunes the current supply and rise/fall output
1899 times for high-speed operation.
1900 [20:19] == 11: Current supply increased
1902 [20:19] == 10: Current supply increased
1904 [20:19] == 01: Design default.
1905 [20:19] == 00: Current supply decreased
1907 [22:21] == 11: Rise and fall times are increased.
1908 [22:21] == 10: Design default.
1909 [22:21] == 01: Rise and fall times are decreased.
1910 [22:21] == 00: Rise and fall times are decreased
1911 further as compared to the 01 setting. */
1912 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1913 Enables or disables bit stuffing on data[15:8]
1914 when bit-stuffing is enabled. */
1915 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1916 Enables or disables bit stuffing on data[7:0]
1917 when bit-stuffing is enabled. */
1918 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
1919 '1': During data transmission the receive is
1921 '0': During data transmission the receive is
1923 Must be '0' for normal operation. */
1924 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
1925 '1' The PHY's analog_test pin is enabled for the
1926 input and output of applicable analog test signals.
1927 '0' THe analog_test pin is disabled. */
1928 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
1929 Used to activate BIST in the PHY. */
1930 uint64_t tdata_sel : 1; /**< Test Data Out Select.
1931 '1' test_data_out[3:0] (PHY) register contents
1932 are output. '0' internaly generated signals are
1934 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
1935 Specifies the register address for writing to or
1936 reading from the PHY test interface register. */
1937 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
1938 This is a test bus. Data is present on [3:0],
1939 and its corresponding select (enable) is present
1941 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
1942 This is a test signal. When the USB Core is
1943 powered up (not in Susned Mode), an automatic
1944 tester can use this to disable phy_clock and
1945 free_clk, then re-eanable them with an aligned
1947 '1': The phy_clk and free_clk outputs are
1948 disabled. "0": The phy_clock and free_clk outputs
1949 are available within a specific period after the
1952 uint64_t ate_reset : 1;
1953 uint64_t tdata_in : 8;
1954 uint64_t taddr_in : 4;
1955 uint64_t tdata_sel : 1;
1956 uint64_t bist_enb : 1;
1957 uint64_t vtest_enb : 1;
1958 uint64_t loop_enb : 1;
1959 uint64_t tx_bs_en : 1;
1960 uint64_t tx_bs_enh : 1;
1961 uint64_t tuning : 4;
1962 uint64_t hst_mode : 1;
1963 uint64_t dm_pulld : 1;
1964 uint64_t dp_pulld : 1;
1966 uint64_t usbp_bist : 1;
1967 uint64_t usbc_end : 1;
1968 uint64_t dma_bmode : 1;
1969 uint64_t txpreemphasistune : 1;
1971 uint64_t tdata_out : 4;
1972 uint64_t bist_err : 1;
1973 uint64_t bist_done : 1;
1974 uint64_t hsbist : 1;
1975 uint64_t fsbist : 1;
1976 uint64_t lsbist : 1;
1977 uint64_t drvvbus : 1;
1978 uint64_t portreset : 1;
1979 uint64_t otgdisable : 1;
1980 uint64_t otgtune : 3;
1981 uint64_t compdistune : 3;
1982 uint64_t sqrxtune : 3;
1983 uint64_t txhsxvtune : 2;
1984 uint64_t txfslstune : 4;
1985 uint64_t txvreftune : 4;
1986 uint64_t txrisetune : 1;
1989 struct cvmx_usbnx_usbp_ctl_status_cn30xx
1991 #if __BYTE_ORDER == __BIG_ENDIAN
1992 uint64_t reserved_38_63 : 26;
1993 uint64_t bist_done : 1; /**< PHY Bist Done.
1994 Asserted at the end of the PHY BIST sequence. */
1995 uint64_t bist_err : 1; /**< PHY Bist Error.
1996 Indicates an internal error was detected during
1997 the BIST sequence. */
1998 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1999 Presents either internaly generated signals or
2000 test register contents, based upon the value of
2001 test_data_out_sel. */
2002 uint64_t reserved_30_31 : 2;
2003 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
2004 with byte-counts between packets. When set to 0
2005 the L2C DMA address is incremented to the next
2006 4-byte aligned address after adding byte-count. */
2007 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
2008 set to '0' for operation. */
2009 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
2010 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
2011 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
2012 This signal enables the pull-down resistance on
2013 the D+ line. '1' pull down-resistance is connected
2014 to D+/ '0' pull down resistance is not connected
2015 to D+. When an A/B device is acting as a host
2016 (downstream-facing port), dp_pulldown and
2017 dm_pulldown are enabled. This must not toggle
2018 during normal opeartion. */
2019 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
2020 This signal enables the pull-down resistance on
2021 the D- line. '1' pull down-resistance is connected
2022 to D-. '0' pull down resistance is not connected
2023 to D-. When an A/B device is acting as a host
2024 (downstream-facing port), dp_pulldown and
2025 dm_pulldown are enabled. This must not toggle
2026 during normal opeartion. */
2027 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
2028 USB is acting as device. This field needs to be
2029 set while the USB is in reset. */
2030 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
2031 Tunes the current supply and rise/fall output
2032 times for high-speed operation.
2033 [20:19] == 11: Current supply increased
2035 [20:19] == 10: Current supply increased
2037 [20:19] == 01: Design default.
2038 [20:19] == 00: Current supply decreased
2040 [22:21] == 11: Rise and fall times are increased.
2041 [22:21] == 10: Design default.
2042 [22:21] == 01: Rise and fall times are decreased.
2043 [22:21] == 00: Rise and fall times are decreased
2044 further as compared to the 01 setting. */
2045 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
2046 Enables or disables bit stuffing on data[15:8]
2047 when bit-stuffing is enabled. */
2048 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
2049 Enables or disables bit stuffing on data[7:0]
2050 when bit-stuffing is enabled. */
2051 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
2052 '1': During data transmission the receive is
2054 '0': During data transmission the receive is
2056 Must be '0' for normal operation. */
2057 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
2058 '1' The PHY's analog_test pin is enabled for the
2059 input and output of applicable analog test signals.
2060 '0' THe analog_test pin is disabled. */
2061 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
2062 Used to activate BIST in the PHY. */
2063 uint64_t tdata_sel : 1; /**< Test Data Out Select.
2064 '1' test_data_out[3:0] (PHY) register contents
2065 are output. '0' internaly generated signals are
2067 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
2068 Specifies the register address for writing to or
2069 reading from the PHY test interface register. */
2070 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
2071 This is a test bus. Data is present on [3:0],
2072 and its corresponding select (enable) is present
2074 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
2075 This is a test signal. When the USB Core is
2076 powered up (not in Susned Mode), an automatic
2077 tester can use this to disable phy_clock and
2078 free_clk, then re-eanable them with an aligned
2080 '1': The phy_clk and free_clk outputs are
2081 disabled. "0": The phy_clock and free_clk outputs
2082 are available within a specific period after the
2085 uint64_t ate_reset : 1;
2086 uint64_t tdata_in : 8;
2087 uint64_t taddr_in : 4;
2088 uint64_t tdata_sel : 1;
2089 uint64_t bist_enb : 1;
2090 uint64_t vtest_enb : 1;
2091 uint64_t loop_enb : 1;
2092 uint64_t tx_bs_en : 1;
2093 uint64_t tx_bs_enh : 1;
2094 uint64_t tuning : 4;
2095 uint64_t hst_mode : 1;
2096 uint64_t dm_pulld : 1;
2097 uint64_t dp_pulld : 1;
2099 uint64_t usbp_bist : 1;
2100 uint64_t usbc_end : 1;
2101 uint64_t dma_bmode : 1;
2102 uint64_t reserved_30_31 : 2;
2103 uint64_t tdata_out : 4;
2104 uint64_t bist_err : 1;
2105 uint64_t bist_done : 1;
2106 uint64_t reserved_38_63 : 26;
2109 struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
2110 struct cvmx_usbnx_usbp_ctl_status_cn50xx
2112 #if __BYTE_ORDER == __BIG_ENDIAN
2113 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
2114 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
2115 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
2116 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
2117 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
2118 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
2119 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
2120 uint64_t otgdisable : 1; /**< OTG Block Disable */
2121 uint64_t portreset : 1; /**< Per_Port Reset */
2122 uint64_t drvvbus : 1; /**< Drive VBUS */
2123 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
2124 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
2125 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
2126 uint64_t bist_done : 1; /**< PHY Bist Done.
2127 Asserted at the end of the PHY BIST sequence. */
2128 uint64_t bist_err : 1; /**< PHY Bist Error.
2129 Indicates an internal error was detected during
2130 the BIST sequence. */
2131 uint64_t tdata_out : 4; /**< PHY Test Data Out.
2132 Presents either internaly generated signals or
2133 test register contents, based upon the value of
2134 test_data_out_sel. */
2135 uint64_t reserved_31_31 : 1;
2136 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
2137 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
2138 with byte-counts between packets. When set to 0
2139 the L2C DMA address is incremented to the next
2140 4-byte aligned address after adding byte-count. */
2141 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
2142 set to '0' for operation. */
2143 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
2144 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
2145 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
2146 This signal enables the pull-down resistance on
2147 the D+ line. '1' pull down-resistance is connected
2148 to D+/ '0' pull down resistance is not connected
2149 to D+. When an A/B device is acting as a host
2150 (downstream-facing port), dp_pulldown and
2151 dm_pulldown are enabled. This must not toggle
2152 during normal opeartion. */
2153 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
2154 This signal enables the pull-down resistance on
2155 the D- line. '1' pull down-resistance is connected
2156 to D-. '0' pull down resistance is not connected
2157 to D-. When an A/B device is acting as a host
2158 (downstream-facing port), dp_pulldown and
2159 dm_pulldown are enabled. This must not toggle
2160 during normal opeartion. */
2161 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
2162 USB is acting as device. This field needs to be
2163 set while the USB is in reset. */
2164 uint64_t reserved_19_22 : 4;
2165 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
2166 Enables or disables bit stuffing on data[15:8]
2167 when bit-stuffing is enabled. */
2168 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
2169 Enables or disables bit stuffing on data[7:0]
2170 when bit-stuffing is enabled. */
2171 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
2172 '1': During data transmission the receive is
2174 '0': During data transmission the receive is
2176 Must be '0' for normal operation. */
2177 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
2178 '1' The PHY's analog_test pin is enabled for the
2179 input and output of applicable analog test signals.
2180 '0' THe analog_test pin is disabled. */
2181 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
2182 Used to activate BIST in the PHY. */
2183 uint64_t tdata_sel : 1; /**< Test Data Out Select.
2184 '1' test_data_out[3:0] (PHY) register contents
2185 are output. '0' internaly generated signals are
2187 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
2188 Specifies the register address for writing to or
2189 reading from the PHY test interface register. */
2190 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
2191 This is a test bus. Data is present on [3:0],
2192 and its corresponding select (enable) is present
2194 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
2195 This is a test signal. When the USB Core is
2196 powered up (not in Susned Mode), an automatic
2197 tester can use this to disable phy_clock and
2198 free_clk, then re-eanable them with an aligned
2200 '1': The phy_clk and free_clk outputs are
2201 disabled. "0": The phy_clock and free_clk outputs
2202 are available within a specific period after the
2205 uint64_t ate_reset : 1;
2206 uint64_t tdata_in : 8;
2207 uint64_t taddr_in : 4;
2208 uint64_t tdata_sel : 1;
2209 uint64_t bist_enb : 1;
2210 uint64_t vtest_enb : 1;
2211 uint64_t loop_enb : 1;
2212 uint64_t tx_bs_en : 1;
2213 uint64_t tx_bs_enh : 1;
2214 uint64_t reserved_19_22 : 4;
2215 uint64_t hst_mode : 1;
2216 uint64_t dm_pulld : 1;
2217 uint64_t dp_pulld : 1;
2219 uint64_t usbp_bist : 1;
2220 uint64_t usbc_end : 1;
2221 uint64_t dma_bmode : 1;
2222 uint64_t txpreemphasistune : 1;
2223 uint64_t reserved_31_31 : 1;
2224 uint64_t tdata_out : 4;
2225 uint64_t bist_err : 1;
2226 uint64_t bist_done : 1;
2227 uint64_t hsbist : 1;
2228 uint64_t fsbist : 1;
2229 uint64_t lsbist : 1;
2230 uint64_t drvvbus : 1;
2231 uint64_t portreset : 1;
2232 uint64_t otgdisable : 1;
2233 uint64_t otgtune : 3;
2234 uint64_t compdistune : 3;
2235 uint64_t sqrxtune : 3;
2236 uint64_t txhsxvtune : 2;
2237 uint64_t txfslstune : 4;
2238 uint64_t txvreftune : 4;
2239 uint64_t txrisetune : 1;
2242 struct cvmx_usbnx_usbp_ctl_status_cn52xx
2244 #if __BYTE_ORDER == __BIG_ENDIAN
2245 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
2246 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
2247 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
2248 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
2249 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
2250 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
2251 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
2252 uint64_t otgdisable : 1; /**< OTG Block Disable */
2253 uint64_t portreset : 1; /**< Per_Port Reset */
2254 uint64_t drvvbus : 1; /**< Drive VBUS */
2255 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
2256 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
2257 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
2258 uint64_t bist_done : 1; /**< PHY Bist Done.
2259 Asserted at the end of the PHY BIST sequence. */
2260 uint64_t bist_err : 1; /**< PHY Bist Error.
2261 Indicates an internal error was detected during
2262 the BIST sequence. */
2263 uint64_t tdata_out : 4; /**< PHY Test Data Out.
2264 Presents either internaly generated signals or
2265 test register contents, based upon the value of
2266 test_data_out_sel. */
2267 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
2268 Normally should be set to zero.
2269 When customers have no intent to use USB PHY
2270 interface, they should:
2271 - still provide 3.3V to USB_VDD33, and
2272 - tie USB_REXT to 3.3V supply, and
2273 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
2274 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
2275 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
2276 with byte-counts between packets. When set to 0
2277 the L2C DMA address is incremented to the next
2278 4-byte aligned address after adding byte-count. */
2279 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
2280 set to '0' for operation. */
2281 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
2282 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
2283 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
2284 This signal enables the pull-down resistance on
2285 the D+ line. '1' pull down-resistance is connected
2286 to D+/ '0' pull down resistance is not connected
2287 to D+. When an A/B device is acting as a host
2288 (downstream-facing port), dp_pulldown and
2289 dm_pulldown are enabled. This must not toggle
2290 during normal opeartion. */
2291 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
2292 This signal enables the pull-down resistance on
2293 the D- line. '1' pull down-resistance is connected
2294 to D-. '0' pull down resistance is not connected
2295 to D-. When an A/B device is acting as a host
2296 (downstream-facing port), dp_pulldown and
2297 dm_pulldown are enabled. This must not toggle
2298 during normal opeartion. */
2299 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
2300 USB is acting as device. This field needs to be
2301 set while the USB is in reset. */
2302 uint64_t reserved_19_22 : 4;
2303 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
2304 Enables or disables bit stuffing on data[15:8]
2305 when bit-stuffing is enabled. */
2306 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
2307 Enables or disables bit stuffing on data[7:0]
2308 when bit-stuffing is enabled. */
2309 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
2310 '1': During data transmission the receive is
2312 '0': During data transmission the receive is
2314 Must be '0' for normal operation. */
2315 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
2316 '1' The PHY's analog_test pin is enabled for the
2317 input and output of applicable analog test signals.
2318 '0' THe analog_test pin is disabled. */
2319 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
2320 Used to activate BIST in the PHY. */
2321 uint64_t tdata_sel : 1; /**< Test Data Out Select.
2322 '1' test_data_out[3:0] (PHY) register contents
2323 are output. '0' internaly generated signals are
2325 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
2326 Specifies the register address for writing to or
2327 reading from the PHY test interface register. */
2328 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
2329 This is a test bus. Data is present on [3:0],
2330 and its corresponding select (enable) is present
2332 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
2333 This is a test signal. When the USB Core is
2334 powered up (not in Susned Mode), an automatic
2335 tester can use this to disable phy_clock and
2336 free_clk, then re-eanable them with an aligned
2338 '1': The phy_clk and free_clk outputs are
2339 disabled. "0": The phy_clock and free_clk outputs
2340 are available within a specific period after the
2343 uint64_t ate_reset : 1;
2344 uint64_t tdata_in : 8;
2345 uint64_t taddr_in : 4;
2346 uint64_t tdata_sel : 1;
2347 uint64_t bist_enb : 1;
2348 uint64_t vtest_enb : 1;
2349 uint64_t loop_enb : 1;
2350 uint64_t tx_bs_en : 1;
2351 uint64_t tx_bs_enh : 1;
2352 uint64_t reserved_19_22 : 4;
2353 uint64_t hst_mode : 1;
2354 uint64_t dm_pulld : 1;
2355 uint64_t dp_pulld : 1;
2357 uint64_t usbp_bist : 1;
2358 uint64_t usbc_end : 1;
2359 uint64_t dma_bmode : 1;
2360 uint64_t txpreemphasistune : 1;
2362 uint64_t tdata_out : 4;
2363 uint64_t bist_err : 1;
2364 uint64_t bist_done : 1;
2365 uint64_t hsbist : 1;
2366 uint64_t fsbist : 1;
2367 uint64_t lsbist : 1;
2368 uint64_t drvvbus : 1;
2369 uint64_t portreset : 1;
2370 uint64_t otgdisable : 1;
2371 uint64_t otgtune : 3;
2372 uint64_t compdistune : 3;
2373 uint64_t sqrxtune : 3;
2374 uint64_t txhsxvtune : 2;
2375 uint64_t txfslstune : 4;
2376 uint64_t txvreftune : 4;
2377 uint64_t txrisetune : 1;
2380 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1;
2381 struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx;
2382 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1;
2384 typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t;
projects / FreeBSD / releng / 9.2.git / blob