sys/dev/acpica/acpi_hpet.c

   1 /*-
   2  * Copyright (c) 2005 Poul-Henning Kamp
   3  * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_acpi.h"
  32 #if defined(__amd64__) || defined(__ia64__)
  33 #define DEV_APIC
  34 #else
  35 #include "opt_apic.h"
  36 #endif
  37 #include <sys/param.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/module.h>
  41 #include <sys/proc.h>
  42 #include <sys/rman.h>
  43 #include <sys/time.h>
  44 #include <sys/smp.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/timeet.h>
  47 #include <sys/timetc.h>
  48
  49 #include <contrib/dev/acpica/include/acpi.h>
  50 #include <contrib/dev/acpica/include/accommon.h>
  51
  52 #include <dev/acpica/acpivar.h>
  53 #include <dev/acpica/acpi_hpet.h>
  54
  55 #ifdef DEV_APIC
  56 #include "pcib_if.h"
  57 #endif
  58
  59 #define HPET_VENDID_AMD         0x4353
  60 #define HPET_VENDID_AMD2        0x1022
  61 #define HPET_VENDID_INTEL       0x8086
  62 #define HPET_VENDID_NVIDIA      0x10de
  63 #define HPET_VENDID_SW          0x1166
  64
  65 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
  66
  67 static devclass_t hpet_devclass;
  68
  69 /* ACPI CA debugging */
  70 #define _COMPONENT      ACPI_TIMER
  71 ACPI_MODULE_NAME("HPET")
  72
  73 struct hpet_softc {
  74         device_t                dev;
  75         int                     mem_rid;
  76         int                     intr_rid;
  77         int                     irq;
  78         int                     useirq;
  79         int                     legacy_route;
  80         int                     per_cpu;
  81         uint32_t                allowed_irqs;
  82         struct resource         *mem_res;
  83         struct resource         *intr_res;
  84         void                    *intr_handle;
  85         ACPI_HANDLE             handle;
  86         uint64_t                freq;
  87         uint32_t                caps;
  88         struct timecounter      tc;
  89         struct hpet_timer {
  90                 struct eventtimer       et;
  91                 struct hpet_softc       *sc;
  92                 int                     num;
  93                 int                     mode;
  94                 int                     intr_rid;
  95                 int                     irq;
  96                 int                     pcpu_cpu;
  97                 int                     pcpu_misrouted;
  98                 int                     pcpu_master;
  99                 int                     pcpu_slaves[MAXCPU];
 100                 struct resource         *intr_res;
 101                 void                    *intr_handle;
 102                 uint32_t                caps;
 103                 uint32_t                vectors;
 104                 uint32_t                div;
 105                 uint32_t                next;
 106                 char                    name[8];
 107         }                       t[32];
 108         int                     num_timers;
 109 };
 110
 111 static u_int hpet_get_timecount(struct timecounter *tc);
 112 static void hpet_test(struct hpet_softc *sc);
 113
 114 static char *hpet_ids[] = { "PNP0103", NULL };
 115
 116 static u_int
 117 hpet_get_timecount(struct timecounter *tc)
 118 {
 119         struct hpet_softc *sc;
 120
 121         sc = tc->tc_priv;
 122         return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
 123 }
 124
 125 static void
 126 hpet_enable(struct hpet_softc *sc)
 127 {
 128         uint32_t val;
 129
 130         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 131         if (sc->legacy_route)
 132                 val |= HPET_CNF_LEG_RT;
 133         else
 134                 val &= ~HPET_CNF_LEG_RT;
 135         val |= HPET_CNF_ENABLE;
 136         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 137 }
 138
 139 static void
 140 hpet_disable(struct hpet_softc *sc)
 141 {
 142         uint32_t val;
 143
 144         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 145         val &= ~HPET_CNF_ENABLE;
 146         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 147 }
 148
 149 static int
 150 hpet_start(struct eventtimer *et,
 151     struct bintime *first, struct bintime *period)
 152 {
 153         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 154         struct hpet_timer *t;
 155         struct hpet_softc *sc = mt->sc;
 156         uint32_t fdiv, now;
 157
 158         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 159         if (period != NULL) {
 160                 t->mode = 1;
 161                 t->div = (sc->freq * (period->frac >> 32)) >> 32;
 162                 if (period->sec != 0)
 163                         t->div += sc->freq * period->sec;
 164         } else {
 165                 t->mode = 2;
 166                 t->div = 0;
 167         }
 168         if (first != NULL) {
 169                 fdiv = (sc->freq * (first->frac >> 32)) >> 32;
 170                 if (first->sec != 0)
 171                         fdiv += sc->freq * first->sec;
 172         } else
 173                 fdiv = t->div;
 174         if (t->irq < 0)
 175                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 176         t->caps |= HPET_TCNF_INT_ENB;
 177         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 178 restart:
 179         t->next = now + fdiv;
 180         if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 181                 t->caps |= HPET_TCNF_TYPE;
 182                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 183                     t->caps | HPET_TCNF_VAL_SET);
 184                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 185                     t->next);
 186                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 187                     t->div);
 188         } else {
 189                 t->caps &= ~HPET_TCNF_TYPE;
 190                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 191                     t->caps);
 192                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 193                     t->next);
 194         }
 195         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 196         if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
 197                 fdiv *= 2;
 198                 goto restart;
 199         }
 200         return (0);
 201 }
 202
 203 static int
 204 hpet_stop(struct eventtimer *et)
 205 {
 206         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 207         struct hpet_timer *t;
 208         struct hpet_softc *sc = mt->sc;
 209
 210         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 211         t->mode = 0;
 212         t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
 213         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 214         return (0);
 215 }
 216
 217 static int
 218 hpet_intr_single(void *arg)
 219 {
 220         struct hpet_timer *t = (struct hpet_timer *)arg;
 221         struct hpet_timer *mt;
 222         struct hpet_softc *sc = t->sc;
 223         uint32_t now;
 224
 225         if (t->mode == 0)
 226                 return (FILTER_STRAY);
 227         /* Check that per-CPU timer interrupt reached right CPU. */
 228         if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
 229                 if ((++t->pcpu_misrouted) % 32 == 0) {
 230                         printf("HPET interrupt routed to the wrong CPU"
 231                             " (timer %d CPU %d -> %d)!\n",
 232                             t->num, t->pcpu_cpu, curcpu);
 233                 }
 234
 235                 /*
 236                  * Reload timer, hoping that next time may be more lucky
 237                  * (system will manage proper interrupt binding).
 238                  */
 239                 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
 240                     t->mode == 2) {
 241                         t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
 242                             sc->freq / 8;
 243                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 244                             t->next);
 245                 }
 246                 return (FILTER_HANDLED);
 247         }
 248         if (t->mode == 1 &&
 249             (t->caps & HPET_TCAP_PER_INT) == 0) {
 250                 t->next += t->div;
 251                 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 252                 if ((int32_t)((now + t->div / 2) - t->next) > 0)
 253                         t->next = now + t->div / 2;
 254                 bus_write_4(sc->mem_res,
 255                     HPET_TIMER_COMPARATOR(t->num), t->next);
 256         } else if (t->mode == 2)
 257                 t->mode = 0;
 258         mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
 259         if (mt->et.et_active)
 260                 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
 261         return (FILTER_HANDLED);
 262 }
 263
 264 static int
 265 hpet_intr(void *arg)
 266 {
 267         struct hpet_softc *sc = (struct hpet_softc *)arg;
 268         int i;
 269         uint32_t val;
 270
 271         val = bus_read_4(sc->mem_res, HPET_ISR);
 272         if (val) {
 273                 bus_write_4(sc->mem_res, HPET_ISR, val);
 274                 val &= sc->useirq;
 275                 for (i = 0; i < sc->num_timers; i++) {
 276                         if ((val & (1 << i)) == 0)
 277                                 continue;
 278                         hpet_intr_single(&sc->t[i]);
 279                 }
 280                 return (FILTER_HANDLED);
 281         }
 282         return (FILTER_STRAY);
 283 }
 284
 285 static ACPI_STATUS
 286 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
 287     void **status)
 288 {
 289         char            **ids;
 290         uint32_t        id = (uint32_t)(uintptr_t)context;
 291         uint32_t        uid = 0;
 292
 293         for (ids = hpet_ids; *ids != NULL; ids++) {
 294                 if (acpi_MatchHid(handle, *ids))
 295                         break;
 296         }
 297         if (*ids == NULL)
 298                 return (AE_OK);
 299         if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
 300             id == uid)
 301                 *((int *)status) = 1;
 302         return (AE_OK);
 303 }
 304
 305 /*
 306  * Find an existing IRQ resource that matches the requested IRQ range
 307  * and return its RID.  If one is not found, use a new RID.
 308  */
 309 static int
 310 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
 311 {
 312         u_long irq;
 313         int error, rid;
 314
 315         for (rid = 0;; rid++) {
 316                 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
 317                 if (error != 0 || (start <= irq && irq <= end))
 318                         return (rid);
 319         }
 320 }
 321
 322 /* Discover the HPET via the ACPI table of the same name. */
 323 static void
 324 hpet_identify(driver_t *driver, device_t parent)
 325 {
 326         ACPI_TABLE_HPET *hpet;
 327         ACPI_STATUS     status;
 328         device_t        child;
 329         int             i, found;
 330
 331         /* Only one HPET device can be added. */
 332         if (devclass_get_device(hpet_devclass, 0))
 333                 return;
 334         for (i = 1; ; i++) {
 335                 /* Search for HPET table. */
 336                 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
 337                 if (ACPI_FAILURE(status))
 338                         return;
 339                 /* Search for HPET device with same ID. */
 340                 found = 0;
 341                 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
 342                     100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found);
 343                 /* If found - let it be probed in normal way. */
 344                 if (found)
 345                         continue;
 346                 /* If not - create it from table info. */
 347                 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
 348                 if (child == NULL) {
 349                         printf("%s: can't add child\n", __func__);
 350                         continue;
 351                 }
 352                 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
 353                     HPET_MEM_WIDTH);
 354         }
 355 }
 356
 357 static int
 358 hpet_probe(device_t dev)
 359 {
 360         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 361
 362         if (acpi_disabled("hpet"))
 363                 return (ENXIO);
 364         if (acpi_get_handle(dev) != NULL &&
 365             ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
 366                 return (ENXIO);
 367
 368         device_set_desc(dev, "High Precision Event Timer");
 369         return (0);
 370 }
 371
 372 static int
 373 hpet_attach(device_t dev)
 374 {
 375         struct hpet_softc *sc;
 376         struct hpet_timer *t;
 377         int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
 378         int pcpu_master;
 379         static int maxhpetet = 0;
 380         uint32_t val, val2, cvectors, dvectors;
 381         uint16_t vendor, rev;
 382
 383         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 384
 385         sc = device_get_softc(dev);
 386         sc->dev = dev;
 387         sc->handle = acpi_get_handle(dev);
 388
 389         sc->mem_rid = 0;
 390         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 391             RF_ACTIVE);
 392         if (sc->mem_res == NULL)
 393                 return (ENOMEM);
 394
 395         /* Validate that we can access the whole region. */
 396         if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
 397                 device_printf(dev, "memory region width %ld too small\n",
 398                     rman_get_size(sc->mem_res));
 399                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 400                 return (ENXIO);
 401         }
 402
 403         /* Be sure timer is enabled. */
 404         hpet_enable(sc);
 405
 406         /* Read basic statistics about the timer. */
 407         val = bus_read_4(sc->mem_res, HPET_PERIOD);
 408         if (val == 0) {
 409                 device_printf(dev, "invalid period\n");
 410                 hpet_disable(sc);
 411                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 412                 return (ENXIO);
 413         }
 414
 415         sc->freq = (1000000000000000LL + val / 2) / val;
 416         sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
 417         vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
 418         rev = sc->caps & HPET_CAP_REV_ID;
 419         num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
 420         /*
 421          * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
 422          * Specification and provides an off by one number
 423          * of timers/comparators.
 424          * Additionally, they use unregistered value in VENDOR_ID field.
 425          */
 426         if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
 427                 num_timers--;
 428         sc->num_timers = num_timers;
 429         if (bootverbose) {
 430                 device_printf(dev,
 431                     "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
 432                     vendor, rev, sc->freq,
 433                     (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
 434                     num_timers,
 435                     (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
 436         }
 437         for (i = 0; i < num_timers; i++) {
 438                 t = &sc->t[i];
 439                 t->sc = sc;
 440                 t->num = i;
 441                 t->mode = 0;
 442                 t->intr_rid = -1;
 443                 t->irq = -1;
 444                 t->pcpu_cpu = -1;
 445                 t->pcpu_misrouted = 0;
 446                 t->pcpu_master = -1;
 447                 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
 448                 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
 449                 if (bootverbose) {
 450                         device_printf(dev,
 451                             " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
 452                             t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
 453                             (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
 454                             (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
 455                             (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
 456                 }
 457         }
 458         if (testenv("debug.acpi.hpet_test"))
 459                 hpet_test(sc);
 460         /*
 461          * Don't attach if the timer never increments.  Since the spec
 462          * requires it to be at least 10 MHz, it has to change in 1 us.
 463          */
 464         val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 465         DELAY(1);
 466         val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 467         if (val == val2) {
 468                 device_printf(dev, "HPET never increments, disabling\n");
 469                 hpet_disable(sc);
 470                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 471                 return (ENXIO);
 472         }
 473         /* Announce first HPET as timecounter. */
 474         if (device_get_unit(dev) == 0) {
 475                 sc->tc.tc_get_timecount = hpet_get_timecount,
 476                 sc->tc.tc_counter_mask = ~0u,
 477                 sc->tc.tc_name = "HPET",
 478                 sc->tc.tc_quality = 950,
 479                 sc->tc.tc_frequency = sc->freq;
 480                 sc->tc.tc_priv = sc;
 481                 tc_init(&sc->tc);
 482         }
 483         /* If not disabled - setup and announce event timers. */
 484         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 485              "clock", &i) == 0 && i == 0)
 486                 return (0);
 487
 488         /* Check whether we can and want legacy routing. */
 489         sc->legacy_route = 0;
 490         resource_int_value(device_get_name(dev), device_get_unit(dev),
 491              "legacy_route", &sc->legacy_route);
 492         if ((sc->caps & HPET_CAP_LEG_RT) == 0)
 493                 sc->legacy_route = 0;
 494         if (sc->legacy_route) {
 495                 sc->t[0].vectors = 0;
 496                 sc->t[1].vectors = 0;
 497         }
 498
 499         /* Check what IRQs we want use. */
 500         /* By default allow any PCI IRQs. */
 501         sc->allowed_irqs = 0xffff0000;
 502         /*
 503          * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
 504          * Lower are also not always working for different reasons.
 505          * SB800 fixed it, but seems do not implements level triggering
 506          * properly, that makes it very unreliable - it freezes after any
 507          * interrupt loss. Avoid legacy IRQs for AMD.
 508          */
 509         if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2)
 510                 sc->allowed_irqs = 0x00000000;
 511         /*
 512          * NVidia MCP5x chipsets have number of unexplained interrupt
 513          * problems. For some reason, using HPET interrupts breaks HDA sound.
 514          */
 515         if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
 516                 sc->allowed_irqs = 0x00000000;
 517         /*
 518          * ServerWorks HT1000 reported to have problems with IRQs >= 16.
 519          * Lower IRQs are working, but allowed mask is not set correctly.
 520          * Legacy_route mode works fine.
 521          */
 522         if (vendor == HPET_VENDID_SW && rev <= 0x01)
 523                 sc->allowed_irqs = 0x00000000;
 524         /*
 525          * Neither QEMU nor VirtualBox report supported IRQs correctly.
 526          * The only way to use HPET there is to specify IRQs manually
 527          * and/or use legacy_route. Legacy_route mode works on both.
 528          */
 529         if (vm_guest)
 530                 sc->allowed_irqs = 0x00000000;
 531         /* Let user override. */
 532         resource_int_value(device_get_name(dev), device_get_unit(dev),
 533              "allowed_irqs", &sc->allowed_irqs);
 534
 535         /* Get how much per-CPU timers we should try to provide. */
 536         sc->per_cpu = 1;
 537         resource_int_value(device_get_name(dev), device_get_unit(dev),
 538              "per_cpu", &sc->per_cpu);
 539
 540         num_msi = 0;
 541         sc->useirq = 0;
 542         /* Find IRQ vectors for all timers. */
 543         cvectors = sc->allowed_irqs & 0xffff0000;
 544         dvectors = sc->allowed_irqs & 0x0000ffff;
 545         if (sc->legacy_route)
 546                 dvectors &= 0x0000fefe;
 547         for (i = 0; i < num_timers; i++) {
 548                 t = &sc->t[i];
 549                 if (sc->legacy_route && i < 2)
 550                         t->irq = (i == 0) ? 0 : 8;
 551 #ifdef DEV_APIC
 552                 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
 553                         if ((j = PCIB_ALLOC_MSIX(
 554                             device_get_parent(device_get_parent(dev)), dev,
 555                             &t->irq))) {
 556                                 device_printf(dev,
 557                                     "Can't allocate interrupt for t%d.\n", j);
 558                         }
 559                 }
 560 #endif
 561                 else if (dvectors & t->vectors) {
 562                         t->irq = ffs(dvectors & t->vectors) - 1;
 563                         dvectors &= ~(1 << t->irq);
 564                 }
 565                 if (t->irq >= 0) {
 566                         t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
 567                         t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 568                             &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
 569                         if (t->intr_res == NULL) {
 570                                 t->irq = -1;
 571                                 device_printf(dev,
 572                                     "Can't map interrupt for t%d.\n", i);
 573                         } else if (bus_setup_intr(dev, t->intr_res,
 574                             INTR_TYPE_CLK, hpet_intr_single, NULL, t,
 575                             &t->intr_handle) != 0) {
 576                                 t->irq = -1;
 577                                 device_printf(dev,
 578                                     "Can't setup interrupt for t%d.\n", i);
 579                         } else {
 580                                 bus_describe_intr(dev, t->intr_res,
 581                                     t->intr_handle, "t%d", i);
 582                                 num_msi++;
 583                         }
 584                 }
 585                 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
 586                         cvectors &= t->vectors;
 587                         sc->useirq |= (1 << i);
 588                 }
 589         }
 590         if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
 591                 sc->legacy_route = 0;
 592         if (sc->legacy_route)
 593                 hpet_enable(sc);
 594         /* Group timers for per-CPU operation. */
 595         num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
 596         num_percpu_t = num_percpu_et * mp_ncpus;
 597         pcpu_master = 0;
 598         cur_cpu = CPU_FIRST();
 599         for (i = 0; i < num_timers; i++) {
 600                 t = &sc->t[i];
 601                 if (t->irq >= 0 && num_percpu_t > 0) {
 602                         if (cur_cpu == CPU_FIRST())
 603                                 pcpu_master = i;
 604                         t->pcpu_cpu = cur_cpu;
 605                         t->pcpu_master = pcpu_master;
 606                         sc->t[pcpu_master].
 607                             pcpu_slaves[cur_cpu] = i;
 608                         bus_bind_intr(dev, t->intr_res, cur_cpu);
 609                         cur_cpu = CPU_NEXT(cur_cpu);
 610                         num_percpu_t--;
 611                 } else if (t->irq >= 0)
 612                         bus_bind_intr(dev, t->intr_res, CPU_FIRST());
 613         }
 614         bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
 615         sc->irq = -1;
 616         /* If at least one timer needs legacy IRQ - set it up. */
 617         if (sc->useirq) {
 618                 j = i = fls(cvectors) - 1;
 619                 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
 620                         j--;
 621                 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
 622                 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 623                     &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
 624                 if (sc->intr_res == NULL)
 625                         device_printf(dev, "Can't map interrupt.\n");
 626                 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
 627                     hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
 628                         device_printf(dev, "Can't setup interrupt.\n");
 629                 } else {
 630                         sc->irq = rman_get_start(sc->intr_res);
 631                         /* Bind IRQ to BSP to avoid live migration. */
 632                         bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
 633                 }
 634         }
 635         /* Program and announce event timers. */
 636         for (i = 0; i < num_timers; i++) {
 637                 t = &sc->t[i];
 638                 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
 639                 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
 640                 t->caps &= ~(HPET_TCNF_INT_TYPE);
 641                 t->caps |= HPET_TCNF_32MODE;
 642                 if (t->irq >= 0 && sc->legacy_route && i < 2) {
 643                         /* Legacy route doesn't need more configuration. */
 644                 } else
 645 #ifdef DEV_APIC
 646                 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
 647                         uint64_t addr;
 648                         uint32_t data;
 649
 650                         if (PCIB_MAP_MSI(
 651                             device_get_parent(device_get_parent(dev)), dev,
 652                             t->irq, &addr, &data) == 0) {
 653                                 bus_write_4(sc->mem_res,
 654                                     HPET_TIMER_FSB_ADDR(i), addr);
 655                                 bus_write_4(sc->mem_res,
 656                                     HPET_TIMER_FSB_VAL(i), data);
 657                                 t->caps |= HPET_TCNF_FSB_EN;
 658                         } else
 659                                 t->irq = -2;
 660                 } else
 661 #endif
 662                 if (t->irq >= 0)
 663                         t->caps |= (t->irq << 9);
 664                 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
 665                         t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
 666                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
 667                 /* Skip event timers without set up IRQ. */
 668                 if (t->irq < 0 &&
 669                     (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
 670                         continue;
 671                 /* Announce the reset. */
 672                 if (maxhpetet == 0)
 673                         t->et.et_name = "HPET";
 674                 else {
 675                         sprintf(t->name, "HPET%d", maxhpetet);
 676                         t->et.et_name = t->name;
 677                 }
 678                 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 679                 t->et.et_quality = 450;
 680                 if (t->pcpu_master >= 0) {
 681                         t->et.et_flags |= ET_FLAGS_PERCPU;
 682                         t->et.et_quality += 100;
 683                 }
 684                 if ((t->caps & HPET_TCAP_PER_INT) == 0)
 685                         t->et.et_quality -= 10;
 686                 t->et.et_frequency = sc->freq;
 687                 t->et.et_min_period.sec = 0;
 688                 t->et.et_min_period.frac =
 689                     (((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq) << 32;
 690                 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq;
 691                 t->et.et_max_period.frac =
 692                     ((0xfffffffeLLU << 32) / sc->freq) << 32;
 693                 t->et.et_start = hpet_start;
 694                 t->et.et_stop = hpet_stop;
 695                 t->et.et_priv = &sc->t[i];
 696                 if (t->pcpu_master < 0 || t->pcpu_master == i) {
 697                         et_register(&t->et);
 698                         maxhpetet++;
 699                 }
 700         }
 701         return (0);
 702 }
 703
 704 static int
 705 hpet_detach(device_t dev)
 706 {
 707         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 708
 709         /* XXX Without a tc_remove() function, we can't detach. */
 710         return (EBUSY);
 711 }
 712
 713 static int
 714 hpet_suspend(device_t dev)
 715 {
 716 //      struct hpet_softc *sc;
 717
 718         /*
 719          * Disable the timer during suspend.  The timer will not lose
 720          * its state in S1 or S2, but we are required to disable
 721          * it.
 722          */
 723 //      sc = device_get_softc(dev);
 724 //      hpet_disable(sc);
 725
 726         return (0);
 727 }
 728
 729 static int
 730 hpet_resume(device_t dev)
 731 {
 732         struct hpet_softc *sc;
 733         struct hpet_timer *t;
 734         int i;
 735
 736         /* Re-enable the timer after a resume to keep the clock advancing. */
 737         sc = device_get_softc(dev);
 738         hpet_enable(sc);
 739         /* Restart event timers that were running on suspend. */
 740         for (i = 0; i < sc->num_timers; i++) {
 741                 t = &sc->t[i];
 742 #ifdef DEV_APIC
 743                 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
 744                         uint64_t addr;
 745                         uint32_t data;
 746
 747                         if (PCIB_MAP_MSI(
 748                             device_get_parent(device_get_parent(dev)), dev,
 749                             t->irq, &addr, &data) == 0) {
 750                                 bus_write_4(sc->mem_res,
 751                                     HPET_TIMER_FSB_ADDR(i), addr);
 752                                 bus_write_4(sc->mem_res,
 753                                     HPET_TIMER_FSB_VAL(i), data);
 754                         }
 755                 }
 756 #endif
 757                 if (t->mode == 0)
 758                         continue;
 759                 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 760                 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 761                         t->caps |= HPET_TCNF_TYPE;
 762                         t->next += t->div;
 763                         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 764                             t->caps | HPET_TCNF_VAL_SET);
 765                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 766                             t->next);
 767                         bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
 768                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 769                             t->div);
 770                 } else {
 771                         t->next += sc->freq / 1024;
 772                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 773                             t->next);
 774                 }
 775                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 776                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 777         }
 778         return (0);
 779 }
 780
 781 /* Print some basic latency/rate information to assist in debugging. */
 782 static void
 783 hpet_test(struct hpet_softc *sc)
 784 {
 785         int i;
 786         uint32_t u1, u2;
 787         struct bintime b0, b1, b2;
 788         struct timespec ts;
 789
 790         binuptime(&b0);
 791         binuptime(&b0);
 792         binuptime(&b1);
 793         u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 794         for (i = 1; i < 1000; i++)
 795                 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 796         binuptime(&b2);
 797         u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 798
 799         bintime_sub(&b2, &b1);
 800         bintime_sub(&b1, &b0);
 801         bintime_sub(&b2, &b1);
 802         bintime2timespec(&b2, &ts);
 803
 804         device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
 805             (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
 806
 807         device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
 808 }
 809
 810 #ifdef DEV_APIC
 811 static int
 812 hpet_remap_intr(device_t dev, device_t child, u_int irq)
 813 {
 814         struct hpet_softc *sc = device_get_softc(dev);
 815         struct hpet_timer *t;
 816         uint64_t addr;
 817         uint32_t data;
 818         int error, i;
 819
 820         for (i = 0; i < sc->num_timers; i++) {
 821                 t = &sc->t[i];
 822                 if (t->irq != irq)
 823                         continue;
 824                 error = PCIB_MAP_MSI(
 825                     device_get_parent(device_get_parent(dev)), dev,
 826                     irq, &addr, &data);
 827                 if (error)
 828                         return (error);
 829                 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
 830                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
 831                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
 832                 hpet_enable(sc);
 833                 return (0);
 834         }
 835         return (ENOENT);
 836 }
 837 #endif
 838
 839 static device_method_t hpet_methods[] = {
 840         /* Device interface */
 841         DEVMETHOD(device_identify, hpet_identify),
 842         DEVMETHOD(device_probe, hpet_probe),
 843         DEVMETHOD(device_attach, hpet_attach),
 844         DEVMETHOD(device_detach, hpet_detach),
 845         DEVMETHOD(device_suspend, hpet_suspend),
 846         DEVMETHOD(device_resume, hpet_resume),
 847
 848 #ifdef DEV_APIC
 849         DEVMETHOD(bus_remap_intr, hpet_remap_intr),
 850 #endif
 851
 852         {0, 0}
 853 };
 854
 855 static driver_t hpet_driver = {
 856         "hpet",
 857         hpet_methods,
 858         sizeof(struct hpet_softc),
 859 };
 860
 861 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
 862 MODULE_DEPEND(hpet, acpi, 1, 1, 1);