2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/led/led.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
54 #include <cam/cam_ccb.h>
55 #include <cam/cam_sim.h>
56 #include <cam/cam_xpt_sim.h>
57 #include <cam/cam_debug.h>
59 /* local prototypes */
60 static int ahci_setup_interrupt(device_t dev);
61 static void ahci_intr(void *data);
62 static void ahci_intr_one(void *data);
63 static int ahci_suspend(device_t dev);
64 static int ahci_resume(device_t dev);
65 static int ahci_ch_init(device_t dev);
66 static int ahci_ch_deinit(device_t dev);
67 static int ahci_ch_suspend(device_t dev);
68 static int ahci_ch_resume(device_t dev);
69 static void ahci_ch_pm(void *arg);
70 static void ahci_ch_intr_locked(void *data);
71 static void ahci_ch_intr(void *data);
72 static void ahci_ch_led(void *priv, int onoff);
73 static int ahci_ctlr_reset(device_t dev);
74 static int ahci_ctlr_setup(device_t dev);
75 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
77 static void ahci_execute_transaction(struct ahci_slot *slot);
78 static void ahci_timeout(struct ahci_slot *slot);
79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
81 static void ahci_dmainit(device_t dev);
82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
83 static void ahci_dmafini(device_t dev);
84 static void ahci_slotsalloc(device_t dev);
85 static void ahci_slotsfree(device_t dev);
86 static void ahci_reset(device_t dev);
87 static void ahci_start(device_t dev, int fbs);
88 static void ahci_stop(device_t dev);
89 static void ahci_clo(device_t dev);
90 static void ahci_start_fr(device_t dev);
91 static void ahci_stop_fr(device_t dev);
93 static int ahci_sata_connect(struct ahci_channel *ch);
94 static int ahci_sata_phy_reset(device_t dev);
95 static int ahci_wait_ready(device_t dev, int t, int t0);
97 static void ahci_issue_recovery(device_t dev);
98 static void ahci_process_read_log(device_t dev, union ccb *ccb);
99 static void ahci_process_request_sense(device_t dev, union ccb *ccb);
101 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
102 static void ahcipoll(struct cam_sim *sim);
104 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
111 #define AHCI_Q_NOFORCE 1
112 #define AHCI_Q_NOPMP 2
113 #define AHCI_Q_NONCQ 4
115 #define AHCI_Q_2CH 16
116 #define AHCI_Q_4CH 32
117 #define AHCI_Q_EDGEIS 64
118 #define AHCI_Q_SATA2 128
119 #define AHCI_Q_NOBSYRES 256
120 #define AHCI_Q_NOAA 512
121 #define AHCI_Q_NOCOUNT 1024
122 #define AHCI_Q_ALTSIG 2048
123 #define AHCI_Q_NOMSI 4096
125 #define AHCI_Q_BIT_STRING \
141 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI},
142 {0x43901002, 0x00, "ATI IXP700", 0},
143 {0x43911002, 0x00, "ATI IXP700", 0},
144 {0x43921002, 0x00, "ATI IXP700", 0},
145 {0x43931002, 0x00, "ATI IXP700", 0},
146 {0x43941002, 0x00, "ATI IXP800", 0},
147 {0x43951002, 0x00, "ATI IXP800", 0},
148 {0x78001022, 0x00, "AMD Hudson-2", 0},
149 {0x78011022, 0x00, "AMD Hudson-2", 0},
150 {0x78021022, 0x00, "AMD Hudson-2", 0},
151 {0x78031022, 0x00, "AMD Hudson-2", 0},
152 {0x78041022, 0x00, "AMD Hudson-2", 0},
153 {0x06121b21, 0x00, "ASMedia ASM1061", 0},
154 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
155 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
156 {0x26818086, 0x00, "Intel ESB2", 0},
157 {0x26828086, 0x00, "Intel ESB2", 0},
158 {0x26838086, 0x00, "Intel ESB2", 0},
159 {0x27c18086, 0x00, "Intel ICH7", 0},
160 {0x27c38086, 0x00, "Intel ICH7", 0},
161 {0x27c58086, 0x00, "Intel ICH7M", 0},
162 {0x27c68086, 0x00, "Intel ICH7M", 0},
163 {0x28218086, 0x00, "Intel ICH8", 0},
164 {0x28228086, 0x00, "Intel ICH8", 0},
165 {0x28248086, 0x00, "Intel ICH8", 0},
166 {0x28298086, 0x00, "Intel ICH8M", 0},
167 {0x282a8086, 0x00, "Intel ICH8M", 0},
168 {0x29228086, 0x00, "Intel ICH9", 0},
169 {0x29238086, 0x00, "Intel ICH9", 0},
170 {0x29248086, 0x00, "Intel ICH9", 0},
171 {0x29258086, 0x00, "Intel ICH9", 0},
172 {0x29278086, 0x00, "Intel ICH9", 0},
173 {0x29298086, 0x00, "Intel ICH9M", 0},
174 {0x292a8086, 0x00, "Intel ICH9M", 0},
175 {0x292b8086, 0x00, "Intel ICH9M", 0},
176 {0x292c8086, 0x00, "Intel ICH9M", 0},
177 {0x292f8086, 0x00, "Intel ICH9M", 0},
178 {0x294d8086, 0x00, "Intel ICH9", 0},
179 {0x294e8086, 0x00, "Intel ICH9M", 0},
180 {0x3a058086, 0x00, "Intel ICH10", 0},
181 {0x3a228086, 0x00, "Intel ICH10", 0},
182 {0x3a258086, 0x00, "Intel ICH10", 0},
183 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
184 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
185 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
186 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
187 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
188 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
189 {0x1c028086, 0x00, "Intel Cougar Point", 0},
190 {0x1c038086, 0x00, "Intel Cougar Point", 0},
191 {0x1c048086, 0x00, "Intel Cougar Point", 0},
192 {0x1c058086, 0x00, "Intel Cougar Point", 0},
193 {0x1d028086, 0x00, "Intel Patsburg", 0},
194 {0x1d048086, 0x00, "Intel Patsburg", 0},
195 {0x1d068086, 0x00, "Intel Patsburg", 0},
196 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
197 {0x1e028086, 0x00, "Intel Panther Point", 0},
198 {0x1e038086, 0x00, "Intel Panther Point", 0},
199 {0x1e048086, 0x00, "Intel Panther Point", 0},
200 {0x1e058086, 0x00, "Intel Panther Point", 0},
201 {0x1e068086, 0x00, "Intel Panther Point", 0},
202 {0x1e078086, 0x00, "Intel Panther Point", 0},
203 {0x1e0e8086, 0x00, "Intel Panther Point", 0},
204 {0x1e0f8086, 0x00, "Intel Panther Point", 0},
205 {0x8c028086, 0x00, "Intel Lynx Point", 0},
206 {0x8c038086, 0x00, "Intel Lynx Point", 0},
207 {0x8c048086, 0x00, "Intel Lynx Point", 0},
208 {0x8c058086, 0x00, "Intel Lynx Point", 0},
209 {0x8c068086, 0x00, "Intel Lynx Point", 0},
210 {0x8c078086, 0x00, "Intel Lynx Point", 0},
211 {0x8c0e8086, 0x00, "Intel Lynx Point", 0},
212 {0x8c0f8086, 0x00, "Intel Lynx Point", 0},
213 {0x23238086, 0x00, "Intel DH89xxCC", 0},
214 {0x2360197b, 0x00, "JMicron JMB360", 0},
215 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
216 {0x2362197b, 0x00, "JMicron JMB362", 0},
217 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
218 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
219 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
220 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
221 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
223 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
224 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
225 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
226 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
227 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
228 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
229 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES},
230 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
231 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
232 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES},
233 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
234 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
235 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES},
236 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES},
237 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES},
238 {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES},
239 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
240 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
241 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES},
242 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
243 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
244 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
245 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
246 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
247 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
248 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
249 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
250 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES},
251 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES},
252 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES},
253 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
254 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
255 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
256 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
257 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
258 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
259 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
260 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
261 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
262 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
263 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
264 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
265 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
266 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
267 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
268 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
269 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
270 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
271 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
272 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
273 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
274 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
275 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
276 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
277 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
278 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
279 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
280 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
281 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
282 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
283 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
284 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
285 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
286 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
287 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
288 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
289 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
290 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
291 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
292 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
293 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
294 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
295 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
296 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
297 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
298 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
299 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
300 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
301 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
302 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
303 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
304 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
305 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
306 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
307 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
308 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
309 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
310 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
311 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
312 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
313 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
314 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
315 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
316 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
317 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
318 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
319 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
320 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
321 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
322 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
323 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
324 {0x11841039, 0x00, "SiS 966", 0},
325 {0x11851039, 0x00, "SiS 968", 0},
326 {0x01861039, 0x00, "SiS 968", 0},
327 {0x00000000, 0x00, NULL, 0}
330 #define recovery_type spriv_field0
331 #define RECOVERY_NONE 0
332 #define RECOVERY_READ_LOG 1
333 #define RECOVERY_REQUEST_SENSE 2
334 #define recovery_slot spriv_field1
336 static int force_ahci = 1;
337 TUNABLE_INT("hw.ahci.force", &force_ahci);
340 ahci_probe(device_t dev)
344 uint32_t devid = pci_get_devid(dev);
345 uint8_t revid = pci_get_revid(dev);
347 /* Is this a possible AHCI candidate? */
348 if (pci_get_class(dev) == PCIC_STORAGE &&
349 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
350 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
352 /* Is this a known AHCI chip? */
353 for (i = 0; ahci_ids[i].id != 0; i++) {
354 if (ahci_ids[i].id == devid &&
355 ahci_ids[i].rev <= revid &&
356 (valid || (force_ahci == 1 &&
357 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
358 /* Do not attach JMicrons with single PCI function. */
359 if (pci_get_vendor(dev) == 0x197b &&
360 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
362 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
364 device_set_desc_copy(dev, buf);
365 return (BUS_PROBE_VENDOR);
370 device_set_desc_copy(dev, "AHCI SATA controller");
371 return (BUS_PROBE_VENDOR);
375 ahci_ata_probe(device_t dev)
379 uint32_t devid = pci_get_devid(dev);
380 uint8_t revid = pci_get_revid(dev);
382 if ((intptr_t)device_get_ivars(dev) >= 0)
384 /* Is this a known AHCI chip? */
385 for (i = 0; ahci_ids[i].id != 0; i++) {
386 if (ahci_ids[i].id == devid &&
387 ahci_ids[i].rev <= revid) {
388 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
390 device_set_desc_copy(dev, buf);
391 return (BUS_PROBE_VENDOR);
394 device_set_desc_copy(dev, "AHCI SATA controller");
395 return (BUS_PROBE_VENDOR);
399 ahci_attach(device_t dev)
401 struct ahci_controller *ctlr = device_get_softc(dev);
403 int error, unit, speed, i;
404 uint32_t devid = pci_get_devid(dev);
405 uint8_t revid = pci_get_revid(dev);
410 while (ahci_ids[i].id != 0 &&
411 (ahci_ids[i].id != devid ||
412 ahci_ids[i].rev > revid))
414 ctlr->quirks = ahci_ids[i].quirks;
415 resource_int_value(device_get_name(dev),
416 device_get_unit(dev), "ccc", &ctlr->ccc);
417 /* if we have a memory BAR(5) we are likely on an AHCI part */
418 ctlr->r_rid = PCIR_BAR(5);
419 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
420 &ctlr->r_rid, RF_ACTIVE)))
422 /* Setup our own memory management for channels. */
423 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
424 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
425 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
426 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
427 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
428 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
431 if ((error = rman_manage_region(&ctlr->sc_iomem,
432 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
433 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
434 rman_fini(&ctlr->sc_iomem);
437 pci_enable_busmaster(dev);
438 /* Reset controller */
439 if ((error = ahci_ctlr_reset(dev)) != 0) {
440 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
441 rman_fini(&ctlr->sc_iomem);
444 /* Get the HW capabilities */
445 version = ATA_INL(ctlr->r_mem, AHCI_VS);
446 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
447 if (version >= 0x00010200)
448 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
449 if (ctlr->caps & AHCI_CAP_EMS)
450 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
451 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
453 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
454 if ((ctlr->quirks & AHCI_Q_NOBSYRES) &&
455 (ctlr->quirks & AHCI_Q_ALTSIG) &&
456 (ctlr->caps & AHCI_CAP_SPM) == 0)
457 ctlr->quirks &= ~AHCI_Q_NOBSYRES;
459 if (ctlr->quirks & AHCI_Q_1CH) {
460 ctlr->caps &= ~AHCI_CAP_NPMASK;
461 ctlr->ichannels &= 0x01;
463 if (ctlr->quirks & AHCI_Q_2CH) {
464 ctlr->caps &= ~AHCI_CAP_NPMASK;
466 ctlr->ichannels &= 0x03;
468 if (ctlr->quirks & AHCI_Q_4CH) {
469 ctlr->caps &= ~AHCI_CAP_NPMASK;
471 ctlr->ichannels &= 0x0f;
473 ctlr->channels = MAX(flsl(ctlr->ichannels),
474 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
475 if (ctlr->quirks & AHCI_Q_NOPMP)
476 ctlr->caps &= ~AHCI_CAP_SPM;
477 if (ctlr->quirks & AHCI_Q_NONCQ)
478 ctlr->caps &= ~AHCI_CAP_SNCQ;
479 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
481 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF);
482 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
484 /* Create controller-wide DMA tag. */
485 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0,
486 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
487 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
488 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
489 0, NULL, NULL, &ctlr->dma_tag)) {
490 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
492 rman_fini(&ctlr->sc_iomem);
496 ahci_ctlr_setup(dev);
497 /* Setup interrupts. */
498 if (ahci_setup_interrupt(dev)) {
499 bus_dma_tag_destroy(ctlr->dma_tag);
500 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
501 rman_fini(&ctlr->sc_iomem);
504 /* Announce HW capabilities. */
505 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
507 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
508 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
509 ((version >> 4) & 0xf0) + (version & 0x0f),
510 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
511 ((speed == 1) ? "1.5":((speed == 2) ? "3":
512 ((speed == 3) ? "6":"?"))),
513 (ctlr->caps & AHCI_CAP_SPM) ?
514 "supported" : "not supported",
515 (ctlr->caps & AHCI_CAP_FBSS) ?
517 if (ctlr->quirks != 0) {
518 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
522 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
523 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
524 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
525 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
526 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
527 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
528 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
529 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
530 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
531 ((speed == 1) ? "1.5":((speed == 2) ? "3":
532 ((speed == 3) ? "6":"?"))));
533 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
534 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
535 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
536 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
537 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
538 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
539 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
540 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
541 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
542 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
543 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
544 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
546 if (bootverbose && version >= 0x00010200) {
547 device_printf(dev, "Caps2:%s%s%s\n",
548 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
549 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
550 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
552 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) {
553 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n",
554 (ctlr->capsem & AHCI_EM_PM) ? " PM":"",
555 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"",
556 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"",
557 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"",
558 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
559 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"",
560 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
561 (ctlr->capsem & AHCI_EM_LED) ? " LED":"");
563 /* Attach all channels on this controller */
564 for (unit = 0; unit < ctlr->channels; unit++) {
565 child = device_add_child(dev, "ahcich", -1);
567 device_printf(dev, "failed to add channel device\n");
570 device_set_ivars(child, (void *)(intptr_t)unit);
571 if ((ctlr->ichannels & (1 << unit)) == 0)
572 device_disable(child);
574 bus_generic_attach(dev);
579 ahci_detach(device_t dev)
581 struct ahci_controller *ctlr = device_get_softc(dev);
584 /* Detach & delete all children */
585 device_delete_children(dev);
587 /* Free interrupts. */
588 for (i = 0; i < ctlr->numirqs; i++) {
589 if (ctlr->irqs[i].r_irq) {
590 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
591 ctlr->irqs[i].handle);
592 bus_release_resource(dev, SYS_RES_IRQ,
593 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
596 pci_release_msi(dev);
597 bus_dma_tag_destroy(ctlr->dma_tag);
599 rman_fini(&ctlr->sc_iomem);
601 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
602 mtx_destroy(&ctlr->em_mtx);
607 ahci_ctlr_reset(device_t dev)
609 struct ahci_controller *ctlr = device_get_softc(dev);
612 if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
613 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
614 pci_write_config(dev, 0x92, 0x01, 1);
615 /* Enable AHCI mode */
616 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
617 /* Reset AHCI controller */
618 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
619 for (timeout = 1000; timeout > 0; timeout--) {
621 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
625 device_printf(dev, "AHCI controller reset failure\n");
628 /* Reenable AHCI mode */
629 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
634 ahci_ctlr_setup(device_t dev)
636 struct ahci_controller *ctlr = device_get_softc(dev);
637 /* Clear interrupts */
638 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
641 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
642 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
643 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
644 (4 << AHCI_CCCC_CC_SHIFT) |
646 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
647 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
650 "CCC with %dms/4cmd enabled on vector %d\n",
651 ctlr->ccc, ctlr->cccv);
654 /* Enable AHCI interrupts */
655 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
656 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
661 ahci_suspend(device_t dev)
663 struct ahci_controller *ctlr = device_get_softc(dev);
665 bus_generic_suspend(dev);
666 /* Disable interupts, so the state change(s) doesn't trigger */
667 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
668 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
673 ahci_resume(device_t dev)
677 if ((res = ahci_ctlr_reset(dev)) != 0)
679 ahci_ctlr_setup(dev);
680 return (bus_generic_resume(dev));
684 ahci_setup_interrupt(device_t dev)
686 struct ahci_controller *ctlr = device_get_softc(dev);
690 if (ctlr->quirks & AHCI_Q_NOMSI)
692 resource_int_value(device_get_name(dev),
693 device_get_unit(dev), "msi", &msi);
697 msi = min(1, pci_msi_count(dev));
699 msi = pci_msi_count(dev);
700 /* Allocate MSI if needed/present. */
701 if (msi && pci_alloc_msi(dev, &msi) == 0) {
707 /* Check for single MSI vector fallback. */
708 if (ctlr->numirqs > 1 &&
709 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
710 device_printf(dev, "Falling back to one MSI\n");
713 /* Allocate all IRQs. */
714 for (i = 0; i < ctlr->numirqs; i++) {
715 ctlr->irqs[i].ctlr = ctlr;
716 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
717 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
718 (ctlr->ccc && i == ctlr->cccv))
719 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
720 else if (i == ctlr->numirqs - 1)
721 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
723 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
724 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
725 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
726 device_printf(dev, "unable to map interrupt\n");
729 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
730 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
731 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
732 /* SOS XXX release r_irq */
733 device_printf(dev, "unable to setup interrupt\n");
736 if (ctlr->numirqs > 1) {
737 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
738 ctlr->irqs[i].handle,
739 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
747 * Common case interrupt handler.
750 ahci_intr(void *data)
752 struct ahci_controller_irq *irq = data;
753 struct ahci_controller *ctlr = irq->ctlr;
754 u_int32_t is, ise = 0;
758 if (irq->mode == AHCI_IRQ_MODE_ALL) {
761 is = ctlr->ichannels;
763 is = ATA_INL(ctlr->r_mem, AHCI_IS);
764 } else { /* AHCI_IRQ_MODE_AFTER */
765 unit = irq->r_irq_rid - 1;
766 is = ATA_INL(ctlr->r_mem, AHCI_IS);
768 /* CCC interrupt is edge triggered. */
770 ise = 1 << ctlr->cccv;
771 /* Some controllers have edge triggered IS. */
772 if (ctlr->quirks & AHCI_Q_EDGEIS)
775 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
776 for (; unit < ctlr->channels; unit++) {
777 if ((is & (1 << unit)) != 0 &&
778 (arg = ctlr->interrupt[unit].argument)) {
779 ctlr->interrupt[unit].function(arg);
782 /* AHCI declares level triggered IS. */
783 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
784 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
788 * Simplified interrupt handler for multivector MSI mode.
791 ahci_intr_one(void *data)
793 struct ahci_controller_irq *irq = data;
794 struct ahci_controller *ctlr = irq->ctlr;
798 unit = irq->r_irq_rid - 1;
799 /* Some controllers have edge triggered IS. */
800 if (ctlr->quirks & AHCI_Q_EDGEIS)
801 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
802 if ((arg = ctlr->interrupt[unit].argument))
803 ctlr->interrupt[unit].function(arg);
804 /* AHCI declares level triggered IS. */
805 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
806 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
809 static struct resource *
810 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
811 u_long start, u_long end, u_long count, u_int flags)
813 struct ahci_controller *ctlr = device_get_softc(dev);
814 int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
815 struct resource *res = NULL;
816 int offset = AHCI_OFFSET + (unit << 7);
821 st = rman_get_start(ctlr->r_mem);
822 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
823 st + offset + 127, 128, RF_ACTIVE, child);
825 bus_space_handle_t bsh;
827 bsh = rman_get_bushandle(ctlr->r_mem);
828 bst = rman_get_bustag(ctlr->r_mem);
829 bus_space_subregion(bst, bsh, offset, 128, &bsh);
830 rman_set_bushandle(res, bsh);
831 rman_set_bustag(res, bst);
835 if (*rid == ATA_IRQ_RID)
836 res = ctlr->irqs[0].r_irq;
843 ahci_release_resource(device_t dev, device_t child, int type, int rid,
849 rman_release_resource(r);
852 if (rid != ATA_IRQ_RID)
860 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
861 int flags, driver_filter_t *filter, driver_intr_t *function,
862 void *argument, void **cookiep)
864 struct ahci_controller *ctlr = device_get_softc(dev);
865 int unit = (intptr_t)device_get_ivars(child);
867 if (filter != NULL) {
868 printf("ahci.c: we cannot use a filter here\n");
871 ctlr->interrupt[unit].function = function;
872 ctlr->interrupt[unit].argument = argument;
877 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
880 struct ahci_controller *ctlr = device_get_softc(dev);
881 int unit = (intptr_t)device_get_ivars(child);
883 ctlr->interrupt[unit].function = NULL;
884 ctlr->interrupt[unit].argument = NULL;
889 ahci_print_child(device_t dev, device_t child)
893 retval = bus_print_child_header(dev, child);
894 retval += printf(" at channel %d",
895 (int)(intptr_t)device_get_ivars(child));
896 retval += bus_print_child_footer(dev, child);
902 ahci_child_location_str(device_t dev, device_t child, char *buf,
906 snprintf(buf, buflen, "channel=%d",
907 (int)(intptr_t)device_get_ivars(child));
912 ahci_get_dma_tag(device_t dev, device_t child)
914 struct ahci_controller *ctlr = device_get_softc(dev);
916 return (ctlr->dma_tag);
919 devclass_t ahci_devclass;
920 static device_method_t ahci_methods[] = {
921 DEVMETHOD(device_probe, ahci_probe),
922 DEVMETHOD(device_attach, ahci_attach),
923 DEVMETHOD(device_detach, ahci_detach),
924 DEVMETHOD(device_suspend, ahci_suspend),
925 DEVMETHOD(device_resume, ahci_resume),
926 DEVMETHOD(bus_print_child, ahci_print_child),
927 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
928 DEVMETHOD(bus_release_resource, ahci_release_resource),
929 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
930 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
931 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
932 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
935 static driver_t ahci_driver = {
938 sizeof(struct ahci_controller)
940 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
941 static device_method_t ahci_ata_methods[] = {
942 DEVMETHOD(device_probe, ahci_ata_probe),
943 DEVMETHOD(device_attach, ahci_attach),
944 DEVMETHOD(device_detach, ahci_detach),
945 DEVMETHOD(device_suspend, ahci_suspend),
946 DEVMETHOD(device_resume, ahci_resume),
947 DEVMETHOD(bus_print_child, ahci_print_child),
948 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
949 DEVMETHOD(bus_release_resource, ahci_release_resource),
950 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
951 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
952 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
955 static driver_t ahci_ata_driver = {
958 sizeof(struct ahci_controller)
960 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
961 MODULE_VERSION(ahci, 1);
962 MODULE_DEPEND(ahci, cam, 1, 1, 1);
965 ahci_ch_probe(device_t dev)
968 device_set_desc_copy(dev, "AHCI channel");
973 ahci_ch_attach(device_t dev)
975 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
976 struct ahci_channel *ch = device_get_softc(dev);
977 struct cam_devq *devq;
978 int rid, error, i, sata_rev = 0;
983 ch->unit = (intptr_t)device_get_ivars(dev);
984 ch->caps = ctlr->caps;
985 ch->caps2 = ctlr->caps2;
986 ch->quirks = ctlr->quirks;
987 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
988 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
989 resource_int_value(device_get_name(dev),
990 device_get_unit(dev), "pm_level", &ch->pm_level);
991 if (ch->pm_level > 3)
992 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
993 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
994 /* Limit speed for my onboard JMicron external port.
995 * It is not eSATA really. */
996 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
997 pci_get_subvendor(ctlr->dev) == 0x1043 &&
998 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
1001 if (ch->quirks & AHCI_Q_SATA2)
1003 resource_int_value(device_get_name(dev),
1004 device_get_unit(dev), "sata_rev", &sata_rev);
1005 for (i = 0; i < 16; i++) {
1006 ch->user[i].revision = sata_rev;
1007 ch->user[i].mode = 0;
1008 ch->user[i].bytecount = 8192;
1009 ch->user[i].tags = ch->numslots;
1010 ch->user[i].caps = 0;
1011 ch->curr[i] = ch->user[i];
1013 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
1014 CTS_SATA_CAPS_H_APST |
1015 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
1017 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
1021 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1025 ahci_slotsalloc(dev);
1029 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1030 &rid, RF_SHAREABLE | RF_ACTIVE))) {
1031 device_printf(dev, "Unable to map interrupt\n");
1035 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
1036 ahci_ch_intr_locked, dev, &ch->ih))) {
1037 device_printf(dev, "Unable to setup interrupt\n");
1041 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
1042 version = ATA_INL(ctlr->r_mem, AHCI_VS);
1043 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
1044 ch->chcaps |= AHCI_P_CMD_FBSCP;
1046 device_printf(dev, "Caps:%s%s%s%s%s\n",
1047 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
1048 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
1049 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
1050 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
1051 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
1053 /* Create the device queue for our SIM. */
1054 devq = cam_simq_alloc(ch->numslots);
1056 device_printf(dev, "Unable to allocate simq\n");
1060 /* Construct SIM entry */
1061 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
1062 device_get_unit(dev), &ch->mtx,
1063 min(2, ch->numslots),
1064 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
1066 if (ch->sim == NULL) {
1067 cam_simq_free(devq);
1068 device_printf(dev, "unable to allocate sim\n");
1072 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
1073 device_printf(dev, "unable to register xpt bus\n");
1077 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
1078 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1079 device_printf(dev, "unable to create path\n");
1083 if (ch->pm_level > 3) {
1084 callout_reset(&ch->pm_timer,
1085 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
1088 mtx_unlock(&ch->mtx);
1089 if ((ch->caps & AHCI_CAP_EMS) &&
1090 (ctlr->capsem & AHCI_EM_LED)) {
1091 for (i = 0; i < AHCI_NUM_LEDS; i++) {
1092 ch->leds[i].dev = dev;
1093 ch->leds[i].num = i;
1095 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) {
1096 snprintf(buf, sizeof(buf), "%s.act",
1097 device_get_nameunit(dev));
1098 ch->leds[0].led = led_create(ahci_ch_led,
1101 snprintf(buf, sizeof(buf), "%s.locate",
1102 device_get_nameunit(dev));
1103 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf);
1104 snprintf(buf, sizeof(buf), "%s.fault",
1105 device_get_nameunit(dev));
1106 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf);
1111 xpt_bus_deregister(cam_sim_path(ch->sim));
1113 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1115 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1117 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1118 mtx_unlock(&ch->mtx);
1119 mtx_destroy(&ch->mtx);
1124 ahci_ch_detach(device_t dev)
1126 struct ahci_channel *ch = device_get_softc(dev);
1129 for (i = 0; i < AHCI_NUM_LEDS; i++) {
1130 if (ch->leds[i].led)
1131 led_destroy(ch->leds[i].led);
1134 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
1135 /* Forget about reset. */
1136 if (ch->resetting) {
1138 xpt_release_simq(ch->sim, TRUE);
1140 xpt_free_path(ch->path);
1141 xpt_bus_deregister(cam_sim_path(ch->sim));
1142 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1143 mtx_unlock(&ch->mtx);
1145 if (ch->pm_level > 3)
1146 callout_drain(&ch->pm_timer);
1147 callout_drain(&ch->reset_timer);
1148 bus_teardown_intr(dev, ch->r_irq, ch->ih);
1149 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1151 ahci_ch_deinit(dev);
1152 ahci_slotsfree(dev);
1155 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1156 mtx_destroy(&ch->mtx);
1161 ahci_ch_init(device_t dev)
1163 struct ahci_channel *ch = device_get_softc(dev);
1166 /* Disable port interrupts */
1167 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1168 /* Setup work areas */
1169 work = ch->dma.work_bus + AHCI_CL_OFFSET;
1170 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
1171 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
1172 work = ch->dma.rfis_bus;
1173 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1174 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1175 /* Activate the channel and power/spin up device */
1176 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1177 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1178 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1179 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1186 ahci_ch_deinit(device_t dev)
1188 struct ahci_channel *ch = device_get_softc(dev);
1190 /* Disable port interrupts. */
1191 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1192 /* Reset command register. */
1195 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1196 /* Allow everything, including partial and slumber modes. */
1197 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1198 /* Request slumber mode transition and give some time to get there. */
1199 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1202 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1207 ahci_ch_suspend(device_t dev)
1209 struct ahci_channel *ch = device_get_softc(dev);
1212 xpt_freeze_simq(ch->sim, 1);
1213 /* Forget about reset. */
1214 if (ch->resetting) {
1216 callout_stop(&ch->reset_timer);
1217 xpt_release_simq(ch->sim, TRUE);
1220 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1221 ahci_ch_deinit(dev);
1222 mtx_unlock(&ch->mtx);
1227 ahci_ch_resume(device_t dev)
1229 struct ahci_channel *ch = device_get_softc(dev);
1234 xpt_release_simq(ch->sim, TRUE);
1235 mtx_unlock(&ch->mtx);
1239 devclass_t ahcich_devclass;
1240 static device_method_t ahcich_methods[] = {
1241 DEVMETHOD(device_probe, ahci_ch_probe),
1242 DEVMETHOD(device_attach, ahci_ch_attach),
1243 DEVMETHOD(device_detach, ahci_ch_detach),
1244 DEVMETHOD(device_suspend, ahci_ch_suspend),
1245 DEVMETHOD(device_resume, ahci_ch_resume),
1248 static driver_t ahcich_driver = {
1251 sizeof(struct ahci_channel)
1253 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
1256 ahci_ch_setleds(device_t dev)
1258 struct ahci_channel *ch;
1259 struct ahci_controller *ctlr;
1264 ctlr = device_get_softc(device_get_parent(dev));
1265 ch = device_get_softc(dev);
1268 for (i = 0; i < AHCI_NUM_LEDS; i++)
1269 val |= ch->leds[i].state << (i * 3);
1271 buf = (ctlr->emloc & 0xffff0000) >> 14;
1272 mtx_lock(&ctlr->em_mtx);
1274 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) &&
1278 device_printf(dev, "EM timeout\n");
1279 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24));
1280 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16));
1281 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM);
1282 mtx_unlock(&ctlr->em_mtx);
1286 ahci_ch_led(void *priv, int onoff)
1288 struct ahci_led *led;
1290 led = (struct ahci_led *)priv;
1293 ahci_ch_setleds(led->dev);
1296 struct ahci_dc_cb_args {
1302 ahci_dmainit(device_t dev)
1304 struct ahci_channel *ch = device_get_softc(dev);
1305 struct ahci_dc_cb_args dcba;
1309 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1310 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1311 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1312 0, NULL, NULL, &ch->dma.work_tag))
1314 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1315 BUS_DMA_ZERO, &ch->dma.work_map))
1317 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1318 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1319 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1322 ch->dma.work_bus = dcba.maddr;
1323 /* FIS receive area. */
1324 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1328 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1329 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1330 NULL, NULL, rfsize, 1, rfsize,
1331 0, NULL, NULL, &ch->dma.rfis_tag))
1333 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1336 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1337 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1338 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1341 ch->dma.rfis_bus = dcba.maddr;
1343 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1344 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1346 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1347 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1348 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1354 device_printf(dev, "WARNING - DMA initialization failed\n");
1359 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1361 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1363 if (!(dcba->error = error))
1364 dcba->maddr = segs[0].ds_addr;
1368 ahci_dmafini(device_t dev)
1370 struct ahci_channel *ch = device_get_softc(dev);
1372 if (ch->dma.data_tag) {
1373 bus_dma_tag_destroy(ch->dma.data_tag);
1374 ch->dma.data_tag = NULL;
1376 if (ch->dma.rfis_bus) {
1377 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1378 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1379 ch->dma.rfis_bus = 0;
1380 ch->dma.rfis_map = NULL;
1381 ch->dma.rfis = NULL;
1383 if (ch->dma.work_bus) {
1384 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1385 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1386 ch->dma.work_bus = 0;
1387 ch->dma.work_map = NULL;
1388 ch->dma.work = NULL;
1390 if (ch->dma.work_tag) {
1391 bus_dma_tag_destroy(ch->dma.work_tag);
1392 ch->dma.work_tag = NULL;
1397 ahci_slotsalloc(device_t dev)
1399 struct ahci_channel *ch = device_get_softc(dev);
1402 /* Alloc and setup command/dma slots */
1403 bzero(ch->slot, sizeof(ch->slot));
1404 for (i = 0; i < ch->numslots; i++) {
1405 struct ahci_slot *slot = &ch->slot[i];
1409 slot->state = AHCI_SLOT_EMPTY;
1411 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1413 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1414 device_printf(ch->dev, "FAILURE - create data_map\n");
1419 ahci_slotsfree(device_t dev)
1421 struct ahci_channel *ch = device_get_softc(dev);
1424 /* Free all dma slots */
1425 for (i = 0; i < ch->numslots; i++) {
1426 struct ahci_slot *slot = &ch->slot[i];
1428 callout_drain(&slot->timeout);
1429 if (slot->dma.data_map) {
1430 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1431 slot->dma.data_map = NULL;
1437 ahci_phy_check_events(device_t dev, u_int32_t serr)
1439 struct ahci_channel *ch = device_get_softc(dev);
1441 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1442 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1443 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1447 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1448 device_printf(dev, "CONNECT requested\n");
1450 device_printf(dev, "DISCONNECT requested\n");
1453 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1455 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1456 cam_sim_path(ch->sim),
1457 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1468 ahci_cpd_check_events(device_t dev)
1470 struct ahci_channel *ch = device_get_softc(dev);
1474 if (ch->pm_level == 0)
1477 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1478 if ((status & AHCI_P_CMD_CPD) == 0)
1482 if (status & AHCI_P_CMD_CPS) {
1483 device_printf(dev, "COLD CONNECT requested\n");
1485 device_printf(dev, "COLD DISCONNECT requested\n");
1488 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1490 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1491 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1499 ahci_notify_events(device_t dev, u_int32_t status)
1501 struct ahci_channel *ch = device_get_softc(dev);
1502 struct cam_path *dpath;
1505 if (ch->caps & AHCI_CAP_SSNTF)
1506 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1508 device_printf(dev, "SNTF 0x%04x\n", status);
1509 for (i = 0; i < 16; i++) {
1510 if ((status & (1 << i)) == 0)
1512 if (xpt_create_path(&dpath, NULL,
1513 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1514 xpt_async(AC_SCSI_AEN, dpath, NULL);
1515 xpt_free_path(dpath);
1521 ahci_ch_intr_locked(void *data)
1523 device_t dev = (device_t)data;
1524 struct ahci_channel *ch = device_get_softc(dev);
1527 xpt_batch_start(ch->sim);
1529 xpt_batch_done(ch->sim);
1530 mtx_unlock(&ch->mtx);
1534 ahci_ch_pm(void *arg)
1536 device_t dev = (device_t)arg;
1537 struct ahci_channel *ch = device_get_softc(dev);
1540 if (ch->numrslots != 0)
1542 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1543 if (ch->pm_level == 4)
1544 work |= AHCI_P_CMD_PARTIAL;
1546 work |= AHCI_P_CMD_SLUMBER;
1547 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1551 ahci_ch_intr(void *data)
1553 device_t dev = (device_t)data;
1554 struct ahci_channel *ch = device_get_softc(dev);
1555 uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err;
1556 enum ahci_err_type et;
1557 int i, ccs, port, reset = 0;
1559 /* Read and clear interrupt statuses. */
1560 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1563 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1564 /* Read command statuses. */
1565 if (ch->numtslots != 0)
1566 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1569 if (ch->numrslots != ch->numtslots)
1570 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1571 /* Read SNTF in one of possible ways. */
1572 if ((istatus & AHCI_P_IX_SDB) &&
1573 (ch->pm_present || ch->curr[0].atapi != 0)) {
1574 if (ch->caps & AHCI_CAP_SSNTF)
1575 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1576 else if (ch->fbs_enabled) {
1577 u_int8_t *fis = ch->dma.rfis + 0x58;
1579 for (i = 0; i < 16; i++) {
1580 if (fis[1] & 0x80) {
1587 u_int8_t *fis = ch->dma.rfis + 0x58;
1590 sntf = (1 << (fis[1] & 0x0f));
1593 /* Process PHY events */
1594 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1595 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1596 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1598 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1599 reset = ahci_phy_check_events(dev, serr);
1602 /* Process cold presence detection events */
1603 if ((istatus & AHCI_P_IX_CPD) && !reset)
1604 ahci_cpd_check_events(dev);
1605 /* Process command errors */
1606 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1607 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1608 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1609 >> AHCI_P_CMD_CCS_SHIFT;
1610 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1611 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1612 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1614 if (ch->fbs_enabled) {
1615 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1616 if (fbs & AHCI_P_FBS_SDE) {
1617 port = (fbs & AHCI_P_FBS_DWE)
1618 >> AHCI_P_FBS_DWE_SHIFT;
1620 for (i = 0; i < 16; i++) {
1621 if (ch->numrslotspd[i] == 0)
1625 else if (port != i) {
1632 err = ch->rslots & cstatus;
1638 /* Complete all successfull commands. */
1639 ok = ch->rslots & ~cstatus;
1640 for (i = 0; i < ch->numslots; i++) {
1642 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1644 /* On error, complete the rest of commands with error statuses. */
1647 union ccb *fccb = ch->frozen;
1649 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1650 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1651 xpt_freeze_devq(fccb->ccb_h.path, 1);
1652 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1656 for (i = 0; i < ch->numslots; i++) {
1657 /* XXX: reqests in loading state. */
1658 if (((err >> i) & 1) == 0)
1661 ch->slot[i].ccb->ccb_h.target_id != port)
1663 if (istatus & AHCI_P_IX_TFE) {
1665 /* Task File Error */
1666 if (ch->numtslotspd[
1667 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1668 /* Untagged operation. */
1672 et = AHCI_ERR_INNOCENT;
1674 /* Tagged operation. */
1681 } else if (istatus & AHCI_P_IX_IF) {
1682 if (ch->numtslots == 0 && i != ccs && port != -2)
1683 et = AHCI_ERR_INNOCENT;
1687 et = AHCI_ERR_INVALID;
1688 ahci_end_transaction(&ch->slot[i], et);
1691 * We can't reinit port if there are some other
1692 * commands active, use resume to complete them.
1694 if (ch->rslots != 0 && !ch->recoverycmd)
1695 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1697 /* Process NOTIFY events */
1699 ahci_notify_events(dev, sntf);
1702 /* Must be called with channel locked. */
1704 ahci_check_collision(device_t dev, union ccb *ccb)
1706 struct ahci_channel *ch = device_get_softc(dev);
1707 int t = ccb->ccb_h.target_id;
1709 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1710 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1711 /* Tagged command while we have no supported tag free. */
1712 if (((~ch->oslots) & (0xffffffff >> (32 -
1713 ch->curr[t].tags))) == 0)
1715 /* If we have FBS */
1716 if (ch->fbs_enabled) {
1717 /* Tagged command while untagged are active. */
1718 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1721 /* Tagged command while untagged are active. */
1722 if (ch->numrslots != 0 && ch->numtslots == 0)
1724 /* Tagged command while tagged to other target is active. */
1725 if (ch->numtslots != 0 &&
1726 ch->taggedtarget != ccb->ccb_h.target_id)
1730 /* If we have FBS */
1731 if (ch->fbs_enabled) {
1732 /* Untagged command while tagged are active. */
1733 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1736 /* Untagged command while tagged are active. */
1737 if (ch->numrslots != 0 && ch->numtslots != 0)
1741 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1742 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1743 /* Atomic command while anything active. */
1744 if (ch->numrslots != 0)
1747 /* We have some atomic command running. */
1748 if (ch->aslots != 0)
1753 /* Must be called with channel locked. */
1755 ahci_begin_transaction(device_t dev, union ccb *ccb)
1757 struct ahci_channel *ch = device_get_softc(dev);
1758 struct ahci_slot *slot;
1761 /* Choose empty slot. */
1762 tags = ch->numslots;
1763 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1764 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1765 tags = ch->curr[ccb->ccb_h.target_id].tags;
1770 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1775 /* Occupy chosen slot. */
1776 slot = &ch->slot[tag];
1778 /* Stop PM timer. */
1779 if (ch->numrslots == 0 && ch->pm_level > 3)
1780 callout_stop(&ch->pm_timer);
1781 /* Update channel stats. */
1782 ch->oslots |= (1 << slot->slot);
1784 ch->numrslotspd[ccb->ccb_h.target_id]++;
1785 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1786 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1788 ch->numtslotspd[ccb->ccb_h.target_id]++;
1789 ch->taggedtarget = ccb->ccb_h.target_id;
1791 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1792 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1793 ch->aslots |= (1 << slot->slot);
1794 slot->dma.nsegs = 0;
1795 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1796 slot->state = AHCI_SLOT_LOADING;
1797 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1798 ahci_dmasetprd, slot, 0);
1800 ahci_execute_transaction(slot);
1803 /* Locked by busdma engine. */
1805 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1807 struct ahci_slot *slot = arg;
1808 struct ahci_channel *ch = device_get_softc(slot->dev);
1809 struct ahci_cmd_tab *ctp;
1810 struct ahci_dma_prd *prd;
1814 device_printf(slot->dev, "DMA load error\n");
1815 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1818 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1819 /* Get a piece of the workspace for this request */
1820 ctp = (struct ahci_cmd_tab *)
1821 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1822 /* Fill S/G table */
1823 prd = &ctp->prd_tab[0];
1824 for (i = 0; i < nsegs; i++) {
1825 prd[i].dba = htole64(segs[i].ds_addr);
1826 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1828 slot->dma.nsegs = nsegs;
1829 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1830 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1831 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1832 ahci_execute_transaction(slot);
1835 /* Must be called with channel locked. */
1837 ahci_execute_transaction(struct ahci_slot *slot)
1839 device_t dev = slot->dev;
1840 struct ahci_channel *ch = device_get_softc(dev);
1841 struct ahci_cmd_tab *ctp;
1842 struct ahci_cmd_list *clp;
1843 union ccb *ccb = slot->ccb;
1844 int port = ccb->ccb_h.target_id & 0x0f;
1845 int fis_size, i, softreset;
1846 uint8_t *fis = ch->dma.rfis + 0x40;
1849 /* Get a piece of the workspace for this request */
1850 ctp = (struct ahci_cmd_tab *)
1851 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1852 /* Setup the FIS for this request */
1853 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1854 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1855 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1858 /* Setup the command list entry */
1859 clp = (struct ahci_cmd_list *)
1860 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1861 clp->cmd_flags = htole16(
1862 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1863 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1864 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1865 (fis_size / sizeof(u_int32_t)) |
1867 clp->prd_length = htole16(slot->dma.nsegs);
1868 /* Special handling for Soft Reset command. */
1869 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1870 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1871 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1873 /* Kick controller into sane state */
1877 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1880 /* Prepare FIS receive area for check. */
1881 for (i = 0; i < 20; i++)
1887 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1888 (AHCI_CT_SIZE * slot->slot));
1889 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1890 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1891 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1892 BUS_DMASYNC_PREREAD);
1893 /* Set ACTIVE bit for NCQ commands. */
1894 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1895 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1896 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1898 /* If FBS is enabled, set PMP port. */
1899 if (ch->fbs_enabled) {
1900 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1901 (port << AHCI_P_FBS_DEV_SHIFT));
1903 /* Issue command to the controller. */
1904 slot->state = AHCI_SLOT_RUNNING;
1905 ch->rslots |= (1 << slot->slot);
1906 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1907 /* Device reset commands doesn't interrupt. Poll them. */
1908 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1909 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1910 int count, timeout = ccb->ccb_h.timeout * 100;
1911 enum ahci_err_type et = AHCI_ERR_NONE;
1913 for (count = 0; count < timeout; count++) {
1915 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1917 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1920 device_printf(ch->dev,
1921 "Poll error on slot %d, TFD: %04x\n",
1922 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1927 /* Workaround for ATI SB600/SB700 chipsets. */
1928 if (ccb->ccb_h.target_id == 15 &&
1929 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1930 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1931 et = AHCI_ERR_TIMEOUT;
1936 /* Marvell controllers do not wait for readyness. */
1937 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 &&
1938 et == AHCI_ERR_NONE) {
1939 while ((val = fis[2]) & ATA_S_BUSY) {
1941 if (count++ >= timeout)
1946 if (timeout && (count >= timeout)) {
1947 device_printf(dev, "Poll timeout on slot %d port %d\n",
1949 device_printf(dev, "is %08x cs %08x ss %08x "
1950 "rs %08x tfd %02x serr %08x cmd %08x\n",
1951 ATA_INL(ch->r_mem, AHCI_P_IS),
1952 ATA_INL(ch->r_mem, AHCI_P_CI),
1953 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1954 ATA_INL(ch->r_mem, AHCI_P_TFD),
1955 ATA_INL(ch->r_mem, AHCI_P_SERR),
1956 ATA_INL(ch->r_mem, AHCI_P_CMD));
1957 et = AHCI_ERR_TIMEOUT;
1960 /* Kick controller into sane state and enable FBS. */
1962 ch->eslots |= (1 << slot->slot);
1963 ahci_end_transaction(slot, et);
1966 /* Start command execution timeout */
1967 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1968 (timeout_t*)ahci_timeout, slot);
1972 /* Must be called with channel locked. */
1974 ahci_process_timeout(device_t dev)
1976 struct ahci_channel *ch = device_get_softc(dev);
1979 mtx_assert(&ch->mtx, MA_OWNED);
1980 /* Handle the rest of commands. */
1981 for (i = 0; i < ch->numslots; i++) {
1982 /* Do we have a running request on slot? */
1983 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1985 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1989 /* Must be called with channel locked. */
1991 ahci_rearm_timeout(device_t dev)
1993 struct ahci_channel *ch = device_get_softc(dev);
1996 mtx_assert(&ch->mtx, MA_OWNED);
1997 for (i = 0; i < ch->numslots; i++) {
1998 struct ahci_slot *slot = &ch->slot[i];
2000 /* Do we have a running request on slot? */
2001 if (slot->state < AHCI_SLOT_RUNNING)
2003 if ((ch->toslots & (1 << i)) == 0)
2005 callout_reset(&slot->timeout,
2006 (int)slot->ccb->ccb_h.timeout * hz / 2000,
2007 (timeout_t*)ahci_timeout, slot);
2011 /* Locked by callout mechanism. */
2013 ahci_timeout(struct ahci_slot *slot)
2015 device_t dev = slot->dev;
2016 struct ahci_channel *ch = device_get_softc(dev);
2021 /* Check for stale timeout. */
2022 if (slot->state < AHCI_SLOT_RUNNING)
2025 /* Check if slot was not being executed last time we checked. */
2026 if (slot->state < AHCI_SLOT_EXECUTING) {
2027 /* Check if slot started executing. */
2028 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
2029 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
2030 >> AHCI_P_CMD_CCS_SHIFT;
2031 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
2032 ch->fbs_enabled || ch->wrongccs)
2033 slot->state = AHCI_SLOT_EXECUTING;
2034 else if ((ch->rslots & (1 << ccs)) == 0) {
2036 slot->state = AHCI_SLOT_EXECUTING;
2039 callout_reset(&slot->timeout,
2040 (int)slot->ccb->ccb_h.timeout * hz / 2000,
2041 (timeout_t*)ahci_timeout, slot);
2045 device_printf(dev, "Timeout on slot %d port %d\n",
2046 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
2047 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
2048 "serr %08x cmd %08x\n",
2049 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
2050 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
2051 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
2052 ATA_INL(ch->r_mem, AHCI_P_CMD));
2054 /* Handle frozen command. */
2056 union ccb *fccb = ch->frozen;
2058 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2059 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2060 xpt_freeze_devq(fccb->ccb_h.path, 1);
2061 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2065 if (!ch->fbs_enabled && !ch->wrongccs) {
2066 /* Without FBS we know real timeout source. */
2068 /* Handle command with timeout. */
2069 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
2070 /* Handle the rest of commands. */
2071 for (i = 0; i < ch->numslots; i++) {
2072 /* Do we have a running request on slot? */
2073 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2075 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2078 /* With FBS we wait for other commands timeout and pray. */
2079 if (ch->toslots == 0)
2080 xpt_freeze_simq(ch->sim, 1);
2081 ch->toslots |= (1 << slot->slot);
2082 if ((ch->rslots & ~ch->toslots) == 0)
2083 ahci_process_timeout(dev);
2085 device_printf(dev, " ... waiting for slots %08x\n",
2086 ch->rslots & ~ch->toslots);
2090 /* Must be called with channel locked. */
2092 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
2094 device_t dev = slot->dev;
2095 struct ahci_channel *ch = device_get_softc(dev);
2096 union ccb *ccb = slot->ccb;
2097 struct ahci_cmd_list *clp;
2101 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
2102 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2103 clp = (struct ahci_cmd_list *)
2104 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
2105 /* Read result registers to the result struct
2106 * May be incorrect if several commands finished same time,
2107 * so read only when sure or have to.
2109 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2110 struct ata_res *res = &ccb->ataio.res;
2112 if ((et == AHCI_ERR_TFE) ||
2113 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
2114 u_int8_t *fis = ch->dma.rfis + 0x40;
2116 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
2117 BUS_DMASYNC_POSTREAD);
2118 if (ch->fbs_enabled) {
2119 fis += ccb->ccb_h.target_id * 256;
2120 res->status = fis[2];
2121 res->error = fis[3];
2123 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
2126 res->error = tfd >> 8;
2128 res->lba_low = fis[4];
2129 res->lba_mid = fis[5];
2130 res->lba_high = fis[6];
2131 res->device = fis[7];
2132 res->lba_low_exp = fis[8];
2133 res->lba_mid_exp = fis[9];
2134 res->lba_high_exp = fis[10];
2135 res->sector_count = fis[12];
2136 res->sector_count_exp = fis[13];
2139 * Some weird controllers do not return signature in
2140 * FIS receive area. Read it from PxSIG register.
2142 if ((ch->quirks & AHCI_Q_ALTSIG) &&
2143 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2144 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
2145 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
2146 res->lba_high = sig >> 24;
2147 res->lba_mid = sig >> 16;
2148 res->lba_low = sig >> 8;
2149 res->sector_count = sig;
2152 bzero(res, sizeof(*res));
2153 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
2154 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2155 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2157 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2160 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2161 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2163 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2166 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2167 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2168 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2169 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2170 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2172 if (et != AHCI_ERR_NONE)
2173 ch->eslots |= (1 << slot->slot);
2174 /* In case of error, freeze device for proper recovery. */
2175 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2176 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2177 xpt_freeze_devq(ccb->ccb_h.path, 1);
2178 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2180 /* Set proper result status. */
2181 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2184 ccb->ccb_h.status |= CAM_REQ_CMP;
2185 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2186 ccb->csio.scsi_status = SCSI_STATUS_OK;
2188 case AHCI_ERR_INVALID:
2190 ccb->ccb_h.status |= CAM_REQ_INVALID;
2192 case AHCI_ERR_INNOCENT:
2193 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2197 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2198 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2199 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2201 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2206 if (!ch->recoverycmd) {
2207 xpt_freeze_simq(ch->sim, 1);
2208 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2209 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2211 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2213 case AHCI_ERR_TIMEOUT:
2214 if (!ch->recoverycmd) {
2215 xpt_freeze_simq(ch->sim, 1);
2216 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2217 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2219 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2223 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2226 ch->oslots &= ~(1 << slot->slot);
2227 ch->rslots &= ~(1 << slot->slot);
2228 ch->aslots &= ~(1 << slot->slot);
2229 slot->state = AHCI_SLOT_EMPTY;
2231 /* Update channel stats. */
2233 ch->numrslotspd[ccb->ccb_h.target_id]--;
2234 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2235 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2237 ch->numtslotspd[ccb->ccb_h.target_id]--;
2239 /* Cancel timeout state if request completed normally. */
2240 if (et != AHCI_ERR_TIMEOUT) {
2241 lastto = (ch->toslots == (1 << slot->slot));
2242 ch->toslots &= ~(1 << slot->slot);
2244 xpt_release_simq(ch->sim, TRUE);
2246 /* If it was first request of reset sequence and there is no error,
2247 * proceed to second request. */
2248 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2249 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2250 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2251 et == AHCI_ERR_NONE) {
2252 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2253 ahci_begin_transaction(dev, ccb);
2256 /* If it was our READ LOG command - process it. */
2257 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2258 ahci_process_read_log(dev, ccb);
2259 /* If it was our REQUEST SENSE command - process it. */
2260 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2261 ahci_process_request_sense(dev, ccb);
2262 /* If it was NCQ or ATAPI command error, put result on hold. */
2263 } else if (et == AHCI_ERR_NCQ ||
2264 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2265 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2266 ch->hold[slot->slot] = ccb;
2270 /* If we have no other active commands, ... */
2271 if (ch->rslots == 0) {
2272 /* if there was fatal error - reset port. */
2273 if (ch->toslots != 0 || ch->fatalerr) {
2276 /* if we have slots in error, we can reinit port. */
2277 if (ch->eslots != 0) {
2282 /* if there commands on hold, we can do READ LOG. */
2283 if (!ch->recoverycmd && ch->numhslots)
2284 ahci_issue_recovery(dev);
2286 /* If all the rest of commands are in timeout - give them chance. */
2287 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2288 et != AHCI_ERR_TIMEOUT)
2289 ahci_rearm_timeout(dev);
2290 /* Unfreeze frozen command. */
2291 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
2292 union ccb *fccb = ch->frozen;
2294 ahci_begin_transaction(dev, fccb);
2295 xpt_release_simq(ch->sim, TRUE);
2297 /* Start PM timer. */
2298 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2299 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2300 callout_schedule(&ch->pm_timer,
2301 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2306 ahci_issue_recovery(device_t dev)
2308 struct ahci_channel *ch = device_get_softc(dev);
2310 struct ccb_ataio *ataio;
2311 struct ccb_scsiio *csio;
2314 /* Find some held command. */
2315 for (i = 0; i < ch->numslots; i++) {
2319 ccb = xpt_alloc_ccb_nowait();
2321 device_printf(dev, "Unable to allocate recovery command\n");
2323 /* We can't do anything -- complete held commands. */
2324 for (i = 0; i < ch->numslots; i++) {
2325 if (ch->hold[i] == NULL)
2327 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2328 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2329 xpt_done(ch->hold[i]);
2336 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2337 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2339 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2340 ccb->ccb_h.func_code = XPT_ATA_IO;
2341 ccb->ccb_h.flags = CAM_DIR_IN;
2342 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2343 ataio = &ccb->ataio;
2344 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2345 if (ataio->data_ptr == NULL) {
2348 "Unable to allocate memory for READ LOG command\n");
2351 ataio->dxfer_len = 512;
2352 bzero(&ataio->cmd, sizeof(ataio->cmd));
2353 ataio->cmd.flags = CAM_ATAIO_48BIT;
2354 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2355 ataio->cmd.sector_count = 1;
2356 ataio->cmd.sector_count_exp = 0;
2357 ataio->cmd.lba_low = 0x10;
2358 ataio->cmd.lba_mid = 0;
2359 ataio->cmd.lba_mid_exp = 0;
2362 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2363 ccb->ccb_h.recovery_slot = i;
2364 ccb->ccb_h.func_code = XPT_SCSI_IO;
2365 ccb->ccb_h.flags = CAM_DIR_IN;
2366 ccb->ccb_h.status = 0;
2367 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2369 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2370 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2372 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2373 csio->cdb_io.cdb_bytes[0] = 0x03;
2374 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2376 /* Freeze SIM while doing recovery. */
2377 ch->recoverycmd = 1;
2378 xpt_freeze_simq(ch->sim, 1);
2379 ahci_begin_transaction(dev, ccb);
2383 ahci_process_read_log(device_t dev, union ccb *ccb)
2385 struct ahci_channel *ch = device_get_softc(dev);
2387 struct ata_res *res;
2390 ch->recoverycmd = 0;
2392 data = ccb->ataio.data_ptr;
2393 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2394 (data[0] & 0x80) == 0) {
2395 for (i = 0; i < ch->numslots; i++) {
2398 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2400 if ((data[0] & 0x1F) == i) {
2401 res = &ch->hold[i]->ataio.res;
2402 res->status = data[2];
2403 res->error = data[3];
2404 res->lba_low = data[4];
2405 res->lba_mid = data[5];
2406 res->lba_high = data[6];
2407 res->device = data[7];
2408 res->lba_low_exp = data[8];
2409 res->lba_mid_exp = data[9];
2410 res->lba_high_exp = data[10];
2411 res->sector_count = data[12];
2412 res->sector_count_exp = data[13];
2414 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2415 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2417 xpt_done(ch->hold[i]);
2422 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2423 device_printf(dev, "Error while READ LOG EXT\n");
2424 else if ((data[0] & 0x80) == 0) {
2425 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2427 for (i = 0; i < ch->numslots; i++) {
2430 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2432 xpt_done(ch->hold[i]);
2437 free(ccb->ataio.data_ptr, M_AHCI);
2439 xpt_release_simq(ch->sim, TRUE);
2443 ahci_process_request_sense(device_t dev, union ccb *ccb)
2445 struct ahci_channel *ch = device_get_softc(dev);
2448 ch->recoverycmd = 0;
2450 i = ccb->ccb_h.recovery_slot;
2451 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2452 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2454 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2455 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2457 xpt_done(ch->hold[i]);
2461 xpt_release_simq(ch->sim, TRUE);
2465 ahci_start(device_t dev, int fbs)
2467 struct ahci_channel *ch = device_get_softc(dev);
2470 /* Clear SATA error register */
2471 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2472 /* Clear any interrupts pending on this channel */
2473 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2474 /* Configure FIS-based switching if supported. */
2475 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2476 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2477 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2478 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2480 /* Start operations on this channel */
2481 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2482 cmd &= ~AHCI_P_CMD_PMA;
2483 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2484 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2488 ahci_stop(device_t dev)
2490 struct ahci_channel *ch = device_get_softc(dev);
2494 /* Kill all activity on this channel */
2495 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2496 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2497 /* Wait for activity stop. */
2501 if (timeout++ > 50000) {
2502 device_printf(dev, "stopping AHCI engine failed\n");
2505 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2510 ahci_clo(device_t dev)
2512 struct ahci_channel *ch = device_get_softc(dev);
2516 /* Issue Command List Override if supported */
2517 if (ch->caps & AHCI_CAP_SCLO) {
2518 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2519 cmd |= AHCI_P_CMD_CLO;
2520 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2524 if (timeout++ > 50000) {
2525 device_printf(dev, "executing CLO failed\n");
2528 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2533 ahci_stop_fr(device_t dev)
2535 struct ahci_channel *ch = device_get_softc(dev);
2539 /* Kill all FIS reception on this channel */
2540 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2541 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2542 /* Wait for FIS reception stop. */
2546 if (timeout++ > 50000) {
2547 device_printf(dev, "stopping AHCI FR engine failed\n");
2550 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2554 ahci_start_fr(device_t dev)
2556 struct ahci_channel *ch = device_get_softc(dev);
2559 /* Start FIS reception on this channel */
2560 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2561 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2565 ahci_wait_ready(device_t dev, int t, int t0)
2567 struct ahci_channel *ch = device_get_softc(dev);
2571 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2572 (ATA_S_BUSY | ATA_S_DRQ)) {
2576 "AHCI reset: device not ready after %dms "
2578 MAX(t, 0) + t0, val);
2586 device_printf(dev, "AHCI reset: device ready after %dms\n",
2592 ahci_reset_to(void *arg)
2595 struct ahci_channel *ch = device_get_softc(dev);
2597 if (ch->resetting == 0)
2600 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0,
2601 (310 - ch->resetting) * 100) == 0) {
2604 xpt_release_simq(ch->sim, TRUE);
2607 if (ch->resetting == 0) {
2610 xpt_release_simq(ch->sim, TRUE);
2613 callout_schedule(&ch->reset_timer, hz / 10);
2617 ahci_reset(device_t dev)
2619 struct ahci_channel *ch = device_get_softc(dev);
2620 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2623 xpt_freeze_simq(ch->sim, 1);
2625 device_printf(dev, "AHCI reset...\n");
2626 /* Forget about previous reset. */
2627 if (ch->resetting) {
2629 callout_stop(&ch->reset_timer);
2630 xpt_release_simq(ch->sim, TRUE);
2632 /* Requeue freezed command. */
2634 union ccb *fccb = ch->frozen;
2636 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2637 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2638 xpt_freeze_devq(fccb->ccb_h.path, 1);
2639 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2643 /* Kill the engine and requeue all running commands. */
2645 for (i = 0; i < ch->numslots; i++) {
2646 /* Do we have a running request on slot? */
2647 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2649 /* XXX; Commands in loading state. */
2650 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2652 for (i = 0; i < ch->numslots; i++) {
2655 xpt_done(ch->hold[i]);
2659 if (ch->toslots != 0)
2660 xpt_release_simq(ch->sim, TRUE);
2665 /* Tell the XPT about the event */
2666 xpt_async(AC_BUS_RESET, ch->path, NULL);
2667 /* Disable port interrupts */
2668 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2669 /* Reset and reconnect PHY, */
2670 if (!ahci_sata_phy_reset(dev)) {
2673 "AHCI reset: device not found\n");
2675 /* Enable wanted port interrupts */
2676 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2677 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2678 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2679 xpt_release_simq(ch->sim, TRUE);
2683 device_printf(dev, "AHCI reset: device found\n");
2684 /* Wait for clearing busy status. */
2685 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) {
2689 ch->resetting = 310;
2692 /* Enable wanted port interrupts */
2693 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2694 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2695 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2696 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2697 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2698 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2699 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2701 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev);
2704 xpt_release_simq(ch->sim, TRUE);
2709 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2711 struct ahci_channel *ch = device_get_softc(dev);
2712 u_int8_t *fis = &ctp->cfis[0];
2714 bzero(ctp->cfis, 16);
2715 fis[0] = 0x27; /* host to device */
2716 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2717 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2719 fis[2] = ATA_PACKET_CMD;
2720 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2721 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2724 fis[5] = ccb->csio.dxfer_len;
2725 fis[6] = ccb->csio.dxfer_len >> 8;
2728 fis[15] = ATA_A_4BIT;
2729 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2730 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2731 ctp->acmd, ccb->csio.cdb_len);
2732 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2733 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2735 fis[2] = ccb->ataio.cmd.command;
2736 fis[3] = ccb->ataio.cmd.features;
2737 fis[4] = ccb->ataio.cmd.lba_low;
2738 fis[5] = ccb->ataio.cmd.lba_mid;
2739 fis[6] = ccb->ataio.cmd.lba_high;
2740 fis[7] = ccb->ataio.cmd.device;
2741 fis[8] = ccb->ataio.cmd.lba_low_exp;
2742 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2743 fis[10] = ccb->ataio.cmd.lba_high_exp;
2744 fis[11] = ccb->ataio.cmd.features_exp;
2745 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2749 fis[12] = ccb->ataio.cmd.sector_count;
2750 fis[13] = ccb->ataio.cmd.sector_count_exp;
2752 fis[15] = ATA_A_4BIT;
2754 fis[15] = ccb->ataio.cmd.control;
2760 ahci_sata_connect(struct ahci_channel *ch)
2763 int timeout, found = 0;
2765 /* Wait up to 100ms for "connect well" */
2766 for (timeout = 0; timeout < 1000 ; timeout++) {
2767 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2768 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2770 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2771 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2772 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2774 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2776 device_printf(ch->dev, "SATA offline status=%08x\n",
2781 if (found == 0 && timeout >= 100)
2785 if (timeout >= 1000 || !found) {
2787 device_printf(ch->dev,
2788 "SATA connect timeout time=%dus status=%08x\n",
2789 timeout * 100, status);
2794 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2795 timeout * 100, status);
2797 /* Clear SATA error register */
2798 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2803 ahci_sata_phy_reset(device_t dev)
2805 struct ahci_channel *ch = device_get_softc(dev);
2809 if (ch->listening) {
2810 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2811 val |= AHCI_P_CMD_SUD;
2812 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2815 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2817 val = ATA_SC_SPD_SPEED_GEN1;
2818 else if (sata_rev == 2)
2819 val = ATA_SC_SPD_SPEED_GEN2;
2820 else if (sata_rev == 3)
2821 val = ATA_SC_SPD_SPEED_GEN3;
2824 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2825 ATA_SC_DET_RESET | val |
2826 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2828 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2829 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2830 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2831 if (!ahci_sata_connect(ch)) {
2832 if (ch->caps & AHCI_CAP_SSS) {
2833 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2834 val &= ~AHCI_P_CMD_SUD;
2835 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2837 } else if (ch->pm_level > 0)
2838 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2845 ahci_check_ids(device_t dev, union ccb *ccb)
2847 struct ahci_channel *ch = device_get_softc(dev);
2849 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2850 ccb->ccb_h.status = CAM_TID_INVALID;
2854 if (ccb->ccb_h.target_lun != 0) {
2855 ccb->ccb_h.status = CAM_LUN_INVALID;
2863 ahciaction(struct cam_sim *sim, union ccb *ccb)
2865 device_t dev, parent;
2866 struct ahci_channel *ch;
2868 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2869 ccb->ccb_h.func_code));
2871 ch = (struct ahci_channel *)cam_sim_softc(sim);
2873 switch (ccb->ccb_h.func_code) {
2874 /* Common cases first */
2875 case XPT_ATA_IO: /* Execute the requested I/O operation */
2877 if (ahci_check_ids(dev, ccb))
2879 if (ch->devices == 0 ||
2880 (ch->pm_present == 0 &&
2881 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2882 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2885 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2886 /* Check for command collision. */
2887 if (ahci_check_collision(dev, ccb)) {
2888 /* Freeze command. */
2890 /* We have only one frozen slot, so freeze simq also. */
2891 xpt_freeze_simq(ch->sim, 1);
2894 ahci_begin_transaction(dev, ccb);
2896 case XPT_EN_LUN: /* Enable LUN as a target */
2897 case XPT_TARGET_IO: /* Execute target I/O request */
2898 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2899 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2900 case XPT_ABORT: /* Abort the specified CCB */
2902 ccb->ccb_h.status = CAM_REQ_INVALID;
2904 case XPT_SET_TRAN_SETTINGS:
2906 struct ccb_trans_settings *cts = &ccb->cts;
2907 struct ahci_device *d;
2909 if (ahci_check_ids(dev, ccb))
2911 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2912 d = &ch->curr[ccb->ccb_h.target_id];
2914 d = &ch->user[ccb->ccb_h.target_id];
2915 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2916 d->revision = cts->xport_specific.sata.revision;
2917 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2918 d->mode = cts->xport_specific.sata.mode;
2919 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2920 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2921 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2922 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2923 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2924 ch->pm_present = cts->xport_specific.sata.pm_present;
2925 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2926 d->atapi = cts->xport_specific.sata.atapi;
2927 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2928 d->caps = cts->xport_specific.sata.caps;
2929 ccb->ccb_h.status = CAM_REQ_CMP;
2932 case XPT_GET_TRAN_SETTINGS:
2933 /* Get default/user set transfer settings for the target */
2935 struct ccb_trans_settings *cts = &ccb->cts;
2936 struct ahci_device *d;
2939 if (ahci_check_ids(dev, ccb))
2941 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2942 d = &ch->curr[ccb->ccb_h.target_id];
2944 d = &ch->user[ccb->ccb_h.target_id];
2945 cts->protocol = PROTO_UNSPECIFIED;
2946 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2947 cts->transport = XPORT_SATA;
2948 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2949 cts->proto_specific.valid = 0;
2950 cts->xport_specific.sata.valid = 0;
2951 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2952 (ccb->ccb_h.target_id == 15 ||
2953 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2954 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2955 if (status & 0x0f0) {
2956 cts->xport_specific.sata.revision =
2957 (status & 0x0f0) >> 4;
2958 cts->xport_specific.sata.valid |=
2959 CTS_SATA_VALID_REVISION;
2961 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2963 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2964 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2965 if (ch->caps2 & AHCI_CAP2_APST)
2966 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2968 if ((ch->caps & AHCI_CAP_SNCQ) &&
2969 (ch->quirks & AHCI_Q_NOAA) == 0)
2970 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2971 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2972 cts->xport_specific.sata.caps &=
2973 ch->user[ccb->ccb_h.target_id].caps;
2974 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2976 cts->xport_specific.sata.revision = d->revision;
2977 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2978 cts->xport_specific.sata.caps = d->caps;
2979 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2981 cts->xport_specific.sata.mode = d->mode;
2982 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2983 cts->xport_specific.sata.bytecount = d->bytecount;
2984 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2985 cts->xport_specific.sata.pm_present = ch->pm_present;
2986 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2987 cts->xport_specific.sata.tags = d->tags;
2988 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2989 cts->xport_specific.sata.atapi = d->atapi;
2990 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2991 ccb->ccb_h.status = CAM_REQ_CMP;
2994 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2995 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2997 ccb->ccb_h.status = CAM_REQ_CMP;
2999 case XPT_TERM_IO: /* Terminate the I/O process */
3001 ccb->ccb_h.status = CAM_REQ_INVALID;
3003 case XPT_PATH_INQ: /* Path routing inquiry */
3005 struct ccb_pathinq *cpi = &ccb->cpi;
3007 parent = device_get_parent(dev);
3008 cpi->version_num = 1; /* XXX??? */
3009 cpi->hba_inquiry = PI_SDTR_ABLE;
3010 if (ch->caps & AHCI_CAP_SNCQ)
3011 cpi->hba_inquiry |= PI_TAG_ABLE;
3012 if (ch->caps & AHCI_CAP_SPM)
3013 cpi->hba_inquiry |= PI_SATAPM;
3014 cpi->target_sprt = 0;
3015 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
3016 cpi->hba_eng_cnt = 0;
3017 if (ch->caps & AHCI_CAP_SPM)
3018 cpi->max_target = 15;
3020 cpi->max_target = 0;
3022 cpi->initiator_id = 0;
3023 cpi->bus_id = cam_sim_bus(sim);
3024 cpi->base_transfer_speed = 150000;
3025 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3026 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
3027 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
3028 cpi->unit_number = cam_sim_unit(sim);
3029 cpi->transport = XPORT_SATA;
3030 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
3031 cpi->protocol = PROTO_ATA;
3032 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
3033 cpi->maxio = MAXPHYS;
3034 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
3035 if (pci_get_devid(parent) == 0x43801002)
3036 cpi->maxio = min(cpi->maxio, 128 * 512);
3037 cpi->hba_vendor = pci_get_vendor(parent);
3038 cpi->hba_device = pci_get_device(parent);
3039 cpi->hba_subvendor = pci_get_subvendor(parent);
3040 cpi->hba_subdevice = pci_get_subdevice(parent);
3041 cpi->ccb_h.status = CAM_REQ_CMP;
3045 ccb->ccb_h.status = CAM_REQ_INVALID;
3052 ahcipoll(struct cam_sim *sim)
3054 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
3056 ahci_ch_intr(ch->dev);
3057 if (ch->resetting != 0 &&
3058 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
3059 ch->resetpolldiv = 1000;
3060 ahci_reset_to(ch->dev);