sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  13 **
  14 ** Redistribution and use in source and binary forms, with or without
  15 ** modification, are permitted provided that the following conditions
  16 ** are met:
  17 ** 1. Redistributions of source code must retain the above copyright
  18 **    notice, this list of conditions and the following disclaimer.
  19 ** 2. Redistributions in binary form must reproduce the above copyright
  20 **    notice, this list of conditions and the following disclaimer in the
  21 **    documentation and/or other materials provided with the distribution.
  22 ** 3. The name of the author may not be used to endorse or promote products
  23 **    derived from this software without specific prior written permission.
  24 **
  25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 ********************************************************************************
  36 ** History
  37 **
  38 **    REV#         DATE         NAME        DESCRIPTION
  39 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  40 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  41 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  42 **                                          clean unused function
  43 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  44 **                                          firmware version check
  45 **                                          and firmware update notify for hardware bug fix
  46 **                                          handling if none zero high part physical address
  47 **                                          of srb resource
  48 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  49 **                                          add iop message xfer
  50 **                                          with scsi pass-through command
  51 **                                          add new device id of sas raid adapters
  52 **                                          code fit for SPARC64 & PPC
  53 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  54 **                                          and cause g_vfs_done() read write error
  55 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  56 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  57 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  58 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  59 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  60 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  61 **                                          for any one LUN device failed
  62 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  63 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  64 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  65 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  66 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  67 **              02/14/2011  Ching Huang     Modified pktRequestCount
  68 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  69 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  70 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  71 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  72 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  73 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  74 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  75 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  76 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  77 ******************************************************************************************
  78 */
  79
  80 #include <sys/cdefs.h>
  81 __FBSDID("$FreeBSD$");
  82
  83 #if 0
  84 #define ARCMSR_DEBUG1                   1
  85 #endif
  86 #include <sys/param.h>
  87 #include <sys/systm.h>
  88 #include <sys/malloc.h>
  89 #include <sys/kernel.h>
  90 #include <sys/bus.h>
  91 #include <sys/queue.h>
  92 #include <sys/stat.h>
  93 #include <sys/devicestat.h>
  94 #include <sys/kthread.h>
  95 #include <sys/module.h>
  96 #include <sys/proc.h>
  97 #include <sys/lock.h>
  98 #include <sys/sysctl.h>
  99 #include <sys/poll.h>
 100 #include <sys/ioccom.h>
 101 #include <vm/vm.h>
 102 #include <vm/vm_param.h>
 103 #include <vm/pmap.h>
 104
 105 #include <isa/rtc.h>
 106
 107 #include <machine/bus.h>
 108 #include <machine/resource.h>
 109 #include <machine/atomic.h>
 110 #include <sys/conf.h>
 111 #include <sys/rman.h>
 112
 113 #include <cam/cam.h>
 114 #include <cam/cam_ccb.h>
 115 #include <cam/cam_sim.h>
 116 #include <cam/cam_periph.h>
 117 #include <cam/cam_xpt_periph.h>
 118 #include <cam/cam_xpt_sim.h>
 119 #include <cam/cam_debug.h>
 120 #include <cam/scsi/scsi_all.h>
 121 #include <cam/scsi/scsi_message.h>
 122 /*
 123 **************************************************************************
 124 **************************************************************************
 125 */
 126 #if __FreeBSD_version >= 500005
 127     #include <sys/selinfo.h>
 128     #include <sys/mutex.h>
 129     #include <sys/endian.h>
 130     #include <dev/pci/pcivar.h>
 131     #include <dev/pci/pcireg.h>
 132 #else
 133     #include <sys/select.h>
 134     #include <pci/pcivar.h>
 135     #include <pci/pcireg.h>
 136 #endif
 137
 138 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
 139 #define CAM_NEW_TRAN_CODE       1
 140 #endif
 141
 142 #if __FreeBSD_version > 500000
 143 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 144 #else
 145 #define arcmsr_callout_init(a)  callout_init(a);
 146 #endif
 147
 148 #define ARCMSR_DRIVER_VERSION   "Driver Version 1.20.00.27 2013-05-06"
 149 #include <dev/arcmsr/arcmsr.h>
 150 /*
 151 **************************************************************************
 152 **************************************************************************
 153 */
 154 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 155 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 156 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 157 static int arcmsr_probe(device_t dev);
 158 static int arcmsr_attach(device_t dev);
 159 static int arcmsr_detach(device_t dev);
 160 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 161 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 162 static int arcmsr_shutdown(device_t dev);
 163 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 164 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 165 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 166 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 167 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 168 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 169 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 170 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 171 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 172 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 173 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 174 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 175 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 176 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 177 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 178 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 179 static int arcmsr_resume(device_t dev);
 180 static int arcmsr_suspend(device_t dev);
 181 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 182 static void     arcmsr_polling_devmap(void *arg);
 183 static void     arcmsr_srb_timeout(void *arg);
 184 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 185 #ifdef ARCMSR_DEBUG1
 186 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 187 #endif
 188 /*
 189 **************************************************************************
 190 **************************************************************************
 191 */
 192 static void UDELAY(u_int32_t us) { DELAY(us); }
 193 /*
 194 **************************************************************************
 195 **************************************************************************
 196 */
 197 static bus_dmamap_callback_t arcmsr_map_free_srb;
 198 static bus_dmamap_callback_t arcmsr_execute_srb;
 199 /*
 200 **************************************************************************
 201 **************************************************************************
 202 */
 203 static d_open_t arcmsr_open;
 204 static d_close_t arcmsr_close;
 205 static d_ioctl_t arcmsr_ioctl;
 206
 207 static device_method_t arcmsr_methods[]={
 208         DEVMETHOD(device_probe,         arcmsr_probe),
 209         DEVMETHOD(device_attach,        arcmsr_attach),
 210         DEVMETHOD(device_detach,        arcmsr_detach),
 211         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 212         DEVMETHOD(device_suspend,       arcmsr_suspend),
 213         DEVMETHOD(device_resume,        arcmsr_resume),
 214
 215 #if __FreeBSD_version >= 803000
 216         DEVMETHOD_END
 217 #else
 218         { 0, 0 }
 219 #endif
 220 };
 221
 222 static driver_t arcmsr_driver={
 223         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 224 };
 225
 226 static devclass_t arcmsr_devclass;
 227 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 228 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 229 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 230 #ifndef BUS_DMA_COHERENT
 231         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 232 #endif
 233 #if __FreeBSD_version >= 501000
 234 static struct cdevsw arcmsr_cdevsw={
 235         #if __FreeBSD_version >= 503000
 236                 .d_version = D_VERSION,
 237         #endif
 238         #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
 239                 .d_flags   = D_NEEDGIANT,
 240         #endif
 241                 .d_open    = arcmsr_open,       /* open     */
 242                 .d_close   = arcmsr_close,      /* close    */
 243                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 244                 .d_name    = "arcmsr",          /* name     */
 245         };
 246 #else
 247         #define ARCMSR_CDEV_MAJOR       180
 248
 249 static struct cdevsw arcmsr_cdevsw = {
 250                 arcmsr_open,                            /* open     */
 251                 arcmsr_close,                           /* close    */
 252                 noread,                                         /* read     */
 253                 nowrite,                                        /* write    */
 254                 arcmsr_ioctl,                           /* ioctl    */
 255                 nopoll,                                         /* poll     */
 256                 nommap,                                         /* mmap     */
 257                 nostrategy,                                     /* strategy */
 258                 "arcmsr",                                       /* name     */
 259                 ARCMSR_CDEV_MAJOR,                      /* major    */
 260                 nodump,                                         /* dump     */
 261                 nopsize,                                        /* psize    */
 262                 0                                                       /* flags    */
 263         };
 264 #endif
 265 /*
 266 **************************************************************************
 267 **************************************************************************
 268 */
 269 #if __FreeBSD_version < 500005
 270         static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
 271 #else
 272         #if __FreeBSD_version < 503000
 273         static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
 274         #else
 275         static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 276         #endif
 277 #endif
 278 {
 279         #if __FreeBSD_version < 503000
 280                 struct AdapterControlBlock *acb = dev->si_drv1;
 281         #else
 282                 int     unit = dev2unit(dev);
 283                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 284         #endif
 285         if(acb == NULL) {
 286                 return ENXIO;
 287         }
 288         return (0);
 289 }
 290 /*
 291 **************************************************************************
 292 **************************************************************************
 293 */
 294 #if __FreeBSD_version < 500005
 295         static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
 296 #else
 297         #if __FreeBSD_version < 503000
 298         static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
 299         #else
 300         static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 301         #endif
 302 #endif
 303 {
 304         #if __FreeBSD_version < 503000
 305                 struct AdapterControlBlock *acb = dev->si_drv1;
 306         #else
 307                 int     unit = dev2unit(dev);
 308                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 309         #endif
 310         if(acb == NULL) {
 311                 return ENXIO;
 312         }
 313         return 0;
 314 }
 315 /*
 316 **************************************************************************
 317 **************************************************************************
 318 */
 319 #if __FreeBSD_version < 500005
 320         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
 321 #else
 322         #if __FreeBSD_version < 503000
 323         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 324         #else
 325         static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 326         #endif
 327 #endif
 328 {
 329         #if __FreeBSD_version < 503000
 330                 struct AdapterControlBlock *acb = dev->si_drv1;
 331         #else
 332                 int     unit = dev2unit(dev);
 333                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 334         #endif
 335
 336         if(acb == NULL) {
 337                 return ENXIO;
 338         }
 339         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 340 }
 341 /*
 342 **********************************************************************
 343 **********************************************************************
 344 */
 345 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 346 {
 347         u_int32_t intmask_org = 0;
 348
 349         switch (acb->adapter_type) {
 350         case ACB_ADAPTER_TYPE_A: {
 351                         /* disable all outbound interrupt */
 352                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 353                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 354                 }
 355                 break;
 356         case ACB_ADAPTER_TYPE_B: {
 357                         /* disable all outbound interrupt */
 358                         intmask_org = CHIP_REG_READ32(HBB_DOORBELL,
 359                                                 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 360                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
 361                 }
 362                 break;
 363         case ACB_ADAPTER_TYPE_C: {
 364                         /* disable all outbound interrupt */
 365                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 366                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 367                 }
 368                 break;
 369         case ACB_ADAPTER_TYPE_D: {
 370                         /* disable all outbound interrupt */
 371                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
 372                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 373                 }
 374                 break;
 375         }
 376         return (intmask_org);
 377 }
 378 /*
 379 **********************************************************************
 380 **********************************************************************
 381 */
 382 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 383 {
 384         u_int32_t mask;
 385
 386         switch (acb->adapter_type) {
 387         case ACB_ADAPTER_TYPE_A: {
 388                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 389                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 390                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 391                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 392                 }
 393                 break;
 394         case ACB_ADAPTER_TYPE_B: {
 395                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 396                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 397                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 398                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 399                 }
 400                 break;
 401         case ACB_ADAPTER_TYPE_C: {
 402                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 403                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 404                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 405                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 406                 }
 407                 break;
 408         case ACB_ADAPTER_TYPE_D: {
 409                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 410                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 411                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 412                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 413                         acb->outbound_int_enable = mask;
 414                 }
 415                 break;
 416         }
 417 }
 418 /*
 419 **********************************************************************
 420 **********************************************************************
 421 */
 422 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 423 {
 424         u_int32_t Index;
 425         u_int8_t Retries = 0x00;
 426
 427         do {
 428                 for(Index=0; Index < 100; Index++) {
 429                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 430                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 431                                 return TRUE;
 432                         }
 433                         UDELAY(10000);
 434                 }/*max 1 seconds*/
 435         }while(Retries++ < 20);/*max 20 sec*/
 436         return (FALSE);
 437 }
 438 /*
 439 **********************************************************************
 440 **********************************************************************
 441 */
 442 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 443 {
 444         u_int32_t Index;
 445         u_int8_t Retries = 0x00;
 446
 447         do {
 448                 for(Index=0; Index < 100; Index++) {
 449                         if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 450                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 451                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 452                                 return TRUE;
 453                         }
 454                         UDELAY(10000);
 455                 }/*max 1 seconds*/
 456         }while(Retries++ < 20);/*max 20 sec*/
 457         return (FALSE);
 458 }
 459 /*
 460 **********************************************************************
 461 **********************************************************************
 462 */
 463 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 464 {
 465         u_int32_t Index;
 466         u_int8_t Retries = 0x00;
 467
 468         do {
 469                 for(Index=0; Index < 100; Index++) {
 470                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 471                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 472                                 return TRUE;
 473                         }
 474                         UDELAY(10000);
 475                 }/*max 1 seconds*/
 476         }while(Retries++ < 20);/*max 20 sec*/
 477         return (FALSE);
 478 }
 479 /*
 480 **********************************************************************
 481 **********************************************************************
 482 */
 483 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 484 {
 485         u_int32_t Index;
 486         u_int8_t Retries = 0x00;
 487
 488         do {
 489                 for(Index=0; Index < 100; Index++) {
 490                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 491                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 492                                 return TRUE;
 493                         }
 494                         UDELAY(10000);
 495                 }/*max 1 seconds*/
 496         }while(Retries++ < 20);/*max 20 sec*/
 497         return (FALSE);
 498 }
 499 /*
 500 ************************************************************************
 501 ************************************************************************
 502 */
 503 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 504 {
 505         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 506
 507         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 508         do {
 509                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 510                         break;
 511                 } else {
 512                         retry_count--;
 513                 }
 514         }while(retry_count != 0);
 515 }
 516 /*
 517 ************************************************************************
 518 ************************************************************************
 519 */
 520 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 521 {
 522         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 523
 524         CHIP_REG_WRITE32(HBB_DOORBELL,
 525         0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 526         do {
 527                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 528                         break;
 529                 } else {
 530                         retry_count--;
 531                 }
 532         }while(retry_count != 0);
 533 }
 534 /*
 535 ************************************************************************
 536 ************************************************************************
 537 */
 538 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 539 {
 540         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 541
 542         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 543         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 544         do {
 545                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 546                         break;
 547                 } else {
 548                         retry_count--;
 549                 }
 550         }while(retry_count != 0);
 551 }
 552 /*
 553 ************************************************************************
 554 ************************************************************************
 555 */
 556 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 557 {
 558         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 559
 560         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 561         do {
 562                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 563                         break;
 564                 } else {
 565                         retry_count--;
 566                 }
 567         }while(retry_count != 0);
 568 }
 569 /*
 570 ************************************************************************
 571 ************************************************************************
 572 */
 573 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 574 {
 575         switch (acb->adapter_type) {
 576         case ACB_ADAPTER_TYPE_A: {
 577                         arcmsr_flush_hba_cache(acb);
 578                 }
 579                 break;
 580         case ACB_ADAPTER_TYPE_B: {
 581                         arcmsr_flush_hbb_cache(acb);
 582                 }
 583                 break;
 584         case ACB_ADAPTER_TYPE_C: {
 585                         arcmsr_flush_hbc_cache(acb);
 586                 }
 587                 break;
 588         case ACB_ADAPTER_TYPE_D: {
 589                         arcmsr_flush_hbd_cache(acb);
 590                 }
 591                 break;
 592         }
 593 }
 594 /*
 595 *******************************************************************************
 596 *******************************************************************************
 597 */
 598 static int arcmsr_suspend(device_t dev)
 599 {
 600         struct AdapterControlBlock      *acb = device_get_softc(dev);
 601
 602         /* flush controller */
 603         arcmsr_iop_parking(acb);
 604         /* disable all outbound interrupt */
 605         arcmsr_disable_allintr(acb);
 606         return(0);
 607 }
 608 /*
 609 *******************************************************************************
 610 *******************************************************************************
 611 */
 612 static int arcmsr_resume(device_t dev)
 613 {
 614         struct AdapterControlBlock      *acb = device_get_softc(dev);
 615
 616         arcmsr_iop_init(acb);
 617         return(0);
 618 }
 619 /*
 620 *********************************************************************************
 621 *********************************************************************************
 622 */
 623 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 624 {
 625         struct AdapterControlBlock *acb;
 626         u_int8_t target_id, target_lun;
 627         struct cam_sim *sim;
 628
 629         sim = (struct cam_sim *) cb_arg;
 630         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 631         switch (code) {
 632         case AC_LOST_DEVICE:
 633                 target_id = xpt_path_target_id(path);
 634                 target_lun = xpt_path_lun_id(path);
 635                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 636                         break;
 637                 }
 638         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 639                 break;
 640         default:
 641                 break;
 642         }
 643 }
 644 /*
 645 **********************************************************************
 646 **********************************************************************
 647 */
 648 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 649 {
 650         union ccb *pccb = srb->pccb;
 651
 652         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 653         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 654         if(pccb->csio.sense_len) {
 655                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 656                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 657                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 658                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 659                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 660         }
 661 }
 662 /*
 663 *********************************************************************
 664 *********************************************************************
 665 */
 666 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 667 {
 668         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 669         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 670                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 671         }
 672 }
 673 /*
 674 *********************************************************************
 675 *********************************************************************
 676 */
 677 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 678 {
 679         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 680         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 681                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 682         }
 683 }
 684 /*
 685 *********************************************************************
 686 *********************************************************************
 687 */
 688 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 689 {
 690         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 691         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 692         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 693                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 694         }
 695 }
 696 /*
 697 *********************************************************************
 698 *********************************************************************
 699 */
 700 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 701 {
 702         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 703         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 704                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 705         }
 706 }
 707 /*
 708 *********************************************************************
 709 *********************************************************************
 710 */
 711 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 712 {
 713         switch (acb->adapter_type) {
 714         case ACB_ADAPTER_TYPE_A: {
 715                         arcmsr_abort_hba_allcmd(acb);
 716                 }
 717                 break;
 718         case ACB_ADAPTER_TYPE_B: {
 719                         arcmsr_abort_hbb_allcmd(acb);
 720                 }
 721                 break;
 722         case ACB_ADAPTER_TYPE_C: {
 723                         arcmsr_abort_hbc_allcmd(acb);
 724                 }
 725                 break;
 726         case ACB_ADAPTER_TYPE_D: {
 727                         arcmsr_abort_hbd_allcmd(acb);
 728                 }
 729                 break;
 730         }
 731 }
 732 /*
 733 **********************************************************************
 734 **********************************************************************
 735 */
 736 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 737 {
 738         struct AdapterControlBlock *acb = srb->acb;
 739         union ccb *pccb = srb->pccb;
 740
 741         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 742                 callout_stop(&srb->ccb_callout);
 743         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 744                 bus_dmasync_op_t op;
 745
 746                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 747                         op = BUS_DMASYNC_POSTREAD;
 748                 } else {
 749                         op = BUS_DMASYNC_POSTWRITE;
 750                 }
 751                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 752                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 753         }
 754         if(stand_flag == 1) {
 755                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 756                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 757                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 758                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 759                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 760                 }
 761         }
 762         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 763                 arcmsr_free_srb(srb);
 764         acb->pktReturnCount++;
 765         xpt_done(pccb);
 766 }
 767 /*
 768 **************************************************************************
 769 **************************************************************************
 770 */
 771 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 772 {
 773         int target, lun;
 774
 775         target = srb->pccb->ccb_h.target_id;
 776         lun = srb->pccb->ccb_h.target_lun;
 777         if(error == FALSE) {
 778                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 779                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 780                 }
 781                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 782                 arcmsr_srb_complete(srb, 1);
 783         } else {
 784                 switch(srb->arcmsr_cdb.DeviceStatus) {
 785                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 786                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 787                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 788                                 }
 789                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 790                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 791                                 arcmsr_srb_complete(srb, 1);
 792                         }
 793                         break;
 794                 case ARCMSR_DEV_ABORTED:
 795                 case ARCMSR_DEV_INIT_FAIL: {
 796                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 797                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 798                                 arcmsr_srb_complete(srb, 1);
 799                         }
 800                         break;
 801                 case SCSISTAT_CHECK_CONDITION: {
 802                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 803                                 arcmsr_report_sense_info(srb);
 804                                 arcmsr_srb_complete(srb, 1);
 805                         }
 806                         break;
 807                 default:
 808                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknow DeviceStatus=0x%x \n"
 809                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 810                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 811                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 812                         /*unknow error or crc error just for retry*/
 813                         arcmsr_srb_complete(srb, 1);
 814                         break;
 815                 }
 816         }
 817 }
 818 /*
 819 **************************************************************************
 820 **************************************************************************
 821 */
 822 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 823 {
 824         struct CommandControlBlock *srb;
 825
 826         /* check if command done with no error*/
 827         switch (acb->adapter_type) {
 828         case ACB_ADAPTER_TYPE_C:
 829         case ACB_ADAPTER_TYPE_D:
 830                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 831                 break;
 832         case ACB_ADAPTER_TYPE_A:
 833         case ACB_ADAPTER_TYPE_B:
 834         default:
 835                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 836                 break;
 837         }
 838         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 839                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 840                         arcmsr_free_srb(srb);
 841                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 842                         return;
 843                 }
 844                 printf("arcmsr%d: return srb has been completed\n"
 845                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 846                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 847                 return;
 848         }
 849         arcmsr_report_srb_state(acb, srb, error);
 850 }
 851 /*
 852 **************************************************************************
 853 **************************************************************************
 854 */
 855 static void     arcmsr_srb_timeout(void *arg)
 856 {
 857         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 858         struct AdapterControlBlock *acb;
 859         int target, lun;
 860         u_int8_t cmd;
 861
 862         target = srb->pccb->ccb_h.target_id;
 863         lun = srb->pccb->ccb_h.target_lun;
 864         acb = srb->acb;
 865         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 866         if(srb->srb_state == ARCMSR_SRB_START)
 867         {
 868                 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
 869                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 870                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 871                 arcmsr_srb_complete(srb, 1);
 872                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 873                                  acb->pci_unit, target, lun, cmd, srb);
 874         }
 875         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 876 #ifdef ARCMSR_DEBUG1
 877         arcmsr_dump_data(acb);
 878 #endif
 879 }
 880
 881 /*
 882 **********************************************************************
 883 **********************************************************************
 884 */
 885 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 886 {
 887         int i=0;
 888         u_int32_t flag_srb;
 889         u_int16_t error;
 890
 891         switch (acb->adapter_type) {
 892         case ACB_ADAPTER_TYPE_A: {
 893                         u_int32_t outbound_intstatus;
 894
 895                         /*clear and abort all outbound posted Q*/
 896                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 897                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 898                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 899                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 900                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 901                         }
 902                 }
 903                 break;
 904         case ACB_ADAPTER_TYPE_B: {
 905                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 906
 907                         /*clear all outbound posted Q*/
 908                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 909                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 910                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
 911                                         phbbmu->done_qbuffer[i] = 0;
 912                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 913                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 914                                 }
 915                                 phbbmu->post_qbuffer[i] = 0;
 916                         }/*drain reply FIFO*/
 917                         phbbmu->doneq_index = 0;
 918                         phbbmu->postq_index = 0;
 919                 }
 920                 break;
 921         case ACB_ADAPTER_TYPE_C: {
 922
 923                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 924                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 925                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 926                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 927                         }
 928                 }
 929                 break;
 930         case ACB_ADAPTER_TYPE_D: {
 931                         arcmsr_hbd_postqueue_isr(acb);
 932                 }
 933                 break;
 934         }
 935 }
 936 /*
 937 ****************************************************************************
 938 ****************************************************************************
 939 */
 940 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 941 {
 942         struct CommandControlBlock *srb;
 943         u_int32_t intmask_org;
 944         u_int32_t i=0;
 945
 946         if(acb->srboutstandingcount>0) {
 947                 /* disable all outbound interrupt */
 948                 intmask_org = arcmsr_disable_allintr(acb);
 949                 /*clear and abort all outbound posted Q*/
 950                 arcmsr_done4abort_postqueue(acb);
 951                 /* talk to iop 331 outstanding command aborted*/
 952                 arcmsr_abort_allcmd(acb);
 953                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 954                         srb = acb->psrb_pool[i];
 955                         if(srb->srb_state == ARCMSR_SRB_START) {
 956                                 srb->srb_state = ARCMSR_SRB_ABORTED;
 957                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 958                                 arcmsr_srb_complete(srb, 1);
 959                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n"
 960                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
 961                                                 , srb->pccb->ccb_h.target_lun, srb);
 962                         }
 963                 }
 964                 /* enable all outbound interrupt */
 965                 arcmsr_enable_allintr(acb, intmask_org);
 966         }
 967         acb->srboutstandingcount = 0;
 968         acb->workingsrb_doneindex = 0;
 969         acb->workingsrb_startindex = 0;
 970         acb->pktRequestCount = 0;
 971         acb->pktReturnCount = 0;
 972 }
 973 /*
 974 **********************************************************************
 975 **********************************************************************
 976 */
 977 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 978                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
 979 {
 980         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
 981         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
 982         u_int32_t address_lo, address_hi;
 983         union ccb *pccb = srb->pccb;
 984         struct ccb_scsiio *pcsio = &pccb->csio;
 985         u_int32_t arccdbsize = 0x30;
 986
 987         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
 988         arcmsr_cdb->Bus = 0;
 989         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
 990         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
 991         arcmsr_cdb->Function = 1;
 992         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
 993         bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
 994         if(nseg != 0) {
 995                 struct AdapterControlBlock *acb = srb->acb;
 996                 bus_dmasync_op_t op;
 997                 u_int32_t length, i, cdb_sgcount = 0;
 998
 999                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1000                         op = BUS_DMASYNC_PREREAD;
1001                 } else {
1002                         op = BUS_DMASYNC_PREWRITE;
1003                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1004                         srb->srb_flags |= SRB_FLAG_WRITE;
1005                 }
1006                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1007                 for(i=0; i < nseg; i++) {
1008                         /* Get the physical address of the current data pointer */
1009                         length = arcmsr_htole32(dm_segs[i].ds_len);
1010                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1011                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1012                         if(address_hi == 0) {
1013                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1014                                 pdma_sg->address = address_lo;
1015                                 pdma_sg->length = length;
1016                                 psge += sizeof(struct SG32ENTRY);
1017                                 arccdbsize += sizeof(struct SG32ENTRY);
1018                         } else {
1019                                 u_int32_t sg64s_size = 0, tmplength = length;
1020
1021                                 while(1) {
1022                                         u_int64_t span4G, length0;
1023                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1024
1025                                         span4G = (u_int64_t)address_lo + tmplength;
1026                                         pdma_sg->addresshigh = address_hi;
1027                                         pdma_sg->address = address_lo;
1028                                         if(span4G > 0x100000000) {
1029                                                 /*see if cross 4G boundary*/
1030                                                 length0 = 0x100000000-address_lo;
1031                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1032                                                 address_hi = address_hi+1;
1033                                                 address_lo = 0;
1034                                                 tmplength = tmplength - (u_int32_t)length0;
1035                                                 sg64s_size += sizeof(struct SG64ENTRY);
1036                                                 psge += sizeof(struct SG64ENTRY);
1037                                                 cdb_sgcount++;
1038                                         } else {
1039                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1040                                                 sg64s_size += sizeof(struct SG64ENTRY);
1041                                                 psge += sizeof(struct SG64ENTRY);
1042                                                 break;
1043                                         }
1044                                 }
1045                                 arccdbsize += sg64s_size;
1046                         }
1047                         cdb_sgcount++;
1048                 }
1049                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1050                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1051                 if( arccdbsize > 256) {
1052                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1053                 }
1054         } else {
1055                 arcmsr_cdb->DataLength = 0;
1056         }
1057     srb->arc_cdb_size = arccdbsize;
1058     arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1059 }
1060 /*
1061 **************************************************************************
1062 **************************************************************************
1063 */
1064 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1065 {
1066         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1067         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1068
1069         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1070         atomic_add_int(&acb->srboutstandingcount, 1);
1071         srb->srb_state = ARCMSR_SRB_START;
1072
1073         switch (acb->adapter_type) {
1074         case ACB_ADAPTER_TYPE_A: {
1075                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1076                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1077                         } else {
1078                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1079                         }
1080                 }
1081                 break;
1082         case ACB_ADAPTER_TYPE_B: {
1083                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1084                         int ending_index, index;
1085
1086                         index = phbbmu->postq_index;
1087                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1088                         phbbmu->post_qbuffer[ending_index] = 0;
1089                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1090                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1091                         } else {
1092                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1093                         }
1094                         index++;
1095                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1096                         phbbmu->postq_index = index;
1097                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1098                 }
1099                 break;
1100     case ACB_ADAPTER_TYPE_C: {
1101             u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1102
1103             arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1104             ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1105                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1106             if(cdb_phyaddr_hi32)
1107             {
1108                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1109                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1110             }
1111             else
1112             {
1113                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1114             }
1115         }
1116         break;
1117         case ACB_ADAPTER_TYPE_D: {
1118                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1119                         u_int16_t index_stripped;
1120                         u_int16_t postq_index;
1121                         struct InBound_SRB *pinbound_srb;
1122
1123                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1124                         postq_index = phbdmu->postq_index;
1125                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1126                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1127                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1128                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1129                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1130                         if (postq_index & 0x4000) {
1131                                 index_stripped = postq_index & 0xFF;
1132                                 index_stripped += 1;
1133                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1134                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1135                         } else {
1136                                 index_stripped = postq_index;
1137                                 index_stripped += 1;
1138                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1139                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1140                         }
1141                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1142                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1143                 }
1144                 break;
1145         }
1146 }
1147 /*
1148 ************************************************************************
1149 ************************************************************************
1150 */
1151 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1152 {
1153         struct QBUFFER *qbuffer=NULL;
1154
1155         switch (acb->adapter_type) {
1156         case ACB_ADAPTER_TYPE_A: {
1157                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1158
1159                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1160                 }
1161                 break;
1162         case ACB_ADAPTER_TYPE_B: {
1163                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1164
1165                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1166                 }
1167                 break;
1168         case ACB_ADAPTER_TYPE_C: {
1169                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1170
1171                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1172                 }
1173                 break;
1174         case ACB_ADAPTER_TYPE_D: {
1175                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1176
1177                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1178                 }
1179                 break;
1180         }
1181         return(qbuffer);
1182 }
1183 /*
1184 ************************************************************************
1185 ************************************************************************
1186 */
1187 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1188 {
1189         struct QBUFFER *qbuffer = NULL;
1190
1191         switch (acb->adapter_type) {
1192         case ACB_ADAPTER_TYPE_A: {
1193                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1194
1195                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1196                 }
1197                 break;
1198         case ACB_ADAPTER_TYPE_B: {
1199                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1200
1201                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1202                 }
1203                 break;
1204         case ACB_ADAPTER_TYPE_C: {
1205                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1206
1207                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1208                 }
1209                 break;
1210         case ACB_ADAPTER_TYPE_D: {
1211                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1212
1213                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1214                 }
1215                 break;
1216         }
1217         return(qbuffer);
1218 }
1219 /*
1220 **************************************************************************
1221 **************************************************************************
1222 */
1223 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1224 {
1225         switch (acb->adapter_type) {
1226         case ACB_ADAPTER_TYPE_A: {
1227                         /* let IOP know data has been read */
1228                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1229                 }
1230                 break;
1231         case ACB_ADAPTER_TYPE_B: {
1232                         /* let IOP know data has been read */
1233                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1234                 }
1235                 break;
1236         case ACB_ADAPTER_TYPE_C: {
1237                         /* let IOP know data has been read */
1238                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1239                 }
1240                 break;
1241         case ACB_ADAPTER_TYPE_D: {
1242                         /* let IOP know data has been read */
1243                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1244                 }
1245                 break;
1246         }
1247 }
1248 /*
1249 **************************************************************************
1250 **************************************************************************
1251 */
1252 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1253 {
1254         switch (acb->adapter_type) {
1255         case ACB_ADAPTER_TYPE_A: {
1256                         /*
1257                         ** push inbound doorbell tell iop, driver data write ok
1258                         ** and wait reply on next hwinterrupt for next Qbuffer post
1259                         */
1260                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1261                 }
1262                 break;
1263         case ACB_ADAPTER_TYPE_B: {
1264                         /*
1265                         ** push inbound doorbell tell iop, driver data write ok
1266                         ** and wait reply on next hwinterrupt for next Qbuffer post
1267                         */
1268                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1269                 }
1270                 break;
1271         case ACB_ADAPTER_TYPE_C: {
1272                         /*
1273                         ** push inbound doorbell tell iop, driver data write ok
1274                         ** and wait reply on next hwinterrupt for next Qbuffer post
1275                         */
1276                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1277                 }
1278                 break;
1279         case ACB_ADAPTER_TYPE_D: {
1280                         /*
1281                         ** push inbound doorbell tell iop, driver data write ok
1282                         ** and wait reply on next hwinterrupt for next Qbuffer post
1283                         */
1284                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1285                 }
1286                 break;
1287         }
1288 }
1289 /*
1290 ************************************************************************
1291 ************************************************************************
1292 */
1293 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1294 {
1295         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1296         CHIP_REG_WRITE32(HBA_MessageUnit,
1297         0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1298         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1299                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1300                         , acb->pci_unit);
1301         }
1302 }
1303 /*
1304 ************************************************************************
1305 ************************************************************************
1306 */
1307 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1308 {
1309         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1310         CHIP_REG_WRITE32(HBB_DOORBELL,
1311         0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1312         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1313                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1314                         , acb->pci_unit);
1315         }
1316 }
1317 /*
1318 ************************************************************************
1319 ************************************************************************
1320 */
1321 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1322 {
1323         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1324         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1325         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1326         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1327                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1328         }
1329 }
1330 /*
1331 ************************************************************************
1332 ************************************************************************
1333 */
1334 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1335 {
1336         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1337         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1338         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1339                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1340         }
1341 }
1342 /*
1343 ************************************************************************
1344 ************************************************************************
1345 */
1346 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1347 {
1348         switch (acb->adapter_type) {
1349         case ACB_ADAPTER_TYPE_A: {
1350                         arcmsr_stop_hba_bgrb(acb);
1351                 }
1352                 break;
1353         case ACB_ADAPTER_TYPE_B: {
1354                         arcmsr_stop_hbb_bgrb(acb);
1355                 }
1356                 break;
1357         case ACB_ADAPTER_TYPE_C: {
1358                         arcmsr_stop_hbc_bgrb(acb);
1359                 }
1360                 break;
1361         case ACB_ADAPTER_TYPE_D: {
1362                         arcmsr_stop_hbd_bgrb(acb);
1363                 }
1364                 break;
1365         }
1366 }
1367 /*
1368 ************************************************************************
1369 ************************************************************************
1370 */
1371 static void arcmsr_poll(struct cam_sim *psim)
1372 {
1373         struct AdapterControlBlock *acb;
1374         int     mutex;
1375
1376         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1377         mutex = mtx_owned(&acb->isr_lock);
1378         if( mutex == 0 )
1379                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1380         arcmsr_interrupt(acb);
1381         if( mutex == 0 )
1382                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1383 }
1384 /*
1385 **************************************************************************
1386 **************************************************************************
1387 */
1388 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1389     struct QBUFFER *prbuffer) {
1390
1391         u_int8_t *pQbuffer;
1392         u_int8_t *buf1 = 0;
1393         u_int32_t *iop_data, *buf2 = 0;
1394         u_int32_t iop_len, data_len;
1395
1396         iop_data = (u_int32_t *)prbuffer->data;
1397         iop_len = (u_int32_t)prbuffer->data_len;
1398         if ( iop_len > 0 )
1399         {
1400                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1401                 buf2 = (u_int32_t *)buf1;
1402                 if( buf1 == NULL)
1403                         return (0);
1404                 data_len = iop_len;
1405                 while(data_len >= 4)
1406                 {
1407                         *buf2++ = *iop_data++;
1408                         data_len -= 4;
1409                 }
1410                 if(data_len)
1411                         *buf2 = *iop_data;
1412                 buf2 = (u_int32_t *)buf1;
1413         }
1414         while (iop_len > 0) {
1415                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1416                 *pQbuffer = *buf1;
1417                 acb->rqbuf_lastindex++;
1418                 /* if last, index number set it to 0 */
1419                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1420                 buf1++;
1421                 iop_len--;
1422         }
1423         if(buf2)
1424                 free( (u_int8_t *)buf2, M_DEVBUF);
1425         /* let IOP know data has been read */
1426         arcmsr_iop_message_read(acb);
1427         return (1);
1428 }
1429 /*
1430 **************************************************************************
1431 **************************************************************************
1432 */
1433 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1434     struct QBUFFER *prbuffer) {
1435
1436         u_int8_t *pQbuffer;
1437         u_int8_t *iop_data;
1438         u_int32_t iop_len;
1439
1440         if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1441                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1442         }
1443         iop_data = (u_int8_t *)prbuffer->data;
1444         iop_len = (u_int32_t)prbuffer->data_len;
1445         while (iop_len > 0) {
1446                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1447                 *pQbuffer = *iop_data;
1448                 acb->rqbuf_lastindex++;
1449                 /* if last, index number set it to 0 */
1450                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1451                 iop_data++;
1452                 iop_len--;
1453         }
1454         /* let IOP know data has been read */
1455         arcmsr_iop_message_read(acb);
1456         return (1);
1457 }
1458 /*
1459 **************************************************************************
1460 **************************************************************************
1461 */
1462 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1463 {
1464         struct QBUFFER *prbuffer;
1465         int my_empty_len;
1466
1467         /*check this iop data if overflow my rqbuffer*/
1468         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1469         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1470         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1471             (ARCMSR_MAX_QBUFFER-1);
1472         if(my_empty_len >= prbuffer->data_len) {
1473                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1474                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1475         } else {
1476                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1477         }
1478         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1479 }
1480 /*
1481 **********************************************************************
1482 **********************************************************************
1483 */
1484 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1485 {
1486         u_int8_t *pQbuffer;
1487         struct QBUFFER *pwbuffer;
1488         u_int8_t *buf1 = 0;
1489         u_int32_t *iop_data, *buf2 = 0;
1490         u_int32_t allxfer_len = 0, data_len;
1491
1492         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1493                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1494                 buf2 = (u_int32_t *)buf1;
1495                 if( buf1 == NULL)
1496                         return;
1497
1498                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1499                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1500                 iop_data = (u_int32_t *)pwbuffer->data;
1501                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1502                         && (allxfer_len < 124)) {
1503                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1504                         *buf1 = *pQbuffer;
1505                         acb->wqbuf_firstindex++;
1506                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1507                         buf1++;
1508                         allxfer_len++;
1509                 }
1510                 pwbuffer->data_len = allxfer_len;
1511                 data_len = allxfer_len;
1512                 buf1 = (u_int8_t *)buf2;
1513                 while(data_len >= 4)
1514                 {
1515                         *iop_data++ = *buf2++;
1516                         data_len -= 4;
1517                 }
1518                 if(data_len)
1519                         *iop_data = *buf2;
1520                 free( buf1, M_DEVBUF);
1521                 arcmsr_iop_message_wrote(acb);
1522         }
1523 }
1524 /*
1525 **********************************************************************
1526 **********************************************************************
1527 */
1528 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1529 {
1530         u_int8_t *pQbuffer;
1531         struct QBUFFER *pwbuffer;
1532         u_int8_t *iop_data;
1533         int32_t allxfer_len=0;
1534
1535         if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1536                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1537                 return;
1538         }
1539         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1540                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1541                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1542                 iop_data = (u_int8_t *)pwbuffer->data;
1543                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1544                         && (allxfer_len < 124)) {
1545                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1546                         *iop_data = *pQbuffer;
1547                         acb->wqbuf_firstindex++;
1548                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1549                         iop_data++;
1550                         allxfer_len++;
1551                 }
1552                 pwbuffer->data_len = allxfer_len;
1553                 arcmsr_iop_message_wrote(acb);
1554         }
1555 }
1556 /*
1557 **************************************************************************
1558 **************************************************************************
1559 */
1560 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1561 {
1562         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1563         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1564         /*
1565         *****************************************************************
1566         **   check if there are any mail packages from user space program
1567         **   in my post bag, now is the time to send them into Areca's firmware
1568         *****************************************************************
1569         */
1570         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1571                 arcmsr_Write_data_2iop_wqbuffer(acb);
1572         }
1573         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1574                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1575         }
1576         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1577 }
1578 /*
1579 **************************************************************************
1580 **************************************************************************
1581 */
1582 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1583 {
1584 /*
1585         if (ccb->ccb_h.status != CAM_REQ_CMP)
1586                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1587                     "failure status=%x\n", ccb->ccb_h.target_id,
1588                     ccb->ccb_h.target_lun, ccb->ccb_h.status);
1589         else
1590                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1591 */
1592         xpt_free_path(ccb->ccb_h.path);
1593         xpt_free_ccb(ccb);
1594 }
1595
1596 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1597 {
1598         struct cam_path     *path;
1599         union ccb           *ccb;
1600
1601         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1602                 return;
1603         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun)
1604             != CAM_REQ_CMP)
1605         {
1606                 xpt_free_ccb(ccb);
1607                 return;
1608         }
1609 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1610         bzero(ccb, sizeof(union ccb));
1611         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1612         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1613         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1614         ccb->crcn.flags = CAM_FLAG_NONE;
1615         xpt_action(ccb);
1616 }
1617
1618
1619 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1620 {
1621         struct CommandControlBlock *srb;
1622         u_int32_t intmask_org;
1623         int i;
1624
1625         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1626         /* disable all outbound interrupts */
1627         intmask_org = arcmsr_disable_allintr(acb);
1628         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1629         {
1630                 srb = acb->psrb_pool[i];
1631                 if (srb->srb_state == ARCMSR_SRB_START)
1632                 {
1633                 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1634             {
1635                         srb->srb_state = ARCMSR_SRB_ABORTED;
1636                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1637                         arcmsr_srb_complete(srb, 1);
1638                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1639                 }
1640                 }
1641         }
1642         /* enable outbound Post Queue, outbound doorbell Interrupt */
1643         arcmsr_enable_allintr(acb, intmask_org);
1644         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1645 }
1646 /*
1647 **************************************************************************
1648 **************************************************************************
1649 */
1650 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1651         u_int32_t       devicemap;
1652         u_int32_t       target, lun;
1653     u_int32_t   deviceMapCurrent[4]={0};
1654     u_int8_t    *pDevMap;
1655
1656         switch (acb->adapter_type) {
1657         case ACB_ADAPTER_TYPE_A:
1658                         devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1659                         for (target = 0; target < 4; target++)
1660                         {
1661                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1662                 devicemap += 4;
1663                         }
1664                         break;
1665
1666         case ACB_ADAPTER_TYPE_B:
1667                         devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1668                         for (target = 0; target < 4; target++)
1669                         {
1670                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1671                 devicemap += 4;
1672                         }
1673                         break;
1674
1675         case ACB_ADAPTER_TYPE_C:
1676                         devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1677                         for (target = 0; target < 4; target++)
1678                         {
1679                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1680                 devicemap += 4;
1681                         }
1682                         break;
1683         case ACB_ADAPTER_TYPE_D:
1684                         devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1685                         for (target = 0; target < 4; target++)
1686                         {
1687                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1688                 devicemap += 4;
1689                         }
1690                         break;
1691         }
1692
1693                 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1694                 {
1695                         acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1696                 }
1697                 /*
1698                 ** adapter posted CONFIG message
1699                 ** copy the new map, note if there are differences with the current map
1700                 */
1701                 pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1702                 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1703                 {
1704                         if (*pDevMap != acb->device_map[target])
1705                         {
1706                 u_int8_t difference, bit_check;
1707
1708                 difference = *pDevMap ^ acb->device_map[target];
1709                 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1710                 {
1711                     bit_check = (1 << lun);                                             /*check bit from 0....31*/
1712                     if(difference & bit_check)
1713                     {
1714                         if(acb->device_map[target] & bit_check)
1715                         {/* unit departed */
1716                                                         printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1717                                                         arcmsr_abort_dr_ccbs(acb, target, lun);
1718                                 arcmsr_rescan_lun(acb, target, lun);
1719                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1720                         }
1721                         else
1722                         {/* unit arrived */
1723                                                         printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1724                                 arcmsr_rescan_lun(acb, target, lun);
1725                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1726                         }
1727                     }
1728                 }
1729 /*                              printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1730                                 acb->device_map[target] = *pDevMap;
1731                         }
1732                         pDevMap++;
1733                 }
1734 }
1735 /*
1736 **************************************************************************
1737 **************************************************************************
1738 */
1739 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1740         u_int32_t outbound_message;
1741
1742         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1743         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1744         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1745                 arcmsr_dr_handle( acb );
1746 }
1747 /*
1748 **************************************************************************
1749 **************************************************************************
1750 */
1751 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1752         u_int32_t outbound_message;
1753
1754         /* clear interrupts */
1755         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1756         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1757         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1758                 arcmsr_dr_handle( acb );
1759 }
1760 /*
1761 **************************************************************************
1762 **************************************************************************
1763 */
1764 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1765         u_int32_t outbound_message;
1766
1767         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1768         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1769         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1770                 arcmsr_dr_handle( acb );
1771 }
1772 /*
1773 **************************************************************************
1774 **************************************************************************
1775 */
1776 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1777         u_int32_t outbound_message;
1778
1779         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1780         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1781         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1782                 arcmsr_dr_handle( acb );
1783 }
1784 /*
1785 **************************************************************************
1786 **************************************************************************
1787 */
1788 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1789 {
1790         u_int32_t outbound_doorbell;
1791
1792         /*
1793         *******************************************************************
1794         **  Maybe here we need to check wrqbuffer_lock is lock or not
1795         **  DOORBELL: din! don!
1796         **  check if there are any mail need to pack from firmware
1797         *******************************************************************
1798         */
1799         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit,
1800         0, outbound_doorbell);
1801         CHIP_REG_WRITE32(HBA_MessageUnit,
1802         0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
1803         if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1804                 arcmsr_iop2drv_data_wrote_handle(acb);
1805         }
1806         if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1807                 arcmsr_iop2drv_data_read_handle(acb);
1808         }
1809 }
1810 /*
1811 **************************************************************************
1812 **************************************************************************
1813 */
1814 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1815 {
1816         u_int32_t outbound_doorbell;
1817
1818         /*
1819         *******************************************************************
1820         **  Maybe here we need to check wrqbuffer_lock is lock or not
1821         **  DOORBELL: din! don!
1822         **  check if there are any mail need to pack from firmware
1823         *******************************************************************
1824         */
1825         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1826         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
1827         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1828                 arcmsr_iop2drv_data_wrote_handle(acb);
1829         }
1830         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1831                 arcmsr_iop2drv_data_read_handle(acb);
1832         }
1833         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1834                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1835         }
1836 }
1837 /*
1838 **************************************************************************
1839 **************************************************************************
1840 */
1841 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1842 {
1843         u_int32_t outbound_Doorbell;
1844
1845         /*
1846         *******************************************************************
1847         **  Maybe here we need to check wrqbuffer_lock is lock or not
1848         **  DOORBELL: din! don!
1849         **  check if there are any mail need to pack from firmware
1850         *******************************************************************
1851         */
1852         outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1853         if(outbound_Doorbell)
1854                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1855         while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1856                 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1857                         arcmsr_iop2drv_data_wrote_handle(acb);
1858                 }
1859                 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1860                         arcmsr_iop2drv_data_read_handle(acb);
1861                 }
1862                 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1863                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1864                 }
1865                 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1866                 if(outbound_Doorbell)
1867                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1868         }
1869 }
1870 /*
1871 **************************************************************************
1872 **************************************************************************
1873 */
1874 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1875 {
1876         u_int32_t flag_srb;
1877         u_int16_t error;
1878
1879         /*
1880         *****************************************************************************
1881         **               areca cdb command done
1882         *****************************************************************************
1883         */
1884         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1885                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1886         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
1887                 0, outbound_queueport)) != 0xFFFFFFFF) {
1888                 /* check if command done with no error*/
1889         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
1890                 arcmsr_drain_donequeue(acb, flag_srb, error);
1891         }       /*drain reply FIFO*/
1892 }
1893 /*
1894 **************************************************************************
1895 **************************************************************************
1896 */
1897 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1898 {
1899         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1900         u_int32_t flag_srb;
1901         int index;
1902         u_int16_t error;
1903
1904         /*
1905         *****************************************************************************
1906         **               areca cdb command done
1907         *****************************************************************************
1908         */
1909         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1910                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1911         index = phbbmu->doneq_index;
1912         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
1913                 phbbmu->done_qbuffer[index] = 0;
1914                 index++;
1915                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1916                 phbbmu->doneq_index = index;
1917                 /* check if command done with no error*/
1918         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1919                 arcmsr_drain_donequeue(acb, flag_srb, error);
1920         }       /*drain reply FIFO*/
1921 }
1922 /*
1923 **************************************************************************
1924 **************************************************************************
1925 */
1926 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1927 {
1928         u_int32_t flag_srb,throttling = 0;
1929         u_int16_t error;
1930
1931         /*
1932         *****************************************************************************
1933         **               areca cdb command done
1934         *****************************************************************************
1935         */
1936         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1937
1938         while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1939
1940                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1941                 /* check if command done with no error*/
1942         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1943                 arcmsr_drain_donequeue(acb, flag_srb, error);
1944         throttling++;
1945         if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1946             CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1947                         throttling = 0;
1948         }
1949         }       /*drain reply FIFO*/
1950 }
1951 /*
1952 **********************************************************************
1953 **
1954 **********************************************************************
1955 */
1956 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1957 {
1958         uint16_t doneq_index, index_stripped;
1959
1960         doneq_index = phbdmu->doneq_index;
1961         if (doneq_index & 0x4000) {
1962                 index_stripped = doneq_index & 0xFF;
1963                 index_stripped += 1;
1964                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1965                 phbdmu->doneq_index = index_stripped ?
1966                     (index_stripped | 0x4000) : index_stripped;
1967         } else {
1968                 index_stripped = doneq_index;
1969                 index_stripped += 1;
1970                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1971                 phbdmu->doneq_index = index_stripped ?
1972                     index_stripped : (index_stripped | 0x4000);
1973         }
1974         return (phbdmu->doneq_index);
1975 }
1976 /*
1977 **************************************************************************
1978 **************************************************************************
1979 */
1980 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
1981 {
1982         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1983         u_int32_t outbound_write_pointer;
1984         u_int32_t addressLow;
1985         uint16_t doneq_index;
1986         u_int16_t error;
1987         /*
1988         *****************************************************************************
1989         **               areca cdb command done
1990         *****************************************************************************
1991         */
1992         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
1993             ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
1994             return;
1995         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1996                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1997         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
1998         doneq_index = phbdmu->doneq_index;
1999         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2000                 doneq_index = arcmsr_get_doneq_index(phbdmu);
2001                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2002                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2003                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2004                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2005                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2006         }
2007         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2008         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2009 }
2010 /*
2011 **********************************************************************
2012 **********************************************************************
2013 */
2014 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2015 {
2016         u_int32_t outbound_intStatus;
2017         /*
2018         *********************************************
2019         **   check outbound intstatus
2020         *********************************************
2021         */
2022         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2023         if(!outbound_intStatus) {
2024                 /*it must be share irq*/
2025                 return;
2026         }
2027         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2028         /* MU doorbell interrupts*/
2029         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2030                 arcmsr_hba_doorbell_isr(acb);
2031         }
2032         /* MU post queue interrupts*/
2033         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2034                 arcmsr_hba_postqueue_isr(acb);
2035         }
2036         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2037                 arcmsr_hba_message_isr(acb);
2038         }
2039 }
2040 /*
2041 **********************************************************************
2042 **********************************************************************
2043 */
2044 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2045 {
2046         u_int32_t outbound_doorbell;
2047         /*
2048         *********************************************
2049         **   check outbound intstatus
2050         *********************************************
2051         */
2052         outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
2053         if(!outbound_doorbell) {
2054                 /*it must be share irq*/
2055                 return;
2056         }
2057         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2058         CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell);
2059         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2060         /* MU ioctl transfer doorbell interrupts*/
2061         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2062                 arcmsr_iop2drv_data_wrote_handle(acb);
2063         }
2064         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2065                 arcmsr_iop2drv_data_read_handle(acb);
2066         }
2067         /* MU post queue interrupts*/
2068         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2069                 arcmsr_hbb_postqueue_isr(acb);
2070         }
2071         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2072                 arcmsr_hbb_message_isr(acb);
2073         }
2074 }
2075 /*
2076 **********************************************************************
2077 **********************************************************************
2078 */
2079 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2080 {
2081         u_int32_t host_interrupt_status;
2082         /*
2083         *********************************************
2084         **   check outbound intstatus
2085         *********************************************
2086         */
2087         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2088         if(!host_interrupt_status) {
2089                 /*it must be share irq*/
2090                 return;
2091         }
2092         /* MU doorbell interrupts*/
2093         if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2094                 arcmsr_hbc_doorbell_isr(acb);
2095         }
2096         /* MU post queue interrupts*/
2097         if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2098                 arcmsr_hbc_postqueue_isr(acb);
2099         }
2100 }
2101 /*
2102 **********************************************************************
2103 **********************************************************************
2104 */
2105 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2106 {
2107         u_int32_t host_interrupt_status;
2108         u_int32_t intmask_org;
2109         /*
2110         *********************************************
2111         **   check outbound intstatus
2112         *********************************************
2113         */
2114         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2115         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2116                 /*it must be share irq*/
2117                 return;
2118         }
2119         /* disable outbound interrupt */
2120         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2121         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2122         /* MU doorbell interrupts*/
2123         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2124                 arcmsr_hbd_doorbell_isr(acb);
2125         }
2126         /* MU post queue interrupts*/
2127         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2128                 arcmsr_hbd_postqueue_isr(acb);
2129         }
2130         /* enable all outbound interrupt */
2131         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2132 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2133 }
2134 /*
2135 ******************************************************************************
2136 ******************************************************************************
2137 */
2138 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2139 {
2140         switch (acb->adapter_type) {
2141         case ACB_ADAPTER_TYPE_A:
2142                 arcmsr_handle_hba_isr(acb);
2143                 break;
2144         case ACB_ADAPTER_TYPE_B:
2145                 arcmsr_handle_hbb_isr(acb);
2146                 break;
2147         case ACB_ADAPTER_TYPE_C:
2148                 arcmsr_handle_hbc_isr(acb);
2149                 break;
2150         case ACB_ADAPTER_TYPE_D:
2151                 arcmsr_handle_hbd_isr(acb);
2152                 break;
2153         default:
2154                 printf("arcmsr%d: interrupt service,"
2155                 " unknow adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2156                 break;
2157         }
2158 }
2159 /*
2160 **********************************************************************
2161 **********************************************************************
2162 */
2163 static void arcmsr_intr_handler(void *arg)
2164 {
2165         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2166
2167         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2168         arcmsr_interrupt(acb);
2169         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2170 }
2171 /*
2172 ******************************************************************************
2173 ******************************************************************************
2174 */
2175 static void     arcmsr_polling_devmap(void *arg)
2176 {
2177         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2178         switch (acb->adapter_type) {
2179         case ACB_ADAPTER_TYPE_A:
2180                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2181                 break;
2182
2183         case ACB_ADAPTER_TYPE_B:
2184                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2185                 break;
2186
2187         case ACB_ADAPTER_TYPE_C:
2188                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2189                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2190                 break;
2191
2192         case ACB_ADAPTER_TYPE_D:
2193                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2194                 break;
2195         }
2196
2197         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2198         {
2199                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2200         }
2201 }
2202
2203 /*
2204 *******************************************************************************
2205 **
2206 *******************************************************************************
2207 */
2208 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2209 {
2210         u_int32_t intmask_org;
2211
2212         if(acb != NULL) {
2213                 /* stop adapter background rebuild */
2214                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2215                         intmask_org = arcmsr_disable_allintr(acb);
2216                         arcmsr_stop_adapter_bgrb(acb);
2217                         arcmsr_flush_adapter_cache(acb);
2218                         arcmsr_enable_allintr(acb, intmask_org);
2219                 }
2220         }
2221 }
2222 /*
2223 ***********************************************************************
2224 **
2225 ************************************************************************
2226 */
2227 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2228 {
2229         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2230         u_int32_t retvalue = EINVAL;
2231
2232         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2233         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2234                 return retvalue;
2235         }
2236         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2237         switch(ioctl_cmd) {
2238         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2239                         u_int8_t *pQbuffer;
2240                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2241                         u_int32_t allxfer_len=0;
2242
2243                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2244                                 && (allxfer_len < 1031)) {
2245                                 /*copy READ QBUFFER to srb*/
2246                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2247                                 *ptmpQbuffer = *pQbuffer;
2248                                 acb->rqbuf_firstindex++;
2249                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2250                                 /*if last index number set it to 0 */
2251                                 ptmpQbuffer++;
2252                                 allxfer_len++;
2253                         }
2254                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2255                                 struct QBUFFER *prbuffer;
2256
2257                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2258                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2259                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2260                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2261                         }
2262                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2263                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2264                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2265                 }
2266                 break;
2267         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2268                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2269                         u_int8_t *pQbuffer;
2270                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2271
2272                         user_len = pcmdmessagefld->cmdmessage.Length;
2273                         /*check if data xfer length of this request will overflow my array qbuffer */
2274                         wqbuf_lastindex = acb->wqbuf_lastindex;
2275                         wqbuf_firstindex = acb->wqbuf_firstindex;
2276                         if(wqbuf_lastindex != wqbuf_firstindex) {
2277                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2278                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2279                         } else {
2280                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2281                                     (ARCMSR_MAX_QBUFFER - 1);
2282                                 if(my_empty_len >= user_len) {
2283                                         while(user_len > 0) {
2284                                                 /*copy srb data to wqbuffer*/
2285                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2286                                                 *pQbuffer = *ptmpuserbuffer;
2287                                                 acb->wqbuf_lastindex++;
2288                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2289                                                 /*if last index number set it to 0 */
2290                                                 ptmpuserbuffer++;
2291                                                 user_len--;
2292                                         }
2293                                         /*post fist Qbuffer*/
2294                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2295                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2296                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2297                                         }
2298                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2299                                 } else {
2300                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2301                                 }
2302                         }
2303                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2304                 }
2305                 break;
2306         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2307                         u_int8_t *pQbuffer = acb->rqbuffer;
2308
2309                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2310                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2311                                 arcmsr_iop_message_read(acb);
2312                                 /*signature, let IOP know data has been readed */
2313                         }
2314                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2315                         acb->rqbuf_firstindex = 0;
2316                         acb->rqbuf_lastindex = 0;
2317                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2318                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2319                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2320                 }
2321                 break;
2322         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2323                 {
2324                         u_int8_t *pQbuffer = acb->wqbuffer;
2325
2326                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2327                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2328                 arcmsr_iop_message_read(acb);
2329                                 /*signature, let IOP know data has been readed */
2330                         }
2331                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2332                         acb->wqbuf_firstindex = 0;
2333                         acb->wqbuf_lastindex = 0;
2334                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2335                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2336                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2337                 }
2338                 break;
2339         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2340                         u_int8_t *pQbuffer;
2341
2342                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2343                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2344                 arcmsr_iop_message_read(acb);
2345                                 /*signature, let IOP know data has been readed */
2346                         }
2347                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2348                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2349                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2350                         acb->rqbuf_firstindex = 0;
2351                         acb->rqbuf_lastindex = 0;
2352                         acb->wqbuf_firstindex = 0;
2353                         acb->wqbuf_lastindex = 0;
2354                         pQbuffer = acb->rqbuffer;
2355                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2356                         pQbuffer = acb->wqbuffer;
2357                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2358                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2359                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2360                 }
2361                 break;
2362         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2363                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2364                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2365                 }
2366                 break;
2367         case ARCMSR_MESSAGE_SAY_HELLO: {
2368                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2369                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2370
2371                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2372                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2373                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2374                                 return ENOIOCTL;
2375                         }
2376                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2377                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2378                 }
2379                 break;
2380         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2381                         arcmsr_iop_parking(acb);
2382                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2383                 }
2384                 break;
2385         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2386                         arcmsr_flush_adapter_cache(acb);
2387                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2388                 }
2389                 break;
2390         }
2391         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2392         return (retvalue);
2393 }
2394 /*
2395 **************************************************************************
2396 **************************************************************************
2397 */
2398 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2399 {
2400         struct AdapterControlBlock      *acb;
2401
2402         acb = srb->acb;
2403         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2404         srb->srb_state = ARCMSR_SRB_DONE;
2405         srb->srb_flags = 0;
2406         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2407         acb->workingsrb_doneindex++;
2408         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2409         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2410 }
2411 /*
2412 **************************************************************************
2413 **************************************************************************
2414 */
2415 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2416 {
2417         struct CommandControlBlock *srb = NULL;
2418         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2419
2420         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2421         workingsrb_doneindex = acb->workingsrb_doneindex;
2422         workingsrb_startindex = acb->workingsrb_startindex;
2423         srb = acb->srbworkingQ[workingsrb_startindex];
2424         workingsrb_startindex++;
2425         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2426         if(workingsrb_doneindex != workingsrb_startindex) {
2427                 acb->workingsrb_startindex = workingsrb_startindex;
2428         } else {
2429                 srb = NULL;
2430         }
2431         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2432         return(srb);
2433 }
2434 /*
2435 **************************************************************************
2436 **************************************************************************
2437 */
2438 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2439 {
2440         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2441         int retvalue = 0, transfer_len = 0;
2442         char *buffer;
2443         u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
2444                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
2445                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8  |
2446                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
2447                                         /* 4 bytes: Areca io control code */
2448         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2449                 buffer = pccb->csio.data_ptr;
2450                 transfer_len = pccb->csio.dxfer_len;
2451         } else {
2452                 retvalue = ARCMSR_MESSAGE_FAIL;
2453                 goto message_out;
2454         }
2455         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2456                 retvalue = ARCMSR_MESSAGE_FAIL;
2457                 goto message_out;
2458         }
2459         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2460         switch(controlcode) {
2461         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2462                         u_int8_t *pQbuffer;
2463                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2464                         int32_t allxfer_len = 0;
2465
2466                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2467                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2468                                 && (allxfer_len < 1031)) {
2469                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2470                                 *ptmpQbuffer = *pQbuffer;
2471                                 acb->rqbuf_firstindex++;
2472                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2473                                 ptmpQbuffer++;
2474                                 allxfer_len++;
2475                         }
2476                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2477                                 struct QBUFFER  *prbuffer;
2478
2479                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2480                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2481                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2482                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2483                         }
2484                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2485                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2486                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2487                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2488                 }
2489                 break;
2490         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2491                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2492                         u_int8_t *pQbuffer;
2493                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2494
2495                         user_len = pcmdmessagefld->cmdmessage.Length;
2496                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2497                         wqbuf_lastindex = acb->wqbuf_lastindex;
2498                         wqbuf_firstindex = acb->wqbuf_firstindex;
2499                         if (wqbuf_lastindex != wqbuf_firstindex) {
2500                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2501                                 /* has error report sensedata */
2502                             if(pccb->csio.sense_len) {
2503                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2504                                 /* Valid,ErrorCode */
2505                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2506                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2507                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2508                                 /* AdditionalSenseLength */
2509                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2510                                 /* AdditionalSenseCode */
2511                                 }
2512                                 retvalue = ARCMSR_MESSAGE_FAIL;
2513                         } else {
2514                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2515                                                 &(ARCMSR_MAX_QBUFFER - 1);
2516                                 if (my_empty_len >= user_len) {
2517                                         while (user_len > 0) {
2518                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2519                                                 *pQbuffer = *ptmpuserbuffer;
2520                                                 acb->wqbuf_lastindex++;
2521                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2522                                                 ptmpuserbuffer++;
2523                                                 user_len--;
2524                                         }
2525                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2526                                                 acb->acb_flags &=
2527                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2528                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2529                                         }
2530                                 } else {
2531                                         /* has error report sensedata */
2532                                         if(pccb->csio.sense_len) {
2533                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2534                                         /* Valid,ErrorCode */
2535                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2536                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2537                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2538                                         /* AdditionalSenseLength */
2539                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2540                                         /* AdditionalSenseCode */
2541                                         }
2542                                         retvalue = ARCMSR_MESSAGE_FAIL;
2543                                 }
2544                         }
2545                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2546                 }
2547                 break;
2548         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2549                         u_int8_t *pQbuffer = acb->rqbuffer;
2550
2551                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2552                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2553                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2554                                 arcmsr_iop_message_read(acb);
2555                         }
2556                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2557                         acb->rqbuf_firstindex = 0;
2558                         acb->rqbuf_lastindex = 0;
2559                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2560                         pcmdmessagefld->cmdmessage.ReturnCode =
2561                             ARCMSR_MESSAGE_RETURNCODE_OK;
2562                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2563                 }
2564                 break;
2565         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2566                         u_int8_t *pQbuffer = acb->wqbuffer;
2567
2568                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2569                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2570                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2571                                 arcmsr_iop_message_read(acb);
2572                         }
2573                         acb->acb_flags |=
2574                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2575                                         ACB_F_MESSAGE_WQBUFFER_READ);
2576                         acb->wqbuf_firstindex = 0;
2577                         acb->wqbuf_lastindex = 0;
2578                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2579                         pcmdmessagefld->cmdmessage.ReturnCode =
2580                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2581                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2582                 }
2583                 break;
2584         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2585                         u_int8_t *pQbuffer;
2586
2587                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2588                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2589                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2590                                 arcmsr_iop_message_read(acb);
2591                         }
2592                         acb->acb_flags |=
2593                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2594                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2595                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2596                         acb->rqbuf_firstindex = 0;
2597                         acb->rqbuf_lastindex = 0;
2598                         acb->wqbuf_firstindex = 0;
2599                         acb->wqbuf_lastindex = 0;
2600                         pQbuffer = acb->rqbuffer;
2601                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2602                         pQbuffer = acb->wqbuffer;
2603                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2604                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2605                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2606                 }
2607                 break;
2608         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2609                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2610                 }
2611                 break;
2612         case ARCMSR_MESSAGE_SAY_HELLO: {
2613                         int8_t *hello_string = "Hello! I am ARCMSR";
2614
2615                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2616                                 , (int16_t)strlen(hello_string));
2617                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2618                 }
2619                 break;
2620         case ARCMSR_MESSAGE_SAY_GOODBYE:
2621                 arcmsr_iop_parking(acb);
2622                 break;
2623         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2624                 arcmsr_flush_adapter_cache(acb);
2625                 break;
2626         default:
2627                 retvalue = ARCMSR_MESSAGE_FAIL;
2628         }
2629 message_out:
2630         return (retvalue);
2631 }
2632 /*
2633 *********************************************************************
2634 *********************************************************************
2635 */
2636 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2637 {
2638         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2639         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2640         union ccb *pccb;
2641         int target, lun;
2642
2643         pccb = srb->pccb;
2644         target = pccb->ccb_h.target_id;
2645         lun = pccb->ccb_h.target_lun;
2646         acb->pktRequestCount++;
2647         if(error != 0) {
2648                 if(error != EFBIG) {
2649                         printf("arcmsr%d: unexpected error %x"
2650                                 " returned from 'bus_dmamap_load' \n"
2651                                 , acb->pci_unit, error);
2652                 }
2653                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2654                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2655                 }
2656                 arcmsr_srb_complete(srb, 0);
2657                 return;
2658         }
2659         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2660                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2661                 arcmsr_srb_complete(srb, 0);
2662                 return;
2663         }
2664         if(acb->acb_flags & ACB_F_BUS_RESET) {
2665                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2666                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2667                 arcmsr_srb_complete(srb, 0);
2668                 return;
2669         }
2670         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2671                 u_int8_t block_cmd, cmd;
2672
2673                 cmd = pccb->csio.cdb_io.cdb_bytes[0];
2674                 block_cmd = cmd & 0x0f;
2675                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2676                         printf("arcmsr%d:block 'read/write' command "
2677                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2678                                 , acb->pci_unit, cmd, target, lun);
2679                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2680                         arcmsr_srb_complete(srb, 0);
2681                         return;
2682                 }
2683         }
2684         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2685                 if(nseg != 0) {
2686                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2687                 }
2688                 arcmsr_srb_complete(srb, 0);
2689                 return;
2690         }
2691         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2692                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2693                 {
2694                         xpt_freeze_simq(acb->psim, 1);
2695                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2696                 }
2697                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2698                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2699                 arcmsr_srb_complete(srb, 0);
2700                 return;
2701         }
2702         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2703         arcmsr_build_srb(srb, dm_segs, nseg);
2704         arcmsr_post_srb(acb, srb);
2705         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2706         {
2707                 arcmsr_callout_init(&srb->ccb_callout);
2708                 callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb);
2709                 srb->srb_flags |= SRB_FLAG_TIMER_START;
2710         }
2711 }
2712 /*
2713 *****************************************************************************************
2714 *****************************************************************************************
2715 */
2716 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2717 {
2718         struct CommandControlBlock *srb;
2719         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2720         u_int32_t intmask_org;
2721         int i = 0;
2722
2723         acb->num_aborts++;
2724         /*
2725         ***************************************************************************
2726         ** It is the upper layer do abort command this lock just prior to calling us.
2727         ** First determine if we currently own this command.
2728         ** Start by searching the device queue. If not found
2729         ** at all, and the system wanted us to just abort the
2730         ** command return success.
2731         ***************************************************************************
2732         */
2733         if(acb->srboutstandingcount != 0) {
2734                 /* disable all outbound interrupt */
2735                 intmask_org = arcmsr_disable_allintr(acb);
2736                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2737                         srb = acb->psrb_pool[i];
2738                         if(srb->srb_state == ARCMSR_SRB_START) {
2739                                 if(srb->pccb == abortccb) {
2740                                         srb->srb_state = ARCMSR_SRB_ABORTED;
2741                                         printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
2742                                                 "outstanding command \n"
2743                                                 , acb->pci_unit, abortccb->ccb_h.target_id
2744                                                 , abortccb->ccb_h.target_lun, srb);
2745                                         arcmsr_polling_srbdone(acb, srb);
2746                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
2747                                         arcmsr_enable_allintr(acb, intmask_org);
2748                                         return (TRUE);
2749                                 }
2750                         }
2751                 }
2752                 /* enable outbound Post Queue, outbound doorbell Interrupt */
2753                 arcmsr_enable_allintr(acb, intmask_org);
2754         }
2755         return(FALSE);
2756 }
2757 /*
2758 ****************************************************************************
2759 ****************************************************************************
2760 */
2761 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2762 {
2763         int retry = 0;
2764
2765         acb->num_resets++;
2766         acb->acb_flags |= ACB_F_BUS_RESET;
2767         while(acb->srboutstandingcount != 0 && retry < 400) {
2768                 arcmsr_interrupt(acb);
2769                 UDELAY(25000);
2770                 retry++;
2771         }
2772         arcmsr_iop_reset(acb);
2773         acb->acb_flags &= ~ACB_F_BUS_RESET;
2774 }
2775 /*
2776 **************************************************************************
2777 **************************************************************************
2778 */
2779 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2780                 union ccb *pccb)
2781 {
2782         if (pccb->ccb_h.target_lun) {
2783                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2784                 xpt_done(pccb);
2785                 return;
2786         }
2787         pccb->ccb_h.status |= CAM_REQ_CMP;
2788         switch (pccb->csio.cdb_io.cdb_bytes[0]) {
2789         case INQUIRY: {
2790                 unsigned char inqdata[36];
2791                 char *buffer = pccb->csio.data_ptr;
2792
2793                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
2794                 inqdata[1] = 0;                         /* rem media bit & Dev Type Modifier */
2795                 inqdata[2] = 0;                         /* ISO, ECMA, & ANSI versions */
2796                 inqdata[3] = 0;
2797                 inqdata[4] = 31;                        /* length of additional data */
2798                 inqdata[5] = 0;
2799                 inqdata[6] = 0;
2800                 inqdata[7] = 0;
2801                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
2802                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
2803                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2804                 memcpy(buffer, inqdata, sizeof(inqdata));
2805                 xpt_done(pccb);
2806         }
2807         break;
2808         case WRITE_BUFFER:
2809         case READ_BUFFER: {
2810                 if (arcmsr_iop_message_xfer(acb, pccb)) {
2811                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2812                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2813                 }
2814                 xpt_done(pccb);
2815         }
2816         break;
2817         default:
2818                 xpt_done(pccb);
2819         }
2820 }
2821 /*
2822 *********************************************************************
2823 *********************************************************************
2824 */
2825 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
2826 {
2827         struct AdapterControlBlock *acb;
2828
2829         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
2830         if(acb == NULL) {
2831                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2832                 xpt_done(pccb);
2833                 return;
2834         }
2835         switch (pccb->ccb_h.func_code) {
2836         case XPT_SCSI_IO: {
2837                         struct CommandControlBlock *srb;
2838                         int target = pccb->ccb_h.target_id;
2839                         int error;
2840
2841                         if(target == 16) {
2842                                 /* virtual device for iop message transfer */
2843                                 arcmsr_handle_virtual_command(acb, pccb);
2844                                 return;
2845                         }
2846                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
2847                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2848                                 xpt_done(pccb);
2849                                 return;
2850                         }
2851                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
2852                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
2853                         srb->pccb = pccb;
2854                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
2855                                 , srb->dm_segs_dmamap
2856                                 , pccb
2857                                 , arcmsr_execute_srb, srb, /*flags*/0);
2858                         if(error == EINPROGRESS) {
2859                                 xpt_freeze_simq(acb->psim, 1);
2860                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2861                         }
2862                         break;
2863                 }
2864         case XPT_TARGET_IO: {
2865                         /* target mode not yet support vendor specific commands. */
2866                         pccb->ccb_h.status |= CAM_REQ_CMP;
2867                         xpt_done(pccb);
2868                         break;
2869                 }
2870         case XPT_PATH_INQ: {
2871                         struct ccb_pathinq *cpi = &pccb->cpi;
2872
2873                         cpi->version_num = 1;
2874                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
2875                         cpi->target_sprt = 0;
2876                         cpi->hba_misc = 0;
2877                         cpi->hba_eng_cnt = 0;
2878                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
2879                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
2880                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2881                         cpi->bus_id = cam_sim_bus(psim);
2882                         strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2883                         strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2884                         strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2885                         cpi->unit_number = cam_sim_unit(psim);
2886                 #ifdef  CAM_NEW_TRAN_CODE
2887                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2888                                 cpi->base_transfer_speed = 600000;
2889                         else
2890                                 cpi->base_transfer_speed = 300000;
2891                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2892                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2893                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2894                         {
2895                                 cpi->transport = XPORT_SAS;
2896                                 cpi->transport_version = 0;
2897                                 cpi->protocol_version = SCSI_REV_SPC2;
2898                         }
2899                         else
2900                         {
2901                                 cpi->transport = XPORT_SPI;
2902                                 cpi->transport_version = 2;
2903                                 cpi->protocol_version = SCSI_REV_2;
2904                         }
2905                         cpi->protocol = PROTO_SCSI;
2906                 #endif
2907                         cpi->ccb_h.status |= CAM_REQ_CMP;
2908                         xpt_done(pccb);
2909                         break;
2910                 }
2911         case XPT_ABORT: {
2912                         union ccb *pabort_ccb;
2913
2914                         pabort_ccb = pccb->cab.abort_ccb;
2915                         switch (pabort_ccb->ccb_h.func_code) {
2916                         case XPT_ACCEPT_TARGET_IO:
2917                         case XPT_IMMED_NOTIFY:
2918                         case XPT_CONT_TARGET_IO:
2919                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2920                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2921                                         xpt_done(pabort_ccb);
2922                                         pccb->ccb_h.status |= CAM_REQ_CMP;
2923                                 } else {
2924                                         xpt_print_path(pabort_ccb->ccb_h.path);
2925                                         printf("Not found\n");
2926                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
2927                                 }
2928                                 break;
2929                         case XPT_SCSI_IO:
2930                                 pccb->ccb_h.status |= CAM_UA_ABORT;
2931                                 break;
2932                         default:
2933                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2934                                 break;
2935                         }
2936                         xpt_done(pccb);
2937                         break;
2938                 }
2939         case XPT_RESET_BUS:
2940         case XPT_RESET_DEV: {
2941                         u_int32_t     i;
2942
2943                         arcmsr_bus_reset(acb);
2944                         for (i=0; i < 500; i++) {
2945                                 DELAY(1000);
2946                         }
2947                         pccb->ccb_h.status |= CAM_REQ_CMP;
2948                         xpt_done(pccb);
2949                         break;
2950                 }
2951         case XPT_TERM_IO: {
2952                         pccb->ccb_h.status |= CAM_REQ_INVALID;
2953                         xpt_done(pccb);
2954                         break;
2955                 }
2956         case XPT_GET_TRAN_SETTINGS: {
2957                         struct ccb_trans_settings *cts;
2958
2959                         if(pccb->ccb_h.target_id == 16) {
2960                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2961                                 xpt_done(pccb);
2962                                 break;
2963                         }
2964                         cts = &pccb->cts;
2965                 #ifdef  CAM_NEW_TRAN_CODE
2966                         {
2967                                 struct ccb_trans_settings_scsi *scsi;
2968                                 struct ccb_trans_settings_spi *spi;
2969                                 struct ccb_trans_settings_sas *sas;
2970
2971                                 scsi = &cts->proto_specific.scsi;
2972                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2973                                 scsi->valid = CTS_SCSI_VALID_TQ;
2974                                 cts->protocol = PROTO_SCSI;
2975
2976                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2977                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2978                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
2979                                 {
2980                                         cts->protocol_version = SCSI_REV_SPC2;
2981                                         cts->transport_version = 0;
2982                                         cts->transport = XPORT_SAS;
2983                                         sas = &cts->xport_specific.sas;
2984                                         sas->valid = CTS_SAS_VALID_SPEED;
2985                                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2986                                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2987                                                 sas->bitrate = 600000;
2988                                         else if(acb->vendor_device_id == PCIDevVenIDARC1680)
2989                                                 sas->bitrate = 300000;
2990                                 }
2991                                 else
2992                                 {
2993                                         cts->protocol_version = SCSI_REV_2;
2994                                         cts->transport_version = 2;
2995                                         cts->transport = XPORT_SPI;
2996                                         spi = &cts->xport_specific.spi;
2997                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
2998                                         spi->sync_period = 2;
2999                                         spi->sync_offset = 32;
3000                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3001                                         spi->valid = CTS_SPI_VALID_DISC
3002                                                 | CTS_SPI_VALID_SYNC_RATE
3003                                                 | CTS_SPI_VALID_SYNC_OFFSET
3004                                                 | CTS_SPI_VALID_BUS_WIDTH;
3005                                 }
3006                         }
3007                 #else
3008                         {
3009                                 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3010                                 cts->sync_period = 2;
3011                                 cts->sync_offset = 32;
3012                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3013                                 cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3014                                 CCB_TRANS_SYNC_OFFSET_VALID |
3015                                 CCB_TRANS_BUS_WIDTH_VALID |
3016                                 CCB_TRANS_DISC_VALID |
3017                                 CCB_TRANS_TQ_VALID;
3018                         }
3019                 #endif
3020                         pccb->ccb_h.status |= CAM_REQ_CMP;
3021                         xpt_done(pccb);
3022                         break;
3023                 }
3024         case XPT_SET_TRAN_SETTINGS: {
3025                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3026                         xpt_done(pccb);
3027                         break;
3028                 }
3029         case XPT_CALC_GEOMETRY:
3030                         if(pccb->ccb_h.target_id == 16) {
3031                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3032                                 xpt_done(pccb);
3033                                 break;
3034                         }
3035 #if __FreeBSD_version >= 500000
3036                         cam_calc_geometry(&pccb->ccg, 1);
3037 #else
3038                         {
3039                         struct ccb_calc_geometry *ccg;
3040                         u_int32_t size_mb;
3041                         u_int32_t secs_per_cylinder;
3042
3043                         ccg = &pccb->ccg;
3044                         if (ccg->block_size == 0) {
3045                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3046                                 xpt_done(pccb);
3047                                 break;
3048                         }
3049                         if(((1024L * 1024L)/ccg->block_size) < 0) {
3050                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3051                                 xpt_done(pccb);
3052                                 break;
3053                         }
3054                         size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3055                         if(size_mb > 1024 ) {
3056                                 ccg->heads = 255;
3057                                 ccg->secs_per_track = 63;
3058                         } else {
3059                                 ccg->heads = 64;
3060                                 ccg->secs_per_track = 32;
3061                         }
3062                         secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3063                         ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3064                         pccb->ccb_h.status |= CAM_REQ_CMP;
3065                         }
3066 #endif
3067                         xpt_done(pccb);
3068                         break;
3069         default:
3070                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3071                 xpt_done(pccb);
3072                 break;
3073         }
3074 }
3075 /*
3076 **********************************************************************
3077 **********************************************************************
3078 */
3079 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3080 {
3081         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3082         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3083         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3084                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3085         }
3086 }
3087 /*
3088 **********************************************************************
3089 **********************************************************************
3090 */
3091 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3092 {
3093         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3094         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,  ARCMSR_MESSAGE_START_BGRB);
3095         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3096                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3097         }
3098 }
3099 /*
3100 **********************************************************************
3101 **********************************************************************
3102 */
3103 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3104 {
3105         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3106         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3107         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3108         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3109                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3110         }
3111 }
3112 /*
3113 **********************************************************************
3114 **********************************************************************
3115 */
3116 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3117 {
3118         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3119         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3120         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3121                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3122         }
3123 }
3124 /*
3125 **********************************************************************
3126 **********************************************************************
3127 */
3128 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3129 {
3130         switch (acb->adapter_type) {
3131         case ACB_ADAPTER_TYPE_A:
3132                 arcmsr_start_hba_bgrb(acb);
3133                 break;
3134         case ACB_ADAPTER_TYPE_B:
3135                 arcmsr_start_hbb_bgrb(acb);
3136                 break;
3137         case ACB_ADAPTER_TYPE_C:
3138                 arcmsr_start_hbc_bgrb(acb);
3139                 break;
3140         case ACB_ADAPTER_TYPE_D:
3141                 arcmsr_start_hbd_bgrb(acb);
3142                 break;
3143         }
3144 }
3145 /*
3146 **********************************************************************
3147 **
3148 **********************************************************************
3149 */
3150 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3151 {
3152         struct CommandControlBlock *srb;
3153         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3154         u_int16_t       error;
3155
3156 polling_ccb_retry:
3157         poll_count++;
3158         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3159         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3160         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3161         while(1) {
3162                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3163                         0, outbound_queueport)) == 0xFFFFFFFF) {
3164                         if(poll_srb_done) {
3165                                 break;/*chip FIFO no ccb for completion already*/
3166                         } else {
3167                                 UDELAY(25000);
3168                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3169                                         break;
3170                                 }
3171                                 goto polling_ccb_retry;
3172                         }
3173                 }
3174                 /* check if command done with no error*/
3175                 srb = (struct CommandControlBlock *)
3176                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3177         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3178                 poll_srb_done = (srb == poll_srb) ? 1:0;
3179                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3180                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3181                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3182                                         "poll command abort successfully \n"
3183                                         , acb->pci_unit
3184                                         , srb->pccb->ccb_h.target_id
3185                                         , srb->pccb->ccb_h.target_lun, srb);
3186                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3187                                 arcmsr_srb_complete(srb, 1);
3188                                 continue;
3189                         }
3190                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3191                                 "srboutstandingcount=%d \n"
3192                                 , acb->pci_unit
3193                                 , srb, acb->srboutstandingcount);
3194                         continue;
3195                 }
3196                 arcmsr_report_srb_state(acb, srb, error);
3197         }       /*drain reply FIFO*/
3198 }
3199 /*
3200 **********************************************************************
3201 **
3202 **********************************************************************
3203 */
3204 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3205 {
3206         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3207         struct CommandControlBlock *srb;
3208         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3209         int index;
3210         u_int16_t       error;
3211
3212 polling_ccb_retry:
3213         poll_count++;
3214         CHIP_REG_WRITE32(HBB_DOORBELL,
3215         0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3216         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3217         while(1) {
3218                 index = phbbmu->doneq_index;
3219                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3220                         if(poll_srb_done) {
3221                                 break;/*chip FIFO no ccb for completion already*/
3222                         } else {
3223                                 UDELAY(25000);
3224                             if ((poll_count > 100) && (poll_srb != NULL)) {
3225                                         break;
3226                                 }
3227                                 goto polling_ccb_retry;
3228                         }
3229                 }
3230                 phbbmu->done_qbuffer[index] = 0;
3231                 index++;
3232                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3233                 phbbmu->doneq_index = index;
3234                 /* check if command done with no error*/
3235                 srb = (struct CommandControlBlock *)
3236                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3237         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3238                 poll_srb_done = (srb == poll_srb) ? 1:0;
3239                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3240                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3241                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3242                                         "poll command abort successfully \n"
3243                                         , acb->pci_unit
3244                                         , srb->pccb->ccb_h.target_id
3245                                         , srb->pccb->ccb_h.target_lun, srb);
3246                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3247                                 arcmsr_srb_complete(srb, 1);
3248                                 continue;
3249                         }
3250                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3251                                 "srboutstandingcount=%d \n"
3252                                 , acb->pci_unit
3253                                 , srb, acb->srboutstandingcount);
3254                         continue;
3255                 }
3256                 arcmsr_report_srb_state(acb, srb, error);
3257         }       /*drain reply FIFO*/
3258 }
3259 /*
3260 **********************************************************************
3261 **
3262 **********************************************************************
3263 */
3264 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3265 {
3266         struct CommandControlBlock *srb;
3267         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3268         u_int16_t       error;
3269
3270 polling_ccb_retry:
3271         poll_count++;
3272         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3273         while(1) {
3274                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3275                         if(poll_srb_done) {
3276                                 break;/*chip FIFO no ccb for completion already*/
3277                         } else {
3278                                 UDELAY(25000);
3279                             if ((poll_count > 100) && (poll_srb != NULL)) {
3280                                         break;
3281                                 }
3282                             if (acb->srboutstandingcount == 0) {
3283                                     break;
3284                             }
3285                                 goto polling_ccb_retry;
3286                         }
3287                 }
3288                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3289                 /* check if command done with no error*/
3290                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3291         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3292                 if (poll_srb != NULL)
3293                         poll_srb_done = (srb == poll_srb) ? 1:0;
3294                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3295                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3296                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3297                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3298                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3299                                 arcmsr_srb_complete(srb, 1);
3300                                 continue;
3301                         }
3302                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3303                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3304                         continue;
3305                 }
3306                 arcmsr_report_srb_state(acb, srb, error);
3307         }       /*drain reply FIFO*/
3308 }
3309 /*
3310 **********************************************************************
3311 **
3312 **********************************************************************
3313 */
3314 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3315 {
3316         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3317         struct CommandControlBlock *srb;
3318         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3319         u_int32_t outbound_write_pointer;
3320         u_int16_t       error, doneq_index;
3321
3322 polling_ccb_retry:
3323         poll_count++;
3324         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3325         while(1) {
3326                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3327                 doneq_index = phbdmu->doneq_index;
3328                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3329                         if(poll_srb_done) {
3330                                 break;/*chip FIFO no ccb for completion already*/
3331                         } else {
3332                                 UDELAY(25000);
3333                             if ((poll_count > 100) && (poll_srb != NULL)) {
3334                                         break;
3335                                 }
3336                             if (acb->srboutstandingcount == 0) {
3337                                     break;
3338                             }
3339                                 goto polling_ccb_retry;
3340                         }
3341                 }
3342                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3343                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3344                 /* check if command done with no error*/
3345                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3346         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3347                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3348                 if (poll_srb != NULL)
3349                         poll_srb_done = (srb == poll_srb) ? 1:0;
3350                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3351                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3352                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3353                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3354                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3355                                 arcmsr_srb_complete(srb, 1);
3356                                 continue;
3357                         }
3358                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3359                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3360                         continue;
3361                 }
3362                 arcmsr_report_srb_state(acb, srb, error);
3363         }       /*drain reply FIFO*/
3364 }
3365 /*
3366 **********************************************************************
3367 **********************************************************************
3368 */
3369 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3370 {
3371         switch (acb->adapter_type) {
3372         case ACB_ADAPTER_TYPE_A: {
3373                         arcmsr_polling_hba_srbdone(acb, poll_srb);
3374                 }
3375                 break;
3376         case ACB_ADAPTER_TYPE_B: {
3377                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
3378                 }
3379                 break;
3380         case ACB_ADAPTER_TYPE_C: {
3381                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
3382                 }
3383                 break;
3384         case ACB_ADAPTER_TYPE_D: {
3385                         arcmsr_polling_hbd_srbdone(acb, poll_srb);
3386                 }
3387                 break;
3388         }
3389 }
3390 /*
3391 **********************************************************************
3392 **********************************************************************
3393 */
3394 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3395 {
3396         char *acb_firm_model = acb->firm_model;
3397         char *acb_firm_version = acb->firm_version;
3398         char *acb_device_map = acb->device_map;
3399         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3400         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3401         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3402         int i;
3403
3404         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3405         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3406                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3407         }
3408         i = 0;
3409         while(i < 8) {
3410                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3411                 /* 8 bytes firm_model, 15, 60-67*/
3412                 acb_firm_model++;
3413                 i++;
3414         }
3415         i=0;
3416         while(i < 16) {
3417                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3418                 /* 16 bytes firm_version, 17, 68-83*/
3419                 acb_firm_version++;
3420                 i++;
3421         }
3422         i=0;
3423         while(i < 16) {
3424                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3425                 acb_device_map++;
3426                 i++;
3427         }
3428         printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3429         printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3430         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3431         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3432         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3433         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3434         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3435         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3436                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3437         else
3438                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3439 }
3440 /*
3441 **********************************************************************
3442 **********************************************************************
3443 */
3444 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3445 {
3446         char *acb_firm_model = acb->firm_model;
3447         char *acb_firm_version = acb->firm_version;
3448         char *acb_device_map = acb->device_map;
3449         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3450         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3451         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3452         int i;
3453
3454         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3455         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3456                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3457         }
3458         i = 0;
3459         while(i < 8) {
3460                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3461                 /* 8 bytes firm_model, 15, 60-67*/
3462                 acb_firm_model++;
3463                 i++;
3464         }
3465         i = 0;
3466         while(i < 16) {
3467                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3468                 /* 16 bytes firm_version, 17, 68-83*/
3469                 acb_firm_version++;
3470                 i++;
3471         }
3472         i = 0;
3473         while(i < 16) {
3474                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3475                 acb_device_map++;
3476                 i++;
3477         }
3478         printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3479         printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3480         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3481         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3482         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3483         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3484         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3485         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3486                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3487         else
3488                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3489 }
3490 /*
3491 **********************************************************************
3492 **********************************************************************
3493 */
3494 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3495 {
3496         char *acb_firm_model = acb->firm_model;
3497         char *acb_firm_version = acb->firm_version;
3498         char *acb_device_map = acb->device_map;
3499         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3500         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3501         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3502         int i;
3503
3504         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3505         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3506         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3507                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3508         }
3509         i = 0;
3510         while(i < 8) {
3511                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3512                 /* 8 bytes firm_model, 15, 60-67*/
3513                 acb_firm_model++;
3514                 i++;
3515         }
3516         i = 0;
3517         while(i < 16) {
3518                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3519                 /* 16 bytes firm_version, 17, 68-83*/
3520                 acb_firm_version++;
3521                 i++;
3522         }
3523         i = 0;
3524         while(i < 16) {
3525                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3526                 acb_device_map++;
3527                 i++;
3528         }
3529         printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3530         printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3531         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3532         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3533         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3534         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3535         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3536         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3537                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3538         else
3539                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3540 }
3541 /*
3542 **********************************************************************
3543 **********************************************************************
3544 */
3545 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3546 {
3547         char *acb_firm_model = acb->firm_model;
3548         char *acb_firm_version = acb->firm_version;
3549         char *acb_device_map = acb->device_map;
3550         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3551         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3552         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3553         int i;
3554
3555         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3556                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3557         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3558         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3559                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3560         }
3561         i = 0;
3562         while(i < 8) {
3563                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3564                 /* 8 bytes firm_model, 15, 60-67*/
3565                 acb_firm_model++;
3566                 i++;
3567         }
3568         i = 0;
3569         while(i < 16) {
3570                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3571                 /* 16 bytes firm_version, 17, 68-83*/
3572                 acb_firm_version++;
3573                 i++;
3574         }
3575         i = 0;
3576         while(i < 16) {
3577                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3578                 acb_device_map++;
3579                 i++;
3580         }
3581         printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3582         printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3583         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_request_len,   1, 04-07*/
3584         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_numbers_queue, 2, 08-11*/
3585         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_sdram_size,    3, 12-15*/
3586         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]);     /*firm_ide_channels,  4, 16-19*/
3587         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3588         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3589                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3590         else
3591                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3592 }
3593 /*
3594 **********************************************************************
3595 **********************************************************************
3596 */
3597 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3598 {
3599         switch (acb->adapter_type) {
3600         case ACB_ADAPTER_TYPE_A: {
3601                         arcmsr_get_hba_config(acb);
3602                 }
3603                 break;
3604         case ACB_ADAPTER_TYPE_B: {
3605                         arcmsr_get_hbb_config(acb);
3606                 }
3607                 break;
3608         case ACB_ADAPTER_TYPE_C: {
3609                         arcmsr_get_hbc_config(acb);
3610                 }
3611                 break;
3612         case ACB_ADAPTER_TYPE_D: {
3613                         arcmsr_get_hbd_config(acb);
3614                 }
3615                 break;
3616         }
3617 }
3618 /*
3619 **********************************************************************
3620 **********************************************************************
3621 */
3622 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3623 {
3624         int     timeout=0;
3625
3626         switch (acb->adapter_type) {
3627         case ACB_ADAPTER_TYPE_A: {
3628                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3629                         {
3630                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3631                                 {
3632                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3633                                         return;
3634                                 }
3635                                 UDELAY(15000); /* wait 15 milli-seconds */
3636                         }
3637                 }
3638                 break;
3639         case ACB_ADAPTER_TYPE_B: {
3640                         while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3641                         {
3642                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3643                                 {
3644                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3645                                         return;
3646                                 }
3647                                 UDELAY(15000); /* wait 15 milli-seconds */
3648                         }
3649                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3650                 }
3651                 break;
3652         case ACB_ADAPTER_TYPE_C: {
3653                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3654                         {
3655                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3656                                 {
3657                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3658                                         return;
3659                                 }
3660                                 UDELAY(15000); /* wait 15 milli-seconds */
3661                         }
3662                 }
3663                 break;
3664         case ACB_ADAPTER_TYPE_D: {
3665                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3666                         {
3667                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3668                                 {
3669                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3670                                         return;
3671                                 }
3672                                 UDELAY(15000); /* wait 15 milli-seconds */
3673                         }
3674                 }
3675                 break;
3676         }
3677 }
3678 /*
3679 **********************************************************************
3680 **********************************************************************
3681 */
3682 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3683 {
3684         u_int32_t outbound_doorbell;
3685
3686         switch (acb->adapter_type) {
3687         case ACB_ADAPTER_TYPE_A: {
3688                         /* empty doorbell Qbuffer if door bell ringed */
3689                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3690                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3691                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3692
3693                 }
3694                 break;
3695         case ACB_ADAPTER_TYPE_B: {
3696                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3697                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3698                         /* let IOP know data has been read */
3699                 }
3700                 break;
3701         case ACB_ADAPTER_TYPE_C: {
3702                         /* empty doorbell Qbuffer if door bell ringed */
3703                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3704                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
3705                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3706                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
3707                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
3708                 }
3709                 break;
3710         case ACB_ADAPTER_TYPE_D: {
3711                         /* empty doorbell Qbuffer if door bell ringed */
3712                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
3713                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3714                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
3715
3716                 }
3717                 break;
3718         }
3719 }
3720 /*
3721 ************************************************************************
3722 ************************************************************************
3723 */
3724 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3725 {
3726         unsigned long srb_phyaddr;
3727         u_int32_t srb_phyaddr_hi32;
3728         u_int32_t srb_phyaddr_lo32;
3729
3730         /*
3731         ********************************************************************
3732         ** here we need to tell iop 331 our freesrb.HighPart
3733         ** if freesrb.HighPart is not zero
3734         ********************************************************************
3735         */
3736         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
3737         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
3738         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
3739         switch (acb->adapter_type) {
3740         case ACB_ADAPTER_TYPE_A: {
3741                         if(srb_phyaddr_hi32 != 0) {
3742                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3743                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3744                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3745                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3746                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3747                                         return FALSE;
3748                                 }
3749                         }
3750                 }
3751                 break;
3752                 /*
3753                 ***********************************************************************
3754                 **    if adapter type B, set window of "post command Q"
3755                 ***********************************************************************
3756                 */
3757         case ACB_ADAPTER_TYPE_B: {
3758                         u_int32_t post_queue_phyaddr;
3759                         struct HBB_MessageUnit *phbbmu;
3760
3761                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3762                         phbbmu->postq_index = 0;
3763                         phbbmu->doneq_index = 0;
3764                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3765                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3766                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3767                                 return FALSE;
3768                         }
3769                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
3770                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
3771                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3772                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3773                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3774                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3775                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3776                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3777                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3778                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3779                                 return FALSE;
3780                         }
3781                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3782                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3783                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3784                                 return FALSE;
3785                         }
3786                 }
3787                 break;
3788         case ACB_ADAPTER_TYPE_C: {
3789                         if(srb_phyaddr_hi32 != 0) {
3790                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3791                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3792                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3793                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3794                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3795                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3796                                         return FALSE;
3797                                 }
3798                         }
3799                 }
3800                 break;
3801         case ACB_ADAPTER_TYPE_D: {
3802                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
3803                         struct HBD_MessageUnit0 *phbdmu;
3804
3805                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3806                         phbdmu->postq_index = 0;
3807                         phbdmu->doneq_index = 0x40FF;
3808                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3809                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
3810                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3811                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
3812                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3813                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3814                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
3815                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
3816                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
3817                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3818                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3819                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3820                                 return FALSE;
3821                         }
3822                 }
3823                 break;
3824         }
3825         return (TRUE);
3826 }
3827 /*
3828 ************************************************************************
3829 ************************************************************************
3830 */
3831 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3832 {
3833         switch (acb->adapter_type)
3834         {
3835         case ACB_ADAPTER_TYPE_A:
3836         case ACB_ADAPTER_TYPE_C:
3837         case ACB_ADAPTER_TYPE_D:
3838                 break;
3839         case ACB_ADAPTER_TYPE_B: {
3840                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3841                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3842                                 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3843                                 return;
3844                         }
3845                 }
3846                 break;
3847         }
3848 }
3849 /*
3850 **********************************************************************
3851 **********************************************************************
3852 */
3853 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3854 {
3855         u_int32_t intmask_org;
3856
3857         /* disable all outbound interrupt */
3858         intmask_org = arcmsr_disable_allintr(acb);
3859         arcmsr_wait_firmware_ready(acb);
3860         arcmsr_iop_confirm(acb);
3861         arcmsr_get_firmware_spec(acb);
3862         /*start background rebuild*/
3863         arcmsr_start_adapter_bgrb(acb);
3864         /* empty doorbell Qbuffer if door bell ringed */
3865         arcmsr_clear_doorbell_queue_buffer(acb);
3866         arcmsr_enable_eoi_mode(acb);
3867         /* enable outbound Post Queue, outbound doorbell Interrupt */
3868         arcmsr_enable_allintr(acb, intmask_org);
3869         acb->acb_flags |= ACB_F_IOP_INITED;
3870 }
3871 /*
3872 **********************************************************************
3873 **********************************************************************
3874 */
3875 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3876 {
3877         struct AdapterControlBlock *acb = arg;
3878         struct CommandControlBlock *srb_tmp;
3879         u_int32_t i;
3880         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
3881
3882         acb->srb_phyaddr.phyaddr = srb_phyaddr;
3883         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
3884         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3885                 if(bus_dmamap_create(acb->dm_segs_dmat,
3886                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
3887                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3888                         printf("arcmsr%d:"
3889                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3890                         return;
3891                 }
3892                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
3893                 {
3894                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
3895                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
3896                 }
3897                 else
3898                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
3899                 srb_tmp->acb = acb;
3900                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
3901                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
3902                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
3903         }
3904         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
3905 }
3906 /*
3907 ************************************************************************
3908 ************************************************************************
3909 */
3910 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3911 {
3912         /* remove the control device */
3913         if(acb->ioctl_dev != NULL) {
3914                 destroy_dev(acb->ioctl_dev);
3915         }
3916         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3917         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3918         bus_dma_tag_destroy(acb->srb_dmat);
3919         bus_dma_tag_destroy(acb->dm_segs_dmat);
3920         bus_dma_tag_destroy(acb->parent_dmat);
3921 }
3922 /*
3923 ************************************************************************
3924 ************************************************************************
3925 */
3926 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
3927 {
3928         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
3929         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
3930         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
3931         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
3932 }
3933 /*
3934 ************************************************************************
3935 ************************************************************************
3936 */
3937 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
3938 {
3939         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3940         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
3941         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
3942         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
3943 }
3944 /*
3945 ************************************************************************
3946 ************************************************************************
3947 */
3948 static u_int32_t arcmsr_initialize(device_t dev)
3949 {
3950         struct AdapterControlBlock *acb = device_get_softc(dev);
3951         u_int16_t pci_command;
3952         int i, j,max_coherent_size;
3953         u_int32_t vendor_dev_id;
3954
3955         vendor_dev_id = pci_get_devid(dev);
3956         acb->vendor_device_id = vendor_dev_id;
3957         switch (vendor_dev_id) {
3958         case PCIDevVenIDARC1880:
3959         case PCIDevVenIDARC1882:
3960         case PCIDevVenIDARC1213:
3961         case PCIDevVenIDARC1223: {
3962                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
3963                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3964                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3965                 }
3966                 break;
3967         case PCIDevVenIDARC1214: {
3968                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
3969                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3970                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
3971                 }
3972                 break;
3973         case PCIDevVenIDARC1200:
3974         case PCIDevVenIDARC1201: {
3975                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
3976                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
3977                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
3978                 }
3979                 break;
3980         case PCIDevVenIDARC1110:
3981         case PCIDevVenIDARC1120:
3982         case PCIDevVenIDARC1130:
3983         case PCIDevVenIDARC1160:
3984         case PCIDevVenIDARC1170:
3985         case PCIDevVenIDARC1210:
3986         case PCIDevVenIDARC1220:
3987         case PCIDevVenIDARC1230:
3988         case PCIDevVenIDARC1231:
3989         case PCIDevVenIDARC1260:
3990         case PCIDevVenIDARC1261:
3991         case PCIDevVenIDARC1270:
3992         case PCIDevVenIDARC1280:
3993         case PCIDevVenIDARC1212:
3994         case PCIDevVenIDARC1222:
3995         case PCIDevVenIDARC1380:
3996         case PCIDevVenIDARC1381:
3997         case PCIDevVenIDARC1680:
3998         case PCIDevVenIDARC1681: {
3999                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
4000                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4001                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4002                 }
4003                 break;
4004         default: {
4005                         printf("arcmsr%d:"
4006                         " unknown RAID adapter type \n", device_get_unit(dev));
4007                         return ENOMEM;
4008                 }
4009         }
4010 #if __FreeBSD_version >= 700000
4011         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4012 #else
4013         if(bus_dma_tag_create(  /*PCI parent*/          NULL,
4014 #endif
4015                                                         /*alignemnt*/   1,
4016                                                         /*boundary*/    0,
4017                                                         /*lowaddr*/             BUS_SPACE_MAXADDR,
4018                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4019                                                         /*filter*/              NULL,
4020                                                         /*filterarg*/   NULL,
4021                                                         /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4022                                                         /*nsegments*/   BUS_SPACE_UNRESTRICTED,
4023                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4024                                                         /*flags*/               0,
4025 #if __FreeBSD_version >= 501102
4026                                                         /*lockfunc*/    NULL,
4027                                                         /*lockarg*/             NULL,
4028 #endif
4029                                                 &acb->parent_dmat) != 0)
4030         {
4031                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4032                 return ENOMEM;
4033         }
4034
4035         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4036         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
4037                                                         /*alignment*/   1,
4038                                                         /*boundary*/    0,
4039 #ifdef PAE
4040                                                         /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4041 #else
4042                                                         /*lowaddr*/             BUS_SPACE_MAXADDR,
4043 #endif
4044                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4045                                                         /*filter*/              NULL,
4046                                                         /*filterarg*/   NULL,
4047                                                         /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4048                                                         /*nsegments*/   ARCMSR_MAX_SG_ENTRIES,
4049                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4050                                                         /*flags*/               0,
4051 #if __FreeBSD_version >= 501102
4052                                                         /*lockfunc*/    busdma_lock_mutex,
4053                                                         /*lockarg*/             &acb->isr_lock,
4054 #endif
4055                                                 &acb->dm_segs_dmat) != 0)
4056         {
4057                 bus_dma_tag_destroy(acb->parent_dmat);
4058                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4059                 return ENOMEM;
4060         }
4061
4062         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4063         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
4064                                                         /*alignment*/   0x20,
4065                                                         /*boundary*/    0,
4066                                                         /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4067                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4068                                                         /*filter*/              NULL,
4069                                                         /*filterarg*/   NULL,
4070                                                         /*maxsize*/             max_coherent_size,
4071                                                         /*nsegments*/   1,
4072                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4073                                                         /*flags*/               0,
4074 #if __FreeBSD_version >= 501102
4075                                                         /*lockfunc*/    NULL,
4076                                                         /*lockarg*/             NULL,
4077 #endif
4078                                                 &acb->srb_dmat) != 0)
4079         {
4080                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4081                 bus_dma_tag_destroy(acb->parent_dmat);
4082                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4083                 return ENXIO;
4084         }
4085         /* Allocation for our srbs */
4086         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4087                 bus_dma_tag_destroy(acb->srb_dmat);
4088                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4089                 bus_dma_tag_destroy(acb->parent_dmat);
4090                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4091                 return ENXIO;
4092         }
4093         /* And permanently map them */
4094         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4095                 bus_dma_tag_destroy(acb->srb_dmat);
4096                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4097                 bus_dma_tag_destroy(acb->parent_dmat);
4098                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4099                 return ENXIO;
4100         }
4101         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4102         pci_command |= PCIM_CMD_BUSMASTEREN;
4103         pci_command |= PCIM_CMD_PERRESPEN;
4104         pci_command |= PCIM_CMD_MWRICEN;
4105         /* Enable Busmaster/Mem */
4106         pci_command |= PCIM_CMD_MEMEN;
4107         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4108         switch(acb->adapter_type) {
4109         case ACB_ADAPTER_TYPE_A: {
4110                         u_int32_t rid0 = PCIR_BAR(0);
4111                         vm_offset_t     mem_base0;
4112
4113                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
4114                         if(acb->sys_res_arcmsr[0] == NULL) {
4115                                 arcmsr_free_resource(acb);
4116                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4117                                 return ENOMEM;
4118                         }
4119                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4120                                 arcmsr_free_resource(acb);
4121                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4122                                 return ENXIO;
4123                         }
4124                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4125                         if(mem_base0 == 0) {
4126                                 arcmsr_free_resource(acb);
4127                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4128                                 return ENXIO;
4129                         }
4130                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4131                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4132                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4133                 }
4134                 break;
4135         case ACB_ADAPTER_TYPE_B: {
4136                         struct HBB_MessageUnit *phbbmu;
4137                         struct CommandControlBlock *freesrb;
4138                         u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4139                         vm_offset_t     mem_base[]={0,0};
4140                         for(i=0; i < 2; i++) {
4141                                 if(i == 0) {
4142                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
4143                                                                                         0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
4144                                 } else {
4145                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
4146                                                                                         0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
4147                                 }
4148                                 if(acb->sys_res_arcmsr[i] == NULL) {
4149                                         arcmsr_free_resource(acb);
4150                                         printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4151                                         return ENOMEM;
4152                                 }
4153                                 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4154                                         arcmsr_free_resource(acb);
4155                                         printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4156                                         return ENXIO;
4157                                 }
4158                                 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4159                                 if(mem_base[i] == 0) {
4160                                         arcmsr_free_resource(acb);
4161                                         printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4162                                         return ENXIO;
4163                                 }
4164                                 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4165                                 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4166                         }
4167                         freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4168                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4169                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4170                         phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4171                         phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4172                 }
4173                 break;
4174         case ACB_ADAPTER_TYPE_C: {
4175                         u_int32_t rid0 = PCIR_BAR(1);
4176                         vm_offset_t     mem_base0;
4177
4178                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
4179                         if(acb->sys_res_arcmsr[0] == NULL) {
4180                                 arcmsr_free_resource(acb);
4181                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4182                                 return ENOMEM;
4183                         }
4184                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4185                                 arcmsr_free_resource(acb);
4186                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4187                                 return ENXIO;
4188                         }
4189                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4190                         if(mem_base0 == 0) {
4191                                 arcmsr_free_resource(acb);
4192                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4193                                 return ENXIO;
4194                         }
4195                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4196                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4197                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4198                 }
4199                 break;
4200         case ACB_ADAPTER_TYPE_D: {
4201                         struct HBD_MessageUnit0 *phbdmu;
4202                         u_int32_t rid0 = PCIR_BAR(0);
4203                         vm_offset_t     mem_base0;
4204
4205                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
4206                         if(acb->sys_res_arcmsr[0] == NULL) {
4207                                 arcmsr_free_resource(acb);
4208                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4209                                 return ENOMEM;
4210                         }
4211                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4212                                 arcmsr_free_resource(acb);
4213                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4214                                 return ENXIO;
4215                         }
4216                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4217                         if(mem_base0 == 0) {
4218                                 arcmsr_free_resource(acb);
4219                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4220                                 return ENXIO;
4221                         }
4222                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4223                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4224                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4225                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4226                         phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4227                 }
4228                 break;
4229         }
4230         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4231                 arcmsr_free_resource(acb);
4232                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4233                 return ENXIO;
4234         }
4235         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4236         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4237         /*
4238         ********************************************************************
4239         ** init raid volume state
4240         ********************************************************************
4241         */
4242         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4243                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4244                         acb->devstate[i][j] = ARECA_RAID_GONE;
4245                 }
4246         }
4247         arcmsr_iop_init(acb);
4248         return(0);
4249 }
4250 /*
4251 ************************************************************************
4252 ************************************************************************
4253 */
4254 static int arcmsr_attach(device_t dev)
4255 {
4256         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4257         u_int32_t unit=device_get_unit(dev);
4258         struct ccb_setasync csa;
4259         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4260         struct resource *irqres;
4261         int     rid;
4262
4263         if(acb == NULL) {
4264                 printf("arcmsr%d: cannot allocate softc\n", unit);
4265                 return (ENOMEM);
4266         }
4267         arcmsr_mutex_init(acb);
4268         if(arcmsr_initialize(dev)) {
4269                 printf("arcmsr%d: initialize failure!\n", unit);
4270                 arcmsr_mutex_destroy(acb);
4271                 return ENXIO;
4272         }
4273         /* After setting up the adapter, map our interrupt */
4274         rid = 0;
4275         irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE);
4276         if(irqres == NULL ||
4277 #if __FreeBSD_version >= 700025
4278                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
4279 #else
4280                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
4281 #endif
4282                 arcmsr_free_resource(acb);
4283                 arcmsr_mutex_destroy(acb);
4284                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4285                 return ENXIO;
4286         }
4287         acb->irqres = irqres;
4288         acb->pci_dev = dev;
4289         acb->pci_unit = unit;
4290         /*
4291          * Now let the CAM generic SCSI layer find the SCSI devices on
4292          * the bus *  start queue to reset to the idle loop. *
4293          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4294          * max_sim_transactions
4295         */
4296         devq = cam_simq_alloc(ARCMSR_MAX_START_JOB);
4297         if(devq == NULL) {
4298             arcmsr_free_resource(acb);
4299                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4300                 arcmsr_mutex_destroy(acb);
4301                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4302                 return ENXIO;
4303         }
4304 #if __FreeBSD_version >= 700025
4305         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4306 #else
4307         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4308 #endif
4309         if(acb->psim == NULL) {
4310                 arcmsr_free_resource(acb);
4311                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4312                 cam_simq_free(devq);
4313                 arcmsr_mutex_destroy(acb);
4314                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4315                 return ENXIO;
4316         }
4317         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4318 #if __FreeBSD_version >= 700044
4319         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4320 #else
4321         if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4322 #endif
4323                 arcmsr_free_resource(acb);
4324                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4325                 cam_sim_free(acb->psim, /*free_devq*/TRUE);
4326                 arcmsr_mutex_destroy(acb);
4327                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4328                 return ENXIO;
4329         }
4330         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4331                 arcmsr_free_resource(acb);
4332                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4333                 xpt_bus_deregister(cam_sim_path(acb->psim));
4334                 cam_sim_free(acb->psim, /* free_simq */ TRUE);
4335                 arcmsr_mutex_destroy(acb);
4336                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4337                 return ENXIO;
4338         }
4339         /*
4340         ****************************************************
4341         */
4342         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4343         csa.ccb_h.func_code = XPT_SASYNC_CB;
4344         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4345         csa.callback = arcmsr_async;
4346         csa.callback_arg = acb->psim;
4347         xpt_action((union ccb *)&csa);
4348         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4349         /* Create the control device.  */
4350         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4351
4352 #if __FreeBSD_version < 503000
4353         acb->ioctl_dev->si_drv1 = acb;
4354 #endif
4355 #if __FreeBSD_version > 500005
4356         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4357 #endif
4358         arcmsr_callout_init(&acb->devmap_callout);
4359         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4360         return (0);
4361 }
4362
4363 /*
4364 ************************************************************************
4365 ************************************************************************
4366 */
4367 static int arcmsr_probe(device_t dev)
4368 {
4369         u_int32_t id;
4370         static char buf[256];
4371         char x_type[]={"X-TYPE"};
4372         char *type;
4373         int raid6 = 1;
4374
4375         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4376                 return (ENXIO);
4377         }
4378         switch(id = pci_get_devid(dev)) {
4379         case PCIDevVenIDARC1110:
4380         case PCIDevVenIDARC1200:
4381         case PCIDevVenIDARC1201:
4382         case PCIDevVenIDARC1210:
4383                 raid6 = 0;
4384                 /*FALLTHRU*/
4385         case PCIDevVenIDARC1120:
4386         case PCIDevVenIDARC1130:
4387         case PCIDevVenIDARC1160:
4388         case PCIDevVenIDARC1170:
4389         case PCIDevVenIDARC1220:
4390         case PCIDevVenIDARC1230:
4391         case PCIDevVenIDARC1231:
4392         case PCIDevVenIDARC1260:
4393         case PCIDevVenIDARC1261:
4394         case PCIDevVenIDARC1270:
4395         case PCIDevVenIDARC1280:
4396                 type = "SATA 3G";
4397                 break;
4398         case PCIDevVenIDARC1212:
4399         case PCIDevVenIDARC1222:
4400         case PCIDevVenIDARC1380:
4401         case PCIDevVenIDARC1381:
4402         case PCIDevVenIDARC1680:
4403         case PCIDevVenIDARC1681:
4404                 type = "SAS 3G";
4405                 break;
4406         case PCIDevVenIDARC1880:
4407         case PCIDevVenIDARC1882:
4408         case PCIDevVenIDARC1213:
4409         case PCIDevVenIDARC1223:
4410                 type = "SAS 6G";
4411                 break;
4412         case PCIDevVenIDARC1214:
4413                 type = "SATA 6G";
4414                 break;
4415         default:
4416                 type = x_type;
4417                 break;
4418         }
4419         if(type == x_type)
4420                 return(ENXIO);
4421         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : "");
4422         device_set_desc_copy(dev, buf);
4423         return 0;
4424 }
4425 /*
4426 ************************************************************************
4427 ************************************************************************
4428 */
4429 static int arcmsr_shutdown(device_t dev)
4430 {
4431         u_int32_t  i;
4432         u_int32_t intmask_org;
4433         struct CommandControlBlock *srb;
4434         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4435
4436         /* stop adapter background rebuild */
4437         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4438         /* disable all outbound interrupt */
4439         intmask_org = arcmsr_disable_allintr(acb);
4440         arcmsr_stop_adapter_bgrb(acb);
4441         arcmsr_flush_adapter_cache(acb);
4442         /* abort all outstanding command */
4443         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4444         acb->acb_flags &= ~ACB_F_IOP_INITED;
4445         if(acb->srboutstandingcount != 0) {
4446                 /*clear and abort all outbound posted Q*/
4447                 arcmsr_done4abort_postqueue(acb);
4448                 /* talk to iop 331 outstanding command aborted*/
4449                 arcmsr_abort_allcmd(acb);
4450                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4451                         srb = acb->psrb_pool[i];
4452                         if(srb->srb_state == ARCMSR_SRB_START) {
4453                                 srb->srb_state = ARCMSR_SRB_ABORTED;
4454                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4455                                 arcmsr_srb_complete(srb, 1);
4456                         }
4457                 }
4458         }
4459         acb->srboutstandingcount = 0;
4460         acb->workingsrb_doneindex = 0;
4461         acb->workingsrb_startindex = 0;
4462         acb->pktRequestCount = 0;
4463         acb->pktReturnCount = 0;
4464         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4465         return (0);
4466 }
4467 /*
4468 ************************************************************************
4469 ************************************************************************
4470 */
4471 static int arcmsr_detach(device_t dev)
4472 {
4473         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4474         int i;
4475
4476         callout_stop(&acb->devmap_callout);
4477         bus_teardown_intr(dev, acb->irqres, acb->ih);
4478         arcmsr_shutdown(dev);
4479         arcmsr_free_resource(acb);
4480         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4481                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
4482         }
4483         bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4484         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4485         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4486         xpt_free_path(acb->ppath);
4487         xpt_bus_deregister(cam_sim_path(acb->psim));
4488         cam_sim_free(acb->psim, TRUE);
4489         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4490         arcmsr_mutex_destroy(acb);
4491         return (0);
4492 }
4493
4494 #ifdef ARCMSR_DEBUG1
4495 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4496 {
4497         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4498                 return;
4499         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
4500         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
4501         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4502         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
4503 }
4504 #endif
4505