2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_cmd_ch_attach(device_t dev);
56 static int ata_cmd_status(device_t dev);
57 static int ata_cmd_setmode(device_t dev, int target, int mode);
58 static int ata_sii_ch_attach(device_t dev);
59 static int ata_sii_ch_detach(device_t dev);
60 static int ata_sii_status(device_t dev);
61 static void ata_sii_reset(device_t dev);
62 static int ata_sii_setmode(device_t dev, int target, int mode);
63 static int ata_siiprb_ch_attach(device_t dev);
64 static int ata_siiprb_ch_detach(device_t dev);
65 static int ata_siiprb_status(device_t dev);
66 static int ata_siiprb_begin_transaction(struct ata_request *request);
67 static int ata_siiprb_end_transaction(struct ata_request *request);
68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70 static u_int32_t ata_siiprb_softreset(device_t dev, int port);
71 static void ata_siiprb_reset(device_t dev);
72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
73 static void ata_siiprb_dmainit(device_t dev);
79 #define SII_SETCLK 0x02
84 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
87 ata_sii_probe(device_t dev)
89 struct ata_pci_controller *ctlr = device_get_softc(dev);
90 static const struct ata_chip_id ids[] =
91 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
92 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
93 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
94 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
95 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
96 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
97 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
98 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
99 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
100 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
102 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
103 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
104 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
105 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
106 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
107 { 0, 0, 0, 0, 0, 0}};
109 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
112 if (!(ctlr->chip = ata_match_chip(dev, ids)))
116 ctlr->chipinit = ata_sii_chipinit;
117 return (BUS_PROBE_DEFAULT);
121 ata_sii_chipinit(device_t dev)
123 struct ata_pci_controller *ctlr = device_get_softc(dev);
125 if (ata_setup_interrupt(dev, ata_generic_intr))
128 switch (ctlr->chip->cfg1) {
130 ctlr->r_type1 = SYS_RES_MEMORY;
131 ctlr->r_rid1 = PCIR_BAR(0);
132 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
133 &ctlr->r_rid1, RF_ACTIVE)))
136 ctlr->r_rid2 = PCIR_BAR(2);
137 ctlr->r_type2 = SYS_RES_MEMORY;
138 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
139 &ctlr->r_rid2, RF_ACTIVE))){
140 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
144 if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
145 rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
146 BUS_SPACE_MAP_LINEAR, NULL)) {
147 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
149 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
154 ctlr->ch_attach = ata_siiprb_ch_attach;
155 ctlr->ch_detach = ata_siiprb_ch_detach;
156 ctlr->reset = ata_siiprb_reset;
157 ctlr->setmode = ata_sata_setmode;
158 ctlr->getrev = ata_sata_getrev;
159 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
161 /* reset controller */
162 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
164 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
168 ctlr->r_type2 = SYS_RES_MEMORY;
169 ctlr->r_rid2 = PCIR_BAR(5);
170 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
171 &ctlr->r_rid2, RF_ACTIVE))){
172 if (ctlr->chip->chipid != ATA_SII0680 ||
173 (pci_read_config(dev, 0x8a, 1) & 1))
177 if (ctlr->chip->cfg2 & SII_SETCLK) {
178 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
179 pci_write_config(dev, 0x8a,
180 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
181 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
182 device_printf(dev, "%s could not set ATA133 clock\n",
186 /* if we have 4 channels enable the second set */
187 if (ctlr->chip->cfg2 & SII_4CH) {
188 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
192 /* dont block interrupts from any channel */
193 pci_write_config(dev, 0x48,
194 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
196 /* enable PCI interrupt as BIOS might not */
197 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
200 ctlr->ch_attach = ata_sii_ch_attach;
201 ctlr->ch_detach = ata_sii_ch_detach;
204 if (ctlr->chip->max_dma >= ATA_SA150) {
205 ctlr->reset = ata_sii_reset;
206 ctlr->setmode = ata_sata_setmode;
207 ctlr->getrev = ata_sata_getrev;
210 ctlr->setmode = ata_sii_setmode;
214 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
215 device_printf(dev, "HW has secondary channel disabled\n");
219 /* enable interrupt as BIOS might not */
220 pci_write_config(dev, 0x71, 0x01, 1);
222 ctlr->ch_attach = ata_cmd_ch_attach;
223 ctlr->ch_detach = ata_pci_ch_detach;
224 ctlr->setmode = ata_cmd_setmode;
231 ata_cmd_ch_attach(device_t dev)
233 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
234 struct ata_channel *ch = device_get_softc(dev);
236 /* setup the usual register normal pci style */
237 if (ata_pci_ch_attach(dev))
240 if (ctlr->chip->cfg2 & SII_INTR)
241 ch->hw.status = ata_cmd_status;
244 ch->flags |= ATA_NO_ATAPI_DMA;
251 ata_cmd_status(device_t dev)
253 struct ata_channel *ch = device_get_softc(dev);
256 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
257 (ch->unit ? 0x08 : 0x04))) {
258 pci_write_config(device_get_parent(dev), 0x71,
259 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
260 return ata_pci_status(dev);
266 ata_cmd_setmode(device_t dev, int target, int mode)
268 device_t parent = device_get_parent(dev);
269 struct ata_pci_controller *ctlr = device_get_softc(parent);
270 struct ata_channel *ch = device_get_softc(dev);
271 int devno = (ch->unit << 1) + target;
272 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
273 int ureg = ch->unit ? 0x7b : 0x73;
275 static const uint8_t piotimings[] =
276 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
277 static const uint8_t udmatimings[][2] =
278 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
279 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
281 mode = min(mode, ctlr->chip->max_dma);
282 if (mode >= ATA_UDMA0) {
283 u_int8_t umode = pci_read_config(parent, ureg, 1);
285 umode &= ~(target == 0 ? 0x35 : 0xca);
286 umode |= udmatimings[mode & ATA_MODE_MASK][target];
287 pci_write_config(parent, ureg, umode, 1);
290 pci_write_config(parent, ureg,
291 pci_read_config(parent, ureg, 1) &
292 ~(target == 0 ? 0x35 : 0xca), 1);
295 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
300 ata_sii_ch_attach(device_t dev)
302 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
303 struct ata_channel *ch = device_get_softc(dev);
304 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
307 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
308 ch->r_io[i].res = ctlr->r_res2;
309 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
311 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
312 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
313 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
314 ata_default_registers(dev);
316 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
317 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
318 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
319 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
320 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
321 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
323 if (ctlr->chip->max_dma >= ATA_SA150) {
324 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
325 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
326 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
327 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
328 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
329 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
330 ch->flags |= ATA_NO_SLAVE;
331 ch->flags |= ATA_SATA;
332 ch->flags |= ATA_KNOWN_PRESENCE;
334 /* enable PHY state change interrupt */
335 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
338 if (ctlr->chip->cfg2 & SII_BUG) {
339 /* work around errata in early chips */
340 ch->dma.boundary = 8192;
341 ch->dma.segsize = 15 * DEV_BSIZE;
345 ch->hw.status = ata_sii_status;
346 if (ctlr->chip->cfg2 & SII_SETCLK)
347 ch->flags |= ATA_CHECKS_CABLE;
349 ata_pci_dmainit(dev);
355 ata_sii_ch_detach(device_t dev)
358 ata_pci_dmafini(dev);
363 ata_sii_status(device_t dev)
365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
366 struct ata_channel *ch = device_get_softc(dev);
367 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
368 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
370 /* do we have any PHY events ? */
371 if (ctlr->chip->max_dma >= ATA_SA150 &&
372 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
373 ata_sata_phy_check_events(dev, -1);
375 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
376 return ata_pci_status(dev);
382 ata_sii_reset(device_t dev)
384 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
385 struct ata_channel *ch = device_get_softc(dev);
386 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
389 /* Apply R_ERR on DMA activate FIS errata workaround. */
390 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
391 if ((val & 0x3) == 0x1)
392 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
394 if (ata_sata_phy_reset(dev, -1, 1))
395 ata_generic_reset(dev);
401 ata_sii_setmode(device_t dev, int target, int mode)
403 device_t parent = device_get_parent(dev);
404 struct ata_pci_controller *ctlr = device_get_softc(parent);
405 struct ata_channel *ch = device_get_softc(dev);
406 int rego = (ch->unit << 4) + (target << 1);
407 int mreg = ch->unit ? 0x84 : 0x80;
408 int mask = 0x03 << (target << 2);
409 int mval = pci_read_config(parent, mreg, 1) & ~mask;
411 u_int8_t preg = 0xa4 + rego;
412 u_int8_t dreg = 0xa8 + rego;
413 u_int8_t ureg = 0xac + rego;
414 static const uint16_t piotimings[] =
415 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
416 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
417 static const uint8_t udmatimings[] =
418 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
420 mode = min(mode, ctlr->chip->max_dma);
422 if (ctlr->chip->cfg2 & SII_SETCLK) {
423 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
424 (pci_read_config(parent, 0x79, 1) &
425 (ch->unit ? 0x02 : 0x01))) {
426 ata_print_cable(dev, "controller");
430 if (mode >= ATA_UDMA0) {
431 pci_write_config(parent, mreg,
432 mval | (0x03 << (target << 2)), 1);
433 pci_write_config(parent, ureg,
434 (pci_read_config(parent, ureg, 1) & ~0x3f) |
435 udmatimings[mode & ATA_MODE_MASK], 1);
437 } else if (mode >= ATA_WDMA0) {
438 pci_write_config(parent, mreg,
439 mval | (0x02 << (target << 2)), 1);
440 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
441 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
442 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
444 pci_write_config(parent, mreg,
445 mval | (0x01 << (target << 2)), 1);
448 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
452 struct ata_siiprb_dma_prdentry {
458 #define ATA_SIIPRB_DMA_ENTRIES 129
459 struct ata_siiprb_ata_command {
460 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
463 struct ata_siiprb_atapi_command {
465 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
468 struct ata_siiprb_command {
470 u_int16_t protocol_override;
471 u_int32_t transfer_count;
474 struct ata_siiprb_ata_command ata;
475 struct ata_siiprb_atapi_command atapi;
480 ata_siiprb_ch_attach(device_t dev)
482 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
483 struct ata_channel *ch = device_get_softc(dev);
484 int offset = ch->unit * 0x2000;
486 ata_siiprb_dmainit(dev);
488 /* set the SATA resources */
489 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
490 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
491 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
492 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
493 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
494 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
495 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
496 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
498 ch->hw.status = ata_siiprb_status;
499 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
500 ch->hw.end_transaction = ata_siiprb_end_transaction;
501 ch->hw.command = NULL; /* not used here */
502 ch->hw.softreset = ata_siiprb_softreset;
503 ch->hw.pm_read = ata_siiprb_pm_read;
504 ch->hw.pm_write = ata_siiprb_pm_write;
505 ch->flags |= ATA_NO_SLAVE;
506 ch->flags |= ATA_SATA;
511 ata_siiprb_ch_detach(device_t dev)
513 struct ata_channel *ch = device_get_softc(dev);
515 if (ch->dma.work_tag && ch->dma.work_map)
516 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
517 BUS_DMASYNC_POSTWRITE);
523 ata_siiprb_status(device_t dev)
525 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
526 struct ata_channel *ch = device_get_softc(dev);
527 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
528 int offset = ch->unit * 0x2000;
530 if (action & (1 << ch->unit)) {
531 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
533 /* do we have any PHY events ? */
534 ata_sata_phy_check_events(dev, -1);
536 /* clear interrupt(s) */
537 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
539 /* do we have any device action ? */
540 return (istatus & 0x00000003);
546 ata_siiprb_begin_transaction(struct ata_request *request)
548 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
549 struct ata_channel *ch = device_get_softc(request->parent);
550 struct ata_siiprb_command *prb;
551 struct ata_siiprb_dma_prdentry *prd;
552 int offset = ch->unit * 0x2000;
556 if (request->u.ata.command == ATA_DEVICE_RESET) {
558 return ATA_OP_FINISHED;
561 /* get a piece of the workspace for this request */
562 prb = (struct ata_siiprb_command *)ch->dma.work;
564 /* clear the prb structure */
565 bzero(prb, sizeof(struct ata_siiprb_command));
567 /* setup the FIS for this request */
568 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
569 device_printf(request->parent, "setting up SATA FIS failed\n");
570 request->result = EIO;
571 return ATA_OP_FINISHED;
574 /* setup transfer type */
575 if (request->flags & ATA_R_ATAPI) {
576 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
577 if (request->flags & ATA_R_ATAPI16)
578 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
580 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
581 if (request->flags & ATA_R_READ)
582 prb->control = htole16(0x0010);
583 if (request->flags & ATA_R_WRITE)
584 prb->control = htole16(0x0020);
585 prd = &prb->u.atapi.prd[0];
588 prd = &prb->u.ata.prd[0];
590 /* if request moves data setup and load SG list */
591 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
592 if (ch->dma.load(request, prd, NULL)) {
593 device_printf(request->parent, "setting up DMA failed\n");
594 request->result = EIO;
595 return ATA_OP_FINISHED;
599 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
601 /* activate the prb */
602 prb_bus = ch->dma.work_bus;
603 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
604 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
606 /* start the timeout */
607 callout_reset(&request->callout, request->timeout * hz,
608 (timeout_t*)ata_timeout, request);
609 return ATA_OP_CONTINUES;
613 ata_siiprb_end_transaction(struct ata_request *request)
615 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
616 struct ata_channel *ch = device_get_softc(request->parent);
617 struct ata_siiprb_command *prb;
618 int offset = ch->unit * 0x2000;
621 /* kill the timeout */
622 callout_stop(&request->callout);
624 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
626 prb = (struct ata_siiprb_command *)
627 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
629 /* any controller errors flagged ? */
630 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
632 printf("ata_siiprb_end_transaction %s error=%08x\n",
633 ata_cmd2str(request), error);
635 /* if device error status get details */
636 if (error == 1 || error == 2) {
637 request->status = prb->fis[2];
638 if (request->status & ATA_S_ERROR)
639 request->error = prb->fis[3];
642 /* SOS XXX handle other controller errors here */
644 /* initialize port */
645 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
647 /* poll for port ready */
648 for (timeout = 0; timeout < 1000; timeout++) {
650 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
655 device_printf(ch->dev, "port initialize timeout\n");
657 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
661 /* Read back registers to the request struct. */
662 if ((request->flags & ATA_R_ATAPI) == 0 &&
663 ((request->status & ATA_S_ERROR) ||
664 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
665 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
666 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
667 ((u_int64_t)prb->fis[6] << 16);
668 if (request->flags & ATA_R_48BIT)
669 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
670 ((u_int64_t)prb->fis[9] << 32) |
671 ((u_int64_t)prb->fis[10] << 40);
673 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
676 /* update progress */
677 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
678 if (request->flags & ATA_R_READ)
679 request->donecount = le32toh(prb->transfer_count);
681 request->donecount = request->bytecount;
684 /* release SG list etc */
685 ch->dma.unload(request);
687 return ATA_OP_FINISHED;
691 ata_siiprb_issue_cmd(device_t dev)
693 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
694 struct ata_channel *ch = device_get_softc(dev);
695 u_int64_t prb_bus = ch->dma.work_bus;
697 int offset = ch->unit * 0x2000;
700 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
702 /* issue command to chip */
703 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
704 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
706 /* poll for command finished */
707 for (timeout = 0; timeout < 10000; timeout++) {
709 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
713 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
715 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
716 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
722 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
728 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
730 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
731 struct ata_channel *ch = device_get_softc(dev);
732 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
733 int offset = ch->unit * 0x2000;
736 *result = ATA_IDX_INL(ch, reg);
754 bzero(prb, sizeof(struct ata_siiprb_command));
755 prb->fis[0] = 0x27; /* host to device */
756 prb->fis[1] = 0x8f; /* command FIS to PM port */
757 prb->fis[2] = ATA_READ_PM;
760 if (ata_siiprb_issue_cmd(dev)) {
761 device_printf(dev, "error reading PM port\n");
764 prb = (struct ata_siiprb_command *)
765 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
766 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
771 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
773 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
774 struct ata_channel *ch = device_get_softc(dev);
775 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
776 int offset = ch->unit * 0x2000;
779 ATA_IDX_OUTL(ch, reg, value);
797 bzero(prb, sizeof(struct ata_siiprb_command));
798 prb->fis[0] = 0x27; /* host to device */
799 prb->fis[1] = 0x8f; /* command FIS to PM port */
800 prb->fis[2] = ATA_WRITE_PM;
803 prb->fis[12] = value & 0xff;
804 prb->fis[4] = (value >> 8) & 0xff;
805 prb->fis[5] = (value >> 16) & 0xff;
806 prb->fis[6] = (value >> 24) & 0xff;
807 if (ata_siiprb_issue_cmd(dev)) {
808 device_printf(dev, "error writing PM port\n");
811 prb = (struct ata_siiprb_command *)
812 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
817 ata_siiprb_softreset(device_t dev, int port)
819 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
820 struct ata_channel *ch = device_get_softc(dev);
821 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
823 int offset = ch->unit * 0x2000;
825 /* setup the workspace for a soft reset command */
826 bzero(prb, sizeof(struct ata_siiprb_command));
827 prb->control = htole16(0x0080);
828 prb->fis[1] = port & 0x0f;
830 /* issue soft reset */
831 if (ata_siiprb_issue_cmd(dev))
836 /* get possible signature */
837 prb = (struct ata_siiprb_command *)
838 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
839 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
841 /* clear error bits/interrupt */
842 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
848 ata_siiprb_reset(device_t dev)
850 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
851 struct ata_channel *ch = device_get_softc(dev);
852 int offset = ch->unit * 0x2000;
853 u_int32_t status, signature;
856 /* disable interrupts */
857 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
859 /* reset channel HW */
860 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
862 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
865 /* poll for channel ready */
866 for (timeout = 0; timeout < 1000; timeout++) {
867 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
874 device_printf(dev, "channel HW reset timeout\n");
876 device_printf(dev, "channel HW reset time=%dms\n", timeout);
880 if (!ata_sata_phy_reset(dev, -1, 1)) {
882 device_printf(dev, "phy reset found no device\n");
887 /* issue soft reset */
888 signature = ata_siiprb_softreset(dev, ATA_PM);
890 device_printf(dev, "SIGNATURE=%08x\n", signature);
892 /* figure out whats there */
893 switch (signature >> 16) {
895 ch->devices = ATA_ATA_MASTER;
898 ch->devices = ATA_PORTMULTIPLIER;
899 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
900 //SOS XXX need to clear all PM status and interrupts!!!!
901 ata_pm_identify(dev);
904 ch->devices = ATA_ATAPI_MASTER;
910 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
913 /* clear interrupt(s) */
914 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
916 /* require explicit interrupt ack */
917 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
920 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
922 /* enable interrupts wanted */
923 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
927 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
929 struct ata_dmasetprd_args *args = xsc;
930 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
933 if ((args->error = error))
936 for (i = 0; i < nsegs; i++) {
937 prd[i].addr = htole64(segs[i].ds_addr);
938 prd[i].count = htole32(segs[i].ds_len);
940 prd[i - 1].control = htole32(ATA_DMA_EOT);
941 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
946 ata_siiprb_dmainit(device_t dev)
948 struct ata_channel *ch = device_get_softc(dev);
950 /* note start and stop are not used here */
951 ch->dma.setprd = ata_siiprb_dmasetprd;
952 ch->dma.max_address = BUS_SPACE_MAXADDR;
953 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
957 ATA_DECLARE_DRIVER(ata_sii);