2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ah_eeprom.h" /* for 5ghz fast clock flag */
26 #include "ar5416/ar5416reg.h" /* NB: includes ar5212reg.h */
28 /* linker set of registered chips */
29 OS_SET_DECLARE(ah_chips, struct ath_hal_chip);
32 * Check the set of registered chips to see if any recognize
33 * the device as one they can support.
36 ath_hal_probe(uint16_t vendorid, uint16_t devid)
38 struct ath_hal_chip * const *pchip;
40 OS_SET_FOREACH(pchip, ah_chips) {
41 const char *name = (*pchip)->probe(vendorid, devid);
49 * Attach detects device chip revisions, initializes the hwLayer
50 * function list, reads EEPROM information,
51 * selects reset vectors, and performs a short self test.
52 * Any failures will return an error that should cause a hardware
56 ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
57 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *error)
59 struct ath_hal_chip * const *pchip;
61 OS_SET_FOREACH(pchip, ah_chips) {
62 struct ath_hal_chip *chip = *pchip;
65 /* XXX don't have vendorid, assume atheros one works */
66 if (chip->probe(ATHEROS_VENDOR_ID, devid) == AH_NULL)
68 ah = chip->attach(devid, sc, st, sh, eepromdata, error);
70 /* copy back private state to public area */
71 ah->ah_devid = AH_PRIVATE(ah)->ah_devid;
72 ah->ah_subvendorid = AH_PRIVATE(ah)->ah_subvendorid;
73 ah->ah_macVersion = AH_PRIVATE(ah)->ah_macVersion;
74 ah->ah_macRev = AH_PRIVATE(ah)->ah_macRev;
75 ah->ah_phyRev = AH_PRIVATE(ah)->ah_phyRev;
76 ah->ah_analog5GhzRev = AH_PRIVATE(ah)->ah_analog5GhzRev;
77 ah->ah_analog2GhzRev = AH_PRIVATE(ah)->ah_analog2GhzRev;
85 ath_hal_mac_name(struct ath_hal *ah)
87 switch (ah->ah_macVersion) {
88 case AR_SREV_VERSION_CRETE:
89 case AR_SREV_VERSION_MAUI_1:
91 case AR_SREV_VERSION_MAUI_2:
92 case AR_SREV_VERSION_OAHU:
94 case AR_SREV_VERSION_VENICE:
96 case AR_SREV_VERSION_GRIFFIN:
98 case AR_SREV_VERSION_CONDOR:
100 case AR_SREV_VERSION_EAGLE:
102 case AR_SREV_VERSION_COBRA:
108 case AR_XSREV_VERSION_OWL_PCI:
110 case AR_XSREV_VERSION_OWL_PCIE:
112 case AR_XSREV_VERSION_HOWL:
114 case AR_XSREV_VERSION_SOWL:
116 case AR_XSREV_VERSION_MERLIN:
118 case AR_XSREV_VERSION_KITE:
120 case AR_XSREV_VERSION_KIWI:
127 * Return the mask of available modes based on the hardware capabilities.
130 ath_hal_getwirelessmodes(struct ath_hal*ah)
132 return ath_hal_getWirelessModes(ah);
135 /* linker set of registered RF backends */
136 OS_SET_DECLARE(ah_rfs, struct ath_hal_rf);
139 * Check the set of registered RF backends to see if
140 * any recognize the device as one they can support.
143 ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)
145 struct ath_hal_rf * const *prf;
147 OS_SET_FOREACH(prf, ah_rfs) {
148 struct ath_hal_rf *rf = *prf;
152 *ecode = HAL_ENOTSUPP;
157 ath_hal_rf_name(struct ath_hal *ah)
159 switch (ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
161 return "5110"; /* NB: made up */
162 case AR_RAD5111_SREV_MAJOR:
163 case AR_RAD5111_SREV_PROD:
165 case AR_RAD2111_SREV_MAJOR:
167 case AR_RAD5112_SREV_MAJOR:
168 case AR_RAD5112_SREV_2_0:
169 case AR_RAD5112_SREV_2_1:
171 case AR_RAD2112_SREV_MAJOR:
172 case AR_RAD2112_SREV_2_0:
173 case AR_RAD2112_SREV_2_1:
175 case AR_RAD2413_SREV_MAJOR:
177 case AR_RAD5413_SREV_MAJOR:
179 case AR_RAD2316_SREV_MAJOR:
181 case AR_RAD2317_SREV_MAJOR:
183 case AR_RAD5424_SREV_MAJOR:
186 case AR_RAD5133_SREV_MAJOR:
188 case AR_RAD2133_SREV_MAJOR:
190 case AR_RAD5122_SREV_MAJOR:
192 case AR_RAD2122_SREV_MAJOR:
199 * Poll the register looking for a specific value.
202 ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)
204 #define AH_TIMEOUT 1000
205 return ath_hal_waitfor(ah, reg, mask, val, AH_TIMEOUT);
210 ath_hal_waitfor(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val, uint32_t timeout)
214 for (i = 0; i < timeout; i++) {
215 if ((OS_REG_READ(ah, reg) & mask) == val)
219 HALDEBUG(ah, HAL_DEBUG_REGIO | HAL_DEBUG_PHYIO,
220 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
221 __func__, reg, OS_REG_READ(ah, reg), mask, val);
226 * Reverse the bits starting at the low bit for a value of
230 ath_hal_reverseBits(uint32_t val, uint32_t n)
235 for (i = 0, retval = 0; i < n; i++) {
236 retval = (retval << 1) | (val & 1);
242 /* 802.11n related timing definitions */
244 #define OFDM_PLCP_BITS 22
250 #define HT_LTF(n) ((n) * 4)
252 #define HT_RC_2_MCS(_rc) ((_rc) & 0xf)
253 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
254 #define IS_HT_RATE(_rc) ( (_rc) & IEEE80211_RATE_MCS)
257 * Calculate the duration of a packet whether it is 11n or legacy.
260 ath_hal_pkt_txtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, uint32_t frameLen,
261 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble)
266 rc = rates->info[rateix].rateCode;
268 /* Legacy rate? Return the old way */
269 if (! IS_HT_RATE(rc))
270 return ath_hal_computetxtime(ah, rates, frameLen, rateix, shortPreamble);
272 /* 11n frame - extract out the number of spatial streams */
273 numStreams = HT_RC_2_STREAMS(rc);
274 KASSERT(numStreams == 1 || numStreams == 2, ("number of spatial streams needs to be 1 or 2: MCS rate 0x%x!", rateix));
276 return ath_computedur_ht(frameLen, rc, numStreams, isht40, shortPreamble);
280 * Calculate the transmit duration of an 11n frame.
281 * This only works for MCS0->MCS15.
284 ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams, HAL_BOOL isht40,
287 static const uint16_t ht20_bps[16] = {
288 26, 52, 78, 104, 156, 208, 234, 260,
289 52, 104, 156, 208, 312, 416, 468, 520
291 static const uint16_t ht40_bps[16] = {
292 54, 108, 162, 216, 324, 432, 486, 540,
293 108, 216, 324, 432, 648, 864, 972, 1080,
295 uint32_t bitsPerSymbol, numBits, numSymbols, txTime;
297 KASSERT(rate & IEEE80211_RATE_MCS, ("not mcs %d", rate));
298 KASSERT((rate &~ IEEE80211_RATE_MCS) < 16, ("bad mcs 0x%x", rate));
301 bitsPerSymbol = ht40_bps[rate & 0xf];
303 bitsPerSymbol = ht20_bps[rate & 0xf];
304 numBits = OFDM_PLCP_BITS + (frameLen << 3);
305 numSymbols = howmany(numBits, bitsPerSymbol);
307 txTime = ((numSymbols * 18) + 4) / 5; /* 3.6us */
309 txTime = numSymbols * 4; /* 4us */
310 return txTime + HT_L_STF + HT_L_LTF +
311 HT_L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
315 * Compute the time to transmit a frame of length frameLen bytes
316 * using the specified rate, phy, and short preamble setting.
319 ath_hal_computetxtime(struct ath_hal *ah,
320 const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix,
321 HAL_BOOL shortPreamble)
323 uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
326 /* Warn if this function is called for 11n rates; it should not be! */
327 if (IS_HT_RATE(rates->info[rateix].rateCode))
328 ath_hal_printf(ah, "%s: MCS rate? (index %d; hwrate 0x%x)\n",
329 __func__, rateix, rates->info[rateix].rateCode);
331 kbps = rates->info[rateix].rateKbps;
333 * index can be invalid duting dynamic Turbo transitions.
338 switch (rates->info[rateix].phy) {
339 case IEEE80211_T_CCK:
340 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
341 if (shortPreamble && rates->info[rateix].shortPreamble)
343 numBits = frameLen << 3;
344 txTime = CCK_SIFS_TIME + phyTime
345 + ((numBits * 1000)/kbps);
347 case IEEE80211_T_OFDM:
348 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
349 HALASSERT(bitsPerSymbol != 0);
351 numBits = OFDM_PLCP_BITS + (frameLen << 3);
352 numSymbols = howmany(numBits, bitsPerSymbol);
353 txTime = OFDM_SIFS_TIME
355 + (numSymbols * OFDM_SYMBOL_TIME);
357 case IEEE80211_T_OFDM_HALF:
358 bitsPerSymbol = (kbps * OFDM_HALF_SYMBOL_TIME) / 1000;
359 HALASSERT(bitsPerSymbol != 0);
361 numBits = OFDM_HALF_PLCP_BITS + (frameLen << 3);
362 numSymbols = howmany(numBits, bitsPerSymbol);
363 txTime = OFDM_HALF_SIFS_TIME
364 + OFDM_HALF_PREAMBLE_TIME
365 + (numSymbols * OFDM_HALF_SYMBOL_TIME);
367 case IEEE80211_T_OFDM_QUARTER:
368 bitsPerSymbol = (kbps * OFDM_QUARTER_SYMBOL_TIME) / 1000;
369 HALASSERT(bitsPerSymbol != 0);
371 numBits = OFDM_QUARTER_PLCP_BITS + (frameLen << 3);
372 numSymbols = howmany(numBits, bitsPerSymbol);
373 txTime = OFDM_QUARTER_SIFS_TIME
374 + OFDM_QUARTER_PREAMBLE_TIME
375 + (numSymbols * OFDM_QUARTER_SYMBOL_TIME);
377 case IEEE80211_T_TURBO:
378 bitsPerSymbol = (kbps * TURBO_SYMBOL_TIME) / 1000;
379 HALASSERT(bitsPerSymbol != 0);
381 numBits = TURBO_PLCP_BITS + (frameLen << 3);
382 numSymbols = howmany(numBits, bitsPerSymbol);
383 txTime = TURBO_SIFS_TIME
384 + TURBO_PREAMBLE_TIME
385 + (numSymbols * TURBO_SYMBOL_TIME);
388 HALDEBUG(ah, HAL_DEBUG_PHYIO,
389 "%s: unknown phy %u (rate ix %u)\n",
390 __func__, rates->info[rateix].phy, rateix);
398 WIRELESS_MODE_11a = 0,
399 WIRELESS_MODE_TURBO = 1,
400 WIRELESS_MODE_11b = 2,
401 WIRELESS_MODE_11g = 3,
402 WIRELESS_MODE_108g = 4,
408 ath_hal_chan2wmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
410 if (IEEE80211_IS_CHAN_B(chan))
411 return WIRELESS_MODE_11b;
412 if (IEEE80211_IS_CHAN_G(chan))
413 return WIRELESS_MODE_11g;
414 if (IEEE80211_IS_CHAN_108G(chan))
415 return WIRELESS_MODE_108g;
416 if (IEEE80211_IS_CHAN_TURBO(chan))
417 return WIRELESS_MODE_TURBO;
418 return WIRELESS_MODE_11a;
422 * Convert between microseconds and core system clocks.
424 /* 11a Turbo 11b 11g 108g */
425 static const uint8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88 };
427 #define CLOCK_FAST_RATE_5GHZ_OFDM 44
430 ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
432 const struct ieee80211_channel *c = AH_PRIVATE(ah)->ah_curchan;
435 /* NB: ah_curchan may be null when called attach time */
436 /* XXX merlin and later specific workaround - 5ghz fast clock is 44 */
437 if (c != AH_NULL && IS_5GHZ_FAST_CLOCK_EN(ah, c)) {
438 clks = usecs * CLOCK_FAST_RATE_5GHZ_OFDM;
439 if (IEEE80211_IS_CHAN_HT40(c))
441 } else if (c != AH_NULL) {
442 clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
443 if (IEEE80211_IS_CHAN_HT40(c))
446 clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
451 ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
453 const struct ieee80211_channel *c = AH_PRIVATE(ah)->ah_curchan;
456 /* NB: ah_curchan may be null when called attach time */
457 /* XXX merlin and later specific workaround - 5ghz fast clock is 44 */
458 if (c != AH_NULL && IS_5GHZ_FAST_CLOCK_EN(ah, c)) {
459 usec = clks / CLOCK_FAST_RATE_5GHZ_OFDM;
460 if (IEEE80211_IS_CHAN_HT40(c))
462 } else if (c != AH_NULL) {
463 usec = clks / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
464 if (IEEE80211_IS_CHAN_HT40(c))
467 usec = clks / CLOCK_RATE[WIRELESS_MODE_11b];
472 * Setup a h/w rate table's reverse lookup table and
473 * fill in ack durations. This routine is called for
474 * each rate table returned through the ah_getRateTable
475 * method. The reverse lookup tables are assumed to be
476 * initialized to zero (or at least the first entry).
477 * We use this as a key that indicates whether or not
478 * we've previously setup the reverse lookup table.
480 * XXX not reentrant, but shouldn't matter
483 ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt)
485 #define N(a) (sizeof(a)/sizeof(a[0]))
488 if (rt->rateCodeToIndex[0] != 0) /* already setup */
490 for (i = 0; i < N(rt->rateCodeToIndex); i++)
491 rt->rateCodeToIndex[i] = (uint8_t) -1;
492 for (i = 0; i < rt->rateCount; i++) {
493 uint8_t code = rt->info[i].rateCode;
494 uint8_t cix = rt->info[i].controlRate;
496 HALASSERT(code < N(rt->rateCodeToIndex));
497 rt->rateCodeToIndex[code] = i;
498 HALASSERT((code | rt->info[i].shortPreamble) <
499 N(rt->rateCodeToIndex));
500 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
502 * XXX for 11g the control rate to use for 5.5 and 11 Mb/s
503 * depends on whether they are marked as basic rates;
504 * the static tables are setup with an 11b-compatible
505 * 2Mb/s rate which will work but is suboptimal
507 rt->info[i].lpAckDuration = ath_hal_computetxtime(ah, rt,
508 WLAN_CTRL_FRAME_SIZE, cix, AH_FALSE);
509 rt->info[i].spAckDuration = ath_hal_computetxtime(ah, rt,
510 WLAN_CTRL_FRAME_SIZE, cix, AH_TRUE);
516 ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
517 uint32_t capability, uint32_t *result)
519 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
522 case HAL_CAP_REG_DMN: /* regulatory domain */
523 *result = AH_PRIVATE(ah)->ah_currentRD;
525 case HAL_CAP_DFS_DMN: /* DFS Domain */
526 *result = AH_PRIVATE(ah)->ah_dfsDomain;
528 case HAL_CAP_CIPHER: /* cipher handled in hardware */
529 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
531 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
533 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
534 return pCap->halHwPhyCounterSupport ? HAL_OK : HAL_ENXIO;
535 case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC when WMM is turned on */
537 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
539 case HAL_CAP_KEYCACHE_SIZE: /* hardware key cache size */
540 *result = pCap->halKeyCacheSize;
542 case HAL_CAP_NUM_TXQUEUES: /* number of hardware tx queues */
543 *result = pCap->halTotalQueues;
545 case HAL_CAP_VEOL: /* hardware supports virtual EOL */
546 return pCap->halVEOLSupport ? HAL_OK : HAL_ENOTSUPP;
547 case HAL_CAP_PSPOLL: /* hardware PS-Poll support works */
548 return pCap->halPSPollBroken ? HAL_ENOTSUPP : HAL_OK;
549 case HAL_CAP_COMPRESSION:
550 return pCap->halCompressSupport ? HAL_OK : HAL_ENOTSUPP;
552 return pCap->halBurstSupport ? HAL_OK : HAL_ENOTSUPP;
553 case HAL_CAP_FASTFRAME:
554 return pCap->halFastFramesSupport ? HAL_OK : HAL_ENOTSUPP;
555 case HAL_CAP_DIAG: /* hardware diagnostic support */
556 *result = AH_PRIVATE(ah)->ah_diagreg;
558 case HAL_CAP_TXPOW: /* global tx power limit */
559 switch (capability) {
560 case 0: /* facility is supported */
562 case 1: /* current limit */
563 *result = AH_PRIVATE(ah)->ah_powerLimit;
565 case 2: /* current max tx power */
566 *result = AH_PRIVATE(ah)->ah_maxPowerLevel;
568 case 3: /* scale factor */
569 *result = AH_PRIVATE(ah)->ah_tpScale;
573 case HAL_CAP_BSSIDMASK: /* hardware supports bssid mask */
574 return pCap->halBssIdMaskSupport ? HAL_OK : HAL_ENOTSUPP;
575 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
576 return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENOTSUPP;
577 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
579 case HAL_CAP_RFSILENT: /* rfsilent support */
580 switch (capability) {
581 case 0: /* facility is supported */
582 return pCap->halRfSilentSupport ? HAL_OK : HAL_ENOTSUPP;
583 case 1: /* current setting */
584 return AH_PRIVATE(ah)->ah_rfkillEnabled ?
585 HAL_OK : HAL_ENOTSUPP;
586 case 2: /* rfsilent config */
587 *result = AH_PRIVATE(ah)->ah_rfsilent;
595 return pCap->halHTSupport ? HAL_OK : HAL_ENOTSUPP;
597 return pCap->halGTTSupport ? HAL_OK : HAL_ENOTSUPP;
598 case HAL_CAP_FAST_CC:
599 return pCap->halFastCCSupport ? HAL_OK : HAL_ENOTSUPP;
600 case HAL_CAP_TX_CHAINMASK: /* mask of TX chains supported */
601 *result = pCap->halTxChainMask;
603 case HAL_CAP_RX_CHAINMASK: /* mask of RX chains supported */
604 *result = pCap->halRxChainMask;
606 case HAL_CAP_NUM_GPIO_PINS:
607 *result = pCap->halNumGpioPins;
610 return pCap->halCSTSupport ? HAL_OK : HAL_ENOTSUPP;
611 case HAL_CAP_RTS_AGGR_LIMIT:
612 *result = pCap->halRtsAggrLimit;
614 case HAL_CAP_4ADDR_AGGR:
615 return pCap->hal4AddrAggrSupport ? HAL_OK : HAL_ENOTSUPP;
616 case HAL_CAP_EXT_CHAN_DFS:
617 return pCap->halExtChanDfsSupport ? HAL_OK : HAL_ENOTSUPP;
618 case HAL_CAP_COMBINED_RADAR_RSSI:
619 return pCap->halUseCombinedRadarRssi ? HAL_OK : HAL_ENOTSUPP;
620 case HAL_CAP_AUTO_SLEEP:
621 return pCap->halAutoSleepSupport ? HAL_OK : HAL_ENOTSUPP;
622 case HAL_CAP_MBSSID_AGGR_SUPPORT:
623 return pCap->halMbssidAggrSupport ? HAL_OK : HAL_ENOTSUPP;
624 case HAL_CAP_SPLIT_4KB_TRANS: /* hardware handles descriptors straddling 4k page boundary */
625 return pCap->hal4kbSplitTransSupport ? HAL_OK : HAL_ENOTSUPP;
626 case HAL_CAP_REG_FLAG:
627 *result = AH_PRIVATE(ah)->ah_currentRDext;
629 case HAL_CAP_BT_COEX:
630 return pCap->halBtCoexSupport ? HAL_OK : HAL_ENOTSUPP;
631 case HAL_CAP_HT20_SGI:
632 return pCap->halHTSGI20Support ? HAL_OK : HAL_ENOTSUPP;
633 case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
634 *result = pCap->halTstampPrecision;
636 case HAL_CAP_ENHANCED_DFS_SUPPORT:
637 return pCap->halEnhancedDfsSupport ? HAL_OK : HAL_ENOTSUPP;
639 /* FreeBSD-specific entries for now */
640 case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
641 return AH_PRIVATE(ah)->ah_rxornIsFatal ? HAL_OK : HAL_ENOTSUPP;
642 case HAL_CAP_INTRMASK: /* mask of supported interrupts */
643 *result = pCap->halIntrMask;
645 case HAL_CAP_BSSIDMATCH: /* hardware has disable bssid match */
646 return pCap->halBssidMatchSupport ? HAL_OK : HAL_ENOTSUPP;
647 case HAL_CAP_STREAMS: /* number of 11n spatial streams */
648 switch (capability) {
650 *result = pCap->halTxStreams;
653 *result = pCap->halRxStreams;
658 case HAL_CAP_RXDESC_SELFLINK: /* hardware supports self-linked final RX descriptors correctly */
659 return pCap->halHasRxSelfLinkedTail ? HAL_OK : HAL_ENOTSUPP;
660 case HAL_CAP_LONG_RXDESC_TSF: /* 32 bit TSF in RX descriptor? */
661 return pCap->halHasLongRxDescTsf ? HAL_OK : HAL_ENOTSUPP;
668 ath_hal_setcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
669 uint32_t capability, uint32_t setting, HAL_STATUS *status)
674 switch (capability) {
676 if (setting <= HAL_TP_SCALE_MIN) {
677 AH_PRIVATE(ah)->ah_tpScale = setting;
683 case HAL_CAP_RFSILENT: /* rfsilent support */
685 * NB: allow even if halRfSilentSupport is false
686 * in case the EEPROM is misprogrammed.
688 switch (capability) {
689 case 1: /* current setting */
690 AH_PRIVATE(ah)->ah_rfkillEnabled = (setting != 0);
692 case 2: /* rfsilent config */
693 /* XXX better done per-chip for validation? */
694 AH_PRIVATE(ah)->ah_rfsilent = setting;
698 case HAL_CAP_REG_DMN: /* regulatory domain */
699 AH_PRIVATE(ah)->ah_currentRD = setting;
701 case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
702 AH_PRIVATE(ah)->ah_rxornIsFatal = setting;
708 *status = HAL_EINVAL;
713 * Common support for getDiagState method.
717 ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,
718 void *dstbuf, int space)
720 uint32_t *dp = dstbuf;
723 for (i = 0; space >= 2*sizeof(uint32_t); i++) {
724 u_int r = regs[i].start;
725 u_int e = regs[i].end;
727 space -= sizeof(uint32_t);
729 *dp++ = OS_REG_READ(ah, r);
730 r += sizeof(uint32_t);
731 space -= sizeof(uint32_t);
732 } while (r <= e && space >= sizeof(uint32_t));
734 return (char *) dp - (char *) dstbuf;
738 ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space)
740 while (space >= sizeof(HAL_REGWRITE)) {
741 OS_REG_WRITE(ah, regs->addr, regs->value);
742 regs++, space -= sizeof(HAL_REGWRITE);
747 ath_hal_getdiagstate(struct ath_hal *ah, int request,
748 const void *args, uint32_t argsize,
749 void **result, uint32_t *resultsize)
753 *result = &AH_PRIVATE(ah)->ah_devid;
754 *resultsize = sizeof(HAL_REVS);
757 *resultsize = ath_hal_getregdump(ah, args, *result,*resultsize);
759 case HAL_DIAG_SETREGS:
760 ath_hal_setregs(ah, args, argsize);
763 case HAL_DIAG_FATALERR:
764 *result = &AH_PRIVATE(ah)->ah_fatalState[0];
765 *resultsize = sizeof(AH_PRIVATE(ah)->ah_fatalState);
767 case HAL_DIAG_EEREAD:
768 if (argsize != sizeof(uint16_t))
770 if (!ath_hal_eepromRead(ah, *(const uint16_t *)args, *result))
772 *resultsize = sizeof(uint16_t);
774 #ifdef AH_PRIVATE_DIAG
775 case HAL_DIAG_SETKEY: {
776 const HAL_DIAG_KEYVAL *dk;
778 if (argsize != sizeof(HAL_DIAG_KEYVAL))
780 dk = (const HAL_DIAG_KEYVAL *)args;
781 return ah->ah_setKeyCacheEntry(ah, dk->dk_keyix,
782 &dk->dk_keyval, dk->dk_mac, dk->dk_xor);
784 case HAL_DIAG_RESETKEY:
785 if (argsize != sizeof(uint16_t))
787 return ah->ah_resetKeyCacheEntry(ah, *(const uint16_t *)args);
788 #ifdef AH_SUPPORT_WRITE_EEPROM
789 case HAL_DIAG_EEWRITE: {
790 const HAL_DIAG_EEVAL *ee;
791 if (argsize != sizeof(HAL_DIAG_EEVAL))
793 ee = (const HAL_DIAG_EEVAL *)args;
794 return ath_hal_eepromWrite(ah, ee->ee_off, ee->ee_data);
796 #endif /* AH_SUPPORT_WRITE_EEPROM */
797 #endif /* AH_PRIVATE_DIAG */
798 case HAL_DIAG_11NCOMPAT:
800 *resultsize = sizeof(uint32_t);
801 *((uint32_t *)(*result)) =
802 AH_PRIVATE(ah)->ah_11nCompat;
803 } else if (argsize == sizeof(uint32_t)) {
804 AH_PRIVATE(ah)->ah_11nCompat = *(const uint32_t *)args;
813 * Set the properties of the tx queue with the parameters
817 ath_hal_setTxQProps(struct ath_hal *ah,
818 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo)
822 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
823 HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
824 "%s: inactive queue\n", __func__);
827 /* XXX validate parameters */
828 qi->tqi_ver = qInfo->tqi_ver;
829 qi->tqi_subtype = qInfo->tqi_subtype;
830 qi->tqi_qflags = qInfo->tqi_qflags;
831 qi->tqi_priority = qInfo->tqi_priority;
832 if (qInfo->tqi_aifs != HAL_TXQ_USEDEFAULT)
833 qi->tqi_aifs = AH_MIN(qInfo->tqi_aifs, 255);
835 qi->tqi_aifs = INIT_AIFS;
836 if (qInfo->tqi_cwmin != HAL_TXQ_USEDEFAULT) {
837 cw = AH_MIN(qInfo->tqi_cwmin, 1024);
838 /* make sure that the CWmin is of the form (2^n - 1) */
840 while (qi->tqi_cwmin < cw)
841 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
843 qi->tqi_cwmin = qInfo->tqi_cwmin;
844 if (qInfo->tqi_cwmax != HAL_TXQ_USEDEFAULT) {
845 cw = AH_MIN(qInfo->tqi_cwmax, 1024);
846 /* make sure that the CWmax is of the form (2^n - 1) */
848 while (qi->tqi_cwmax < cw)
849 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
851 qi->tqi_cwmax = INIT_CWMAX;
852 /* Set retry limit values */
853 if (qInfo->tqi_shretry != 0)
854 qi->tqi_shretry = AH_MIN(qInfo->tqi_shretry, 15);
856 qi->tqi_shretry = INIT_SH_RETRY;
857 if (qInfo->tqi_lgretry != 0)
858 qi->tqi_lgretry = AH_MIN(qInfo->tqi_lgretry, 15);
860 qi->tqi_lgretry = INIT_LG_RETRY;
861 qi->tqi_cbrPeriod = qInfo->tqi_cbrPeriod;
862 qi->tqi_cbrOverflowLimit = qInfo->tqi_cbrOverflowLimit;
863 qi->tqi_burstTime = qInfo->tqi_burstTime;
864 qi->tqi_readyTime = qInfo->tqi_readyTime;
866 switch (qInfo->tqi_subtype) {
868 if (qi->tqi_type == HAL_TX_QUEUE_DATA)
869 qi->tqi_intFlags = HAL_TXQ_USE_LOCKOUT_BKOFF_DIS;
872 break; /* NB: silence compiler */
878 ath_hal_getTxQProps(struct ath_hal *ah,
879 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi)
881 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
882 HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
883 "%s: inactive queue\n", __func__);
887 qInfo->tqi_qflags = qi->tqi_qflags;
888 qInfo->tqi_ver = qi->tqi_ver;
889 qInfo->tqi_subtype = qi->tqi_subtype;
890 qInfo->tqi_qflags = qi->tqi_qflags;
891 qInfo->tqi_priority = qi->tqi_priority;
892 qInfo->tqi_aifs = qi->tqi_aifs;
893 qInfo->tqi_cwmin = qi->tqi_cwmin;
894 qInfo->tqi_cwmax = qi->tqi_cwmax;
895 qInfo->tqi_shretry = qi->tqi_shretry;
896 qInfo->tqi_lgretry = qi->tqi_lgretry;
897 qInfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
898 qInfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
899 qInfo->tqi_burstTime = qi->tqi_burstTime;
900 qInfo->tqi_readyTime = qi->tqi_readyTime;
904 /* 11a Turbo 11b 11g 108g */
905 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93 };
908 * Read the current channel noise floor and return.
909 * If nf cal hasn't finished, channel noise floor should be 0
910 * and we return a nominal value based on band and frequency.
912 * NB: This is a private routine used by per-chip code to
913 * implement the ah_getChanNoise method.
916 ath_hal_getChanNoise(struct ath_hal *ah, const struct ieee80211_channel *chan)
918 HAL_CHANNEL_INTERNAL *ichan;
920 ichan = ath_hal_checkchannel(ah, chan);
921 if (ichan == AH_NULL) {
922 HALDEBUG(ah, HAL_DEBUG_NFCAL,
923 "%s: invalid channel %u/0x%x; no mapping\n",
924 __func__, chan->ic_freq, chan->ic_flags);
927 if (ichan->rawNoiseFloor == 0) {
928 WIRELESS_MODE mode = ath_hal_chan2wmode(ah, chan);
930 HALASSERT(mode < WIRELESS_MODE_MAX);
931 return NOISE_FLOOR[mode] + ath_hal_getNfAdjust(ah, ichan);
933 return ichan->rawNoiseFloor + ichan->noiseFloorAdjust;
937 * Fetch the current setup of ctl/ext noise floor values.
939 * If the CHANNEL_MIMO_NF_VALID flag isn't set, the array is simply
940 * populated with values from NOISE_FLOOR[] + ath_hal_getNfAdjust().
942 * The caller must supply ctl/ext NF arrays which are at least
943 * AH_MIMO_MAX_CHAINS entries long.
946 ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
947 const struct ieee80211_channel *chan, int16_t *nf_ctl,
950 #ifdef AH_SUPPORT_AR5416
951 HAL_CHANNEL_INTERNAL *ichan;
954 ichan = ath_hal_checkchannel(ah, chan);
955 if (ichan == AH_NULL) {
956 HALDEBUG(ah, HAL_DEBUG_NFCAL,
957 "%s: invalid channel %u/0x%x; no mapping\n",
958 __func__, chan->ic_freq, chan->ic_flags);
959 for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
960 nf_ctl[i] = nf_ext[i] = 0;
965 /* Return 0 if there's no valid MIMO values (yet) */
966 if (! (ichan->privFlags & CHANNEL_MIMO_NF_VALID)) {
967 for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
968 nf_ctl[i] = nf_ext[i] = 0;
972 if (ichan->rawNoiseFloor == 0) {
973 WIRELESS_MODE mode = ath_hal_chan2wmode(ah, chan);
974 HALASSERT(mode < WIRELESS_MODE_MAX);
976 * See the comment below - this could cause issues for
977 * stations which have a very low RSSI, below the
978 * 'normalised' NF values in NOISE_FLOOR[].
980 for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
981 nf_ctl[i] = nf_ext[i] = NOISE_FLOOR[mode] +
982 ath_hal_getNfAdjust(ah, ichan);
987 * The value returned here from a MIMO radio is presumed to be
988 * "good enough" as a NF calculation. As RSSI values are calculated
989 * against this, an adjusted NF may be higher than the RSSI value
990 * returned from a vary weak station, resulting in an obscenely
991 * high signal strength calculation being returned.
993 * This should be re-evaluated at a later date, along with any
994 * signal strength calculations which are made. Quite likely the
995 * RSSI values will need to be adjusted to ensure the calculations
996 * don't "wrap" when RSSI is less than the "adjusted" NF value.
997 * ("Adjust" here is via ichan->noiseFloorAdjust.)
999 for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
1000 nf_ctl[i] = ichan->noiseFloorCtl[i] + ath_hal_getNfAdjust(ah, ichan);
1001 nf_ext[i] = ichan->noiseFloorExt[i] + ath_hal_getNfAdjust(ah, ichan);
1007 #endif /* AH_SUPPORT_AR5416 */
1011 * Process all valid raw noise floors into the dBm noise floor values.
1012 * Though our device has no reference for a dBm noise floor, we perform
1013 * a relative minimization of NF's based on the lowest NF found across a
1017 ath_hal_process_noisefloor(struct ath_hal *ah)
1019 HAL_CHANNEL_INTERNAL *c;
1020 int16_t correct2, correct5;
1021 int16_t lowest2, lowest5;
1025 * Find the lowest 2GHz and 5GHz noise floor values after adjusting
1026 * for statistically recorded NF/channel deviation.
1028 correct2 = lowest2 = 0;
1029 correct5 = lowest5 = 0;
1030 for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {
1034 c = &AH_PRIVATE(ah)->ah_channels[i];
1035 if (c->rawNoiseFloor >= 0)
1037 /* XXX can't identify proper mode */
1038 mode = IS_CHAN_5GHZ(c) ? WIRELESS_MODE_11a : WIRELESS_MODE_11g;
1039 nf = c->rawNoiseFloor + NOISE_FLOOR[mode] +
1040 ath_hal_getNfAdjust(ah, c);
1041 if (IS_CHAN_5GHZ(c)) {
1044 correct5 = NOISE_FLOOR[mode] -
1045 (c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));
1050 correct2 = NOISE_FLOOR[mode] -
1051 (c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));
1056 /* Correct the channels to reach the expected NF value */
1057 for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {
1058 c = &AH_PRIVATE(ah)->ah_channels[i];
1059 if (c->rawNoiseFloor >= 0)
1061 /* Apply correction factor */
1062 c->noiseFloorAdjust = ath_hal_getNfAdjust(ah, c) +
1063 (IS_CHAN_5GHZ(c) ? correct5 : correct2);
1064 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%u raw nf %d adjust %d\n",
1065 c->channel, c->rawNoiseFloor, c->noiseFloorAdjust);
1070 * INI support routines.
1074 ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
1079 HALASSERT(col < ia->cols);
1080 for (r = 0; r < ia->rows; r++) {
1081 OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0),
1082 HAL_INI_VAL(ia, r, col));
1084 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */
1085 if (HAL_INI_VAL(ia, r, 0) >= 0x7800 && HAL_INI_VAL(ia, r, 0) < 0x7900)
1094 ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, int col)
1098 HALASSERT(col < ia->cols);
1099 for (r = 0; r < ia->rows; r++)
1100 data[r] = HAL_INI_VAL(ia, r, col);
1104 ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
1105 const uint32_t data[], int regWr)
1109 for (r = 0; r < ia->rows; r++) {
1110 OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0), data[r]);
1117 * These are EEPROM board related routines which should likely live in
1118 * a helper library of some sort.
1121 /**************************************************************
1122 * ath_ee_getLowerUppderIndex
1124 * Return indices surrounding the value in sorted integer lists.
1125 * Requirement: the input list must be monotonically increasing
1126 * and populated up to the list size
1127 * Returns: match is set if an index in the array matches exactly
1128 * or a the target is before or after the range of the array.
1131 ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
1132 uint16_t *indexL, uint16_t *indexR)
1137 * Check first and last elements for beyond ordered array cases.
1139 if (target <= pList[0]) {
1140 *indexL = *indexR = 0;
1143 if (target >= pList[listSize-1]) {
1144 *indexL = *indexR = (uint16_t)(listSize - 1);
1148 /* look for value being near or between 2 values in list */
1149 for (i = 0; i < listSize - 1; i++) {
1151 * If value is close to the current value of the list
1152 * then target is not between values, it is one of the values
1154 if (pList[i] == target) {
1155 *indexL = *indexR = i;
1159 * Look for value being between current value and next value
1160 * if so return these 2 values
1162 if (target < pList[i + 1]) {
1164 *indexR = (uint16_t)(i + 1);
1169 *indexL = *indexR = 0;
1173 /**************************************************************
1174 * ath_ee_FillVpdTable
1176 * Fill the Vpdlist for indices Pmax-Pmin
1177 * Note: pwrMin, pwrMax and Vpdlist are all in dBm * 4
1180 ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
1181 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
1184 uint8_t currPwr = pwrMin;
1185 uint16_t idxL, idxR;
1187 HALASSERT(pwrMax > pwrMin);
1188 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
1189 ath_ee_getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
1192 idxR = 1; /* extrapolate below */
1193 if (idxL == numIntercepts - 1)
1194 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */
1195 if (pPwrList[idxL] == pPwrList[idxR])
1198 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
1199 (pPwrList[idxR] - pPwrList[idxL]) );
1201 pRetVpdList[i] = (uint8_t)k;
1202 currPwr += 2; /* half dB steps */
1208 /**************************************************************************
1209 * ath_ee_interpolate
1211 * Returns signed interpolated or the scaled up interpolated value
1214 ath_ee_interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
1215 int16_t targetLeft, int16_t targetRight)
1219 if (srcRight == srcLeft) {
1222 rv = (int16_t)( ((target - srcLeft) * targetRight +
1223 (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
1232 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta)
1234 /* XXX handle wrap/overflow */
1235 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta);
1239 * Enable or disable CCA.
1242 ath_hal_setcca(struct ath_hal *ah, int ena)
1245 * NB: fill me in; this is not provided by default because disabling
1246 * CCA in most locales violates regulatory.
1254 ath_hal_getcca(struct ath_hal *ah)
1257 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK)
1259 return ((diag & 0x500000) == 0);