2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
25 #include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
27 #include "ar9002/ar9280.h"
28 #include "ar9002/ar9285.h"
29 #include "ar5416/ar5416reg.h"
30 #include "ar5416/ar5416phy.h"
32 #include "ar9002/ar9285.ini"
33 #include "ar9002/ar9285v2.ini"
34 #include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
36 #include "ar9002/ar9285_cal.h"
37 #include "ar9002/ar9285_phy.h"
38 #include "ar9002/ar9285_diversity.h"
40 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
41 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
42 .calNumSamples = MIN_CAL_SAMPLES,
43 .calCountMax = PER_MAX_LOG_COUNT,
44 .calCollect = ar5416IQCalCollect,
45 .calPostProc = ar5416IQCalibration
47 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
48 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
49 .calNumSamples = MIN_CAL_SAMPLES,
50 .calCountMax = PER_MIN_LOG_COUNT,
51 .calCollect = ar5416AdcGainCalCollect,
52 .calPostProc = ar5416AdcGainCalibration
54 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
55 .calName = "ADC DC", .calType = ADC_DC_CAL,
56 .calNumSamples = MIN_CAL_SAMPLES,
57 .calCountMax = PER_MIN_LOG_COUNT,
58 .calCollect = ar5416AdcDcCalCollect,
59 .calPostProc = ar5416AdcDcCalibration
61 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
62 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
63 .calNumSamples = MIN_CAL_SAMPLES,
64 .calCountMax = INIT_LOG_COUNT,
65 .calCollect = ar5416AdcDcCalCollect,
66 .calPostProc = ar5416AdcDcCalibration
69 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
70 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
71 static void ar9285WriteIni(struct ath_hal *ah,
72 const struct ieee80211_channel *chan);
75 ar9285AniSetup(struct ath_hal *ah)
78 * These are the parameters from the AR5416 ANI code;
79 * they likely need quite a bit of adjustment for the
82 static const struct ar5212AniParams aniparams = {
83 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
84 .totalSizeDesired = { -55, -55, -55, -55, -62 },
85 .coarseHigh = { -14, -14, -14, -14, -12 },
86 .coarseLow = { -64, -64, -64, -64, -70 },
87 .firpwr = { -78, -78, -78, -78, -80 },
88 .maxSpurImmunityLevel = 2,
89 .cycPwrThr1 = { 2, 4, 6 },
90 .maxFirstepLevel = 2, /* levels 0..2 */
91 .firstep = { 0, 4, 8 },
100 /* NB: disable ANI noise immmunity for reliable RIFS rx */
101 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
103 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
107 * Attach for an AR9285 part.
109 static struct ath_hal *
110 ar9285Attach(uint16_t devid, HAL_SOFTC sc,
111 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
114 struct ath_hal_9285 *ahp9285;
115 struct ath_hal_5212 *ahp;
121 HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
122 __func__, sc, (void*) st, (void*) sh);
124 /* NB: memory is returned zero'd */
125 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
126 if (ahp9285 == AH_NULL) {
127 HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
128 "%s: cannot allocate memory for state block\n", __func__);
129 *status = HAL_ENOMEM;
132 ahp = AH5212(ahp9285);
133 ah = &ahp->ah_priv.h;
135 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
137 /* XXX override with 9285 specific state */
138 /* override 5416 methods for our needs */
139 AH5416(ah)->ah_initPLL = ar9280InitPLL;
141 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
142 ah->ah_configPCIE = ar9285ConfigPCIE;
143 ah->ah_setTxPower = ar9285SetTransmitPower;
144 ah->ah_setBoardValues = ar9285SetBoardValues;
146 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
147 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
148 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
149 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
150 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
152 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
153 AH5416(ah)->ah_writeIni = ar9285WriteIni;
154 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
155 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
157 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
159 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
161 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
167 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
168 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
173 /* Read Revisions from Chips before taking out of reset */
174 val = OS_REG_READ(ah, AR_SREV);
175 HALDEBUG(ah, HAL_DEBUG_ATTACH,
176 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
177 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
178 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
179 /* NB: include chip type to differentiate from pre-Sowl versions */
180 AH_PRIVATE(ah)->ah_macVersion =
181 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
182 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
183 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
185 /* setup common ini data; rf backends handle remainder */
186 if (AR_SREV_KITE_12_OR_LATER(ah)) {
187 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
188 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
189 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
190 ar9285PciePhy_clkreq_always_on_L1_v2, 2);
192 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
193 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
194 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
195 ar9285PciePhy_clkreq_always_on_L1, 2);
197 ar5416AttachPCIE(ah);
199 /* Attach methods that require MAC version/revision info */
200 if (AR_SREV_KITE_12_OR_LATER(ah))
201 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
202 if (AR_SREV_KITE_11_OR_LATER(ah))
203 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
205 ecode = ath_hal_v4kEepromAttach(ah);
209 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
210 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
216 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
218 if (!ar5212ChipTest(ah)) {
219 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
221 ecode = HAL_ESELFTEST;
226 * Set correct Baseband to analog shift
227 * setting to access analog chips.
229 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
231 /* Read Radio Chip Rev Extract */
232 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
233 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
234 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
235 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
238 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
239 AH_PRIVATE(ah)->ah_analog5GhzRev =
240 AR_RAD5133_SREV_MAJOR;
244 HALDEBUG(ah, HAL_DEBUG_ANY,
245 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
246 "this driver\n", __func__,
247 AH_PRIVATE(ah)->ah_analog5GhzRev);
248 ecode = HAL_ENOTSUPP;
252 rfStatus = ar9285RfAttach(ah, &ecode);
254 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
259 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
262 if (AR_SREV_9285E_20(ah))
263 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
265 /* setup txgain table */
266 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
267 case AR5416_EEP_TXGAIN_HIGH_POWER:
268 if (AR_SREV_9285E_20(ah))
269 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
270 ar9285Modes_XE2_0_high_power, 6);
272 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
273 ar9285Modes_high_power_tx_gain_v2, 6);
275 case AR5416_EEP_TXGAIN_ORIG:
276 if (AR_SREV_9285E_20(ah))
277 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
278 ar9285Modes_XE2_0_normal_power, 6);
280 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
281 ar9285Modes_original_tx_gain_v2, 6);
285 goto bad; /* XXX ? try to continue */
289 * Got everything we need now to setup the capabilities.
291 if (!ar9285FillCapabilityInfo(ah)) {
296 /* Print out whether the EEPROM settings enable AR9285 diversity */
297 if (ar9285_check_div_comb(ah)) {
298 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
299 ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan;
302 /* Disable 11n for the AR2427 */
303 if (devid == AR2427_DEVID_PCIE)
304 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
306 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
307 if (ecode != HAL_OK) {
308 HALDEBUG(ah, HAL_DEBUG_ANY,
309 "%s: error getting mac address from EEPROM\n", __func__);
312 /* XXX How about the serial number ? */
313 /* Read Reg Domain */
314 AH_PRIVATE(ah)->ah_currentRD =
315 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
317 * For Kite and later chipsets, the following bits are not
318 * programmed in EEPROM and so are set as enabled always.
320 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
323 * ah_miscMode is populated by ar5416FillCapabilityInfo()
324 * starting from griffin. Set here to make sure that
325 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
326 * placed into hardware.
328 if (ahp->ah_miscMode != 0)
329 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
331 ar9285AniSetup(ah); /* Anti Noise Immunity */
333 /* Setup noise floor min/max/nominal values */
334 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
335 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
336 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
337 /* XXX no 5ghz values? */
339 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
341 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
353 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
355 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
356 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
358 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
359 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
364 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
366 u_int modesIndex, freqIndex;
369 /* Setup the indices for the next set of register array writes */
370 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
372 if (IEEE80211_IS_CHAN_HT40(chan))
374 else if (IEEE80211_IS_CHAN_108G(chan))
379 /* Set correct Baseband to analog shift setting to access analog chips. */
380 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
381 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
382 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
383 modesIndex, regWrites);
384 if (AR_SREV_KITE_12_OR_LATER(ah)) {
385 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
386 modesIndex, regWrites);
388 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
393 * Fill all software cached or static hardware state information.
394 * Return failure if capabilities are to come from EEPROM and
398 ar9285FillCapabilityInfo(struct ath_hal *ah)
400 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
402 if (!ar5416FillCapabilityInfo(ah))
404 pCap->halNumGpioPins = 12;
405 pCap->halWowSupport = AH_TRUE;
406 pCap->halWowMatchPatternExact = AH_TRUE;
408 pCap->halWowMatchPatternDword = AH_TRUE;
410 /* AR9285 has 2 antennas but is a 1x1 stream device */
411 pCap->halTxStreams = 1;
412 pCap->halRxStreams = 1;
414 pCap->halCSTSupport = AH_TRUE;
415 pCap->halRifsRxSupport = AH_TRUE;
416 pCap->halRifsTxSupport = AH_TRUE;
417 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
418 pCap->halExtChanDfsSupport = AH_TRUE;
419 pCap->halUseCombinedRadarRssi = AH_TRUE;
422 pCap->halBtCoexSupport = AH_TRUE;
424 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
425 pCap->hal4kbSplitTransSupport = AH_FALSE;
426 /* Disable this so Block-ACK works correctly */
427 pCap->halHasRxSelfLinkedTail = AH_FALSE;
428 pCap->halMbssidAggrSupport = AH_TRUE;
429 pCap->hal4AddrAggrSupport = AH_TRUE;
431 if (AR_SREV_KITE_12_OR_LATER(ah))
432 pCap->halPSPollBroken = AH_FALSE;
434 /* Only RX STBC supported */
435 pCap->halRxStbcSupport = 1;
436 pCap->halTxStbcSupport = 0;
442 ar9285Probe(uint16_t vendorid, uint16_t devid)
444 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
445 return "Atheros 9285";
446 if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
447 return "Atheros 2427";
451 AH_CHIP(AR9285, ar9285Probe, ar9285Attach);