2 * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef _BXE_FW_DEFS_H
36 #define _BXE_FW_DEFS_H
38 #define CSTORM_ASSERT_LIST_INDEX_OFFSET \
39 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
40 #define CSTORM_ASSERT_LIST_OFFSET(idx) \
41 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
42 #define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
43 (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
44 ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
45 0x40) + (index * 0x4)))
46 #define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
47 (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
48 ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
49 0x80) + (index * 0x4)))
50 #define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
51 (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
52 ((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
53 #define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
54 (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
55 ((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
56 #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
57 (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
58 ((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
59 #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
60 (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
61 ((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
62 #define CSTORM_FUNCTION_MODE_OFFSET \
63 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
64 #define CSTORM_HC_BTR_C_OFFSET(port) \
65 (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
66 #define CSTORM_HC_BTR_U_OFFSET(port) \
67 (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
68 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
69 (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
71 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
72 (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
74 #define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
75 (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
76 (0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
77 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
78 (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
79 (0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
80 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
81 (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
82 (0x241c + (function * 0xc0) + (eqIdx * 0x18)))
83 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
84 (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
85 (0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
86 #define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
87 (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
88 (0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
89 #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
90 (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
91 (0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
92 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
93 (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
94 (0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
95 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
96 (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
98 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
99 (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
101 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
102 (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
104 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
105 (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
107 #define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
108 (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
109 (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
111 #define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
112 (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
113 (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
115 #define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
116 (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
117 (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
119 #define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
120 (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
121 (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
123 #define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
124 (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
125 (0x3040 + (port * 0x280) + (cpu_id * 0x28)))
126 #define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
127 (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
128 (0x4000 + (port * 0x800) + (cpu_id * 0x80)))
129 #define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
130 (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
131 (0x3048 + (port * 0x280) + (cpu_id * 0x28)))
132 #define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
133 (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
134 (0x4008 + (port * 0x800) + (cpu_id * 0x80)))
135 #define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
136 #define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
137 #define CSTORM_STATS_FLAGS_OFFSET(function) \
138 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
140 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
141 (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
142 #define TSTORM_ASSERT_LIST_INDEX_OFFSET \
143 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
144 #define TSTORM_ASSERT_LIST_OFFSET(idx) \
145 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
146 #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
147 (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
148 : (0x9c0 + (port * 0x120) + (client_id * 0x10)))
149 #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
150 (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
151 #define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
152 (IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
153 #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
154 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
155 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
156 0x28) + (index * 0x4)))
157 #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
158 (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
159 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
160 #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
161 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
162 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
163 #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
164 (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
166 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
167 (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
169 #define TSTORM_FUNCTION_MODE_OFFSET \
170 (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
171 #define TSTORM_HC_BTR_OFFSET(port) \
172 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
173 #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
174 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
176 #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
177 #define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
178 (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
179 : (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
180 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
181 (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
183 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
184 (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
186 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
187 (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
189 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
190 (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
192 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
193 (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
195 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
196 (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
198 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
199 (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
201 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
202 (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
204 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
205 (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
207 #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
208 (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
209 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
210 #define TSTORM_STATS_FLAGS_OFFSET(function) \
211 (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
213 #define TSTORM_TCP_MAX_CWND_OFFSET(function) \
214 (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
216 #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
217 #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
218 #define USTORM_ASSERT_LIST_INDEX_OFFSET \
219 (IS_E1H_OFFSET ? 0x8000 : 0x1000)
220 #define USTORM_ASSERT_LIST_OFFSET(idx) \
221 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
222 #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
223 (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
224 (0x4010 + (port * 0x360) + (clientId * 0x30)))
226 #define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
227 (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
228 (0x4028 + (port * 0x360) + (clientId * 0x30)))
230 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
231 (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
232 #define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
233 (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
235 #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
236 (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
238 #define USTORM_FUNCTION_MODE_OFFSET \
239 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
240 #define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
241 (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
243 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
244 (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
246 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
247 (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
249 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
250 (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
252 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
253 (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
255 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
256 (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
258 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
259 (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
261 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
262 (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
264 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
265 (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
267 #define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
268 (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
270 #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
271 (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
272 (0x4018 + (port * 0x360) + (clientId * 0x30)))
273 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
274 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
276 #define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
277 (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
278 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
279 #define USTORM_RX_PRODS_OFFSET(port, client_id) \
280 (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
281 : (0x4000 + (port * 0x360) + (client_id * 0x30)))
282 #define USTORM_STATS_FLAGS_OFFSET(function) \
283 (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
285 #define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
286 #define USTORM_TPA_BTR_SIZE 0x1
287 #define XSTORM_ASSERT_LIST_INDEX_OFFSET \
288 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
289 #define XSTORM_ASSERT_LIST_OFFSET(idx) \
290 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
291 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
292 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
293 #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
294 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
295 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
296 0x28) + (index * 0x4)))
297 #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
298 (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
299 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
300 #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
301 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
302 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
303 #define XSTORM_E1HOV_OFFSET(function) \
304 (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
305 #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
306 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
308 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
309 (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
311 #define XSTORM_FUNCTION_MODE_OFFSET \
312 (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
313 #define XSTORM_HC_BTR_OFFSET(port) \
314 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
315 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
316 (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
318 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
319 (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
321 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
322 (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
324 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
325 (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
327 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
328 (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
330 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
331 (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
333 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
334 (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
336 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
337 (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
339 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
340 (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
342 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
343 (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
345 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
346 (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
348 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
349 (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
351 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
352 (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
354 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
355 (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
357 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
358 (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
360 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
361 (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
363 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
364 (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
366 #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
367 (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
368 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
369 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
370 (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
372 #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
373 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
375 #define XSTORM_SPQ_PROD_OFFSET(function) \
376 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
378 #define XSTORM_STATS_FLAGS_OFFSET(function) \
379 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
381 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
382 (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
383 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
384 (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
385 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
386 (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
387 * 0x4)) : (0x1978 + (function * 0x4)))
388 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
391 * This file defines HSI constants for the ETH flow
393 #ifdef _EVEREST_MICROCODE
394 #include "microcode_constants.h"
395 #include "eth_rx_bd.h"
396 #include "eth_tx_bd.h"
397 #include "eth_rx_cqe.h"
398 #include "eth_rx_sge.h"
399 #include "eth_rx_cqe_next_page.h"
403 #define DEFAULT_HASH_TYPE 0
404 #define IPV4_HASH_TYPE 1
405 #define TCP_IPV4_HASH_TYPE 2
406 #define IPV6_HASH_TYPE 3
407 #define TCP_IPV6_HASH_TYPE 4
408 #define VLAN_PRI_HASH_TYPE 5
409 #define E1HOV_PRI_HASH_TYPE 6
410 #define DSCP_HASH_TYPE 7
413 /* Ethernet Ring parameters */
414 #define X_ETH_LOCAL_RING_SIZE 13
415 #define FIRST_BD_IN_PKT 0
416 #define PARSE_BD_INDEX 1
417 #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
418 #define U_ETH_NUM_OF_SGES_TO_FETCH 8
419 #define U_ETH_MAX_SGES_FOR_PACKET 3
422 #define U_ETH_LOCAL_BD_RING_SIZE 8
423 #define U_ETH_LOCAL_SGE_RING_SIZE 10
424 #define U_ETH_SGL_SIZE 8
427 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
428 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
430 #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
431 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
432 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
434 #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
435 #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
436 #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
438 #define U_ETH_UNDEFINED_Q 0xFF
440 /* values of command IDs in the ramrod message */
441 #define RAMROD_CMD_ID_ETH_PORT_SETUP 80
442 #define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
443 #define RAMROD_CMD_ID_ETH_STAT_QUERY 90
444 #define RAMROD_CMD_ID_ETH_UPDATE 100
445 #define RAMROD_CMD_ID_ETH_HALT 105
446 #define RAMROD_CMD_ID_ETH_SET_MAC 110
447 #define RAMROD_CMD_ID_ETH_CFC_DEL 115
448 #define RAMROD_CMD_ID_ETH_PORT_DEL 120
449 #define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
452 /* command values for set mac command */
453 #define T_ETH_MAC_COMMAND_SET 0
454 #define T_ETH_MAC_COMMAND_INVALIDATE 1
456 #define T_ETH_INDIRECTION_TABLE_SIZE 128
458 /*The CRC32 seed, that is used for the hash(reduction) multicast address */
459 #define T_ETH_CRC32_HASH_SEED 0x00000000
461 /* Maximal L2 clients supported */
462 #define ETH_MAX_RX_CLIENTS_E1 18
463 #define ETH_MAX_RX_CLIENTS_E1H 26
465 /* Maximal aggregation queues supported */
466 #define ETH_MAX_AGGREGATION_QUEUES_E1 32
467 #define ETH_MAX_AGGREGATION_QUEUES_E1H 64
470 #define ETH_RSS_MODE_DISABLED 0
471 #define ETH_RSS_MODE_REGULAR 1
472 #define ETH_RSS_MODE_VLAN_PRI 2
473 #define ETH_RSS_MODE_E1HOV_PRI 3
474 #define ETH_RSS_MODE_IP_DSCP 4
478 * This file defines HSI constants common to all microcode flows
481 /* Connection types */
482 #define ETH_CONNECTION_TYPE 0
483 #define TOE_CONNECTION_TYPE 1
484 #define RDMA_CONNECTION_TYPE 2
485 #define ISCSI_CONNECTION_TYPE 3
486 #define FCOE_CONNECTION_TYPE 4
487 #define RESERVED_CONNECTION_TYPE_0 5
488 #define RESERVED_CONNECTION_TYPE_1 6
489 #define RESERVED_CONNECTION_TYPE_2 7
492 #define PROTOCOL_STATE_BIT_OFFSET 6
494 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
495 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
496 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
498 /* microcode fixed page page size 4K (chains and ring segments) */
499 #define MC_PAGE_SIZE 4096
502 /* Host coalescing constants */
503 #define HC_IGU_BC_MODE 0
504 #define HC_IGU_NBC_MODE 1
506 #define HC_REGULAR_SEGMENT 0
507 #define HC_DEFAULT_SEGMENT 1
510 #define HC_USTORM_DEF_SB_NUM_INDICES 8
511 #define HC_CSTORM_DEF_SB_NUM_INDICES 8
512 #define HC_XSTORM_DEF_SB_NUM_INDICES 4
513 #define HC_TSTORM_DEF_SB_NUM_INDICES 4
514 #define HC_USTORM_SB_NUM_INDICES 4
515 #define HC_CSTORM_SB_NUM_INDICES 4
517 /* index values - which counter to update */
519 #define HC_INDEX_U_TOE_RX_CQ_CONS 0
520 #define HC_INDEX_U_ETH_RX_CQ_CONS 1
521 #define HC_INDEX_U_ETH_RX_BD_CONS 2
522 #define HC_INDEX_U_FCOE_EQ_CONS 3
524 #define HC_INDEX_C_TOE_TX_CQ_CONS 0
525 #define HC_INDEX_C_ETH_TX_CQ_CONS 1
526 #define HC_INDEX_C_ISCSI_EQ_CONS 2
528 #define HC_INDEX_DEF_X_SPQ_CONS 0
530 #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
531 #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
532 #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
533 #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
534 #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
535 #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
536 #define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
538 #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
539 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
540 #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
541 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
542 #define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
543 #define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
545 /* used by the driver to get the SB offset */
550 #define ATTENTION_ID 4
552 /* max number of slow path commands per port */
553 #define MAX_RAMRODS_PER_PORT 8
555 /* values for RX ETH CQE type field */
556 #define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
557 #define RX_ETH_CQE_TYPE_ETH_RAMROD 1
560 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
561 #define EMULATION_FREQUENCY_FACTOR 1600
562 #define FPGA_FREQUENCY_FACTOR 100
564 #define TIMERS_TICK_SIZE_CHIP (1e-3)
565 #define TIMERS_TICK_SIZE_EMUL \
566 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
567 #define TIMERS_TICK_SIZE_FPGA \
568 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
570 #define TSEMI_CLK1_RESUL_CHIP (1e-3)
571 #define TSEMI_CLK1_RESUL_EMUL \
572 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
573 #define TSEMI_CLK1_RESUL_FPGA \
574 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
576 #define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
577 #define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
578 #define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
580 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
581 #define XSEMI_CLK1_RESUL_EMUL \
582 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
583 #define XSEMI_CLK1_RESUL_FPGA \
584 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
586 #define XSEMI_CLK2_RESUL_CHIP (1e-6)
587 #define XSEMI_CLK2_RESUL_EMUL \
588 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
589 #define XSEMI_CLK2_RESUL_FPGA \
590 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
592 #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
593 #define SDM_TIMER_TICK_RESUL_EMUL \
594 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
595 #define SDM_TIMER_TICK_RESUL_FPGA \
596 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
599 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
600 #define XSTORM_IP_ID_ROLL_HALF 0x8000
601 #define XSTORM_IP_ID_ROLL_ALL 0
603 #define FW_LOG_LIST_SIZE 50
605 #define NUM_OF_PROTOCOLS 4
606 #define NUM_OF_SAFC_BITS 16
607 #define MAX_COS_NUMBER 4
608 #define MAX_T_STAT_COUNTER_ID 18
609 #define MAX_X_STAT_COUNTER_ID 18
610 #define MAX_U_STAT_COUNTER_ID 18
613 #define UNKNOWN_ADDRESS 0
614 #define UNICAST_ADDRESS 1
615 #define MULTICAST_ADDRESS 2
616 #define BROADCAST_ADDRESS 3
618 #define SINGLE_FUNCTION 0
619 #define MULTI_FUNCTION 1