2 * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef _BXE_SELF_TEST_H
36 #define _BXE_SELF_TEST_H
38 static int idle_chk_errors;
39 static int idle_chk_warnings;
43 bxe_reg_read32 (struct bxe_softc *, bus_size_t);
45 bxe_reg_write32 (struct bxe_softc *, bus_size_t, uint32_t);
48 #define IDLE_CHK_E1 0x1
49 #define IDLE_CHK_E1H 0x2
51 #define IDLE_CHK_ERROR 1
52 #define IDLE_CHK_ERROR_NO_TRAFFIC 2
53 #define IDLE_CHK_WARNING 3
55 #define CHIP_MASK_CHK(chip_mask) \
56 (((((chip_mask) & IDLE_CHK_E1) && is_e1) || \
57 (((chip_mask) & IDLE_CHK_E1H) && is_e1h)) ? 1 : 0)
59 #define CONDITION_CHK(condition, severity, fail_msg, arg_list...) do { \
62 case IDLE_CHK_ERROR: \
63 BXE_PRINTF("ERROR " fail_msg, ##arg_list); \
66 case IDLE_CHK_ERROR_NO_TRAFFIC: \
67 BXE_PRINTF("WARNING " fail_msg, ##arg_list); \
69 case IDLE_CHK_WARNING: \
70 BXE_PRINTF("INFO " fail_msg, ##arg_list); \
71 idle_chk_warnings++; \
77 /* Read one reg and check the condition. */
78 #define IDLE_CHK_1(chip_mask, offset, condition, severity, fail_msg) do { \
79 if (CHIP_MASK_CHK(chip_mask)) { \
80 val = REG_RD(sc, offset); \
81 CONDITION_CHK(condition, severity, \
82 fail_msg ". Value is 0x%x\n", val); \
86 /* Loop to read one reg and check the condition. */
87 #define IDLE_CHK_2(chip_mask, offset, loop, inc, condition, severity, \
89 if (CHIP_MASK_CHK(chip_mask)) \
90 for (int i = 0; i < (loop); i++) { \
91 val = REG_RD(sc, offset + i * (inc)); \
92 CONDITION_CHK(condition, severity, \
93 fail_msg ". Value is 0x%x\n", i, val); \
97 /* Read two regs and check the condition. */
98 #define IDLE_CHK_3(chip_mask, offset1, offset2, condition, severity, \
100 if (CHIP_MASK_CHK(chip_mask)) { \
101 val1 = REG_RD(sc, offset1); \
102 val2 = REG_RD(sc, offset2); \
103 CONDITION_CHK(condition, severity, fail_msg \
104 ". Values are 0x%x 0x%x\n", val1, val2); \
108 /* Loop to read two regs and check the condition. */
109 #define IDLE_CHK_4(chip_mask, offset1, offset2, loop, inc, condition, \
110 severity, fail_msg) do { \
111 if (CHIP_MASK_CHK(chip_mask)) \
112 for (int i = 0; i < (loop); i++) { \
113 val1 = REG_RD(sc, offset1 + i * (inc)); \
114 val2 = (REG_RD(sc, offset2 + i * (inc)) >> 1); \
115 CONDITION_CHK(condition, severity, fail_msg \
116 " - LCID %d CID_CAM 0x%x Value is 0x%x\n", \
121 /* Read one reg and check according to another reg. */
122 #define IDLE_CHK_5(chip_mask,offset,offset1,offset2,condition,severity, \
124 if (CHIP_MASK_CHK(chip_mask)) \
125 if (!REG_RD(sc, offset)) \
126 IDLE_CHK_3(chip_mask, offset1, offset2, \
127 condition, severity, fail_msg); \
130 /* Read wide-bus reg and check sub-fields. */
131 #define IDLE_CHK_6(chip_mask, offset, loop, inc, severity) \
132 bxe_idle_chk6(sc, chip_mask, offset, loop, inc, severity)
141 bxe_idle_chk6(struct bxe_softc *sc, uint32_t chip_mask, uint32_t offset,
142 int loop, int inc, int severity)
145 uint32_t rd_ptr, wr_ptr, rd_bank, wr_bank;
146 int i, is_e1, is_e1h;
148 is_e1 = CHIP_IS_E1(sc);
149 is_e1h = CHIP_IS_E1H(sc);
151 if (!CHIP_MASK_CHK(chip_mask))
154 for (i = 0; i < loop; i++) {
155 val1 = REG_RD(sc, offset + i*inc);
156 val2 = REG_RD(sc, offset + i*inc + 4);
157 rd_ptr = ((val1 & 0x3FFFFFC0) >> 6);
158 wr_ptr = ((((val1 & 0xC0000000) >> 30) & 0x3) |
159 ((val2 & 0x3FFFFF) << 2));
160 CONDITION_CHK((rd_ptr != wr_ptr), severity,
161 "QM: PTRTBL entry %d - rd_ptr is not"
162 " equal to wr_ptr. Values are 0x%x 0x%x\n",
164 rd_bank = ((val1 & 0x30) >> 4);
165 wr_bank = (val1 & 0x03);
166 CONDITION_CHK((rd_bank != wr_bank), severity,
167 "QM: PTRTBL entry %d - rd_bank is not"
168 " equal to wr_bank. Values are 0x%x 0x%x\n",
169 i, rd_bank, wr_bank);
173 /* Loop to read wide-bus reg and check according to another reg. */
174 #define IDLE_CHK_7(chip_mask, offset, offset1, offset2, loop, inc, \
175 condition, severity, fail_msg) do { \
176 if (CHIP_MASK_CHK(chip_mask)) \
177 for (int i = 0; i < (loop); i++) { \
178 if (REG_RD(sc, offset + i * 4) == 1) { \
179 val1 = REG_RD(sc, offset1 + i * (inc)); \
180 val1 = REG_RD(sc, offset1 + i * (inc) + 4); \
181 val1 = ((REG_RD(sc, offset1 + i * (inc) + 8) & \
183 val2 = (REG_RD(sc, offset2 + i * 4) >> 1); \
184 CONDITION_CHK(condition, severity, \
185 fail_msg " - LCID %d CID_CAM 0x%x " \
186 "Value is 0x%x\n", i, val2, val1); \
194 * Performs a series of register reads and compares the returned values to
195 * expected values, looking for obvious errors. The comparisons used here
196 * (IDLE_CHK_*) are machine generated and should not be modifed.
199 * The number of errors encountered.
202 bxe_idle_chk(struct bxe_softc *sc)
205 uint32_t val, val1, val2;
209 idle_chk_warnings = 0;
211 is_e1 = CHIP_IS_E1(sc);
212 is_e1h = CHIP_IS_E1H(sc);
214 /* Don't run this code if the inteface hasn't been initialized. */
215 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
216 goto bxe_idle_chk_exit;
219 "------------------------------"
221 "------------------------------\n");
223 /* ToDo: Don't run this code is driver is NOT running. */
225 /* Perform the idle checks. */
226 IDLE_CHK_1(0x3, 0x2114, ((val & 0x0ff010) != 0), IDLE_CHK_ERROR,
227 "PCIE: ucorr_err_status is not 0");
228 IDLE_CHK_1(0x3, 0x2114, ((val & 0x100000) != 0), IDLE_CHK_WARNING,
229 "PCIE: ucorr_err_status - Unsupported request error");
230 IDLE_CHK_1(0x3, 0x2120,
231 (((val & 0x31c1) != 0x2000) && ((val & 0x31c1) != 0)),
232 IDLE_CHK_WARNING, "PCIE: corr_err_status is not 0x2000");
233 IDLE_CHK_1(0x3, 0x2814, ((val & ~0x40100) != 0), IDLE_CHK_ERROR,
234 "PCIE: attentions register is not 0x40100");
235 IDLE_CHK_1(0x2, 0x281c, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR,
236 "PCIE: attentions register is not 0x40040100");
237 IDLE_CHK_1(0x2, 0x2820, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR,
238 "PCIE: attentions register is not 0x40040100");
239 IDLE_CHK_1(0x1, PXP2_REG_PGL_EXP_ROM2, (val != 0xffffffff),
241 "PXP2: There are outstanding read requests. Not all"
242 " completions have arrived for read requests on tags that"
243 " are marked with 0");
244 IDLE_CHK_2(0x3, 0x212c, 4, 4, ((val != 0) && (idle_chk_errors > 0)),
245 IDLE_CHK_WARNING, "PCIE: error packet header %d is not 0");
247 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ0_ENTRY_CNT, (val != 0),
248 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ0 is not empty");
249 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ1_ENTRY_CNT, (val != 0),
250 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ1 is not empty");
251 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ2_ENTRY_CNT, (val != 0),
252 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ2 is not empty");
253 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ3_ENTRY_CNT, (val > 2),
254 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ3 is not empty");
255 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ4_ENTRY_CNT, (val != 0),
256 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ4 is not empty");
257 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ5_ENTRY_CNT, (val != 0),
258 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ5 is not empty");
259 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ6_ENTRY_CNT, (val != 0),
260 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ6 is not empty");
261 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ7_ENTRY_CNT, (val != 0),
262 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ7 is not empty");
263 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ8_ENTRY_CNT, (val != 0),
264 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ8 is not empty");
265 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ9_ENTRY_CNT, (val != 0),
266 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ9 is not empty");
267 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ10_ENTRY_CNT, (val != 0),
268 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ10 is not empty");
269 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ11_ENTRY_CNT, (val != 0),
270 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ11 is not empty");
271 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ12_ENTRY_CNT, (val != 0),
272 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ12 is not empty");
273 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ13_ENTRY_CNT, (val != 0),
274 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ13 is not empty");
275 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ14_ENTRY_CNT, (val != 0),
276 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ14 is not empty");
277 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ15_ENTRY_CNT, (val != 0),
278 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ15 is not empty");
279 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ16_ENTRY_CNT, (val != 0),
280 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ16 is not empty");
281 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ17_ENTRY_CNT, (val != 0),
282 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ17 is not empty");
283 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ18_ENTRY_CNT, (val != 0),
284 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ18 is not empty");
285 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ19_ENTRY_CNT, (val != 0),
286 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ19 is not empty");
287 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ20_ENTRY_CNT, (val != 0),
288 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ20 is not empty");
289 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ21_ENTRY_CNT, (val != 0),
290 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ21 is not empty");
291 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ22_ENTRY_CNT, (val != 0),
292 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ22 is not empty");
293 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ23_ENTRY_CNT, (val != 0),
294 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ23 is not empty");
295 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ24_ENTRY_CNT, (val != 0),
296 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ24 is not empty");
297 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ25_ENTRY_CNT, (val != 0),
298 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ25 is not empty");
299 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ26_ENTRY_CNT, (val != 0),
300 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ26 is not empty");
301 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ27_ENTRY_CNT, (val != 0),
302 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ27 is not empty");
303 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ28_ENTRY_CNT, (val != 0),
304 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ28 is not empty");
305 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ29_ENTRY_CNT, (val != 0),
306 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ29 is not empty");
307 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ30_ENTRY_CNT, (val != 0),
308 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ30 is not empty");
309 IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ31_ENTRY_CNT, (val != 0),
310 IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ31 is not empty");
312 IDLE_CHK_1(0x3, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, (val != 0),
313 IDLE_CHK_ERROR, "PXP2: rq_ufifo_num_of_entry is not 0");
314 IDLE_CHK_1(0x3, PXP2_REG_RQ_RBC_DONE, (val != 1), IDLE_CHK_ERROR,
315 "PXP2: rq_rbc_done is not 1");
316 IDLE_CHK_1(0x3, PXP2_REG_RQ_CFG_DONE, (val != 1), IDLE_CHK_ERROR,
317 "PXP2: rq_cfg_done is not 1");
318 IDLE_CHK_1(0x3, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x1b),
320 "PXP2: rq_read_credit and rq_write_credit are not 3");
321 IDLE_CHK_1(0x3, PXP2_REG_RD_START_INIT, (val != 1), IDLE_CHK_ERROR,
322 "PXP2: rd_start_init is not 1");
323 IDLE_CHK_1(0x3, PXP2_REG_RD_INIT_DONE, (val != 1), IDLE_CHK_ERROR,
324 "PXP2: rd_init_done is not 1");
326 IDLE_CHK_3(0x3, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG,
327 (val1 != (val2-1)), IDLE_CHK_WARNING,
328 "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg");
329 IDLE_CHK_3(0x3, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG,
330 (val1 != val2), IDLE_CHK_WARNING,
331 "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg");
333 IDLE_CHK_3(0x3, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG,
334 (val1 < (val2-3)), IDLE_CHK_ERROR_NO_TRAFFIC,
335 "PXP2: There are more than two unused SRs");
336 IDLE_CHK_3(0x3, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG,
337 (val1 < (val2-2)), IDLE_CHK_ERROR_NO_TRAFFIC,
338 "PXP2: There are more than two unused blocks");
340 IDLE_CHK_1(0x3, PXP2_REG_RD_PORT_IS_IDLE_0, (val != 1),
341 IDLE_CHK_ERROR_NO_TRAFFIC,
342 "PXP2: P0 All delivery ports are not idle");
343 IDLE_CHK_1(0x3, PXP2_REG_RD_PORT_IS_IDLE_1, (val != 1),
344 IDLE_CHK_ERROR_NO_TRAFFIC,
345 "PXP2: P1 All delivery ports are not idle");
347 IDLE_CHK_2(0x3, PXP2_REG_RD_ALMOST_FULL_0, 11, 4, (val != 0),
348 IDLE_CHK_ERROR, "PXP2: rd_almost_full_%d is not 0");
350 IDLE_CHK_1(0x3, PXP2_REG_RD_DISABLE_INPUTS, (val != 0),
351 IDLE_CHK_ERROR, "PXP2: PSWRD inputs are disabled");
352 IDLE_CHK_1(0x3, PXP2_REG_HST_HEADER_FIFO_STATUS, (val != 0),
353 IDLE_CHK_ERROR_NO_TRAFFIC,
354 "PXP2: HST header FIFO status is not 0");
355 IDLE_CHK_1(0x3, PXP2_REG_HST_DATA_FIFO_STATUS, (val != 0),
356 IDLE_CHK_ERROR_NO_TRAFFIC,
357 "PXP2: HST data FIFO status is not 0");
358 IDLE_CHK_1(0x3, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0),
359 IDLE_CHK_ERROR, "PXP2: pgl_write_blocked is not 0");
360 IDLE_CHK_1(0x3, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_ERROR,
361 "PXP2: pgl_read_blocked is not 0");
362 IDLE_CHK_1(0x3, PXP2_REG_PGL_TXW_CDTS, (((val >> 17) & 1) != 0),
363 IDLE_CHK_ERROR_NO_TRAFFIC,
364 "PXP2: There is data which is ready");
366 IDLE_CHK_1(0x3, PXP_REG_HST_ARB_IS_IDLE, (val != 1), IDLE_CHK_WARNING,
367 "PXP: HST arbiter is not idle");
368 IDLE_CHK_1(0x3, PXP_REG_HST_CLIENTS_WAITING_TO_ARB, (val != 0),
370 "PXP: HST one of the clients is waiting for delivery");
371 IDLE_CHK_1(0x2, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
372 (val != 0), IDLE_CHK_WARNING,
373 "PXP: HST Close the gates: Discarding internal writes");
374 IDLE_CHK_1(0x2, PXP_REG_HST_DISCARD_DOORBELLS_STATUS, (val != 0),
376 "PXP: HST Close the gates: Discarding doorbells");
378 IDLE_CHK_1(0x3, DMAE_REG_GO_C0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
379 "DMAE: command 0 go is not 0");
380 IDLE_CHK_1(0x3, DMAE_REG_GO_C1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
381 "DMAE: command 1 go is not 0");
382 IDLE_CHK_1(0x3, DMAE_REG_GO_C2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
383 "DMAE: command 2 go is not 0");
384 IDLE_CHK_1(0x3, DMAE_REG_GO_C3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
385 "DMAE: command 3 go is not 0");
386 IDLE_CHK_1(0x3, DMAE_REG_GO_C4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
387 "DMAE: command 4 go is not 0");
388 IDLE_CHK_1(0x3, DMAE_REG_GO_C5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
389 "DMAE: command 5 go is not 0");
390 IDLE_CHK_1(0x3, DMAE_REG_GO_C6, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
391 "DMAE: command 6 go is not 0");
392 IDLE_CHK_1(0x3, DMAE_REG_GO_C7, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
393 "DMAE: command 7 go is not 0");
394 IDLE_CHK_1(0x3, DMAE_REG_GO_C8, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
395 "DMAE: command 8 go is not 0");
396 IDLE_CHK_1(0x3, DMAE_REG_GO_C9, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
397 "DMAE: command 9 go is not 0");
398 IDLE_CHK_1(0x3, DMAE_REG_GO_C10, (val != 0),
399 IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 10 go is not 0");
400 IDLE_CHK_1(0x3, DMAE_REG_GO_C11, (val != 0),
401 IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 11 go is not 0");
402 IDLE_CHK_1(0x3, DMAE_REG_GO_C12, (val != 0),
403 IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 12 go is not 0");
404 IDLE_CHK_1(0x3, DMAE_REG_GO_C13, (val != 0),
405 IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 13 go is not 0");
406 IDLE_CHK_1(0x3, DMAE_REG_GO_C14, (val != 0),
407 IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 14 go is not 0");
408 IDLE_CHK_1(0x3, DMAE_REG_GO_C15, (val != 0),
409 IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 15 go is not 0");
411 IDLE_CHK_1(0x3, CFC_REG_ERROR_VECTOR, (val != 0), IDLE_CHK_ERROR,
412 "CFC: error vector is not 0");
413 IDLE_CHK_1(0x3, CFC_REG_NUM_LCIDS_ARRIVING, (val != 0),
414 IDLE_CHK_ERROR, "CFC: number of arriving LCIDs is not 0");
415 IDLE_CHK_1(0x3, CFC_REG_NUM_LCIDS_ALLOC, (val != 0), IDLE_CHK_ERROR,
416 "CFC: number of alloc LCIDs is not 0");
417 IDLE_CHK_1(0x3, CFC_REG_NUM_LCIDS_LEAVING, (val != 0), IDLE_CHK_ERROR,
418 "CFC: number of leaving LCIDs is not 0");
420 IDLE_CHK_4(0x3, CFC_REG_ACTIVITY_COUNTER, CFC_REG_CID_CAM,
421 (CFC_REG_ACTIVITY_COUNTER_SIZE >> 2), 4, (val1 > 1),
422 IDLE_CHK_ERROR, "CFC: AC > 1");
423 IDLE_CHK_7(0x3, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM,
424 CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16,
425 (val1 == 3), IDLE_CHK_WARNING,
426 "CFC: AC is 1, connType is 3");
427 IDLE_CHK_7(0x3, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM,
428 CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16,
429 ((val1 != 0) && (val1 != 3)), IDLE_CHK_ERROR,
430 "CFC: AC is 1, connType is not 0 nor 3");
432 IDLE_CHK_2(0x3, QM_REG_QTASKCTR_0, 64, 4, (val != 0),
433 IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Q_%d, queue is not empty");
435 IDLE_CHK_3(0x3, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0,
436 (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
437 "QM: VOQ_0, VOQ credit is not equal to initial credit");
438 IDLE_CHK_3(0x3, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1,
439 (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
440 "QM: VOQ_1, VOQ credit is not equal to initial credit");
441 IDLE_CHK_3(0x3, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4,
442 (val1 != val2), IDLE_CHK_ERROR,
443 "QM: VOQ_4, VOQ credit is not equal to initial credit");
445 IDLE_CHK_3(0x3, QM_REG_PORT0BYTECRD, QM_REG_BYTECRDINITVAL,
446 (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
447 "QM: P0 Byte credit is not equal to initial credit");
448 IDLE_CHK_3(0x3, QM_REG_PORT1BYTECRD, QM_REG_BYTECRDINITVAL,
449 (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
450 "QM: P1 Byte credit is not equal to initial credit");
452 IDLE_CHK_1(0x3, CCM_REG_CAM_OCCUP, (val != 0),
453 IDLE_CHK_ERROR_NO_TRAFFIC,
454 "CCM: XX protection CAM is not empty");
455 IDLE_CHK_1(0x3, TCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR,
456 "TCM: XX protection CAM is not empty");
457 IDLE_CHK_1(0x3, UCM_REG_CAM_OCCUP, (val != 0),
458 IDLE_CHK_ERROR_NO_TRAFFIC,
459 "UCM: XX protection CAM is not empty");
460 IDLE_CHK_1(0x3, XCM_REG_CAM_OCCUP, (val != 0),
461 IDLE_CHK_ERROR_NO_TRAFFIC,
462 "XCM: XX protection CAM is not empty");
464 IDLE_CHK_1(0x3, BRB1_REG_NUM_OF_FULL_BLOCKS, (val != 0),
465 IDLE_CHK_ERROR_NO_TRAFFIC, "BRB1: BRB is not empty");
467 IDLE_CHK_1(0x3, CSEM_REG_SLEEP_THREADS_VALID, (val != 0),
468 IDLE_CHK_ERROR, "CSEM: There are sleeping threads");
469 IDLE_CHK_1(0x3, TSEM_REG_SLEEP_THREADS_VALID, (val != 0),
470 IDLE_CHK_ERROR_NO_TRAFFIC,
471 "TSEM: There are sleeping threads");
472 IDLE_CHK_1(0x3, USEM_REG_SLEEP_THREADS_VALID, (val != 0),
473 IDLE_CHK_ERROR_NO_TRAFFIC,
474 "USEM: There are sleeping threads");
475 IDLE_CHK_1(0x3, XSEM_REG_SLEEP_THREADS_VALID, (val != 0),
476 IDLE_CHK_ERROR_NO_TRAFFIC,
477 "XSEM: There are sleeping threads");
479 IDLE_CHK_1(0x3, CSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
480 IDLE_CHK_ERROR, "CSEM: External store FIFO is not empty");
481 IDLE_CHK_1(0x3, TSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
482 IDLE_CHK_ERROR_NO_TRAFFIC,
483 "TSEM: External store FIFO is not empty");
484 IDLE_CHK_1(0x3, USEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
485 IDLE_CHK_ERROR_NO_TRAFFIC,
486 "USEM: External store FIFO is not empty");
487 IDLE_CHK_1(0x3, XSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
488 IDLE_CHK_ERROR_NO_TRAFFIC,
489 "XSEM: External store FIFO is not empty");
491 IDLE_CHK_1(0x3, CSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
492 IDLE_CHK_ERROR, "CSDM: Parser serial FIFO is not empty");
493 IDLE_CHK_1(0x3, TSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
494 IDLE_CHK_ERROR_NO_TRAFFIC,
495 "TSDM: Parser serial FIFO is not empty");
496 IDLE_CHK_1(0x3, USDM_REG_SYNC_PARSER_EMPTY, (val != 1),
497 IDLE_CHK_ERROR, "USDM: Parser serial FIFO is not empty");
498 IDLE_CHK_1(0x3, XSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
499 IDLE_CHK_ERROR, "XSDM: Parser serial FIFO is not empty");
501 IDLE_CHK_1(0x3, CSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
502 "CSDM: Parser SYNC serial FIFO is not empty");
503 IDLE_CHK_1(0x3, TSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
504 "TSDM: Parser SYNC serial FIFO is not empty");
505 IDLE_CHK_1(0x3, USDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
506 "USDM: Parser SYNC serial FIFO is not empty");
507 IDLE_CHK_1(0x3, XSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
508 "XSDM: Parser SYNC serial FIFO is not empty");
510 IDLE_CHK_1(0x3, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
512 "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
513 IDLE_CHK_1(0x3, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
515 "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
516 IDLE_CHK_1(0x3, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
517 IDLE_CHK_ERROR_NO_TRAFFIC,
518 "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
519 IDLE_CHK_1(0x3, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
520 IDLE_CHK_ERROR_NO_TRAFFIC,
521 "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
523 IDLE_CHK_1(0x3, DORQ_REG_DQ_FILL_LVLF, (val != 0),
524 IDLE_CHK_ERROR_NO_TRAFFIC, "DQ: DORQ queue is not empty");
526 IDLE_CHK_1(0x3, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR,
527 "CFC: interrupt status is not 0");
528 IDLE_CHK_1(0x3, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR,
529 "CDU: interrupt status is not 0");
530 IDLE_CHK_1(0x3, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
531 "CCM: interrupt status is not 0");
532 IDLE_CHK_1(0x3, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
533 "TCM: interrupt status is not 0");
534 IDLE_CHK_1(0x3, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
535 "UCM: interrupt status is not 0");
536 IDLE_CHK_1(0x3, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
537 "XCM: interrupt status is not 0");
538 IDLE_CHK_1(0x3, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR,
539 "PBF: interrupt status is not 0");
540 IDLE_CHK_1(0x3, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR,
541 "TIMERS: interrupt status is not 0");
542 IDLE_CHK_1(0x3, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR,
543 "DQ: interrupt status is not 0");
544 IDLE_CHK_1(0x3, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR,
545 "SRCH: interrupt status is not 0");
546 IDLE_CHK_1(0x3, PRS_REG_PRS_INT_STS, (val != 0), IDLE_CHK_ERROR,
547 "PRS: interrupt status is not 0");
548 IDLE_CHK_1(0x3, BRB1_REG_BRB1_INT_STS, ((val & ~0xfc00) != 0),
549 IDLE_CHK_ERROR, "BRB1: interrupt status is not 0");
550 IDLE_CHK_1(0x3, GRCBASE_XPB + PB_REG_PB_INT_STS, (val != 0),
551 IDLE_CHK_ERROR, "XPB: interrupt status is not 0");
552 IDLE_CHK_1(0x3, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0),
553 IDLE_CHK_ERROR, "UPB: interrupt status is not 0");
554 IDLE_CHK_1(0x3, PXP2_REG_PXP2_INT_STS_0, (val != 0), IDLE_CHK_WARNING,
555 "PXP2: interrupt status 0 is not 0");
556 IDLE_CHK_1(0x2, PXP2_REG_PXP2_INT_STS_1, (val != 0), IDLE_CHK_WARNING,
557 "PXP2: interrupt status 1 is not 0");
558 IDLE_CHK_1(0x3, QM_REG_QM_INT_STS, (val != 0), IDLE_CHK_ERROR,
559 "QM: interrupt status is not 0");
560 IDLE_CHK_1(0x3, PXP_REG_PXP_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
561 "PXP: interrupt status 0 is not 0");
562 IDLE_CHK_1(0x3, PXP_REG_PXP_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
563 "PXP: interrupt status 1 is not 0");
565 IDLE_CHK_1(0x3, DORQ_REG_RSPA_CRD_CNT, (val != 2),
566 IDLE_CHK_ERROR_NO_TRAFFIC,
567 "DQ: Credit to XCM is not full");
568 IDLE_CHK_1(0x3, DORQ_REG_RSPB_CRD_CNT, (val != 2), IDLE_CHK_ERROR,
569 "DQ: Credit to UCM is not full");
571 IDLE_CHK_1(0x3, QM_REG_VOQCRDERRREG, (val != 0), IDLE_CHK_ERROR,
572 "QM: Credit error register is not 0 (byte or credit"
573 " overflow/underflow)");
574 IDLE_CHK_1(0x3, DORQ_REG_DQ_FULL_ST, (val != 0), IDLE_CHK_ERROR,
575 "DQ: DORQ queue is full");
577 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
578 ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
579 "AEU: P0 AFTER_INVERT_1 is not 0");
580 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0, (val != 0),
581 IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_2 is not 0");
582 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
583 ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
584 "AEU: P0 AFTER_INVERT_3 is not 0");
585 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
586 ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
587 "AEU: P0 AFTER_INVERT_4 is not 0");
589 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
590 ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
591 "AEU: P1 AFTER_INVERT_1 is not 0");
592 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1, (val != 0),
593 IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_2 is not 0");
594 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
595 ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
596 "AEU: P1 AFTER_INVERT_3 is not 0");
597 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
598 ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
599 "AEU: P1 AFTER_INVERT_4 is not 0");
601 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_MCP,
602 ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
603 "AEU: MCP AFTER_INVERT_1 is not 0");
604 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_MCP, (val != 0),
605 IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_2 is not 0");
606 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_MCP,
607 ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
608 "AEU: MCP AFTER_INVERT_3 is not 0");
609 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_MCP,
610 ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
611 "AEU: MCP AFTER_INVERT_4 is not 0");
613 IDLE_CHK_5(0x3, PBF_REG_DISABLE_NEW_TASK_PROC_P0, PBF_REG_P0_CREDIT,
614 PBF_REG_P0_INIT_CRD, (val1 != val2),
615 IDLE_CHK_ERROR_NO_TRAFFIC,
616 "PBF: P0 credit is not equal to init_crd");
617 IDLE_CHK_5(0x3, PBF_REG_DISABLE_NEW_TASK_PROC_P1, PBF_REG_P1_CREDIT,
618 PBF_REG_P1_INIT_CRD, (val1 != val2),
619 IDLE_CHK_ERROR_NO_TRAFFIC,
620 "PBF: P1 credit is not equal to init_crd");
621 IDLE_CHK_3(0x3, PBF_REG_P4_CREDIT, PBF_REG_P4_INIT_CRD,
622 (val1 != val2), IDLE_CHK_ERROR,
623 "PBF: P4 credit is not equal to init_crd");
625 IDLE_CHK_1(0x3, PBF_REG_P0_TASK_CNT, (val != 0),
626 IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 task_cnt is not 0");
627 IDLE_CHK_1(0x3, PBF_REG_P1_TASK_CNT, (val != 0),
628 IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 task_cnt is not 0");
629 IDLE_CHK_1(0x3, PBF_REG_P4_TASK_CNT, (val != 0), IDLE_CHK_ERROR,
630 "PBF: P4 task_cnt is not 0");
632 IDLE_CHK_1(0x3, XCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
633 "XCM: CFC_INIT_CRD is not 1");
634 IDLE_CHK_1(0x3, UCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
635 "UCM: CFC_INIT_CRD is not 1");
636 IDLE_CHK_1(0x3, TCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
637 "TCM: CFC_INIT_CRD is not 1");
638 IDLE_CHK_1(0x3, CCM_REG_CFC_INIT_CRD, (val != 1),
639 IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CFC_INIT_CRD is not 1");
641 IDLE_CHK_1(0x3, XCM_REG_XQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
642 "XCM: XQM_INIT_CRD is not 32");
643 IDLE_CHK_1(0x3, UCM_REG_UQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
644 "UCM: UQM_INIT_CRD is not 32");
645 IDLE_CHK_1(0x3, TCM_REG_TQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
646 "TCM: TQM_INIT_CRD is not 32");
647 IDLE_CHK_1(0x3, CCM_REG_CQM_INIT_CRD, (val != 32),
648 IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CQM_INIT_CRD is not 32");
650 IDLE_CHK_1(0x3, XCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR,
651 "XCM: TM_INIT_CRD is not 4");
652 IDLE_CHK_1(0x3, UCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR,
653 "UCM: TM_INIT_CRD is not 4");
655 IDLE_CHK_1(0x3, XCM_REG_FIC0_INIT_CRD, (val != 64),
656 IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: FIC0_INIT_CRD is not 64");
657 IDLE_CHK_1(0x3, UCM_REG_FIC0_INIT_CRD, (val != 64),
658 IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC0_INIT_CRD is not 64");
659 IDLE_CHK_1(0x3, TCM_REG_FIC0_INIT_CRD, (val != 64),
660 IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC0_INIT_CRD is not 64");
661 IDLE_CHK_1(0x3, CCM_REG_FIC0_INIT_CRD, (val != 64),
662 IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC0_INIT_CRD is not 64");
664 IDLE_CHK_1(0x3, XCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
665 "XCM: FIC1_INIT_CRD is not 64");
666 IDLE_CHK_1(0x3, UCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
667 "UCM: FIC1_INIT_CRD is not 64");
668 IDLE_CHK_1(0x3, TCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
669 "TCM: FIC1_INIT_CRD is not 64");
670 IDLE_CHK_1(0x3, CCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
671 "CCM: FIC1_INIT_CRD is not 64");
673 IDLE_CHK_1(0x1, XCM_REG_XX_FREE, (val != 31), IDLE_CHK_ERROR,
674 "XCM: XX_FREE is not 31");
675 IDLE_CHK_1(0x2, XCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR,
676 "XCM: XX_FREE is not 32");
677 IDLE_CHK_1(0x3, UCM_REG_XX_FREE, (val != 27),
678 IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX_FREE is not 27");
679 IDLE_CHK_1(0x3, TCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR,
680 "TCM: XX_FREE is not 32");
681 IDLE_CHK_1(0x3, CCM_REG_XX_FREE, (val != 24), IDLE_CHK_ERROR,
682 "CCM: XX_FREE is not 24");
684 IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x18000, (val != 0),
685 IDLE_CHK_ERROR_NO_TRAFFIC,
686 "XSEM: FOC0 credit less than initial credit");
687 IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x18040, (val != 24),
688 IDLE_CHK_ERROR_NO_TRAFFIC,
689 "XSEM: FOC1 credit less than initial credit");
690 IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x18080, (val != 12),
691 IDLE_CHK_ERROR_NO_TRAFFIC,
692 "XSEM: FOC2 credit less than initial credit");
693 IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x180C0, (val != 102),
694 IDLE_CHK_ERROR_NO_TRAFFIC,
695 "XSEM: FOC3 credit less than initial credit");
697 IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x18000, (val != 26),
698 IDLE_CHK_ERROR_NO_TRAFFIC,
699 "USEM: FOC0 credit less than initial credit");
700 IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x18040, (val != 78),
701 IDLE_CHK_ERROR_NO_TRAFFIC,
702 "USEM: FOC1 credit less than initial credit");
703 IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x18080, (val != 16),
704 IDLE_CHK_ERROR_NO_TRAFFIC,
705 "USEM: FOC2 credit less than initial credit");
706 IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x180C0, (val != 32),
707 IDLE_CHK_ERROR_NO_TRAFFIC,
708 "USEM: FOC3 credit less than initial credit");
710 IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x18000, (val != 52),
711 IDLE_CHK_ERROR_NO_TRAFFIC,
712 "TSEM: FOC0 credit less than initial credit");
713 IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x18040, (val != 24),
714 IDLE_CHK_ERROR_NO_TRAFFIC,
715 "TSEM: FOC1 credit less than initial credit");
716 IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x18080, (val != 12),
717 IDLE_CHK_ERROR_NO_TRAFFIC,
718 "TSEM: FOC2 credit less than initial credit");
719 IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x180C0, (val != 32),
720 IDLE_CHK_ERROR_NO_TRAFFIC,
721 "TSEM: FOC3 credit less than initial credit");
723 IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x18000, (val != 16),
724 IDLE_CHK_ERROR_NO_TRAFFIC,
725 "CSEM: FOC0 credit less than initial credit");
726 IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x18040, (val != 18),
727 IDLE_CHK_ERROR_NO_TRAFFIC,
728 "CSEM: FOC1 credit less than initial credit");
729 IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x18080, (val != 48),
730 IDLE_CHK_ERROR_NO_TRAFFIC,
731 "CSEM: FOC2 credit less than initial credit");
732 IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x180C0, (val != 14),
733 IDLE_CHK_ERROR_NO_TRAFFIC,
734 "CSEM: FOC3 credit less than initial credit");
736 IDLE_CHK_1(0x3, PRS_REG_TSDM_CURRENT_CREDIT, (val != 0),
737 IDLE_CHK_ERROR_NO_TRAFFIC,
738 "PRS: TSDM current credit is not 0");
739 IDLE_CHK_1(0x3, PRS_REG_TCM_CURRENT_CREDIT, (val != 0),
740 IDLE_CHK_ERROR_NO_TRAFFIC,
741 "PRS: TCM current credit is not 0");
742 IDLE_CHK_1(0x3, PRS_REG_CFC_LD_CURRENT_CREDIT, (val != 0),
743 IDLE_CHK_ERROR, "PRS: CFC_LD current credit is not 0");
744 IDLE_CHK_1(0x3, PRS_REG_CFC_SEARCH_CURRENT_CREDIT, (val != 0),
745 IDLE_CHK_ERROR, "PRS: CFC_SEARCH current credit is not 0");
746 IDLE_CHK_1(0x3, PRS_REG_SRC_CURRENT_CREDIT, (val != 0),
747 IDLE_CHK_ERROR_NO_TRAFFIC,
748 "PRS: SRCH current credit is not 0");
750 IDLE_CHK_1(0x3, PRS_REG_PENDING_BRB_PRS_RQ, (val != 0),
751 IDLE_CHK_ERROR_NO_TRAFFIC,
752 "PRS: PENDING_BRB_PRS_RQ is not 0");
753 IDLE_CHK_2(0x3, PRS_REG_PENDING_BRB_CAC0_RQ, 5, 4, (val != 0),
754 IDLE_CHK_ERROR_NO_TRAFFIC,
755 "PRS: PENDING_BRB_CAC%d_RQ is not 0");
757 IDLE_CHK_1(0x3, PRS_REG_SERIAL_NUM_STATUS_LSB, (val != 0),
758 IDLE_CHK_ERROR_NO_TRAFFIC,
759 "PRS: SERIAL_NUM_STATUS_LSB is not 0");
760 IDLE_CHK_1(0x3, PRS_REG_SERIAL_NUM_STATUS_MSB, (val != 0),
761 IDLE_CHK_ERROR_NO_TRAFFIC,
762 "PRS: SERIAL_NUM_STATUS_MSB is not 0");
764 IDLE_CHK_1(0x3, CDU_REG_ERROR_DATA, (val != 0), IDLE_CHK_ERROR,
765 "CDU: ERROR_DATA is not 0");
767 IDLE_CHK_1(0x3, CCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
768 "CCM: STORM declared message length unequal to actual");
769 IDLE_CHK_1(0x3, CCM_REG_CSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
770 "CCM: CSDM declared message length unequal to actual");
771 IDLE_CHK_1(0x3, CCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
772 "CCM: TSEM declared message length unequal to actual");
773 IDLE_CHK_1(0x3, CCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
774 "CCM: XSEM declared message length unequal to actual");
775 IDLE_CHK_1(0x3, CCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
776 "CCM: USEM declared message length unequal to actual");
777 IDLE_CHK_1(0x3, CCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
778 "CCM: PBF declared message length unequal to actual");
780 IDLE_CHK_1(0x3, TCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
781 "TCM: STORM declared message length unequal to actual");
782 IDLE_CHK_1(0x3, TCM_REG_TSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
783 "TCM: TSDM declared message length unequal to actual");
784 IDLE_CHK_1(0x3, TCM_REG_PRS_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
785 "TCM: PRS declared message length unequal to actual");
786 IDLE_CHK_1(0x3, TCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
787 "TCM: PBF declared message length unequal to actual");
788 IDLE_CHK_1(0x3, TCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
789 "TCM: USEM declared message length unequal to actual");
790 IDLE_CHK_1(0x3, TCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
791 "TCM: CSEM declared message length unequal to actual");
793 IDLE_CHK_1(0x3, UCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
794 "UCM: STORM declared message length unequal to actual");
795 IDLE_CHK_1(0x3, UCM_REG_USDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
796 "UCM: USDM declared message length unequal to actual");
797 IDLE_CHK_1(0x3, UCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
798 "UCM: TSEM declared message length unequal to actual");
799 IDLE_CHK_1(0x3, UCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
800 "UCM: CSEM declared message length unequal to actual");
801 IDLE_CHK_1(0x3, UCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
802 "UCM: XSEM declared message length unequal to actual");
803 IDLE_CHK_1(0x3, UCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
804 "UCM: DORQ declared message length unequal to actual");
806 IDLE_CHK_1(0x3, XCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
807 "XCM: STORM declared message length unequal to actual");
808 IDLE_CHK_1(0x3, XCM_REG_XSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
809 "XCM: XSDM declared message length unequal to actual");
810 IDLE_CHK_1(0x3, XCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
811 "XCM: TSEM declared message length unequal to actual");
812 IDLE_CHK_1(0x3, XCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
813 "XCM: CSEM declared message length unequal to actual");
814 IDLE_CHK_1(0x3, XCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
815 "XCM: USEM declared message length unequal to actual");
816 IDLE_CHK_1(0x3, XCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
817 "XCM: DORQ declared message length unequal to actual");
818 IDLE_CHK_1(0x3, XCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
819 "XCM: PBF declared message length unequal to actual");
820 IDLE_CHK_1(0x3, XCM_REG_NIG0_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
821 "XCM: NIG0 declared message length unequal to actual");
822 IDLE_CHK_1(0x3, XCM_REG_NIG1_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
823 "XCM: NIG1 declared message length unequal to actual");
825 IDLE_CHK_1(0x3, QM_REG_XQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
826 "QM: XQM wrc_fifolvl is not 0");
827 IDLE_CHK_1(0x3, QM_REG_UQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
828 "QM: UQM wrc_fifolvl is not 0");
829 IDLE_CHK_1(0x3, QM_REG_TQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
830 "QM: TQM wrc_fifolvl is not 0");
831 IDLE_CHK_1(0x3, QM_REG_CQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
832 "QM: CQM wrc_fifolvl is not 0");
833 IDLE_CHK_1(0x3, QM_REG_QSTATUS_LOW, (val != 0), IDLE_CHK_ERROR,
834 "QM: QSTATUS_LOW is not 0");
835 IDLE_CHK_1(0x3, QM_REG_QSTATUS_HIGH, (val != 0), IDLE_CHK_ERROR,
836 "QM: QSTATUS_HIGH is not 0");
837 IDLE_CHK_1(0x3, QM_REG_PAUSESTATE0, (val != 0), IDLE_CHK_ERROR,
838 "QM: PAUSESTATE0 is not 0");
839 IDLE_CHK_1(0x3, QM_REG_PAUSESTATE1, (val != 0), IDLE_CHK_ERROR,
840 "QM: PAUSESTATE1 is not 0");
841 IDLE_CHK_1(0x3, QM_REG_OVFQNUM, (val != 0), IDLE_CHK_ERROR,
842 "QM: OVFQNUM is not 0");
843 IDLE_CHK_1(0x3, QM_REG_OVFERROR, (val != 0), IDLE_CHK_ERROR,
844 "QM: OVFERROR is not 0");
846 IDLE_CHK_6(0x3, QM_REG_PTRTBL, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC);
848 IDLE_CHK_1(0x3, BRB1_REG_BRB1_PRTY_STS, ((val & ~0x8) != 0),
849 IDLE_CHK_WARNING, "BRB1: parity status is not 0");
850 IDLE_CHK_1(0x3, CDU_REG_CDU_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
851 "CDU: parity status is not 0");
852 IDLE_CHK_1(0x3, CFC_REG_CFC_PRTY_STS, ((val & ~0x2) != 0),
853 IDLE_CHK_WARNING, "CFC: parity status is not 0");
854 IDLE_CHK_1(0x3, CSDM_REG_CSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
855 "CSDM: parity status is not 0");
856 IDLE_CHK_1(0x3, DBG_REG_DBG_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
857 "DBG: parity status is not 0");
858 IDLE_CHK_1(0x3, DMAE_REG_DMAE_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
859 "DMAE: parity status is not 0");
860 IDLE_CHK_1(0x3, DORQ_REG_DORQ_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
861 "DQ: parity status is not 0");
862 IDLE_CHK_1(0x1, TCM_REG_TCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
863 IDLE_CHK_WARNING, "TCM: parity status is not 0");
864 IDLE_CHK_1(0x2, TCM_REG_TCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
865 "TCM: parity status is not 0");
866 IDLE_CHK_1(0x1, CCM_REG_CCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
867 IDLE_CHK_WARNING, "CCM: parity status is not 0");
868 IDLE_CHK_1(0x2, CCM_REG_CCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
869 "CCM: parity status is not 0");
870 IDLE_CHK_1(0x1, UCM_REG_UCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
871 IDLE_CHK_WARNING, "UCM: parity status is not 0");
872 IDLE_CHK_1(0x2, UCM_REG_UCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
873 "UCM: parity status is not 0");
874 IDLE_CHK_1(0x1, XCM_REG_XCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
875 IDLE_CHK_WARNING, "XCM: parity status is not 0");
876 IDLE_CHK_1(0x2, XCM_REG_XCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
877 "XCM: parity status is not 0");
878 IDLE_CHK_1(0x1, HC_REG_HC_PRTY_STS, ((val & ~0x1) != 0),
879 IDLE_CHK_WARNING, "HC: parity status is not 0");
880 IDLE_CHK_1(0x1, MISC_REG_MISC_PRTY_STS, ((val & ~0x1) != 0),
881 IDLE_CHK_WARNING, "MISC: parity status is not 0");
882 IDLE_CHK_1(0x3, PRS_REG_PRS_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
883 "PRS: parity status is not 0");
884 IDLE_CHK_1(0x3, PXP_REG_PXP_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
885 "PXP: parity status is not 0");
886 IDLE_CHK_1(0x3, QM_REG_QM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
887 "QM: parity status is not 0");
888 IDLE_CHK_1(0x1, SRC_REG_SRC_PRTY_STS, ((val & ~0x4) != 0),
889 IDLE_CHK_WARNING, "SRCH: parity status is not 0");
890 IDLE_CHK_1(0x3, TSDM_REG_TSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
891 "TSDM: parity status is not 0");
892 IDLE_CHK_1(0x3, USDM_REG_USDM_PRTY_STS, ((val & ~0x20) != 0),
893 IDLE_CHK_WARNING, "USDM: parity status is not 0");
894 IDLE_CHK_1(0x3, XSDM_REG_XSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
895 "XSDM: parity status is not 0");
896 IDLE_CHK_1(0x3, GRCBASE_XPB + PB_REG_PB_PRTY_STS, (val != 0),
897 IDLE_CHK_WARNING, "XPB: parity status is not 0");
898 IDLE_CHK_1(0x3, GRCBASE_UPB + PB_REG_PB_PRTY_STS, (val != 0),
899 IDLE_CHK_WARNING, "UPB: parity status is not 0");
901 IDLE_CHK_1(0x3, CSEM_REG_CSEM_PRTY_STS_0, (val != 0),
902 IDLE_CHK_WARNING, "CSEM: parity status 0 is not 0");
903 IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0xfff40020) != 0),
904 IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0");
905 IDLE_CHK_1(0x2, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0x20) != 0),
906 IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0");
907 IDLE_CHK_1(0x3, TSEM_REG_TSEM_PRTY_STS_0, (val != 0),
908 IDLE_CHK_WARNING, "TSEM: parity status 0 is not 0");
909 IDLE_CHK_1(0x3, USEM_REG_USEM_PRTY_STS_0, (val != 0),
910 IDLE_CHK_WARNING, "USEM: parity status 0 is not 0");
911 IDLE_CHK_1(0x3, XSEM_REG_XSEM_PRTY_STS_0, (val != 0),
912 IDLE_CHK_WARNING, "XSEM: parity status 0 is not 0");
914 IDLE_CHK_1(0x3, CSEM_REG_CSEM_PRTY_STS_1, (val != 0),
915 IDLE_CHK_WARNING, "CSEM: parity status 1 is not 0");
916 IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_1, ((val & ~0x20) != 0),
917 IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0");
918 IDLE_CHK_1(0x2, PXP2_REG_PXP2_PRTY_STS_1, (val != 0),
919 IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0");
920 IDLE_CHK_1(0x3, TSEM_REG_TSEM_PRTY_STS_1, (val != 0),
921 IDLE_CHK_WARNING, "TSEM: parity status 1 is not 0");
922 IDLE_CHK_1(0x3, USEM_REG_USEM_PRTY_STS_1, (val != 0),
923 IDLE_CHK_WARNING, "USEM: parity status 1 is not 0");
924 IDLE_CHK_1(0x3, XSEM_REG_XSEM_PRTY_STS_1, (val != 0),
925 IDLE_CHK_WARNING, "XSEM: parity status 1 is not 0");
927 IDLE_CHK_2(0x2, QM_REG_QTASKCTR_EXT_A_0, 64, 4, (val != 0),
928 IDLE_CHK_ERROR_NO_TRAFFIC,
929 "QM: Q_EXT_A_%d, queue is not empty");
930 IDLE_CHK_1(0x2, QM_REG_QSTATUS_LOW_EXT_A, (val != 0), IDLE_CHK_ERROR,
931 "QM: QSTATUS_LOW_EXT_A is not 0");
932 IDLE_CHK_1(0x2, QM_REG_QSTATUS_HIGH_EXT_A, (val != 0), IDLE_CHK_ERROR,
933 "QM: QSTATUS_HIGH_EXT_A is not 0");
934 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE2, (val != 0), IDLE_CHK_ERROR,
935 "QM: PAUSESTATE2 is not 0");
936 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE3, (val != 0), IDLE_CHK_ERROR,
937 "QM: PAUSESTATE3 is not 0");
938 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE4, (val != 0), IDLE_CHK_ERROR,
939 "QM: PAUSESTATE4 is not 0");
940 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE5, (val != 0), IDLE_CHK_ERROR,
941 "QM: PAUSESTATE5 is not 0");
942 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE6, (val != 0), IDLE_CHK_ERROR,
943 "QM: PAUSESTATE6 is not 0");
944 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE7, (val != 0), IDLE_CHK_ERROR,
945 "QM: PAUSESTATE7 is not 0");
946 IDLE_CHK_6(0x2, QM_REG_PTRTBL_EXT_A, 64, 8,
947 IDLE_CHK_ERROR_NO_TRAFFIC);
949 IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_OCCURRED, (val != 0),
950 IDLE_CHK_ERROR, "MISC: system kill occurd;");
951 IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_0, (val != 0),
953 "MISC: system kill occurd; status_0 register");
954 IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_1, (val != 0),
956 "MISC: system kill occurd; status_1 register");
957 IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_2, (val != 0),
959 "MISC: system kill occurd; status_2 register");
960 IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_3, (val != 0),
962 "MISC: system kill occurd; status_3 register");
963 IDLE_CHK_1(0x2, MISC_REG_PCIE_HOT_RESET, (val != 0), IDLE_CHK_WARNING,
964 "MISC: pcie_rst_b was asserted without perst assertion");
966 IDLE_CHK_1(0x3, NIG_REG_NIG_INT_STS_0, ((val & ~0x300) != 0),
967 IDLE_CHK_ERROR, "NIG: interrupt status 0 is not 0");
968 IDLE_CHK_1(0x3, NIG_REG_NIG_INT_STS_0, (val == 0x300),
970 "NIG: Access to BMAC while not active. If tested on FPGA,"
971 " ignore this warning.");
972 IDLE_CHK_1(0x3, NIG_REG_NIG_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
973 "NIG: interrupt status 1 is not 0");
974 IDLE_CHK_1(0x2, NIG_REG_NIG_PRTY_STS, ((val & ~0xffc00000) != 0),
975 IDLE_CHK_WARNING, "NIG: parity status is not 0");
977 IDLE_CHK_1(0x3, TSEM_REG_TSEM_INT_STS_0, ((val & ~0x10000000) != 0),
978 IDLE_CHK_ERROR, "TSEM: interrupt status 0 is not 0");
979 IDLE_CHK_1(0x3, TSEM_REG_TSEM_INT_STS_0, (val == 0x10000000),
980 IDLE_CHK_WARNING, "TSEM: interrupt status 0 is not 0");
981 IDLE_CHK_1(0x3, TSEM_REG_TSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
982 "TSEM: interrupt status 1 is not 0");
984 IDLE_CHK_1(0x3, CSEM_REG_CSEM_INT_STS_0, ((val & ~0x10000000) != 0),
985 IDLE_CHK_ERROR, "CSEM: interrupt status 0 is not 0");
986 IDLE_CHK_1(0x3, CSEM_REG_CSEM_INT_STS_0, (val == 0x10000000),
987 IDLE_CHK_WARNING, "CSEM: interrupt status 0 is not 0");
988 IDLE_CHK_1(0x3, CSEM_REG_CSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
989 "CSEM: interrupt status 1 is not 0");
991 IDLE_CHK_1(0x3, USEM_REG_USEM_INT_STS_0, ((val & ~0x10000000) != 0),
992 IDLE_CHK_ERROR, "USEM: interrupt status 0 is not 0");
993 IDLE_CHK_1(0x3, USEM_REG_USEM_INT_STS_0, (val == 0x10000000),
994 IDLE_CHK_WARNING, "USEM: interrupt status 0 is not 0");
995 IDLE_CHK_1(0x3, USEM_REG_USEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
996 "USEM: interrupt status 1 is not 0");
998 IDLE_CHK_1(0x3, XSEM_REG_XSEM_INT_STS_0, ((val & ~0x10000000) != 0),
999 IDLE_CHK_ERROR, "XSEM: interrupt status 0 is not 0");
1000 IDLE_CHK_1(0x3, XSEM_REG_XSEM_INT_STS_0, (val == 0x10000000),
1001 IDLE_CHK_WARNING, "XSEM: interrupt status 0 is not 0");
1002 IDLE_CHK_1(0x3, XSEM_REG_XSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
1003 "XSEM: interrupt status 1 is not 0");
1005 IDLE_CHK_1(0x3, TSDM_REG_TSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
1006 "TSDM: interrupt status 0 is not 0");
1007 IDLE_CHK_1(0x3, TSDM_REG_TSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
1008 "TSDM: interrupt status 1 is not 0");
1010 IDLE_CHK_1(0x3, CSDM_REG_CSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
1011 "CSDM: interrupt status 0 is not 0");
1012 IDLE_CHK_1(0x3, CSDM_REG_CSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
1013 "CSDM: interrupt status 1 is not 0");
1015 IDLE_CHK_1(0x3, USDM_REG_USDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
1016 "USDM: interrupt status 0 is not 0");
1017 IDLE_CHK_1(0x3, USDM_REG_USDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
1018 "USDM: interrupt status 1 is not 0");
1020 IDLE_CHK_1(0x3, XSDM_REG_XSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
1021 "XSDM: interrupt status 0 is not 0");
1022 IDLE_CHK_1(0x3, XSDM_REG_XSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
1023 "XSDM: interrupt status 1 is not 0");
1025 IDLE_CHK_1(0x2, HC_REG_HC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
1026 "HC: parity status is not 0");
1027 IDLE_CHK_1(0x2, MISC_REG_MISC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
1028 "MISC: parity status is not 0");
1029 IDLE_CHK_1(0x2, SRC_REG_SRC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
1030 "SRCH: parity status is not 0");
1032 if (idle_chk_errors == 0) {
1033 BXE_PRINTF("%s(): Completed successfuly with %d warning(s).\n",
1034 __FUNCTION__, idle_chk_warnings);
1036 BXE_PRINTF("%s(): Failed with %d error(s) and %d warning(s)!\n",
1037 __FUNCTION__, idle_chk_errors, idle_chk_warnings);
1041 "----------------------------"
1043 "----------------------------\n");
1046 return (idle_chk_errors);
1049 #endif /* _BXE_SELF_TEST_H */