1 /**************************************************************************
3 Copyright (c) 2007-2009 Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
30 ***************************************************************************/
35 CPL_PASS_OPEN_REQ = 0x1,
36 CPL_PASS_ACCEPT_RPL = 0x2,
37 CPL_ACT_OPEN_REQ = 0x3,
39 CPL_SET_TCB_FIELD = 0x5,
42 CPL_CLOSE_CON_REQ = 0x8,
43 CPL_CLOSE_LISTSRV_REQ = 0x9,
47 CPL_RX_DATA_ACK = 0xD,
49 CPL_RTE_DELETE_REQ = 0xF,
50 CPL_RTE_WRITE_REQ = 0x10,
51 CPL_RTE_READ_REQ = 0x11,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_L2T_READ_REQ = 0x13,
54 CPL_SMT_WRITE_REQ = 0x14,
55 CPL_SMT_READ_REQ = 0x15,
56 CPL_TX_PKT_LSO = 0x16,
59 CPL_TID_RELEASE = 0x1A,
61 CPL_CLOSE_LISTSRV_RPL = 0x20,
63 CPL_GET_TCB_RPL = 0x22,
64 CPL_L2T_WRITE_RPL = 0x23,
65 CPL_PCMD_READ_RPL = 0x24,
67 CPL_PEER_CLOSE = 0x26,
68 CPL_RTE_DELETE_RPL = 0x27,
69 CPL_RTE_WRITE_RPL = 0x28,
70 CPL_RX_DDP_COMPLETE = 0x29,
71 CPL_RX_PHYS_ADDR = 0x2A,
73 CPL_RX_URG_NOTIFY = 0x2C,
74 CPL_SET_TCB_RPL = 0x2D,
75 CPL_SMT_WRITE_RPL = 0x2E,
76 CPL_TX_DATA_ACK = 0x2F,
78 CPL_ABORT_REQ_RSS = 0x30,
79 CPL_ABORT_RPL_RSS = 0x31,
80 CPL_CLOSE_CON_RPL = 0x32,
82 CPL_L2T_READ_RPL = 0x34,
84 CPL_RDMA_CQE_READ_RSP = 0x36,
85 CPL_RDMA_CQE_ERR = 0x37,
86 CPL_RTE_READ_RPL = 0x38,
89 CPL_ACT_OPEN_RPL = 0x40,
90 CPL_PASS_OPEN_RPL = 0x41,
91 CPL_RX_DATA_DDP = 0x42,
92 CPL_SMT_READ_RPL = 0x43,
94 CPL_ACT_ESTABLISH = 0x50,
95 CPL_PASS_ESTABLISH = 0x51,
97 CPL_PASS_ACCEPT_REQ = 0x70,
99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
101 CPL_TX_DMA_ACK = 0xA0,
102 CPL_RDMA_READ_REQ = 0xA1,
103 CPL_RDMA_TERMINATE = 0xA2,
104 CPL_TRACE_PKT = 0xA3,
105 CPL_RDMA_EC_STATUS = 0xA5,
106 CPL_SGE_EC_CR_RETURN = 0xA6,
108 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
113 CPL_ERR_TCAM_PARITY = 1,
114 CPL_ERR_TCAM_FULL = 3,
115 CPL_ERR_CONN_RESET = 20,
116 CPL_ERR_CONN_EXIST = 22,
117 CPL_ERR_ARP_MISS = 23,
118 CPL_ERR_BAD_SYN = 24,
119 CPL_ERR_CONN_TIMEDOUT = 30,
120 CPL_ERR_XMIT_TIMEDOUT = 31,
121 CPL_ERR_PERSIST_TIMEDOUT = 32,
122 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
123 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
124 CPL_ERR_RTX_NEG_ADVICE = 35,
125 CPL_ERR_PERSIST_NEG_ADVICE = 36,
126 CPL_ERR_ABORT_FAILED = 42,
131 CPL_CONN_POLICY_AUTO = 0,
132 CPL_CONN_POLICY_ASK = 1,
133 CPL_CONN_POLICY_FILTER = 2,
134 CPL_CONN_POLICY_DENY = 3
139 ULP_MODE_TCP_DDP = 1,
146 ULP_CRC_HEADER = 1 << 0,
147 ULP_CRC_DATA = 1 << 1
151 CPL_PASS_OPEN_ACCEPT,
152 CPL_PASS_OPEN_REJECT,
153 CPL_PASS_OPEN_ACCEPT_TNL
157 CPL_ABORT_SEND_RST = 0,
159 CPL_ABORT_POST_CLOSE_REQ = 2
162 enum { /* TX_PKT_LSO ethernet types */
169 enum { /* TCP congestion control algorithms */
176 enum { /* RSS hash type */
178 RSS_HASH_2_TUPLE = 1,
179 RSS_HASH_4_TUPLE = 2,
189 #define V_OPCODE(x) ((x) << S_OPCODE)
190 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
191 #define G_TID(x) ((x) & 0xFFFFFF)
193 /* tid is assumed to be 24-bits */
194 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
196 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
198 /* extract the TID from a CPL command */
199 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
204 #if defined(__LITTLE_ENDIAN_BITFIELD)
219 #if defined(__LITTLE_ENDIAN_BITFIELD)
230 #define S_HASHTYPE 22
231 #define M_HASHTYPE 0x3
232 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
235 #define M_QNUM 0xFFFF
236 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
239 struct work_request_hdr {
251 #define wrh_hi u.ilp32.wr_hi
252 #define wrh_lo u.ilp32.wr_lo
253 #define wrh_hilo u.lp64.wr_hilo
256 #define S_WR_SGE_CREDITS 0
257 #define M_WR_SGE_CREDITS 0xFF
258 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
259 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
261 #define S_WR_SGLSFLT 8
262 #define M_WR_SGLSFLT 0xFF
263 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
264 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
266 #define S_WR_BCNTLFLT 16
267 #define M_WR_BCNTLFLT 0xF
268 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
269 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
272 * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before
273 * and after the BYPASS WR if the ATOMIC bit is set.
275 #define S_WR_ATOMIC 16
276 #define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
277 #define F_WR_ATOMIC V_WR_ATOMIC(1U)
280 * Applicable to BYPASS WRs only: the uP will flush buffered non abort
283 #define S_WR_FLUSH 17
284 #define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
285 #define F_WR_FLUSH V_WR_FLUSH(1U)
288 #define V_WR_CHN(x) ((x) << S_WR_CHN)
289 #define F_WR_CHN V_WR_CHN(1U)
291 #define S_WR_CHN_VLD 19
292 #define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD)
293 #define F_WR_CHN_VLD V_WR_CHN_VLD(1U)
295 #define S_WR_DATATYPE 20
296 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
297 #define F_WR_DATATYPE V_WR_DATATYPE(1U)
299 #define S_WR_COMPL 21
300 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
301 #define F_WR_COMPL V_WR_COMPL(1U)
304 #define V_WR_EOP(x) ((x) << S_WR_EOP)
305 #define F_WR_EOP V_WR_EOP(1U)
308 #define V_WR_SOP(x) ((x) << S_WR_SOP)
309 #define F_WR_SOP V_WR_SOP(1U)
313 #define V_WR_OP(x) ((x) << S_WR_OP)
314 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
318 #define M_WR_LEN 0xFF
319 #define V_WR_LEN(x) ((x) << S_WR_LEN)
320 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
323 #define M_WR_TID 0xFFFFF
324 #define V_WR_TID(x) ((x) << S_WR_TID)
325 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
327 #define S_WR_CR_FLUSH 30
328 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
329 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
332 #define V_WR_GEN(x) ((x) << S_WR_GEN)
333 #define F_WR_GEN V_WR_GEN(1U)
334 #define G_WR_GEN(x) ((x) >> S_WR_GEN)
336 # define WR_HDR struct work_request_hdr wr
340 # define RSS_HDR struct rss_header rss_hdr;
343 /* option 0 lower-half fields */
344 #define S_CPL_STATUS 0
345 #define M_CPL_STATUS 0xFF
346 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
347 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
349 #define S_INJECT_TIMER 6
350 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
351 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
353 #define S_NO_OFFLOAD 7
354 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
355 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
358 #define M_ULP_MODE 0xF
359 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
360 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
362 #define S_RCV_BUFSIZ 12
363 #define M_RCV_BUFSIZ 0x3FFF
364 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
365 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
369 #define V_TOS(x) ((x) << S_TOS)
370 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
372 /* option 0 upper-half fields */
374 #define V_DELACK(x) ((x) << S_DELACK)
375 #define F_DELACK V_DELACK(1U)
378 #define V_NO_CONG(x) ((x) << S_NO_CONG)
379 #define F_NO_CONG V_NO_CONG(1U)
381 #define S_SRC_MAC_SEL 2
382 #define M_SRC_MAC_SEL 0x3
383 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
384 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
387 #define M_L2T_IDX 0x7FF
388 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
389 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
391 #define S_TX_CHANNEL 15
392 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
393 #define F_TX_CHANNEL V_TX_CHANNEL(1U)
395 #define S_TCAM_BYPASS 16
396 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
397 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
400 #define V_NAGLE(x) ((x) << S_NAGLE)
401 #define F_NAGLE V_NAGLE(1U)
403 #define S_WND_SCALE 18
404 #define M_WND_SCALE 0xF
405 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
406 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
408 #define S_KEEP_ALIVE 22
409 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
410 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
412 #define S_MAX_RETRANS 23
413 #define M_MAX_RETRANS 0xF
414 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
415 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
417 #define S_MAX_RETRANS_OVERRIDE 27
418 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
419 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
422 #define M_MSS_IDX 0xF
423 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
424 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
426 /* option 1 fields */
427 #define S_RSS_ENABLE 0
428 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
429 #define F_RSS_ENABLE V_RSS_ENABLE(1U)
431 #define S_RSS_MASK_LEN 1
432 #define M_RSS_MASK_LEN 0x7
433 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
434 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
437 #define M_CPU_IDX 0x3F
438 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
439 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
441 #define S_OPT1_VLAN 6
442 #define M_OPT1_VLAN 0xFFF
443 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
444 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
446 #define S_MAC_MATCH_VALID 18
447 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
448 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
450 #define S_CONN_POLICY 19
451 #define M_CONN_POLICY 0x3
452 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
453 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
455 #define S_SYN_DEFENSE 21
456 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
457 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
459 #define S_VLAN_PRI 22
460 #define M_VLAN_PRI 0x3
461 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
462 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
464 #define S_VLAN_PRI_VALID 24
465 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
466 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
468 #define S_PKT_TYPE 25
469 #define M_PKT_TYPE 0x3
470 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
471 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
473 #define S_MAC_MATCH 27
474 #define M_MAC_MATCH 0x1F
475 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
476 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
478 /* option 2 fields */
479 #define S_CPU_INDEX 0
480 #define M_CPU_INDEX 0x7F
481 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
482 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
484 #define S_CPU_INDEX_VALID 7
485 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
486 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
488 #define S_RX_COALESCE 8
489 #define M_RX_COALESCE 0x3
490 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
491 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
493 #define S_RX_COALESCE_VALID 10
494 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
495 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
497 #define S_CONG_CONTROL_FLAVOR 11
498 #define M_CONG_CONTROL_FLAVOR 0x3
499 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
500 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
502 #define S_PACING_FLAVOR 13
503 #define M_PACING_FLAVOR 0x3
504 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
505 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
507 #define S_FLAVORS_VALID 15
508 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
509 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
511 #define S_RX_FC_DISABLE 16
512 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
513 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
515 #define S_RX_FC_VALID 17
516 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
517 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
519 struct cpl_pass_open_req {
532 struct cpl_pass_open_rpl {
543 struct cpl_pass_establish {
557 /* cpl_pass_establish.tos_tid fields */
558 #define S_PASS_OPEN_TID 0
559 #define M_PASS_OPEN_TID 0xFFFFFF
560 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
561 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
563 #define S_PASS_OPEN_TOS 24
564 #define M_PASS_OPEN_TOS 0xFF
565 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
566 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
568 /* cpl_pass_establish.l2t_idx fields */
569 #define S_L2T_IDX16 5
570 #define M_L2T_IDX16 0x7FF
571 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
572 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
574 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
575 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
576 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
577 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
578 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
579 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
581 struct cpl_pass_accept_req {
589 struct tcp_options tcp_options;
593 #if defined(__LITTLE_ENDIAN_BITFIELD)
609 struct cpl_pass_accept_rpl {
619 struct cpl_act_open_req {
632 /* cpl_act_open_req.params fields */
633 #define S_AOPEN_VLAN_PRI 9
634 #define M_AOPEN_VLAN_PRI 0x3
635 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
636 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
638 #define S_AOPEN_VLAN_PRI_VALID 11
639 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
640 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
642 #define S_AOPEN_PKT_TYPE 12
643 #define M_AOPEN_PKT_TYPE 0x3
644 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
645 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
647 #define S_AOPEN_MAC_MATCH 14
648 #define M_AOPEN_MAC_MATCH 0x1F
649 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
650 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
652 #define S_AOPEN_MAC_MATCH_VALID 19
653 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
654 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
656 #define S_AOPEN_IFF_VLAN 20
657 #define M_AOPEN_IFF_VLAN 0xFFF
658 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
659 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
661 struct cpl_act_open_rpl {
673 struct cpl_act_establish {
694 struct cpl_get_tcb_rpl {
710 /* cpl_set_tcb.reply fields */
712 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
713 #define F_NO_REPLY V_NO_REPLY(1U)
715 struct cpl_set_tcb_field {
725 struct cpl_set_tcb_rpl {
736 #if defined(__LITTLE_ENDIAN_BITFIELD)
750 struct cpl_pcmd_reply {
758 struct cpl_close_con_req {
764 struct cpl_close_con_rpl {
773 struct cpl_close_listserv_req {
781 struct cpl_close_listserv_rpl {
788 struct cpl_abort_req_rss {
797 struct cpl_abort_req {
806 struct cpl_abort_rpl_rss {
815 struct cpl_abort_rpl {
824 struct cpl_peer_close {
838 /* tx_data_wr.flags fields */
839 #define S_TX_ACK_PAGES 21
840 #define M_TX_ACK_PAGES 0x7
841 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
842 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
844 /* tx_data_wr.param fields */
846 #define M_TX_PORT 0x7
847 #define V_TX_PORT(x) ((x) << S_TX_PORT)
848 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
852 #define V_TX_MSS(x) ((x) << S_TX_MSS)
853 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
856 #define M_TX_QOS 0xFF
857 #define V_TX_QOS(x) ((x) << S_TX_QOS)
858 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
860 #define S_TX_SNDBUF 16
861 #define M_TX_SNDBUF 0xFFFF
862 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
863 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
873 /* cpl_tx_data.flags fields */
874 #define S_TX_ULP_SUBMODE 6
875 #define M_TX_ULP_SUBMODE 0xF
876 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
877 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
879 #define S_TX_ULP_MODE 10
880 #define M_TX_ULP_MODE 0xF
881 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
882 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
884 #define S_TX_SHOVE 14
885 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
886 #define F_TX_SHOVE V_TX_SHOVE(1U)
889 #define V_TX_MORE(x) ((x) << S_TX_MORE)
890 #define F_TX_MORE V_TX_MORE(1U)
892 /* additional tx_data_wr.flags fields */
893 #define S_TX_CPU_IDX 0
894 #define M_TX_CPU_IDX 0x3F
895 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
896 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
899 #define V_TX_URG(x) ((x) << S_TX_URG)
900 #define F_TX_URG V_TX_URG(1U)
902 #define S_TX_CLOSE 17
903 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
904 #define F_TX_CLOSE V_TX_CLOSE(1U)
907 #define V_TX_INIT(x) ((x) << S_TX_INIT)
908 #define F_TX_INIT V_TX_INIT(1U)
910 #define S_TX_IMM_ACK 19
911 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
912 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
914 #define S_TX_IMM_DMA 20
915 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
916 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
918 struct cpl_tx_data_ack {
933 struct cpl_sge_ec_cr_return {
941 struct cpl_rdma_ec_status {
948 struct mngt_pktsched_wr {
960 struct cpl_iscsi_hdr {
971 /* cpl_iscsi_hdr.pdu_len_ddp fields */
972 #define S_ISCSI_PDU_LEN 0
973 #define M_ISCSI_PDU_LEN 0x7FFF
974 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
975 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
977 #define S_ISCSI_DDP 15
978 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
979 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
988 #if defined(__LITTLE_ENDIAN_BITFIELD)
1004 struct cpl_rx_data_ack {
1006 union opcode_tid ot;
1010 /* cpl_rx_data_ack.ack_seq fields */
1011 #define S_RX_CREDITS 0
1012 #define M_RX_CREDITS 0x7FFFFFF
1013 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1014 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1016 #define S_RX_MODULATE 27
1017 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
1018 #define F_RX_MODULATE V_RX_MODULATE(1U)
1020 #define S_RX_FORCE_ACK 28
1021 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1022 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1024 #define S_RX_DACK_MODE 29
1025 #define M_RX_DACK_MODE 0x3
1026 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1027 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1029 #define S_RX_DACK_CHANGE 31
1030 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1031 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1033 struct cpl_rx_urg_notify {
1035 union opcode_tid ot;
1039 struct cpl_rx_ddp_complete {
1041 union opcode_tid ot;
1045 struct cpl_rx_data_ddp {
1047 union opcode_tid ot;
1056 __be32 ddpvld_status;
1059 /* cpl_rx_data_ddp.ddpvld_status fields */
1060 #define S_DDP_STATUS 0
1061 #define M_DDP_STATUS 0xFF
1062 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1063 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1065 #define S_DDP_VALID 15
1066 #define M_DDP_VALID 0x1FFFF
1067 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1068 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1070 #define S_DDP_PPOD_MISMATCH 15
1071 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1072 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1074 #define S_DDP_PDU 16
1075 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1076 #define F_DDP_PDU V_DDP_PDU(1U)
1078 #define S_DDP_LLIMIT_ERR 17
1079 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1080 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1082 #define S_DDP_PPOD_PARITY_ERR 18
1083 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1084 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1086 #define S_DDP_PADDING_ERR 19
1087 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1088 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1090 #define S_DDP_HDRCRC_ERR 20
1091 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1092 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1094 #define S_DDP_DATACRC_ERR 21
1095 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1096 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1098 #define S_DDP_INVALID_TAG 22
1099 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1100 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1102 #define S_DDP_ULIMIT_ERR 23
1103 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1104 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1106 #define S_DDP_OFFSET_ERR 24
1107 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1108 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1110 #define S_DDP_COLOR_ERR 25
1111 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1112 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1114 #define S_DDP_TID_MISMATCH 26
1115 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1116 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1118 #define S_DDP_INVALID_PPOD 27
1119 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1120 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1122 #define S_DDP_ULP_MODE 28
1123 #define M_DDP_ULP_MODE 0xF
1124 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1125 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1127 /* cpl_rx_data_ddp.ddp_report fields */
1128 #define S_DDP_OFFSET 0
1129 #define M_DDP_OFFSET 0x3FFFFF
1130 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1131 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1133 #define S_DDP_DACK_MODE 22
1134 #define M_DDP_DACK_MODE 0x3
1135 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1136 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1138 #define S_DDP_URG 24
1139 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1140 #define F_DDP_URG V_DDP_URG(1U)
1142 #define S_DDP_PSH 25
1143 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1144 #define F_DDP_PSH V_DDP_PSH(1U)
1146 #define S_DDP_BUF_COMPLETE 26
1147 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1148 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1150 #define S_DDP_BUF_TIMED_OUT 27
1151 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1152 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1154 #define S_DDP_BUF_IDX 28
1155 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1156 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1164 struct cpl_tx_pkt_coalesce {
1170 struct tx_pkt_coalesce_wr {
1172 struct cpl_tx_pkt_coalesce cpl[0];
1175 struct cpl_tx_pkt_lso {
1184 struct cpl_tx_pkt_batch_entry {
1190 struct cpl_tx_pkt_batch {
1192 struct cpl_tx_pkt_batch_entry pkt_entry[7];
1196 /* cpl_tx_pkt*.cntrl fields */
1197 #define S_TXPKT_VLAN 0
1198 #define M_TXPKT_VLAN 0xFFFF
1199 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1200 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1202 #define S_TXPKT_INTF 16
1203 #define M_TXPKT_INTF 0xF
1204 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1205 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1207 #define S_TXPKT_IPCSUM_DIS 20
1208 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1209 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1211 #define S_TXPKT_L4CSUM_DIS 21
1212 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1213 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1215 #define S_TXPKT_VLAN_VLD 22
1216 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1217 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1219 #define S_TXPKT_LOOPBACK 23
1220 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1221 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1223 #define S_TXPKT_OPCODE 24
1224 #define M_TXPKT_OPCODE 0xFF
1225 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1226 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1228 /* cpl_tx_pkt_lso.lso_info fields */
1230 #define M_LSO_MSS 0x3FFF
1231 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1232 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1234 #define S_LSO_ETH_TYPE 14
1235 #define M_LSO_ETH_TYPE 0x3
1236 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1237 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1239 #define S_LSO_TCPHDR_WORDS 16
1240 #define M_LSO_TCPHDR_WORDS 0xF
1241 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1242 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1244 #define S_LSO_IPHDR_WORDS 20
1245 #define M_LSO_IPHDR_WORDS 0xF
1246 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1247 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1249 #define S_LSO_IPV6 24
1250 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1251 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1253 struct cpl_trace_pkt {
1256 #if defined(__LITTLE_ENDIAN_BITFIELD)
1264 #if defined(__LITTLE_ENDIAN_BITFIELD)
1272 #endif /* CHELSIO_FW */
1275 #if defined(__LITTLE_ENDIAN_BITFIELD)
1289 #if defined(__LITTLE_ENDIAN_BITFIELD)
1307 struct cpl_l2t_write_req {
1309 union opcode_tid ot;
1316 /* cpl_l2t_write_req.params fields */
1317 #define S_L2T_W_IDX 0
1318 #define M_L2T_W_IDX 0x7FF
1319 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1320 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1322 #define S_L2T_W_VLAN 11
1323 #define M_L2T_W_VLAN 0xFFF
1324 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1325 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1327 #define S_L2T_W_IFF 23
1328 #define M_L2T_W_IFF 0xF
1329 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1330 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1332 #define S_L2T_W_PRIO 27
1333 #define M_L2T_W_PRIO 0x7
1334 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1335 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1337 struct cpl_l2t_write_rpl {
1339 union opcode_tid ot;
1344 struct cpl_l2t_read_req {
1346 union opcode_tid ot;
1351 struct cpl_l2t_read_rpl {
1353 union opcode_tid ot;
1359 /* cpl_l2t_read_rpl.params fields */
1360 #define S_L2T_R_PRIO 0
1361 #define M_L2T_R_PRIO 0x7
1362 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1363 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1365 #define S_L2T_R_VLAN 8
1366 #define M_L2T_R_VLAN 0xFFF
1367 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1368 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1370 #define S_L2T_R_IFF 20
1371 #define M_L2T_R_IFF 0xF
1372 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1373 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1375 #define S_L2T_STATUS 24
1376 #define M_L2T_STATUS 0xFF
1377 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1378 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1380 struct cpl_smt_write_req {
1382 union opcode_tid ot;
1384 #if defined(__LITTLE_ENDIAN_BITFIELD)
1398 struct cpl_smt_write_rpl {
1400 union opcode_tid ot;
1405 struct cpl_smt_read_req {
1407 union opcode_tid ot;
1409 #if defined(__LITTLE_ENDIAN_BITFIELD)
1419 struct cpl_smt_read_rpl {
1421 union opcode_tid ot;
1423 #if defined(__LITTLE_ENDIAN_BITFIELD)
1437 struct cpl_rte_delete_req {
1439 union opcode_tid ot;
1443 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1444 #define S_RTE_REQ_LUT_IX 8
1445 #define M_RTE_REQ_LUT_IX 0x7FF
1446 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1447 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1449 #define S_RTE_REQ_LUT_BASE 19
1450 #define M_RTE_REQ_LUT_BASE 0x7FF
1451 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1452 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1454 #define S_RTE_READ_REQ_SELECT 31
1455 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1456 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1458 struct cpl_rte_delete_rpl {
1460 union opcode_tid ot;
1465 struct cpl_rte_write_req {
1467 union opcode_tid ot;
1468 #if defined(__LITTLE_ENDIAN_BITFIELD)
1471 __u8 write_l2t_lut:1;
1473 __u8 write_l2t_lut:1;
1485 /* cpl_rte_write_req.lut_params fields */
1486 #define S_RTE_WRITE_REQ_LUT_IX 10
1487 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1488 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1489 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1491 #define S_RTE_WRITE_REQ_LUT_BASE 21
1492 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1493 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1494 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1496 struct cpl_rte_write_rpl {
1498 union opcode_tid ot;
1503 struct cpl_rte_read_req {
1505 union opcode_tid ot;
1509 struct cpl_rte_read_rpl {
1511 union opcode_tid ot;
1515 #if defined(__LITTLE_ENDIAN_BITFIELD)
1526 struct cpl_tid_release {
1528 union opcode_tid ot;
1532 struct cpl_barrier {
1538 struct cpl_rdma_read_req {
1543 struct cpl_rdma_terminate {
1547 #if defined(__LITTLE_ENDIAN_BITFIELD)
1561 /* cpl_rdma_terminate.tid_len fields */
1562 #define S_FLIT_CNT 0
1563 #define M_FLIT_CNT 0xFF
1564 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1565 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1567 #define S_TERM_TID 8
1568 #define M_TERM_TID 0xFFFFF
1569 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1570 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1572 /* ULP_TX opcodes */
1573 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1575 #define S_ULPTX_CMD 28
1576 #define M_ULPTX_CMD 0xF
1577 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1579 #define S_ULPTX_NFLITS 0
1580 #define M_ULPTX_NFLITS 0xFF
1581 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1585 __be32 cmd_lock_addr;
1589 /* ulp_mem_io.cmd_lock_addr fields */
1590 #define S_ULP_MEMIO_ADDR 0
1591 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
1592 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1594 #define S_ULP_MEMIO_LOCK 27
1595 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1596 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1598 /* ulp_mem_io.len fields */
1599 #define S_ULP_MEMIO_DATA_LEN 28
1600 #define M_ULP_MEMIO_DATA_LEN 0xF
1601 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1608 /* ulp_txpkt.cmd_dest fields */
1609 #define S_ULP_TXPKT_DEST 24
1610 #define M_ULP_TXPKT_DEST 0xF
1611 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1613 #endif /* T3_CPL_H */