2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 CPL_PASS_OPEN_REQ = 0x1,
35 CPL_PASS_ACCEPT_RPL = 0x2,
36 CPL_ACT_OPEN_REQ = 0x3,
38 CPL_SET_TCB_FIELD = 0x5,
40 CPL_CLOSE_CON_REQ = 0x8,
41 CPL_CLOSE_LISTSRV_REQ = 0x9,
45 CPL_RX_DATA_ACK = 0xD,
47 CPL_RTE_DELETE_REQ = 0xF,
48 CPL_RTE_WRITE_REQ = 0x10,
49 CPL_RTE_READ_REQ = 0x11,
50 CPL_L2T_WRITE_REQ = 0x12,
51 CPL_L2T_READ_REQ = 0x13,
52 CPL_SMT_WRITE_REQ = 0x14,
53 CPL_SMT_READ_REQ = 0x15,
54 CPL_TAG_WRITE_REQ = 0x16,
56 CPL_TID_RELEASE = 0x1A,
57 CPL_TAG_READ_REQ = 0x1B,
58 CPL_TX_PKT_FSO = 0x1E,
59 CPL_TX_PKT_ISO = 0x1F,
61 CPL_CLOSE_LISTSRV_RPL = 0x20,
63 CPL_GET_TCB_RPL = 0x22,
64 CPL_L2T_WRITE_RPL = 0x23,
65 CPL_PASS_OPEN_RPL = 0x24,
66 CPL_ACT_OPEN_RPL = 0x25,
67 CPL_PEER_CLOSE = 0x26,
68 CPL_RTE_DELETE_RPL = 0x27,
69 CPL_RTE_WRITE_RPL = 0x28,
70 CPL_RX_URG_PKT = 0x29,
71 CPL_TAG_WRITE_RPL = 0x2A,
72 CPL_ABORT_REQ_RSS = 0x2B,
73 CPL_RX_URG_NOTIFY = 0x2C,
74 CPL_ABORT_RPL_RSS = 0x2D,
75 CPL_SMT_WRITE_RPL = 0x2E,
76 CPL_TX_DATA_ACK = 0x2F,
78 CPL_RX_PHYS_ADDR = 0x30,
79 CPL_PCMD_READ_RPL = 0x31,
80 CPL_CLOSE_CON_RPL = 0x32,
82 CPL_L2T_READ_RPL = 0x34,
84 CPL_RDMA_CQE_READ_RSP = 0x36,
85 CPL_RDMA_CQE_ERR = 0x37,
86 CPL_RTE_READ_RPL = 0x38,
88 CPL_SET_TCB_RPL = 0x3A,
90 CPL_TAG_READ_RPL = 0x3C,
91 CPL_HIT_NOTIFY = 0x3D,
92 CPL_PKT_NOTIFY = 0x3E,
93 CPL_RX_DDP_COMPLETE = 0x3F,
95 CPL_ACT_ESTABLISH = 0x40,
96 CPL_PASS_ESTABLISH = 0x41,
97 CPL_RX_DATA_DDP = 0x42,
98 CPL_SMT_READ_RPL = 0x43,
99 CPL_PASS_ACCEPT_REQ = 0x44,
100 CPL_RX2TX_PKT = 0x45,
101 CPL_RX_FCOE_DDP = 0x46,
103 CPL_T5_TRACE_PKT = 0x48,
104 CPL_RX_ISCSI_DDP = 0x49,
105 CPL_RX_FCOE_DIF = 0x4A,
106 CPL_RX_DATA_DIF = 0x4B,
107 CPL_ERR_NOTIFY = 0x4D,
109 CPL_RDMA_READ_REQ = 0x60,
110 CPL_RX_ISCSI_DIF = 0x60,
112 CPL_SET_LE_REQ = 0x80,
113 CPL_PASS_OPEN_REQ6 = 0x81,
114 CPL_ACT_OPEN_REQ6 = 0x83,
116 CPL_RDMA_TERMINATE = 0xA2,
117 CPL_RDMA_WRITE = 0xA4,
118 CPL_SGE_EGR_UPDATE = 0xA5,
119 CPL_SET_LE_RPL = 0xA6,
122 CPL_T5_RDMA_READ_REQ = 0xA9,
123 CPL_RDMA_ATOMIC_REQ = 0xAA,
124 CPL_RDMA_ATOMIC_RPL = 0xAB,
125 CPL_RDMA_IMM_DATA = 0xAC,
126 CPL_RDMA_IMM_DATA_SE = 0xAD,
128 CPL_TRACE_PKT = 0xB0,
129 CPL_TRACE_PKT_T5 = 0x48,
130 CPL_RX2TX_DATA = 0xB1,
131 CPL_ISCSI_DATA = 0xB2,
132 CPL_FCOE_DATA = 0xB3,
140 CPL_TX_PKT_LSO = 0xED,
141 CPL_TX_PKT_XT = 0xEE,
143 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
148 CPL_ERR_TCAM_PARITY = 1,
149 CPL_ERR_TCAM_FULL = 3,
150 CPL_ERR_BAD_LENGTH = 15,
151 CPL_ERR_BAD_ROUTE = 18,
152 CPL_ERR_CONN_RESET = 20,
153 CPL_ERR_CONN_EXIST_SYNRECV = 21,
154 CPL_ERR_CONN_EXIST = 22,
155 CPL_ERR_ARP_MISS = 23,
156 CPL_ERR_BAD_SYN = 24,
157 CPL_ERR_CONN_TIMEDOUT = 30,
158 CPL_ERR_XMIT_TIMEDOUT = 31,
159 CPL_ERR_PERSIST_TIMEDOUT = 32,
160 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
161 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
162 CPL_ERR_RTX_NEG_ADVICE = 35,
163 CPL_ERR_PERSIST_NEG_ADVICE = 36,
164 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
165 CPL_ERR_WAIT_ARP_RPL = 41,
166 CPL_ERR_ABORT_FAILED = 42,
167 CPL_ERR_IWARP_FLM = 50,
171 CPL_CONN_POLICY_AUTO = 0,
172 CPL_CONN_POLICY_ASK = 1,
173 CPL_CONN_POLICY_FILTER = 2,
174 CPL_CONN_POLICY_DENY = 3
186 ULP_CRC_HEADER = 1 << 0,
187 ULP_CRC_DATA = 1 << 1
191 CPL_PASS_OPEN_ACCEPT,
192 CPL_PASS_OPEN_REJECT,
193 CPL_PASS_OPEN_ACCEPT_TNL
197 CPL_ABORT_SEND_RST = 0,
201 enum { /* TX_PKT_XT checksum types */
215 enum { /* packet type in CPL_RX_PKT */
216 PKTYPE_XACT_UCAST = 0,
217 PKTYPE_HASH_UCAST = 1,
218 PKTYPE_XACT_MCAST = 2,
219 PKTYPE_HASH_MCAST = 3,
225 enum { /* DMAC type in CPL_RX_PKT */
231 enum { /* TCP congestion control algorithms */
238 enum { /* RSS hash type */
239 RSS_HASH_NONE = 0, /* no hash computed */
240 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */
241 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */
242 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */
245 enum { /* LE commands */
250 enum { /* LE request size */
264 #define S_CPL_OPCODE 24
265 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
266 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF)
267 #define G_TID(x) ((x) & 0xFFFFFF)
269 /* tid is assumed to be 24-bits */
270 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
272 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
274 /* extract the TID from a CPL command */
275 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
277 /* partitioning of TID fields that also carry a queue id */
279 #define M_TID_TID 0x3fff
280 #define V_TID_TID(x) ((x) << S_TID_TID)
281 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
284 #define M_TID_QID 0x3ff
285 #define V_TID_QID(x) ((x) << S_TID_QID)
286 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID)
296 #if defined(__LITTLE_ENDIAN_BITFIELD)
313 #if defined(__LITTLE_ENDIAN_BITFIELD)
332 #define S_HASHTYPE 20
333 #define M_HASHTYPE 0x3
334 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
337 #define M_QNUM 0xFFFF
338 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
341 struct work_request_hdr {
349 #define M_WR_LEN16 0xFF
350 #define V_WR_LEN16(x) ((x) << S_WR_LEN16)
351 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16)
356 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
357 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
359 # define WR_HDR struct work_request_hdr wr
360 # define WR_HDR_SIZE sizeof(struct work_request_hdr)
364 # define WR_HDR_SIZE 0
365 # define RSS_HDR struct rss_header rss_hdr;
368 /* option 0 fields */
369 #define S_ACCEPT_MODE 0
370 #define M_ACCEPT_MODE 0x3
371 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
372 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE)
375 #define M_TX_CHAN 0x3
376 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
377 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN)
380 #define V_NO_CONG(x) ((x) << S_NO_CONG)
381 #define F_NO_CONG V_NO_CONG(1U)
384 #define V_DELACK(x) ((x) << S_DELACK)
385 #define F_DELACK V_DELACK(1U)
387 #define S_INJECT_TIMER 6
388 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
389 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
391 #define S_NON_OFFLOAD 7
392 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
393 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
396 #define M_ULP_MODE 0xF
397 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
398 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
400 #define S_RCV_BUFSIZ 12
401 #define M_RCV_BUFSIZ 0x3FFU
402 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
403 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
407 #define V_DSCP(x) ((x) << S_DSCP)
408 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP)
410 #define S_SMAC_SEL 28
411 #define M_SMAC_SEL 0xFF
412 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
413 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL)
416 #define M_L2T_IDX 0xFFF
417 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
418 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
420 #define S_TCAM_BYPASS 48
421 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
422 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
425 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
426 #define F_NAGLE V_NAGLE(1ULL)
428 #define S_WND_SCALE 50
429 #define M_WND_SCALE 0xF
430 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
431 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
433 #define S_KEEP_ALIVE 54
434 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
435 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL)
439 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
440 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT)
442 #define S_MAX_RT_OVERRIDE 59
443 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
444 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL)
447 #define M_MSS_IDX 0xF
448 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
449 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
451 /* option 1 fields */
452 #define S_SYN_RSS_ENABLE 0
453 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
454 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U)
456 #define S_SYN_RSS_USE_HASH 1
457 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
458 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U)
460 #define S_SYN_RSS_QUEUE 2
461 #define M_SYN_RSS_QUEUE 0x3FF
462 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
463 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE)
465 #define S_LISTEN_INTF 12
466 #define M_LISTEN_INTF 0xFF
467 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
468 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF)
470 #define S_LISTEN_FILTER 20
471 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
472 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U)
474 #define S_SYN_DEFENSE 21
475 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
476 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
478 #define S_CONN_POLICY 22
479 #define M_CONN_POLICY 0x3
480 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
481 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
483 #define S_FILT_INFO 28
484 #define M_FILT_INFO 0xfffffffffULL
485 #define V_FILT_INFO(x) ((x) << S_FILT_INFO)
486 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO)
488 /* option 2 fields */
489 #define S_RSS_QUEUE 0
490 #define M_RSS_QUEUE 0x3FF
491 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
492 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
494 #define S_RSS_QUEUE_VALID 10
495 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
496 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
498 #define S_RX_COALESCE_VALID 11
499 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
500 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
502 #define S_RX_COALESCE 12
503 #define M_RX_COALESCE 0x3
504 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
505 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
507 #define S_CONG_CNTRL 14
508 #define M_CONG_CNTRL 0x3
509 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
510 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
514 #define V_PACE(x) ((x) << S_PACE)
515 #define G_PACE(x) (((x) >> S_PACE) & M_PACE)
517 #define S_CONG_CNTRL_VALID 18
518 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
519 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
521 #define S_PACE_VALID 19
522 #define V_PACE_VALID(x) ((x) << S_PACE_VALID)
523 #define F_PACE_VALID V_PACE_VALID(1U)
525 #define S_RX_FC_DISABLE 20
526 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
527 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
529 #define S_RX_FC_DDP 21
530 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
531 #define F_RX_FC_DDP V_RX_FC_DDP(1U)
533 #define S_RX_FC_VALID 22
534 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
535 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
537 #define S_TX_QUEUE 23
538 #define M_TX_QUEUE 0x7
539 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
540 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE)
542 #define S_RX_CHANNEL 26
543 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
544 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
546 #define S_CCTRL_ECN 27
547 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
548 #define F_CCTRL_ECN V_CCTRL_ECN(1U)
550 #define S_WND_SCALE_EN 28
551 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
552 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U)
554 #define S_TSTAMPS_EN 29
555 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
556 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
559 #define V_SACK_EN(x) ((x) << S_SACK_EN)
560 #define F_SACK_EN V_SACK_EN(1U)
562 #define S_T5_OPT_2_VALID 31
563 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
564 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
566 struct cpl_pass_open_req {
577 struct cpl_pass_open_req6 {
590 struct cpl_pass_open_rpl {
597 struct cpl_pass_establish {
608 /* cpl_pass_establish.tos_stid fields */
609 #define S_PASS_OPEN_TID 0
610 #define M_PASS_OPEN_TID 0xFFFFFF
611 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
612 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
614 #define S_PASS_OPEN_TOS 24
615 #define M_PASS_OPEN_TOS 0xFF
616 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
617 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
619 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
620 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
621 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
622 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
623 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
624 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
626 struct cpl_pass_accept_req {
635 struct tcp_options tcpopt;
638 /* cpl_pass_accept_req.hdr_len fields */
639 #define S_SYN_RX_CHAN 0
640 #define M_SYN_RX_CHAN 0xF
641 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
642 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
644 #define S_TCP_HDR_LEN 10
645 #define M_TCP_HDR_LEN 0x3F
646 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
647 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
649 #define S_IP_HDR_LEN 16
650 #define M_IP_HDR_LEN 0x3FF
651 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
652 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
654 #define S_ETH_HDR_LEN 26
655 #define M_ETH_HDR_LEN 0x3F
656 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
657 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
659 /* cpl_pass_accept_req.l2info fields */
660 #define S_SYN_MAC_IDX 0
661 #define M_SYN_MAC_IDX 0x1FF
662 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
663 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
665 #define S_SYN_XACT_MATCH 9
666 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
667 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
669 #define S_SYN_INTF 12
670 #define M_SYN_INTF 0xF
671 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
672 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
674 struct cpl_pass_accept_rpl {
681 struct cpl_t5_pass_accept_rpl {
690 struct cpl_act_open_req {
702 #define S_FILTER_TUPLE 24
703 #define M_FILTER_TUPLE 0xFFFFFFFFFF
704 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
705 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
706 struct cpl_t5_act_open_req {
719 struct cpl_act_open_req6 {
733 struct cpl_t5_act_open_req6 {
748 struct cpl_act_open_rpl {
754 /* cpl_act_open_rpl.atid_status fields */
755 #define S_AOPEN_STATUS 0
756 #define M_AOPEN_STATUS 0xFF
757 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
758 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
760 #define S_AOPEN_ATID 8
761 #define M_AOPEN_ATID 0xFFFFFF
762 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
763 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
765 struct cpl_act_establish {
783 /* cpl_get_tcb.reply_ctrl fields */
785 #define M_QUEUENO 0x3FF
786 #define V_QUEUENO(x) ((x) << S_QUEUENO)
787 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
789 #define S_REPLY_CHAN 14
790 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
791 #define F_REPLY_CHAN V_REPLY_CHAN(1U)
793 #define S_NO_REPLY 15
794 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
795 #define F_NO_REPLY V_NO_REPLY(1U)
797 struct cpl_get_tcb_rpl {
812 struct cpl_set_tcb_field {
821 struct cpl_set_tcb_field_core {
829 /* cpl_set_tcb_field.word_cookie fields */
832 #define V_WORD(x) ((x) << S_WORD)
833 #define G_WORD(x) (((x) >> S_WORD) & M_WORD)
837 #define V_COOKIE(x) ((x) << S_COOKIE)
838 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
840 struct cpl_set_tcb_rpl {
849 struct cpl_close_con_req {
855 struct cpl_close_con_rpl {
864 struct cpl_close_listsvr_req {
871 /* additional cpl_close_listsvr_req.reply_ctrl field */
872 #define S_LISTSVR_IPV6 14
873 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
874 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U)
876 struct cpl_close_listsvr_rpl {
883 struct cpl_abort_req_rss {
890 struct cpl_abort_req {
899 struct cpl_abort_rpl_rss {
906 struct cpl_abort_rpl {
915 struct cpl_peer_close {
921 struct cpl_tid_release {
936 /* tx_data_wr.flags fields */
937 #define S_TX_ACK_PAGES 21
938 #define M_TX_ACK_PAGES 0x7
939 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
940 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
942 /* tx_data_wr.param fields */
944 #define M_TX_PORT 0x7
945 #define V_TX_PORT(x) ((x) << S_TX_PORT)
946 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
950 #define V_TX_MSS(x) ((x) << S_TX_MSS)
951 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
954 #define M_TX_QOS 0xFF
955 #define V_TX_QOS(x) ((x) << S_TX_QOS)
956 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
958 #define S_TX_SNDBUF 16
959 #define M_TX_SNDBUF 0xFFFF
960 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
961 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
970 /* cpl_tx_data.flags fields */
972 #define V_TX_PROXY(x) ((x) << S_TX_PROXY)
973 #define F_TX_PROXY V_TX_PROXY(1U)
975 #define S_TX_ULP_SUBMODE 6
976 #define M_TX_ULP_SUBMODE 0xF
977 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
978 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
980 #define S_TX_ULP_MODE 10
981 #define M_TX_ULP_MODE 0xF
982 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
983 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
985 #define S_TX_SHOVE 14
986 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
987 #define F_TX_SHOVE V_TX_SHOVE(1U)
990 #define V_TX_MORE(x) ((x) << S_TX_MORE)
991 #define F_TX_MORE V_TX_MORE(1U)
994 #define V_TX_URG(x) ((x) << S_TX_URG)
995 #define F_TX_URG V_TX_URG(1U)
997 #define S_TX_FLUSH 17
998 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
999 #define F_TX_FLUSH V_TX_FLUSH(1U)
1001 #define S_TX_SAVE 18
1002 #define V_TX_SAVE(x) ((x) << S_TX_SAVE)
1003 #define F_TX_SAVE V_TX_SAVE(1U)
1006 #define V_TX_TNL(x) ((x) << S_TX_TNL)
1007 #define F_TX_TNL V_TX_TNL(1U)
1009 /* additional tx_data_wr.flags fields */
1010 #define S_TX_CPU_IDX 0
1011 #define M_TX_CPU_IDX 0x3F
1012 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
1013 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
1015 #define S_TX_CLOSE 17
1016 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
1017 #define F_TX_CLOSE V_TX_CLOSE(1U)
1019 #define S_TX_INIT 18
1020 #define V_TX_INIT(x) ((x) << S_TX_INIT)
1021 #define F_TX_INIT V_TX_INIT(1U)
1023 #define S_TX_IMM_ACK 19
1024 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
1025 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
1027 #define S_TX_IMM_DMA 20
1028 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
1029 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
1031 struct cpl_tx_data_ack {
1033 union opcode_tid ot;
1037 struct cpl_wr_ack { /* XXX */
1039 union opcode_tid ot;
1046 struct cpl_tx_pkt_core {
1055 struct cpl_tx_pkt_core c;
1058 #define cpl_tx_pkt_xt cpl_tx_pkt
1060 /* cpl_tx_pkt_core.ctrl0 fields */
1061 #define S_TXPKT_VF 0
1062 #define M_TXPKT_VF 0xFF
1063 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
1064 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF)
1066 #define S_TXPKT_PF 8
1067 #define M_TXPKT_PF 0x7
1068 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
1069 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
1071 #define S_TXPKT_VF_VLD 11
1072 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1073 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1075 #define S_TXPKT_OVLAN_IDX 12
1076 #define M_TXPKT_OVLAN_IDX 0xF
1077 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1078 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1080 #define S_TXPKT_T5_OVLAN_IDX 12
1081 #define M_TXPKT_T5_OVLAN_IDX 0x7
1082 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX)
1083 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \
1084 M_TXPKT_T5_OVLAN_IDX)
1086 #define S_TXPKT_INTF 16
1087 #define M_TXPKT_INTF 0xF
1088 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1089 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1091 #define S_TXPKT_SPECIAL_STAT 20
1092 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1093 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1095 #define S_TXPKT_T5_FCS_DIS 21
1096 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS)
1097 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U)
1099 #define S_TXPKT_INS_OVLAN 21
1100 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1101 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1103 #define S_TXPKT_T5_INS_OVLAN 15
1104 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN)
1105 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U)
1107 #define S_TXPKT_STAT_DIS 22
1108 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1109 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1111 #define S_TXPKT_LOOPBACK 23
1112 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1113 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1115 #define S_TXPKT_TSTAMP 23
1116 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP)
1117 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U)
1119 #define S_TXPKT_OPCODE 24
1120 #define M_TXPKT_OPCODE 0xFF
1121 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1122 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1124 /* cpl_tx_pkt_core.ctrl1 fields */
1125 #define S_TXPKT_SA_IDX 0
1126 #define M_TXPKT_SA_IDX 0xFFF
1127 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
1128 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX)
1130 #define S_TXPKT_CSUM_END 12
1131 #define M_TXPKT_CSUM_END 0xFF
1132 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
1133 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END)
1135 #define S_TXPKT_CSUM_START 20
1136 #define M_TXPKT_CSUM_START 0x3FF
1137 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
1138 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START)
1140 #define S_TXPKT_IPHDR_LEN 20
1141 #define M_TXPKT_IPHDR_LEN 0x3FFF
1142 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
1143 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
1145 #define S_TXPKT_CSUM_LOC 30
1146 #define M_TXPKT_CSUM_LOC 0x3FF
1147 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
1148 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC)
1150 #define S_TXPKT_ETHHDR_LEN 34
1151 #define M_TXPKT_ETHHDR_LEN 0x3F
1152 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
1153 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
1155 #define S_TXPKT_CSUM_TYPE 40
1156 #define M_TXPKT_CSUM_TYPE 0xF
1157 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
1158 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
1160 #define S_TXPKT_VLAN 44
1161 #define M_TXPKT_VLAN 0xFFFF
1162 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
1163 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1165 #define S_TXPKT_VLAN_VLD 60
1166 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
1167 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
1169 #define S_TXPKT_IPSEC 61
1170 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
1171 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL)
1173 #define S_TXPKT_IPCSUM_DIS 62
1174 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
1175 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
1177 #define S_TXPKT_L4CSUM_DIS 63
1178 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
1179 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
1181 struct cpl_tx_pkt_lso_core {
1185 __be32 seqno_offset;
1187 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1190 struct cpl_tx_pkt_lso {
1192 struct cpl_tx_pkt_lso_core c;
1193 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1196 struct cpl_tx_pkt_ufo_core {
1203 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1206 struct cpl_tx_pkt_ufo {
1208 struct cpl_tx_pkt_ufo_core c;
1209 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1212 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
1213 #define S_LSO_TCPHDR_LEN 0
1214 #define M_LSO_TCPHDR_LEN 0xF
1215 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
1216 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
1218 #define S_LSO_IPHDR_LEN 4
1219 #define M_LSO_IPHDR_LEN 0xFFF
1220 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
1221 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
1223 #define S_LSO_ETHHDR_LEN 16
1224 #define M_LSO_ETHHDR_LEN 0xF
1225 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
1226 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
1228 #define S_LSO_IPV6 20
1229 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1230 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1232 #define S_LSO_OFLD_ENCAP 21
1233 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
1234 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U)
1236 #define S_LSO_LAST_SLICE 22
1237 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
1238 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
1240 #define S_LSO_FIRST_SLICE 23
1241 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1242 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1244 #define S_LSO_OPCODE 24
1245 #define M_LSO_OPCODE 0xFF
1246 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1247 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1249 #define S_LSO_T5_XFER_SIZE 0
1250 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
1251 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
1252 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
1254 /* cpl_tx_pkt_lso_core.mss fields */
1256 #define M_LSO_MSS 0x3FFF
1257 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1258 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1260 #define S_LSO_IPID_SPLIT 15
1261 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
1262 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U)
1264 struct cpl_tx_pkt_fso {
1269 __be32 param_offset;
1271 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */
1274 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
1275 #define S_FSO_XCHG_CLASS 21
1276 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS)
1277 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U)
1279 #define S_FSO_INITIATOR 20
1280 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR)
1281 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U)
1283 #define S_FSO_FCHDR_LEN 12
1284 #define M_FSO_FCHDR_LEN 0xF
1285 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN)
1286 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN)
1288 struct cpl_iscsi_hdr_no_rss {
1289 union opcode_tid ot;
1298 struct cpl_tx_data_iso {
1306 /* encapsulated CPL_TX_DATA follows here */
1309 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
1310 #define S_ISO_CPLHDR_LEN 18
1311 #define M_ISO_CPLHDR_LEN 0xF
1312 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN)
1313 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN)
1315 #define S_ISO_HDR_CRC 17
1316 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC)
1317 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U)
1319 #define S_ISO_DATA_CRC 16
1320 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC)
1321 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U)
1323 #define S_ISO_IMD_DATA_EN 15
1324 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN)
1325 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U)
1327 #define S_ISO_PDU_TYPE 13
1328 #define M_ISO_PDU_TYPE 0x3
1329 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE)
1330 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE)
1332 struct cpl_iscsi_hdr {
1334 union opcode_tid ot;
1343 /* cpl_iscsi_hdr.pdu_len_ddp fields */
1344 #define S_ISCSI_PDU_LEN 0
1345 #define M_ISCSI_PDU_LEN 0x7FFF
1346 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
1347 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
1349 #define S_ISCSI_DDP 15
1350 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
1351 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
1353 struct cpl_iscsi_data {
1355 union opcode_tid ot;
1364 struct cpl_rx_data {
1366 union opcode_tid ot;
1371 #if defined(__LITTLE_ENDIAN_BITFIELD)
1387 struct cpl_fcoe_hdr {
1389 union opcode_tid ot;
1403 struct cpl_fcoe_data {
1405 union opcode_tid ot;
1413 struct cpl_rx_urg_notify {
1415 union opcode_tid ot;
1419 struct cpl_rx_urg_pkt {
1421 union opcode_tid ot;
1426 struct cpl_rx_data_ack {
1428 union opcode_tid ot;
1432 struct cpl_rx_data_ack_core {
1433 union opcode_tid ot;
1437 /* cpl_rx_data_ack.ack_seq fields */
1438 #define S_RX_CREDITS 0
1439 #define M_RX_CREDITS 0x3FFFFFF
1440 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1441 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1443 #define S_RX_MODULATE_TX 26
1444 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
1445 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U)
1447 #define S_RX_MODULATE_RX 27
1448 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
1449 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U)
1451 #define S_RX_FORCE_ACK 28
1452 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1453 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1455 #define S_RX_DACK_MODE 29
1456 #define M_RX_DACK_MODE 0x3
1457 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1458 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1460 #define S_RX_DACK_CHANGE 31
1461 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1462 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1464 struct cpl_rx_ddp_complete {
1466 union opcode_tid ot;
1472 struct cpl_rx_data_ddp {
1474 union opcode_tid ot;
1486 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
1488 struct cpl_rx_fcoe_ddp {
1490 union opcode_tid ot;
1499 struct cpl_rx_data_dif {
1501 union opcode_tid ot;
1513 struct cpl_rx_iscsi_dif {
1515 union opcode_tid ot;
1530 struct cpl_rx_fcoe_dif {
1532 union opcode_tid ot;
1541 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */
1542 #define S_DDP_VALID 15
1543 #define M_DDP_VALID 0x1FFFF
1544 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1545 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1547 #define S_DDP_PPOD_MISMATCH 15
1548 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1549 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1551 #define S_DDP_PDU 16
1552 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1553 #define F_DDP_PDU V_DDP_PDU(1U)
1555 #define S_DDP_LLIMIT_ERR 17
1556 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1557 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1559 #define S_DDP_PPOD_PARITY_ERR 18
1560 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1561 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1563 #define S_DDP_PADDING_ERR 19
1564 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1565 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1567 #define S_DDP_HDRCRC_ERR 20
1568 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1569 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1571 #define S_DDP_DATACRC_ERR 21
1572 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1573 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1575 #define S_DDP_INVALID_TAG 22
1576 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1577 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1579 #define S_DDP_ULIMIT_ERR 23
1580 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1581 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1583 #define S_DDP_OFFSET_ERR 24
1584 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1585 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1587 #define S_DDP_COLOR_ERR 25
1588 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1589 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1591 #define S_DDP_TID_MISMATCH 26
1592 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1593 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1595 #define S_DDP_INVALID_PPOD 27
1596 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1597 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1599 #define S_DDP_ULP_MODE 28
1600 #define M_DDP_ULP_MODE 0xF
1601 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1602 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1604 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */
1605 #define S_DDP_OFFSET 0
1606 #define M_DDP_OFFSET 0xFFFFFF
1607 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1608 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1610 #define S_DDP_DACK_MODE 24
1611 #define M_DDP_DACK_MODE 0x3
1612 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1613 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1615 #define S_DDP_BUF_IDX 26
1616 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1617 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1619 #define S_DDP_URG 27
1620 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1621 #define F_DDP_URG V_DDP_URG(1U)
1623 #define S_DDP_PSH 28
1624 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1625 #define F_DDP_PSH V_DDP_PSH(1U)
1627 #define S_DDP_BUF_COMPLETE 29
1628 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1629 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1631 #define S_DDP_BUF_TIMED_OUT 30
1632 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1633 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1635 #define S_DDP_INV 31
1636 #define V_DDP_INV(x) ((x) << S_DDP_INV)
1637 #define F_DDP_INV V_DDP_INV(1U)
1642 #if defined(__LITTLE_ENDIAN_BITFIELD)
1663 /* rx_pkt.l2info fields */
1664 #define S_RX_ETHHDR_LEN 0
1665 #define M_RX_ETHHDR_LEN 0x1F
1666 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
1667 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
1669 #define S_RX_T5_ETHHDR_LEN 0
1670 #define M_RX_T5_ETHHDR_LEN 0x3F
1671 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
1672 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
1674 #define S_RX_PKTYPE 5
1675 #define M_RX_PKTYPE 0x7
1676 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
1677 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE)
1679 #define S_RX_T5_DATYPE 6
1680 #define M_RX_T5_DATYPE 0x3
1681 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE)
1682 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE)
1684 #define S_RX_MACIDX 8
1685 #define M_RX_MACIDX 0x1FF
1686 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
1687 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
1689 #define S_RX_T5_PKTYPE 17
1690 #define M_RX_T5_PKTYPE 0x7
1691 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE)
1692 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE)
1694 #define S_RX_DATYPE 18
1695 #define M_RX_DATYPE 0x3
1696 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
1697 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE)
1699 #define S_RXF_PSH 20
1700 #define V_RXF_PSH(x) ((x) << S_RXF_PSH)
1701 #define F_RXF_PSH V_RXF_PSH(1U)
1703 #define S_RXF_SYN 21
1704 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
1705 #define F_RXF_SYN V_RXF_SYN(1U)
1707 #define S_RXF_UDP 22
1708 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
1709 #define F_RXF_UDP V_RXF_UDP(1U)
1711 #define S_RXF_TCP 23
1712 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
1713 #define F_RXF_TCP V_RXF_TCP(1U)
1716 #define V_RXF_IP(x) ((x) << S_RXF_IP)
1717 #define F_RXF_IP V_RXF_IP(1U)
1719 #define S_RXF_IP6 25
1720 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
1721 #define F_RXF_IP6 V_RXF_IP6(1U)
1723 #define S_RXF_SYN_COOKIE 26
1724 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
1725 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U)
1727 #define S_RXF_FCOE 26
1728 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
1729 #define F_RXF_FCOE V_RXF_FCOE(1U)
1731 #define S_RXF_LRO 27
1732 #define V_RXF_LRO(x) ((x) << S_RXF_LRO)
1733 #define F_RXF_LRO V_RXF_LRO(1U)
1735 #define S_RX_CHAN 28
1736 #define M_RX_CHAN 0xF
1737 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
1738 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
1740 /* rx_pkt.hdr_len fields */
1741 #define S_RX_TCPHDR_LEN 0
1742 #define M_RX_TCPHDR_LEN 0x3F
1743 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
1744 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
1746 #define S_RX_IPHDR_LEN 6
1747 #define M_RX_IPHDR_LEN 0x3FF
1748 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
1749 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
1751 /* rx_pkt.err_vec fields */
1752 #define S_RXERR_OR 0
1753 #define V_RXERR_OR(x) ((x) << S_RXERR_OR)
1754 #define F_RXERR_OR V_RXERR_OR(1U)
1756 #define S_RXERR_MAC 1
1757 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
1758 #define F_RXERR_MAC V_RXERR_MAC(1U)
1760 #define S_RXERR_IPVERS 2
1761 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
1762 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U)
1764 #define S_RXERR_FRAG 3
1765 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
1766 #define F_RXERR_FRAG V_RXERR_FRAG(1U)
1768 #define S_RXERR_ATTACK 4
1769 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
1770 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U)
1772 #define S_RXERR_ETHHDR_LEN 5
1773 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
1774 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U)
1776 #define S_RXERR_IPHDR_LEN 6
1777 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
1778 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U)
1780 #define S_RXERR_TCPHDR_LEN 7
1781 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
1782 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U)
1784 #define S_RXERR_PKT_LEN 8
1785 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
1786 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U)
1788 #define S_RXERR_TCP_OPT 9
1789 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
1790 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U)
1792 #define S_RXERR_IPCSUM 12
1793 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
1794 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U)
1796 #define S_RXERR_CSUM 13
1797 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
1798 #define F_RXERR_CSUM V_RXERR_CSUM(1U)
1800 #define S_RXERR_PING 14
1801 #define V_RXERR_PING(x) ((x) << S_RXERR_PING)
1802 #define F_RXERR_PING V_RXERR_PING(1U)
1804 struct cpl_trace_pkt {
1808 #if defined(__LITTLE_ENDIAN_BITFIELD)
1826 struct cpl_t5_trace_pkt {
1830 #if defined(__LITTLE_ENDIAN_BITFIELD)
1849 struct cpl_rte_delete_req {
1851 union opcode_tid ot;
1855 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */
1856 #define S_RTE_REQ_LUT_IX 8
1857 #define M_RTE_REQ_LUT_IX 0x7FF
1858 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1859 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1861 #define S_RTE_REQ_LUT_BASE 19
1862 #define M_RTE_REQ_LUT_BASE 0x7FF
1863 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1864 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1866 #define S_RTE_READ_REQ_SELECT 31
1867 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1868 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1870 struct cpl_rte_delete_rpl {
1872 union opcode_tid ot;
1877 struct cpl_rte_write_req {
1879 union opcode_tid ot;
1887 /* cpl_rte_write_req.write_sel fields */
1888 #define S_RTE_WR_L2TIDX 31
1889 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
1890 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U)
1892 #define S_RTE_WR_FADDR 30
1893 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
1894 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U)
1896 /* cpl_rte_write_req.lut_params fields */
1897 #define S_RTE_WR_LUT_IX 10
1898 #define M_RTE_WR_LUT_IX 0x7FF
1899 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
1900 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX)
1902 #define S_RTE_WR_LUT_BASE 21
1903 #define M_RTE_WR_LUT_BASE 0x7FF
1904 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
1905 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE)
1907 struct cpl_rte_write_rpl {
1909 union opcode_tid ot;
1914 struct cpl_rte_read_req {
1916 union opcode_tid ot;
1920 struct cpl_rte_read_rpl {
1922 union opcode_tid ot;
1926 #if defined(__LITTLE_ENDIAN_BITFIELD)
1936 struct cpl_l2t_write_req {
1938 union opcode_tid ot;
1945 /* cpl_l2t_write_req.params fields */
1946 #define S_L2T_W_INFO 2
1947 #define M_L2T_W_INFO 0x3F
1948 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
1949 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
1951 #define S_L2T_W_PORT 8
1952 #define M_L2T_W_PORT 0x3
1953 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
1954 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
1956 #define S_L2T_W_LPBK 10
1957 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
1958 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U)
1960 #define S_L2T_W_ARPMISS 11
1961 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
1962 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U)
1964 #define S_L2T_W_NOREPLY 15
1965 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
1966 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
1968 #define CPL_L2T_VLAN_NONE 0xfff
1970 struct cpl_l2t_write_rpl {
1972 union opcode_tid ot;
1977 struct cpl_l2t_read_req {
1979 union opcode_tid ot;
1983 struct cpl_l2t_read_rpl {
1985 union opcode_tid ot;
1987 #if defined(__LITTLE_ENDIAN_BITFIELD)
1999 struct cpl_smt_write_req {
2001 union opcode_tid ot;
2009 struct cpl_smt_write_rpl {
2011 union opcode_tid ot;
2016 struct cpl_smt_read_req {
2018 union opcode_tid ot;
2022 struct cpl_smt_read_rpl {
2024 union opcode_tid ot;
2034 /* cpl_smt_{read,write}_req.params fields */
2035 #define S_SMTW_OVLAN_IDX 16
2036 #define M_SMTW_OVLAN_IDX 0xF
2037 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
2038 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX)
2040 #define S_SMTW_IDX 20
2041 #define M_SMTW_IDX 0x7F
2042 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
2043 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
2045 #define S_SMTW_NORPL 31
2046 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
2047 #define F_SMTW_NORPL V_SMTW_NORPL(1U)
2049 /* cpl_smt_{read,write}_req.pfvf? fields */
2051 #define M_SMTW_VF 0xFF
2052 #define V_SMTW_VF(x) ((x) << S_SMTW_VF)
2053 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF)
2056 #define M_SMTW_PF 0x7
2057 #define V_SMTW_PF(x) ((x) << S_SMTW_PF)
2058 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF)
2060 #define S_SMTW_VF_VLD 11
2061 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
2062 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U)
2064 struct cpl_tag_write_req {
2066 union opcode_tid ot;
2071 struct cpl_tag_write_rpl {
2073 union opcode_tid ot;
2079 struct cpl_tag_read_req {
2081 union opcode_tid ot;
2085 struct cpl_tag_read_rpl {
2087 union opcode_tid ot;
2089 #if defined(__LITTLE_ENDIAN_BITFIELD)
2105 /* cpl_tag{read,write}_req.params fields */
2106 #define S_TAGW_IDX 0
2107 #define M_TAGW_IDX 0x7F
2108 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX)
2109 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX)
2111 #define S_TAGW_LEN 20
2112 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN)
2113 #define F_TAGW_LEN V_TAGW_LEN(1U)
2115 #define S_TAGW_INS_ENABLE 23
2116 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE)
2117 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U)
2119 #define S_TAGW_NORPL 31
2120 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL)
2121 #define F_TAGW_NORPL V_TAGW_NORPL(1U)
2123 struct cpl_barrier {
2131 /* cpl_barrier.chan_map fields */
2132 #define S_CHAN_MAP 4
2133 #define M_CHAN_MAP 0xF
2134 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
2135 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP)
2139 union opcode_tid ot;
2143 struct cpl_hit_notify {
2145 union opcode_tid ot;
2151 struct cpl_pkt_notify {
2153 union opcode_tid ot;
2160 /* cpl_{hit,pkt}_notify.info fields */
2161 #define S_NTFY_MAC_IDX 0
2162 #define M_NTFY_MAC_IDX 0x1FF
2163 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
2164 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX)
2166 #define S_NTFY_INTF 10
2167 #define M_NTFY_INTF 0xF
2168 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
2169 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF)
2171 #define S_NTFY_TCPHDR_LEN 14
2172 #define M_NTFY_TCPHDR_LEN 0xF
2173 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
2174 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN)
2176 #define S_NTFY_IPHDR_LEN 18
2177 #define M_NTFY_IPHDR_LEN 0x1FF
2178 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
2179 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN)
2181 #define S_NTFY_ETHHDR_LEN 27
2182 #define M_NTFY_ETHHDR_LEN 0x1F
2183 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
2184 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN)
2186 #define S_NTFY_T5_IPHDR_LEN 18
2187 #define M_NTFY_T5_IPHDR_LEN 0xFF
2188 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN)
2189 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN)
2191 #define S_NTFY_T5_ETHHDR_LEN 26
2192 #define M_NTFY_T5_ETHHDR_LEN 0x3F
2193 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN)
2194 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN)
2196 struct cpl_rdma_terminate {
2198 union opcode_tid ot;
2203 struct cpl_set_le_req {
2205 union opcode_tid ot;
2214 /* cpl_set_le_req.reply_ctrl additional fields */
2215 #define S_LE_REQ_IP6 13
2216 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
2217 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U)
2219 /* cpl_set_le_req.params fields */
2221 #define M_LE_CHAN 0x3
2222 #define V_LE_CHAN(x) ((x) << S_LE_CHAN)
2223 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN)
2225 #define S_LE_OFFSET 5
2226 #define M_LE_OFFSET 0x7
2227 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
2228 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET)
2231 #define V_LE_MORE(x) ((x) << S_LE_MORE)
2232 #define F_LE_MORE V_LE_MORE(1U)
2234 #define S_LE_REQSIZE 9
2235 #define M_LE_REQSIZE 0x7
2236 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
2237 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE)
2239 #define S_LE_REQCMD 12
2240 #define M_LE_REQCMD 0xF
2241 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
2242 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
2244 struct cpl_set_le_rpl {
2246 union opcode_tid ot;
2252 /* cpl_set_le_rpl.info fields */
2253 #define S_LE_RSPCMD 0
2254 #define M_LE_RSPCMD 0xF
2255 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
2256 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD)
2258 #define S_LE_RSPSIZE 4
2259 #define M_LE_RSPSIZE 0x7
2260 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
2261 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE)
2263 #define S_LE_RSPTYPE 7
2264 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
2265 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U)
2267 struct cpl_sge_egr_update {
2274 /* cpl_sge_egr_update.ot fields */
2276 #define M_EGR_QID 0x1FFFF
2277 #define V_EGR_QID(x) ((x) << S_EGR_QID)
2278 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID)
2280 /* cpl_fw*.type values */
2282 FW_TYPE_CMD_RPL = 0,
2285 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
2289 struct cpl_fw2_pld {
2296 struct cpl_fw4_pld {
2307 struct cpl_fw6_pld {
2315 struct cpl_fw2_msg {
2317 union opcode_info oi;
2320 struct cpl_fw4_msg {
2329 struct cpl_fw4_ack {
2331 union opcode_tid ot;
2341 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
2342 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
2343 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
2346 struct cpl_fw6_msg {
2355 /* cpl_fw6_msg.type values */
2357 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL,
2358 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL,
2359 FW6_TYPE_CQE = FW_TYPE_CQE,
2360 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL,
2361 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
2366 struct cpl_fw6_msg_ofld_connection_wr_rpl {
2368 __be32 tid; /* or atid in case of active failure */
2374 /* ULP_TX opcodes */
2376 ULP_TX_MEM_READ = 2,
2377 ULP_TX_MEM_WRITE = 3,
2382 ULP_TX_SC_NOOP = 0x80,
2383 ULP_TX_SC_IMM = 0x81,
2384 ULP_TX_SC_DSGL = 0x82,
2385 ULP_TX_SC_ISGL = 0x83
2388 #define S_ULPTX_CMD 24
2389 #define M_ULPTX_CMD 0xFF
2390 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
2392 #define S_ULPTX_LEN16 0
2393 #define M_ULPTX_LEN16 0xFF
2394 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
2396 #define S_ULP_TX_SC_MORE 23
2397 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
2398 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
2400 struct ulptx_sge_pair {
2409 #if !(defined C99_NOT_SUPPORTED)
2410 struct ulptx_sge_pair sge[0];
2423 #if !(defined C99_NOT_SUPPORTED)
2424 struct ulptx_isge sge[0];
2428 struct ulptx_idata {
2433 #define S_ULPTX_NSGE 0
2434 #define M_ULPTX_NSGE 0xFFFF
2435 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
2440 __be32 len16; /* command length */
2441 __be32 dlen; /* data length in 32-byte units */
2445 /* additional ulp_mem_io.cmd fields */
2446 #define S_ULP_MEMIO_ORDER 23
2447 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2448 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2450 #define S_T5_ULP_MEMIO_IMM 23
2451 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
2452 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
2454 #define S_T5_ULP_MEMIO_ORDER 22
2455 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
2456 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
2458 /* ulp_mem_io.lock_addr fields */
2459 #define S_ULP_MEMIO_ADDR 0
2460 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
2461 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2463 #define S_ULP_MEMIO_LOCK 31
2464 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2465 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2467 /* ulp_mem_io.dlen fields */
2468 #define S_ULP_MEMIO_DATA_LEN 0
2469 #define M_ULP_MEMIO_DATA_LEN 0x1F
2470 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2472 /* ULP_TXPKT field values */
2474 ULP_TXPKT_DEST_TP = 0,
2477 ULP_TXPKT_DEST_DEVNULL,
2485 /* ulp_txpkt.cmd_dest fields */
2486 #define S_ULP_TXPKT_DEST 16
2487 #define M_ULP_TXPKT_DEST 0x3
2488 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2490 #define S_ULP_TXPKT_FID 4
2491 #define M_ULP_TXPKT_FID 0x7ff
2492 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2494 #define S_ULP_TXPKT_RO 3
2495 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
2496 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
2498 #endif /* T4_MSG_H */