1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
32 * The Bridge device's PCI config space has information about the
33 * fb aperture size and the amount of pre-reserved memory.
35 #define INTEL_GMCH_CTRL 0x52
36 #define INTEL_GMCH_ENABLED 0x4
37 #define INTEL_GMCH_MEM_MASK 0x1
38 #define INTEL_GMCH_MEM_64M 0x1
39 #define INTEL_GMCH_MEM_128M 0
41 #define INTEL_GMCH_GMS_MASK (0xf << 4)
42 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
46 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
47 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
49 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
50 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
51 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
52 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
53 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
54 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
55 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
56 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
58 /* PCI config space */
60 #define HPLLCC 0xc0 /* 855 only */
61 #define GC_CLOCK_CONTROL_MASK (3 << 0)
62 #define GC_CLOCK_133_200 (0 << 0)
63 #define GC_CLOCK_100_200 (1 << 0)
64 #define GC_CLOCK_100_133 (2 << 0)
65 #define GC_CLOCK_166_250 (3 << 0)
66 #define GCFGC 0xf0 /* 915+ only */
67 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
68 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
69 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
70 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
75 #define VGA_ST01_MDA 0x3ba
76 #define VGA_ST01_CGA 0x3da
78 #define VGA_MSR_WRITE 0x3c2
79 #define VGA_MSR_READ 0x3cc
80 #define VGA_MSR_MEM_EN (1<<1)
81 #define VGA_MSR_CGA_MODE (1<<0)
83 #define VGA_SR_INDEX 0x3c4
84 #define VGA_SR_DATA 0x3c5
86 #define VGA_AR_INDEX 0x3c0
87 #define VGA_AR_VID_EN (1<<5)
88 #define VGA_AR_DATA_WRITE 0x3c0
89 #define VGA_AR_DATA_READ 0x3c1
91 #define VGA_GR_INDEX 0x3ce
92 #define VGA_GR_DATA 0x3cf
94 #define VGA_GR_MEM_READ_MODE_SHIFT 3
95 #define VGA_GR_MEM_READ_MODE_PLANE 1
97 #define VGA_GR_MEM_MODE_MASK 0xc
98 #define VGA_GR_MEM_MODE_SHIFT 2
99 #define VGA_GR_MEM_A0000_AFFFF 0
100 #define VGA_GR_MEM_A0000_BFFFF 1
101 #define VGA_GR_MEM_B0000_B7FFF 2
102 #define VGA_GR_MEM_B0000_BFFFF 3
104 #define VGA_DACMASK 0x3c6
105 #define VGA_DACRX 0x3c7
106 #define VGA_DACWX 0x3c8
107 #define VGA_DACDATA 0x3c9
109 #define VGA_CR_INDEX_MDA 0x3b4
110 #define VGA_CR_DATA_MDA 0x3b5
111 #define VGA_CR_INDEX_CGA 0x3d4
112 #define VGA_CR_DATA_CGA 0x3d5
115 * Memory interface instructions used by the kernel
117 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
119 #define MI_NOOP MI_INSTR(0, 0)
120 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
121 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
122 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
123 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
124 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
125 #define MI_FLUSH MI_INSTR(0x04, 0)
126 #define MI_READ_FLUSH (1 << 0)
127 #define MI_EXE_FLUSH (1 << 1)
128 #define MI_NO_WRITE_FLUSH (1 << 2)
129 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
130 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
131 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
132 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
133 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
134 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
135 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
136 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
137 #define MI_STORE_DWORD_INDEX_SHIFT 2
138 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
139 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
140 #define MI_BATCH_NON_SECURE (1)
141 #define MI_BATCH_NON_SECURE_I965 (1<<8)
142 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
145 * 3D instructions used by the kernel
147 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
149 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
150 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
151 #define SC_UPDATE_SCISSOR (0x1<<1)
152 #define SC_ENABLE_MASK (0x1<<0)
153 #define SC_ENABLE (0x1<<0)
154 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
155 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
156 #define SCI_YMIN_MASK (0xffff<<16)
157 #define SCI_XMIN_MASK (0xffff<<0)
158 #define SCI_YMAX_MASK (0xffff<<16)
159 #define SCI_XMAX_MASK (0xffff<<0)
160 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
161 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
162 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
163 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
164 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
165 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
166 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
167 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
168 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
169 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
170 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
171 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
172 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
173 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
174 #define BLT_DEPTH_8 (0<<24)
175 #define BLT_DEPTH_16_565 (1<<24)
176 #define BLT_DEPTH_16_1555 (2<<24)
177 #define BLT_DEPTH_32 (3<<24)
178 #define BLT_ROP_GXCOPY (0xcc<<16)
179 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
180 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
181 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
182 #define ASYNC_FLIP (1<<22)
183 #define DISPLAY_PLANE_A (0<<20)
184 #define DISPLAY_PLANE_B (1<<20)
189 #define FENCE_REG_830_0 0x2000
190 #define FENCE_REG_945_8 0x3000
191 #define I830_FENCE_START_MASK 0x07f80000
192 #define I830_FENCE_TILING_Y_SHIFT 12
193 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
194 #define I830_FENCE_PITCH_SHIFT 4
195 #define I830_FENCE_REG_VALID (1<<0)
197 #define I915_FENCE_START_MASK 0x0ff00000
198 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
200 #define FENCE_REG_965_0 0x03000
201 #define I965_FENCE_PITCH_SHIFT 2
202 #define I965_FENCE_TILING_Y_SHIFT 1
203 #define I965_FENCE_REG_VALID (1<<0)
206 * Instruction and interrupt control regs
208 #define PRB0_TAIL 0x02030
209 #define PRB0_HEAD 0x02034
210 #define PRB0_START 0x02038
211 #define PRB0_CTL 0x0203c
212 #define TAIL_ADDR 0x001FFFF8
213 #define HEAD_WRAP_COUNT 0xFFE00000
214 #define HEAD_WRAP_ONE 0x00200000
215 #define HEAD_ADDR 0x001FFFFC
216 #define RING_NR_PAGES 0x001FF000
217 #define RING_REPORT_MASK 0x00000006
218 #define RING_REPORT_64K 0x00000002
219 #define RING_REPORT_128K 0x00000004
220 #define RING_NO_REPORT 0x00000000
221 #define RING_VALID_MASK 0x00000001
222 #define RING_VALID 0x00000001
223 #define RING_INVALID 0x00000000
224 #define PRB1_TAIL 0x02040 /* 915+ only */
225 #define PRB1_HEAD 0x02044 /* 915+ only */
226 #define PRB1_START 0x02048 /* 915+ only */
227 #define PRB1_CTL 0x0204c /* 915+ only */
228 #define ACTHD_I965 0x02074
229 #define HWS_PGA 0x02080
230 #define HWS_ADDRESS_MASK 0xfffff000
231 #define HWS_START_ADDRESS_SHIFT 4
232 #define IPEIR 0x02088
233 #define NOPID 0x02094
234 #define HWSTAM 0x02098
235 #define SCPD0 0x0209c /* 915+ only */
240 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
241 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
242 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
243 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
244 #define I915_HWB_OOM_INTERRUPT (1<<13)
245 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
246 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
247 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
248 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
249 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
250 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
251 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
252 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
253 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
254 #define I915_DEBUG_INTERRUPT (1<<2)
255 #define I915_USER_INTERRUPT (1<<1)
256 #define I915_ASLE_INTERRUPT (1<<0)
260 #define INSTPM 0x020c0
261 #define ACTHD 0x020c8
262 #define FW_BLC 0x020d8
263 #define FW_BLC_SELF 0x020e0 /* 915+ only */
264 #define MI_ARB_STATE 0x020e4 /* 915+ only */
265 #define CACHE_MODE_0 0x02120 /* 915+ only */
266 #define CM0_MASK_SHIFT 16
267 #define CM0_IZ_OPT_DISABLE (1<<6)
268 #define CM0_ZR_OPT_DISABLE (1<<5)
269 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
270 #define CM0_COLOR_EVICT_DISABLE (1<<3)
271 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
272 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
273 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
277 * Framebuffer compression (915+ only)
280 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
281 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
282 #define FBC_CONTROL 0x03208
283 #define FBC_CTL_EN (1<<31)
284 #define FBC_CTL_PERIODIC (1<<30)
285 #define FBC_CTL_INTERVAL_SHIFT (16)
286 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
287 #define FBC_CTL_STRIDE_SHIFT (5)
288 #define FBC_CTL_FENCENO (1<<0)
289 #define FBC_COMMAND 0x0320c
290 #define FBC_CMD_COMPRESS (1<<0)
291 #define FBC_STATUS 0x03210
292 #define FBC_STAT_COMPRESSING (1<<31)
293 #define FBC_STAT_COMPRESSED (1<<30)
294 #define FBC_STAT_MODIFIED (1<<29)
295 #define FBC_STAT_CURRENT_LINE (1<<0)
296 #define FBC_CONTROL2 0x03214
297 #define FBC_CTL_FENCE_DBL (0<<4)
298 #define FBC_CTL_IDLE_IMM (0<<2)
299 #define FBC_CTL_IDLE_FULL (1<<2)
300 #define FBC_CTL_IDLE_LINE (2<<2)
301 #define FBC_CTL_IDLE_DEBUG (3<<2)
302 #define FBC_CTL_CPU_FENCE (1<<1)
303 #define FBC_CTL_PLANEA (0<<0)
304 #define FBC_CTL_PLANEB (1<<0)
305 #define FBC_FENCE_OFF 0x0321b
307 #define FBC_LL_SIZE (1536)
320 # define GPIO_CLOCK_DIR_MASK (1 << 0)
321 # define GPIO_CLOCK_DIR_IN (0 << 1)
322 # define GPIO_CLOCK_DIR_OUT (1 << 1)
323 # define GPIO_CLOCK_VAL_MASK (1 << 2)
324 # define GPIO_CLOCK_VAL_OUT (1 << 3)
325 # define GPIO_CLOCK_VAL_IN (1 << 4)
326 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
327 # define GPIO_DATA_DIR_MASK (1 << 8)
328 # define GPIO_DATA_DIR_IN (0 << 9)
329 # define GPIO_DATA_DIR_OUT (1 << 9)
330 # define GPIO_DATA_VAL_MASK (1 << 10)
331 # define GPIO_DATA_VAL_OUT (1 << 11)
332 # define GPIO_DATA_VAL_IN (1 << 12)
333 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
336 * Clock control & power management
341 #define VGA_PD 0x6010
342 #define VGA0_PD_P2_DIV_4 (1 << 7)
343 #define VGA0_PD_P1_DIV_2 (1 << 5)
344 #define VGA0_PD_P1_SHIFT 0
345 #define VGA0_PD_P1_MASK (0x1f << 0)
346 #define VGA1_PD_P2_DIV_4 (1 << 15)
347 #define VGA1_PD_P1_DIV_2 (1 << 13)
348 #define VGA1_PD_P1_SHIFT 8
349 #define VGA1_PD_P1_MASK (0x1f << 8)
350 #define DPLL_A 0x06014
351 #define DPLL_B 0x06018
352 #define DPLL_VCO_ENABLE (1 << 31)
353 #define DPLL_DVO_HIGH_SPEED (1 << 30)
354 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
355 #define DPLL_VGA_MODE_DIS (1 << 28)
356 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
357 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
358 #define DPLL_MODE_MASK (3 << 26)
359 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
360 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
361 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
362 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
363 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
364 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
365 #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
367 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
368 #define I915_CRC_ERROR_ENABLE (1UL<<29)
369 #define I915_CRC_DONE_ENABLE (1UL<<28)
370 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
371 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
372 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
373 #define I915_DPST_EVENT_ENABLE (1UL<<23)
374 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
375 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
376 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
377 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
378 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
379 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
380 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
381 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
382 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
383 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
384 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
385 #define I915_DPST_EVENT_STATUS (1UL<<7)
386 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
387 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
388 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
389 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
390 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
391 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
393 #define SRX_INDEX 0x3c4
394 #define SRX_DATA 0x3c5
396 #define SR01_SCREEN_OFF (1<<5)
399 #define PPCR_ON (1<<0)
402 #define DVOB_ON (1<<31)
404 #define DVOC_ON (1<<31)
406 #define LVDS_ON (1<<31)
409 #define ADPA_DPMS_MASK (~(3<<10))
410 #define ADPA_DPMS_ON (0<<10)
411 #define ADPA_DPMS_SUSPEND (1<<10)
412 #define ADPA_DPMS_STANDBY (2<<10)
413 #define ADPA_DPMS_OFF (3<<10)
415 #define RING_TAIL 0x00
416 #define TAIL_ADDR 0x001FFFF8
417 #define RING_HEAD 0x04
418 #define HEAD_WRAP_COUNT 0xFFE00000
419 #define HEAD_WRAP_ONE 0x00200000
420 #define HEAD_ADDR 0x001FFFFC
421 #define RING_START 0x08
422 #define START_ADDR 0xFFFFF000
423 #define RING_LEN 0x0C
424 #define RING_NR_PAGES 0x001FF000
425 #define RING_REPORT_MASK 0x00000006
426 #define RING_REPORT_64K 0x00000002
427 #define RING_REPORT_128K 0x00000004
428 #define RING_NO_REPORT 0x00000000
429 #define RING_VALID_MASK 0x00000001
430 #define RING_VALID 0x00000001
431 #define RING_INVALID 0x00000000
433 /* Scratch pad debug 0 reg:
435 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
437 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
438 * this field (only one bit may be set).
440 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
441 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
442 #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
443 /* i830, required in DVO non-gang */
444 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
445 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
446 #define PLL_REF_INPUT_DREFCLK (0 << 13)
447 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
448 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
449 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
450 #define PLL_REF_INPUT_MASK (3 << 13)
451 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
453 * Parallel to Serial Load Pulse phase selection.
454 * Selects the phase for the 10X DPLL clock for the PCIe
455 * digital display port. The range is 4 to 13; 10 or more
456 * is just a flip delay. The default is 6
458 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
459 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
461 * SDVO multiplier for 945G/GM. Not used on 965.
463 #define SDVO_MULTIPLIER_MASK 0x000000ff
464 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
465 #define SDVO_MULTIPLIER_SHIFT_VGA 0
466 #define DPLL_A_MD 0x0601c /* 965+ only */
468 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
470 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
472 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
473 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
474 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
475 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
476 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
478 * SDVO/UDI pixel multiplier.
480 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
481 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
482 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
483 * dummy bytes in the datastream at an increased clock rate, with both sides of
484 * the link knowing how many bytes are fill.
486 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
487 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
488 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
489 * through an SDVO command.
491 * This register field has values of multiplication factor minus 1, with
492 * a maximum multiplier of 5 for SDVO.
494 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
495 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
497 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
498 * This best be set to the default value (3) or the CRT won't work. No,
499 * I don't entirely understand what this does...
501 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
502 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
503 #define DPLL_B_MD 0x06020 /* 965+ only */
508 #define FP_N_DIV_MASK 0x003f0000
509 #define FP_N_IGD_DIV_MASK 0x00ff0000
510 #define FP_N_DIV_SHIFT 16
511 #define FP_M1_DIV_MASK 0x00003f00
512 #define FP_M1_DIV_SHIFT 8
513 #define FP_M2_DIV_MASK 0x0000003f
514 #define FP_M2_IGD_DIV_MASK 0x000000ff
515 #define FP_M2_DIV_SHIFT 0
516 #define DPLL_TEST 0x606c
517 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
518 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
519 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
520 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
521 #define DPLLB_TEST_N_BYPASS (1 << 19)
522 #define DPLLB_TEST_M_BYPASS (1 << 18)
523 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
524 #define DPLLA_TEST_N_BYPASS (1 << 3)
525 #define DPLLA_TEST_M_BYPASS (1 << 2)
526 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
527 #define D_STATE 0x6104
528 #define CG_2D_DIS 0x6200
529 #define CG_3D_DIS 0x6204
535 #define PALETTE_A 0x0a000
536 #define PALETTE_B 0x0a800
543 * This mirrors the MCHBAR MMIO space whose location is determined by
544 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
545 * every way. It is not accessible from the CP register read instructions.
548 #define MCHBAR_MIRROR_BASE 0x10000
550 /** 915-945 and GM965 MCH register controlling DRAM channel access */
552 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
553 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
554 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
555 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
556 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
557 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
559 /** 965 MCH register controlling DRAM channel configuration */
560 #define C0DRB3 0x10206
561 #define C1DRB3 0x10606
563 /** GM965 GM45 render standby register */
564 #define MCHBAR_RENDER_STANDBY 0x111B8
566 #define PEG_BAND_GAP_DATA 0x14d68
572 #define OVADD 0x30000
573 #define DOVSTA 0x30008
574 #define OC_BUF (0x3<<20)
575 #define OGAMC5 0x30010
576 #define OGAMC4 0x30014
577 #define OGAMC3 0x30018
578 #define OGAMC2 0x3001c
579 #define OGAMC1 0x30020
580 #define OGAMC0 0x30024
583 * Display engine regs
586 /* Pipe A timing regs */
587 #define HTOTAL_A 0x60000
588 #define HBLANK_A 0x60004
589 #define HSYNC_A 0x60008
590 #define VTOTAL_A 0x6000c
591 #define VBLANK_A 0x60010
592 #define VSYNC_A 0x60014
593 #define PIPEASRC 0x6001c
594 #define BCLRPAT_A 0x60020
596 /* Pipe B timing regs */
597 #define HTOTAL_B 0x61000
598 #define HBLANK_B 0x61004
599 #define HSYNC_B 0x61008
600 #define VTOTAL_B 0x6100c
601 #define VBLANK_B 0x61010
602 #define VSYNC_B 0x61014
603 #define PIPEBSRC 0x6101c
604 #define BCLRPAT_B 0x61020
606 /* VGA port control */
608 #define ADPA_DAC_ENABLE (1<<31)
609 #define ADPA_DAC_DISABLE 0
610 #define ADPA_PIPE_SELECT_MASK (1<<30)
611 #define ADPA_PIPE_A_SELECT 0
612 #define ADPA_PIPE_B_SELECT (1<<30)
613 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
614 #define ADPA_SETS_HVPOLARITY 0
615 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
616 #define ADPA_VSYNC_CNTL_ENABLE 0
617 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
618 #define ADPA_HSYNC_CNTL_ENABLE 0
619 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
620 #define ADPA_VSYNC_ACTIVE_LOW 0
621 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
622 #define ADPA_HSYNC_ACTIVE_LOW 0
623 #define ADPA_DPMS_MASK (~(3<<10))
624 #define ADPA_DPMS_ON (0<<10)
625 #define ADPA_DPMS_SUSPEND (1<<10)
626 #define ADPA_DPMS_STANDBY (2<<10)
627 #define ADPA_DPMS_OFF (3<<10)
629 /* Hotplug control (945+ only) */
630 #define PORT_HOTPLUG_EN 0x61110
631 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
632 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
633 #define HDMID_HOTPLUG_INT_EN (1 << 27)
634 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
635 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
636 #define TV_HOTPLUG_INT_EN (1 << 18)
637 #define CRT_HOTPLUG_INT_EN (1 << 9)
638 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
640 #define PORT_HOTPLUG_STAT 0x61114
641 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
642 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
643 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
644 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
645 #define TV_HOTPLUG_INT_STATUS (1 << 10)
646 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
647 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
648 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
649 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
650 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
651 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
653 /* SDVO port control */
654 #define SDVOB 0x61140
655 #define SDVOC 0x61160
656 #define SDVO_ENABLE (1 << 31)
657 #define SDVO_PIPE_B_SELECT (1 << 30)
658 #define SDVO_STALL_SELECT (1 << 29)
659 #define SDVO_INTERRUPT_ENABLE (1 << 26)
661 * 915G/GM SDVO pixel multiplier.
663 * Programmed value is multiplier - 1, up to 5x.
665 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
667 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
668 #define SDVO_PORT_MULTIPLY_SHIFT 23
669 #define SDVO_PHASE_SELECT_MASK (15 << 19)
670 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
671 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
672 #define SDVOC_GANG_MODE (1 << 16)
673 #define SDVO_ENCODING_SDVO (0x0 << 10)
674 #define SDVO_ENCODING_HDMI (0x2 << 10)
675 /** Requird for HDMI operation */
676 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
677 #define SDVO_BORDER_ENABLE (1 << 7)
678 #define SDVO_AUDIO_ENABLE (1 << 6)
679 /** New with 965, default is to be set */
680 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
681 /** New with 965, default is to be set */
682 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
683 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
684 #define SDVO_DETECTED (1 << 2)
685 /* Bits to be preserved when writing */
686 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
687 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
689 /* DVO port control */
693 #define DVO_ENABLE (1 << 31)
694 #define DVO_PIPE_B_SELECT (1 << 30)
695 #define DVO_PIPE_STALL_UNUSED (0 << 28)
696 #define DVO_PIPE_STALL (1 << 28)
697 #define DVO_PIPE_STALL_TV (2 << 28)
698 #define DVO_PIPE_STALL_MASK (3 << 28)
699 #define DVO_USE_VGA_SYNC (1 << 15)
700 #define DVO_DATA_ORDER_I740 (0 << 14)
701 #define DVO_DATA_ORDER_FP (1 << 14)
702 #define DVO_VSYNC_DISABLE (1 << 11)
703 #define DVO_HSYNC_DISABLE (1 << 10)
704 #define DVO_VSYNC_TRISTATE (1 << 9)
705 #define DVO_HSYNC_TRISTATE (1 << 8)
706 #define DVO_BORDER_ENABLE (1 << 7)
707 #define DVO_DATA_ORDER_GBRG (1 << 6)
708 #define DVO_DATA_ORDER_RGGB (0 << 6)
709 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
710 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
711 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
712 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
713 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
714 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
715 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
716 #define DVO_PRESERVE_MASK (0x7<<24)
717 #define DVOA_SRCDIM 0x61124
718 #define DVOB_SRCDIM 0x61144
719 #define DVOC_SRCDIM 0x61164
720 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
721 #define DVO_SRCDIM_VERTICAL_SHIFT 0
723 /* LVDS port control */
726 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
727 * the DPLL semantics change when the LVDS is assigned to that pipe.
729 #define LVDS_PORT_EN (1 << 31)
730 /* Selects pipe B for LVDS data. Must be set on pre-965. */
731 #define LVDS_PIPEB_SELECT (1 << 30)
733 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
736 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
737 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
738 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
740 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
741 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
744 #define LVDS_A3_POWER_MASK (3 << 6)
745 #define LVDS_A3_POWER_DOWN (0 << 6)
746 #define LVDS_A3_POWER_UP (3 << 6)
748 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
751 #define LVDS_CLKB_POWER_MASK (3 << 4)
752 #define LVDS_CLKB_POWER_DOWN (0 << 4)
753 #define LVDS_CLKB_POWER_UP (3 << 4)
755 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
756 * setting for whether we are in dual-channel mode. The B3 pair will
757 * additionally only be powered up when LVDS_A3_POWER_UP is set.
759 #define LVDS_B0B3_POWER_MASK (3 << 2)
760 #define LVDS_B0B3_POWER_DOWN (0 << 2)
761 #define LVDS_B0B3_POWER_UP (3 << 2)
763 /* Panel power sequencing */
764 #define PP_STATUS 0x61200
765 #define PP_ON (1 << 31)
767 * Indicates that all dependencies of the panel are on:
771 * - LVDS/DVOB/DVOC on
773 #define PP_READY (1 << 30)
774 #define PP_SEQUENCE_NONE (0 << 28)
775 #define PP_SEQUENCE_ON (1 << 28)
776 #define PP_SEQUENCE_OFF (2 << 28)
777 #define PP_SEQUENCE_MASK 0x30000000
778 #define PP_CONTROL 0x61204
779 #define POWER_TARGET_ON (1 << 0)
780 #define PP_ON_DELAYS 0x61208
781 #define PP_OFF_DELAYS 0x6120c
782 #define PP_DIVISOR 0x61210
785 #define PFIT_CONTROL 0x61230
786 #define PFIT_ENABLE (1 << 31)
787 #define PFIT_PIPE_MASK (3 << 29)
788 #define PFIT_PIPE_SHIFT 29
789 #define VERT_INTERP_DISABLE (0 << 10)
790 #define VERT_INTERP_BILINEAR (1 << 10)
791 #define VERT_INTERP_MASK (3 << 10)
792 #define VERT_AUTO_SCALE (1 << 9)
793 #define HORIZ_INTERP_DISABLE (0 << 6)
794 #define HORIZ_INTERP_BILINEAR (1 << 6)
795 #define HORIZ_INTERP_MASK (3 << 6)
796 #define HORIZ_AUTO_SCALE (1 << 5)
797 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
798 #define PFIT_PGM_RATIOS 0x61234
799 #define PFIT_VERT_SCALE_MASK 0xfff00000
800 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
801 #define PFIT_AUTO_RATIOS 0x61238
803 /* Backlight control */
804 #define BLC_PWM_CTL 0x61254
805 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
806 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
807 #define BLM_COMBINATION_MODE (1 << 30)
809 * This is the most significant 15 bits of the number of backlight cycles in a
810 * complete cycle of the modulated backlight control.
812 * The actual value is this field multiplied by two.
814 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
815 #define BLM_LEGACY_MODE (1 << 16)
817 * This is the number of cycles out of the backlight modulation cycle for which
818 * the backlight is on.
820 * This field must be no greater than the number of cycles in the complete
821 * backlight modulation cycle.
823 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
824 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
826 /* TV port control */
827 #define TV_CTL 0x68000
828 /** Enables the TV encoder */
829 # define TV_ENC_ENABLE (1 << 31)
830 /** Sources the TV encoder input from pipe B instead of A. */
831 # define TV_ENC_PIPEB_SELECT (1 << 30)
832 /** Outputs composite video (DAC A only) */
833 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
834 /** Outputs SVideo video (DAC B/C) */
835 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
836 /** Outputs Component video (DAC A/B/C) */
837 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
838 /** Outputs Composite and SVideo (DAC A/B/C) */
839 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
840 # define TV_TRILEVEL_SYNC (1 << 21)
841 /** Enables slow sync generation (945GM only) */
842 # define TV_SLOW_SYNC (1 << 20)
843 /** Selects 4x oversampling for 480i and 576p */
844 # define TV_OVERSAMPLE_4X (0 << 18)
845 /** Selects 2x oversampling for 720p and 1080i */
846 # define TV_OVERSAMPLE_2X (1 << 18)
847 /** Selects no oversampling for 1080p */
848 # define TV_OVERSAMPLE_NONE (2 << 18)
849 /** Selects 8x oversampling */
850 # define TV_OVERSAMPLE_8X (3 << 18)
851 /** Selects progressive mode rather than interlaced */
852 # define TV_PROGRESSIVE (1 << 17)
853 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
854 # define TV_PAL_BURST (1 << 16)
855 /** Field for setting delay of Y compared to C */
856 # define TV_YC_SKEW_MASK (7 << 12)
857 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
858 # define TV_ENC_SDP_FIX (1 << 11)
860 * Enables a fix for the 915GM only.
862 * Not sure what it does.
864 # define TV_ENC_C0_FIX (1 << 10)
865 /** Bits that must be preserved by software */
866 # define TV_CTL_SAVE ((3 << 8) | (3 << 6))
867 # define TV_FUSE_STATE_MASK (3 << 4)
868 /** Read-only state that reports all features enabled */
869 # define TV_FUSE_STATE_ENABLED (0 << 4)
870 /** Read-only state that reports that Macrovision is disabled in hardware*/
871 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
872 /** Read-only state that reports that TV-out is disabled in hardware. */
873 # define TV_FUSE_STATE_DISABLED (2 << 4)
874 /** Normal operation */
875 # define TV_TEST_MODE_NORMAL (0 << 0)
876 /** Encoder test pattern 1 - combo pattern */
877 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
878 /** Encoder test pattern 2 - full screen vertical 75% color bars */
879 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
880 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
881 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
882 /** Encoder test pattern 4 - random noise */
883 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
884 /** Encoder test pattern 5 - linear color ramps */
885 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
887 * This test mode forces the DACs to 50% of full output.
889 * This is used for load detection in combination with TVDAC_SENSE_MASK
891 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
892 # define TV_TEST_MODE_MASK (7 << 0)
894 #define TV_DAC 0x68004
896 * Reports that DAC state change logic has reported change (RO).
898 * This gets cleared when TV_DAC_STATE_EN is cleared
900 # define TVDAC_STATE_CHG (1 << 31)
901 # define TVDAC_SENSE_MASK (7 << 28)
902 /** Reports that DAC A voltage is above the detect threshold */
903 # define TVDAC_A_SENSE (1 << 30)
904 /** Reports that DAC B voltage is above the detect threshold */
905 # define TVDAC_B_SENSE (1 << 29)
906 /** Reports that DAC C voltage is above the detect threshold */
907 # define TVDAC_C_SENSE (1 << 28)
909 * Enables DAC state detection logic, for load-based TV detection.
911 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
912 * to off, for load detection to work.
914 # define TVDAC_STATE_CHG_EN (1 << 27)
915 /** Sets the DAC A sense value to high */
916 # define TVDAC_A_SENSE_CTL (1 << 26)
917 /** Sets the DAC B sense value to high */
918 # define TVDAC_B_SENSE_CTL (1 << 25)
919 /** Sets the DAC C sense value to high */
920 # define TVDAC_C_SENSE_CTL (1 << 24)
921 /** Overrides the ENC_ENABLE and DAC voltage levels */
922 # define DAC_CTL_OVERRIDE (1 << 7)
923 /** Sets the slew rate. Must be preserved in software */
924 # define ENC_TVDAC_SLEW_FAST (1 << 6)
925 # define DAC_A_1_3_V (0 << 4)
926 # define DAC_A_1_1_V (1 << 4)
927 # define DAC_A_0_7_V (2 << 4)
928 # define DAC_A_OFF (3 << 4)
929 # define DAC_B_1_3_V (0 << 2)
930 # define DAC_B_1_1_V (1 << 2)
931 # define DAC_B_0_7_V (2 << 2)
932 # define DAC_B_OFF (3 << 2)
933 # define DAC_C_1_3_V (0 << 0)
934 # define DAC_C_1_1_V (1 << 0)
935 # define DAC_C_0_7_V (2 << 0)
936 # define DAC_C_OFF (3 << 0)
939 * CSC coefficients are stored in a floating point format with 9 bits of
940 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
941 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
942 * -1 (0x3) being the only legal negative value.
944 #define TV_CSC_Y 0x68010
945 # define TV_RY_MASK 0x07ff0000
946 # define TV_RY_SHIFT 16
947 # define TV_GY_MASK 0x00000fff
948 # define TV_GY_SHIFT 0
950 #define TV_CSC_Y2 0x68014
951 # define TV_BY_MASK 0x07ff0000
952 # define TV_BY_SHIFT 16
954 * Y attenuation for component video.
956 * Stored in 1.9 fixed point.
958 # define TV_AY_MASK 0x000003ff
959 # define TV_AY_SHIFT 0
961 #define TV_CSC_U 0x68018
962 # define TV_RU_MASK 0x07ff0000
963 # define TV_RU_SHIFT 16
964 # define TV_GU_MASK 0x000007ff
965 # define TV_GU_SHIFT 0
967 #define TV_CSC_U2 0x6801c
968 # define TV_BU_MASK 0x07ff0000
969 # define TV_BU_SHIFT 16
971 * U attenuation for component video.
973 * Stored in 1.9 fixed point.
975 # define TV_AU_MASK 0x000003ff
976 # define TV_AU_SHIFT 0
978 #define TV_CSC_V 0x68020
979 # define TV_RV_MASK 0x0fff0000
980 # define TV_RV_SHIFT 16
981 # define TV_GV_MASK 0x000007ff
982 # define TV_GV_SHIFT 0
984 #define TV_CSC_V2 0x68024
985 # define TV_BV_MASK 0x07ff0000
986 # define TV_BV_SHIFT 16
988 * V attenuation for component video.
990 * Stored in 1.9 fixed point.
992 # define TV_AV_MASK 0x000007ff
993 # define TV_AV_SHIFT 0
995 #define TV_CLR_KNOBS 0x68028
996 /** 2s-complement brightness adjustment */
997 # define TV_BRIGHTNESS_MASK 0xff000000
998 # define TV_BRIGHTNESS_SHIFT 24
999 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1000 # define TV_CONTRAST_MASK 0x00ff0000
1001 # define TV_CONTRAST_SHIFT 16
1002 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1003 # define TV_SATURATION_MASK 0x0000ff00
1004 # define TV_SATURATION_SHIFT 8
1005 /** Hue adjustment, as an integer phase angle in degrees */
1006 # define TV_HUE_MASK 0x000000ff
1007 # define TV_HUE_SHIFT 0
1009 #define TV_CLR_LEVEL 0x6802c
1010 /** Controls the DAC level for black */
1011 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1012 # define TV_BLACK_LEVEL_SHIFT 16
1013 /** Controls the DAC level for blanking */
1014 # define TV_BLANK_LEVEL_MASK 0x000001ff
1015 # define TV_BLANK_LEVEL_SHIFT 0
1017 #define TV_H_CTL_1 0x68030
1018 /** Number of pixels in the hsync. */
1019 # define TV_HSYNC_END_MASK 0x1fff0000
1020 # define TV_HSYNC_END_SHIFT 16
1021 /** Total number of pixels minus one in the line (display and blanking). */
1022 # define TV_HTOTAL_MASK 0x00001fff
1023 # define TV_HTOTAL_SHIFT 0
1025 #define TV_H_CTL_2 0x68034
1026 /** Enables the colorburst (needed for non-component color) */
1027 # define TV_BURST_ENA (1 << 31)
1028 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1029 # define TV_HBURST_START_SHIFT 16
1030 # define TV_HBURST_START_MASK 0x1fff0000
1031 /** Length of the colorburst */
1032 # define TV_HBURST_LEN_SHIFT 0
1033 # define TV_HBURST_LEN_MASK 0x0001fff
1035 #define TV_H_CTL_3 0x68038
1036 /** End of hblank, measured in pixels minus one from start of hsync */
1037 # define TV_HBLANK_END_SHIFT 16
1038 # define TV_HBLANK_END_MASK 0x1fff0000
1039 /** Start of hblank, measured in pixels minus one from start of hsync */
1040 # define TV_HBLANK_START_SHIFT 0
1041 # define TV_HBLANK_START_MASK 0x0001fff
1043 #define TV_V_CTL_1 0x6803c
1045 # define TV_NBR_END_SHIFT 16
1046 # define TV_NBR_END_MASK 0x07ff0000
1048 # define TV_VI_END_F1_SHIFT 8
1049 # define TV_VI_END_F1_MASK 0x00003f00
1051 # define TV_VI_END_F2_SHIFT 0
1052 # define TV_VI_END_F2_MASK 0x0000003f
1054 #define TV_V_CTL_2 0x68040
1055 /** Length of vsync, in half lines */
1056 # define TV_VSYNC_LEN_MASK 0x07ff0000
1057 # define TV_VSYNC_LEN_SHIFT 16
1058 /** Offset of the start of vsync in field 1, measured in one less than the
1059 * number of half lines.
1061 # define TV_VSYNC_START_F1_MASK 0x00007f00
1062 # define TV_VSYNC_START_F1_SHIFT 8
1064 * Offset of the start of vsync in field 2, measured in one less than the
1065 * number of half lines.
1067 # define TV_VSYNC_START_F2_MASK 0x0000007f
1068 # define TV_VSYNC_START_F2_SHIFT 0
1070 #define TV_V_CTL_3 0x68044
1071 /** Enables generation of the equalization signal */
1072 # define TV_EQUAL_ENA (1 << 31)
1073 /** Length of vsync, in half lines */
1074 # define TV_VEQ_LEN_MASK 0x007f0000
1075 # define TV_VEQ_LEN_SHIFT 16
1076 /** Offset of the start of equalization in field 1, measured in one less than
1077 * the number of half lines.
1079 # define TV_VEQ_START_F1_MASK 0x0007f00
1080 # define TV_VEQ_START_F1_SHIFT 8
1082 * Offset of the start of equalization in field 2, measured in one less than
1083 * the number of half lines.
1085 # define TV_VEQ_START_F2_MASK 0x000007f
1086 # define TV_VEQ_START_F2_SHIFT 0
1088 #define TV_V_CTL_4 0x68048
1090 * Offset to start of vertical colorburst, measured in one less than the
1091 * number of lines from vertical start.
1093 # define TV_VBURST_START_F1_MASK 0x003f0000
1094 # define TV_VBURST_START_F1_SHIFT 16
1096 * Offset to the end of vertical colorburst, measured in one less than the
1097 * number of lines from the start of NBR.
1099 # define TV_VBURST_END_F1_MASK 0x000000ff
1100 # define TV_VBURST_END_F1_SHIFT 0
1102 #define TV_V_CTL_5 0x6804c
1104 * Offset to start of vertical colorburst, measured in one less than the
1105 * number of lines from vertical start.
1107 # define TV_VBURST_START_F2_MASK 0x003f0000
1108 # define TV_VBURST_START_F2_SHIFT 16
1110 * Offset to the end of vertical colorburst, measured in one less than the
1111 * number of lines from the start of NBR.
1113 # define TV_VBURST_END_F2_MASK 0x000000ff
1114 # define TV_VBURST_END_F2_SHIFT 0
1116 #define TV_V_CTL_6 0x68050
1118 * Offset to start of vertical colorburst, measured in one less than the
1119 * number of lines from vertical start.
1121 # define TV_VBURST_START_F3_MASK 0x003f0000
1122 # define TV_VBURST_START_F3_SHIFT 16
1124 * Offset to the end of vertical colorburst, measured in one less than the
1125 * number of lines from the start of NBR.
1127 # define TV_VBURST_END_F3_MASK 0x000000ff
1128 # define TV_VBURST_END_F3_SHIFT 0
1130 #define TV_V_CTL_7 0x68054
1132 * Offset to start of vertical colorburst, measured in one less than the
1133 * number of lines from vertical start.
1135 # define TV_VBURST_START_F4_MASK 0x003f0000
1136 # define TV_VBURST_START_F4_SHIFT 16
1138 * Offset to the end of vertical colorburst, measured in one less than the
1139 * number of lines from the start of NBR.
1141 # define TV_VBURST_END_F4_MASK 0x000000ff
1142 # define TV_VBURST_END_F4_SHIFT 0
1144 #define TV_SC_CTL_1 0x68060
1145 /** Turns on the first subcarrier phase generation DDA */
1146 # define TV_SC_DDA1_EN (1 << 31)
1147 /** Turns on the first subcarrier phase generation DDA */
1148 # define TV_SC_DDA2_EN (1 << 30)
1149 /** Turns on the first subcarrier phase generation DDA */
1150 # define TV_SC_DDA3_EN (1 << 29)
1151 /** Sets the subcarrier DDA to reset frequency every other field */
1152 # define TV_SC_RESET_EVERY_2 (0 << 24)
1153 /** Sets the subcarrier DDA to reset frequency every fourth field */
1154 # define TV_SC_RESET_EVERY_4 (1 << 24)
1155 /** Sets the subcarrier DDA to reset frequency every eighth field */
1156 # define TV_SC_RESET_EVERY_8 (2 << 24)
1157 /** Sets the subcarrier DDA to never reset the frequency */
1158 # define TV_SC_RESET_NEVER (3 << 24)
1159 /** Sets the peak amplitude of the colorburst.*/
1160 # define TV_BURST_LEVEL_MASK 0x00ff0000
1161 # define TV_BURST_LEVEL_SHIFT 16
1162 /** Sets the increment of the first subcarrier phase generation DDA */
1163 # define TV_SCDDA1_INC_MASK 0x00000fff
1164 # define TV_SCDDA1_INC_SHIFT 0
1166 #define TV_SC_CTL_2 0x68064
1167 /** Sets the rollover for the second subcarrier phase generation DDA */
1168 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1169 # define TV_SCDDA2_SIZE_SHIFT 16
1170 /** Sets the increent of the second subcarrier phase generation DDA */
1171 # define TV_SCDDA2_INC_MASK 0x00007fff
1172 # define TV_SCDDA2_INC_SHIFT 0
1174 #define TV_SC_CTL_3 0x68068
1175 /** Sets the rollover for the third subcarrier phase generation DDA */
1176 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1177 # define TV_SCDDA3_SIZE_SHIFT 16
1178 /** Sets the increent of the third subcarrier phase generation DDA */
1179 # define TV_SCDDA3_INC_MASK 0x00007fff
1180 # define TV_SCDDA3_INC_SHIFT 0
1182 #define TV_WIN_POS 0x68070
1183 /** X coordinate of the display from the start of horizontal active */
1184 # define TV_XPOS_MASK 0x1fff0000
1185 # define TV_XPOS_SHIFT 16
1186 /** Y coordinate of the display from the start of vertical active (NBR) */
1187 # define TV_YPOS_MASK 0x00000fff
1188 # define TV_YPOS_SHIFT 0
1190 #define TV_WIN_SIZE 0x68074
1191 /** Horizontal size of the display window, measured in pixels*/
1192 # define TV_XSIZE_MASK 0x1fff0000
1193 # define TV_XSIZE_SHIFT 16
1195 * Vertical size of the display window, measured in pixels.
1197 * Must be even for interlaced modes.
1199 # define TV_YSIZE_MASK 0x00000fff
1200 # define TV_YSIZE_SHIFT 0
1202 #define TV_FILTER_CTL_1 0x68080
1204 * Enables automatic scaling calculation.
1206 * If set, the rest of the registers are ignored, and the calculated values can
1207 * be read back from the register.
1209 # define TV_AUTO_SCALE (1 << 31)
1211 * Disables the vertical filter.
1213 * This is required on modes more than 1024 pixels wide */
1214 # define TV_V_FILTER_BYPASS (1 << 29)
1215 /** Enables adaptive vertical filtering */
1216 # define TV_VADAPT (1 << 28)
1217 # define TV_VADAPT_MODE_MASK (3 << 26)
1218 /** Selects the least adaptive vertical filtering mode */
1219 # define TV_VADAPT_MODE_LEAST (0 << 26)
1220 /** Selects the moderately adaptive vertical filtering mode */
1221 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1222 /** Selects the most adaptive vertical filtering mode */
1223 # define TV_VADAPT_MODE_MOST (3 << 26)
1225 * Sets the horizontal scaling factor.
1227 * This should be the fractional part of the horizontal scaling factor divided
1228 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1230 * (src width - 1) / ((oversample * dest width) - 1)
1232 # define TV_HSCALE_FRAC_MASK 0x00003fff
1233 # define TV_HSCALE_FRAC_SHIFT 0
1235 #define TV_FILTER_CTL_2 0x68084
1237 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1239 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1241 # define TV_VSCALE_INT_MASK 0x00038000
1242 # define TV_VSCALE_INT_SHIFT 15
1244 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1246 * \sa TV_VSCALE_INT_MASK
1248 # define TV_VSCALE_FRAC_MASK 0x00007fff
1249 # define TV_VSCALE_FRAC_SHIFT 0
1251 #define TV_FILTER_CTL_3 0x68088
1253 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1255 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1257 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1259 # define TV_VSCALE_IP_INT_MASK 0x00038000
1260 # define TV_VSCALE_IP_INT_SHIFT 15
1262 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1264 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1266 * \sa TV_VSCALE_IP_INT_MASK
1268 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1269 # define TV_VSCALE_IP_FRAC_SHIFT 0
1271 #define TV_CC_CONTROL 0x68090
1272 # define TV_CC_ENABLE (1 << 31)
1274 * Specifies which field to send the CC data in.
1276 * CC data is usually sent in field 0.
1278 # define TV_CC_FID_MASK (1 << 27)
1279 # define TV_CC_FID_SHIFT 27
1280 /** Sets the horizontal position of the CC data. Usually 135. */
1281 # define TV_CC_HOFF_MASK 0x03ff0000
1282 # define TV_CC_HOFF_SHIFT 16
1283 /** Sets the vertical position of the CC data. Usually 21 */
1284 # define TV_CC_LINE_MASK 0x0000003f
1285 # define TV_CC_LINE_SHIFT 0
1287 #define TV_CC_DATA 0x68094
1288 # define TV_CC_RDY (1 << 31)
1289 /** Second word of CC data to be transmitted. */
1290 # define TV_CC_DATA_2_MASK 0x007f0000
1291 # define TV_CC_DATA_2_SHIFT 16
1292 /** First word of CC data to be transmitted. */
1293 # define TV_CC_DATA_1_MASK 0x0000007f
1294 # define TV_CC_DATA_1_SHIFT 0
1296 #define TV_H_LUMA_0 0x68100
1297 #define TV_H_LUMA_59 0x681ec
1298 #define TV_H_CHROMA_0 0x68200
1299 #define TV_H_CHROMA_59 0x682ec
1300 #define TV_V_LUMA_0 0x68300
1301 #define TV_V_LUMA_42 0x683a8
1302 #define TV_V_CHROMA_0 0x68400
1303 #define TV_V_CHROMA_42 0x684a8
1305 /* Display & cursor control */
1308 #define PIPEADSL 0x70000
1309 #define PIPEACONF 0x70008
1310 #define PIPEACONF_ENABLE (1<<31)
1311 #define PIPEACONF_DISABLE 0
1312 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1313 #define I965_PIPECONF_ACTIVE (1<<30)
1314 #define PIPEACONF_SINGLE_WIDE 0
1315 #define PIPEACONF_PIPE_UNLOCKED 0
1316 #define PIPEACONF_PIPE_LOCKED (1<<25)
1317 #define PIPEACONF_PALETTE 0
1318 #define PIPEACONF_GAMMA (1<<24)
1319 #define PIPECONF_FORCE_BORDER (1<<25)
1320 #define PIPECONF_PROGRESSIVE (0 << 21)
1321 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1322 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1323 #define PIPEASTAT 0x70024
1324 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1325 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1326 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1327 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1328 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1329 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1330 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1331 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1332 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1333 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1334 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1335 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1336 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1337 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1338 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1339 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1340 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1341 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1342 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1343 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1344 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1345 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1346 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1347 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1348 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1349 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1350 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1351 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1352 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1354 #define DSPARB 0x70030
1355 #define DSPARB_CSTART_MASK (0x7f << 7)
1356 #define DSPARB_CSTART_SHIFT 7
1357 #define DSPARB_BSTART_MASK (0x7f)
1358 #define DSPARB_BSTART_SHIFT 0
1360 * The two pipe frame counter registers are not synchronized, so
1361 * reading a stable value is somewhat tricky. The following code
1365 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1366 * PIPE_FRAME_HIGH_SHIFT;
1367 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1368 * PIPE_FRAME_LOW_SHIFT);
1369 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1370 * PIPE_FRAME_HIGH_SHIFT);
1371 * } while (high1 != high2);
1372 * frame = (high1 << 8) | low1;
1374 #define PIPEAFRAMEHIGH 0x70040
1375 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1376 #define PIPE_FRAME_HIGH_SHIFT 0
1377 #define PIPEAFRAMEPIXEL 0x70044
1378 #define PIPE_FRAME_LOW_MASK 0xff000000
1379 #define PIPE_FRAME_LOW_SHIFT 24
1380 #define PIPE_PIXEL_MASK 0x00ffffff
1381 #define PIPE_PIXEL_SHIFT 0
1382 /* GM45+ just has to be different */
1383 #define PIPEA_FRMCOUNT_GM45 0x70040
1384 #define PIPEA_FLIPCOUNT_GM45 0x70044
1386 /* Cursor A & B regs */
1387 #define CURACNTR 0x70080
1388 #define CURSOR_MODE_DISABLE 0x00
1389 #define CURSOR_MODE_64_32B_AX 0x07
1390 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1391 #define MCURSOR_GAMMA_ENABLE (1 << 26)
1392 #define CURABASE 0x70084
1393 #define CURAPOS 0x70088
1394 #define CURSOR_POS_MASK 0x007FF
1395 #define CURSOR_POS_SIGN 0x8000
1396 #define CURSOR_X_SHIFT 0
1397 #define CURSOR_Y_SHIFT 16
1398 #define CURBCNTR 0x700c0
1399 #define CURBBASE 0x700c4
1400 #define CURBPOS 0x700c8
1402 /* Display A control */
1403 #define DSPACNTR 0x70180
1404 #define DISPLAY_PLANE_ENABLE (1<<31)
1405 #define DISPLAY_PLANE_DISABLE 0
1406 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1407 #define DISPPLANE_GAMMA_DISABLE 0
1408 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1409 #define DISPPLANE_8BPP (0x2<<26)
1410 #define DISPPLANE_15_16BPP (0x4<<26)
1411 #define DISPPLANE_16BPP (0x5<<26)
1412 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1413 #define DISPPLANE_32BPP (0x7<<26)
1414 #define DISPPLANE_STEREO_ENABLE (1<<25)
1415 #define DISPPLANE_STEREO_DISABLE 0
1416 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1417 #define DISPPLANE_SEL_PIPE_A 0
1418 #define DISPPLANE_SEL_PIPE_B (1<<24)
1419 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1420 #define DISPPLANE_SRC_KEY_DISABLE 0
1421 #define DISPPLANE_LINE_DOUBLE (1<<20)
1422 #define DISPPLANE_NO_LINE_DOUBLE 0
1423 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1424 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1425 #define DSPAADDR 0x70184
1426 #define DSPASTRIDE 0x70188
1427 #define DSPAPOS 0x7018C /* reserved */
1428 #define DSPASIZE 0x70190
1429 #define DSPASURF 0x7019C /* 965+ only */
1430 #define DSPATILEOFF 0x701A4 /* 965+ only */
1433 #define SWF00 0x71410
1434 #define SWF01 0x71414
1435 #define SWF02 0x71418
1436 #define SWF03 0x7141c
1437 #define SWF04 0x71420
1438 #define SWF05 0x71424
1439 #define SWF06 0x71428
1440 #define SWF10 0x70410
1441 #define SWF11 0x70414
1442 #define SWF14 0x71420
1443 #define SWF30 0x72414
1444 #define SWF31 0x72418
1445 #define SWF32 0x7241c
1448 #define PIPEBDSL 0x71000
1449 #define PIPEBCONF 0x71008
1450 #define PIPEBSTAT 0x71024
1451 #define PIPEBFRAMEHIGH 0x71040
1452 #define PIPEBFRAMEPIXEL 0x71044
1453 #define PIPEB_FRMCOUNT_GM45 0x71040
1454 #define PIPEB_FLIPCOUNT_GM45 0x71044
1457 /* Display B control */
1458 #define DSPBCNTR 0x71180
1459 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1460 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1461 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1462 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1463 #define DSPBADDR 0x71184
1464 #define DSPBSTRIDE 0x71188
1465 #define DSPBPOS 0x7118C
1466 #define DSPBSIZE 0x71190
1467 #define DSPBSURF 0x7119C
1468 #define DSPBTILEOFF 0x711A4
1471 #define VGACNTRL 0x71400
1472 # define VGA_DISP_DISABLE (1 << 31)
1473 # define VGA_2X_MODE (1 << 30)
1474 # define VGA_PIPE_B_SELECT (1 << 29)
1476 #endif /* _I915_REG_H_ */
projects / FreeBSD / releng / 9.2.git / blob