sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2013, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                      0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  50 #define E1000_DEV_ID_82544GC_LOM                0x100D
  51 #define E1000_DEV_ID_82540EM                    0x100E
  52 #define E1000_DEV_ID_82540EM_LOM                0x1015
  53 #define E1000_DEV_ID_82540EP_LOM                0x1016
  54 #define E1000_DEV_ID_82540EP                    0x1017
  55 #define E1000_DEV_ID_82540EP_LP                 0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  70 #define E1000_DEV_ID_82541EI                    0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  72 #define E1000_DEV_ID_82541ER_LOM                0x1014
  73 #define E1000_DEV_ID_82541ER                    0x1078
  74 #define E1000_DEV_ID_82541GI                    0x1076
  75 #define E1000_DEV_ID_82541GI_LF                 0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  77 #define E1000_DEV_ID_82547EI                    0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  79 #define E1000_DEV_ID_82547GI                    0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  92 #define E1000_DEV_ID_82572EI                    0x10B9
  93 #define E1000_DEV_ID_82573E                     0x108B
  94 #define E1000_DEV_ID_82573E_IAMT                0x108C
  95 #define E1000_DEV_ID_82573L                     0x109A
  96 #define E1000_DEV_ID_82574L                     0x10D3
  97 #define E1000_DEV_ID_82574LA                    0x10F6
  98 #define E1000_DEV_ID_82583V                     0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 123 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 124 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 125 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 126 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 127 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 128 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 129 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 130 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 131 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 132 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 133 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 136 #define E1000_DEV_ID_82576                      0x10C9
 137 #define E1000_DEV_ID_82576_FIBER                0x10E6
 138 #define E1000_DEV_ID_82576_SERDES               0x10E7
 139 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 140 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 141 #define E1000_DEV_ID_82576_NS                   0x150A
 142 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 143 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 144 #define E1000_DEV_ID_82576_VF                   0x10CA
 145 #define E1000_DEV_ID_82576_VF_HV                0x152D
 146 #define E1000_DEV_ID_I350_VF                    0x1520
 147 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 148 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 149 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 150 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 151 #define E1000_DEV_ID_82580_COPPER               0x150E
 152 #define E1000_DEV_ID_82580_FIBER                0x150F
 153 #define E1000_DEV_ID_82580_SERDES               0x1510
 154 #define E1000_DEV_ID_82580_SGMII                0x1511
 155 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 156 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 157 #define E1000_DEV_ID_I350_COPPER                0x1521
 158 #define E1000_DEV_ID_I350_FIBER                 0x1522
 159 #define E1000_DEV_ID_I350_SERDES                0x1523
 160 #define E1000_DEV_ID_I350_SGMII                 0x1524
 161 #define E1000_DEV_ID_I350_DA4                   0x1546
 162 #define E1000_DEV_ID_I210_COPPER                0x1533
 163 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 164 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 165 #define E1000_DEV_ID_I210_FIBER                 0x1536
 166 #define E1000_DEV_ID_I210_SERDES                0x1537
 167 #define E1000_DEV_ID_I210_SGMII                 0x1538
 168 #define E1000_DEV_ID_I211_COPPER                0x1539
 169 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 170 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 171 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 172 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 173
 174 #define E1000_REVISION_0        0
 175 #define E1000_REVISION_1        1
 176 #define E1000_REVISION_2        2
 177 #define E1000_REVISION_3        3
 178 #define E1000_REVISION_4        4
 179
 180 #define E1000_FUNC_0            0
 181 #define E1000_FUNC_1            1
 182 #define E1000_FUNC_2            2
 183 #define E1000_FUNC_3            3
 184
 185 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 186 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 187 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 188 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 189
 190 enum e1000_mac_type {
 191         e1000_undefined = 0,
 192         e1000_82542,
 193         e1000_82543,
 194         e1000_82544,
 195         e1000_82540,
 196         e1000_82545,
 197         e1000_82545_rev_3,
 198         e1000_82546,
 199         e1000_82546_rev_3,
 200         e1000_82541,
 201         e1000_82541_rev_2,
 202         e1000_82547,
 203         e1000_82547_rev_2,
 204         e1000_82571,
 205         e1000_82572,
 206         e1000_82573,
 207         e1000_82574,
 208         e1000_82583,
 209         e1000_80003es2lan,
 210         e1000_ich8lan,
 211         e1000_ich9lan,
 212         e1000_ich10lan,
 213         e1000_pchlan,
 214         e1000_pch2lan,
 215         e1000_pch_lpt,
 216         e1000_82575,
 217         e1000_82576,
 218         e1000_82580,
 219         e1000_i350,
 220         e1000_i210,
 221         e1000_i211,
 222         e1000_vfadapt,
 223         e1000_vfadapt_i350,
 224         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 225 };
 226
 227 enum e1000_media_type {
 228         e1000_media_type_unknown = 0,
 229         e1000_media_type_copper = 1,
 230         e1000_media_type_fiber = 2,
 231         e1000_media_type_internal_serdes = 3,
 232         e1000_num_media_types
 233 };
 234
 235 enum e1000_nvm_type {
 236         e1000_nvm_unknown = 0,
 237         e1000_nvm_none,
 238         e1000_nvm_eeprom_spi,
 239         e1000_nvm_eeprom_microwire,
 240         e1000_nvm_flash_hw,
 241         e1000_nvm_flash_sw
 242 };
 243
 244 enum e1000_nvm_override {
 245         e1000_nvm_override_none = 0,
 246         e1000_nvm_override_spi_small,
 247         e1000_nvm_override_spi_large,
 248         e1000_nvm_override_microwire_small,
 249         e1000_nvm_override_microwire_large
 250 };
 251
 252 enum e1000_phy_type {
 253         e1000_phy_unknown = 0,
 254         e1000_phy_none,
 255         e1000_phy_m88,
 256         e1000_phy_igp,
 257         e1000_phy_igp_2,
 258         e1000_phy_gg82563,
 259         e1000_phy_igp_3,
 260         e1000_phy_ife,
 261         e1000_phy_bm,
 262         e1000_phy_82578,
 263         e1000_phy_82577,
 264         e1000_phy_82579,
 265         e1000_phy_i217,
 266         e1000_phy_82580,
 267         e1000_phy_vf,
 268         e1000_phy_i210,
 269 };
 270
 271 enum e1000_bus_type {
 272         e1000_bus_type_unknown = 0,
 273         e1000_bus_type_pci,
 274         e1000_bus_type_pcix,
 275         e1000_bus_type_pci_express,
 276         e1000_bus_type_reserved
 277 };
 278
 279 enum e1000_bus_speed {
 280         e1000_bus_speed_unknown = 0,
 281         e1000_bus_speed_33,
 282         e1000_bus_speed_66,
 283         e1000_bus_speed_100,
 284         e1000_bus_speed_120,
 285         e1000_bus_speed_133,
 286         e1000_bus_speed_2500,
 287         e1000_bus_speed_5000,
 288         e1000_bus_speed_reserved
 289 };
 290
 291 enum e1000_bus_width {
 292         e1000_bus_width_unknown = 0,
 293         e1000_bus_width_pcie_x1,
 294         e1000_bus_width_pcie_x2,
 295         e1000_bus_width_pcie_x4 = 4,
 296         e1000_bus_width_pcie_x8 = 8,
 297         e1000_bus_width_32,
 298         e1000_bus_width_64,
 299         e1000_bus_width_reserved
 300 };
 301
 302 enum e1000_1000t_rx_status {
 303         e1000_1000t_rx_status_not_ok = 0,
 304         e1000_1000t_rx_status_ok,
 305         e1000_1000t_rx_status_undefined = 0xFF
 306 };
 307
 308 enum e1000_rev_polarity {
 309         e1000_rev_polarity_normal = 0,
 310         e1000_rev_polarity_reversed,
 311         e1000_rev_polarity_undefined = 0xFF
 312 };
 313
 314 enum e1000_fc_mode {
 315         e1000_fc_none = 0,
 316         e1000_fc_rx_pause,
 317         e1000_fc_tx_pause,
 318         e1000_fc_full,
 319         e1000_fc_default = 0xFF
 320 };
 321
 322 enum e1000_ffe_config {
 323         e1000_ffe_config_enabled = 0,
 324         e1000_ffe_config_active,
 325         e1000_ffe_config_blocked
 326 };
 327
 328 enum e1000_dsp_config {
 329         e1000_dsp_config_disabled = 0,
 330         e1000_dsp_config_enabled,
 331         e1000_dsp_config_activated,
 332         e1000_dsp_config_undefined = 0xFF
 333 };
 334
 335 enum e1000_ms_type {
 336         e1000_ms_hw_default = 0,
 337         e1000_ms_force_master,
 338         e1000_ms_force_slave,
 339         e1000_ms_auto
 340 };
 341
 342 enum e1000_smart_speed {
 343         e1000_smart_speed_default = 0,
 344         e1000_smart_speed_on,
 345         e1000_smart_speed_off
 346 };
 347
 348 enum e1000_serdes_link_state {
 349         e1000_serdes_link_down = 0,
 350         e1000_serdes_link_autoneg_progress,
 351         e1000_serdes_link_autoneg_complete,
 352         e1000_serdes_link_forced_up
 353 };
 354
 355 #define __le16 u16
 356 #define __le32 u32
 357 #define __le64 u64
 358 /* Receive Descriptor */
 359 struct e1000_rx_desc {
 360         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 361         __le16 length;      /* Length of data DMAed into data buffer */
 362         __le16 csum; /* Packet checksum */
 363         u8  status;  /* Descriptor status */
 364         u8  errors;  /* Descriptor Errors */
 365         __le16 special;
 366 };
 367
 368 /* Receive Descriptor - Extended */
 369 union e1000_rx_desc_extended {
 370         struct {
 371                 __le64 buffer_addr;
 372                 __le64 reserved;
 373         } read;
 374         struct {
 375                 struct {
 376                         __le32 mrq; /* Multiple Rx Queues */
 377                         union {
 378                                 __le32 rss; /* RSS Hash */
 379                                 struct {
 380                                         __le16 ip_id;  /* IP id */
 381                                         __le16 csum;   /* Packet Checksum */
 382                                 } csum_ip;
 383                         } hi_dword;
 384                 } lower;
 385                 struct {
 386                         __le32 status_error;  /* ext status/error */
 387                         __le16 length;
 388                         __le16 vlan; /* VLAN tag */
 389                 } upper;
 390         } wb;  /* writeback */
 391 };
 392
 393 #define MAX_PS_BUFFERS 4
 394 /* Receive Descriptor - Packet Split */
 395 union e1000_rx_desc_packet_split {
 396         struct {
 397                 /* one buffer for protocol header(s), three data buffers */
 398                 __le64 buffer_addr[MAX_PS_BUFFERS];
 399         } read;
 400         struct {
 401                 struct {
 402                         __le32 mrq;  /* Multiple Rx Queues */
 403                         union {
 404                                 __le32 rss; /* RSS Hash */
 405                                 struct {
 406                                         __le16 ip_id;    /* IP id */
 407                                         __le16 csum;     /* Packet Checksum */
 408                                 } csum_ip;
 409                         } hi_dword;
 410                 } lower;
 411                 struct {
 412                         __le32 status_error;  /* ext status/error */
 413                         __le16 length0;  /* length of buffer 0 */
 414                         __le16 vlan;  /* VLAN tag */
 415                 } middle;
 416                 struct {
 417                         __le16 header_status;
 418                         __le16 length[3];     /* length of buffers 1-3 */
 419                 } upper;
 420                 __le64 reserved;
 421         } wb; /* writeback */
 422 };
 423
 424 /* Transmit Descriptor */
 425 struct e1000_tx_desc {
 426         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 427         union {
 428                 __le32 data;
 429                 struct {
 430                         __le16 length;  /* Data buffer length */
 431                         u8 cso;  /* Checksum offset */
 432                         u8 cmd;  /* Descriptor control */
 433                 } flags;
 434         } lower;
 435         union {
 436                 __le32 data;
 437                 struct {
 438                         u8 status; /* Descriptor status */
 439                         u8 css;  /* Checksum start */
 440                         __le16 special;
 441                 } fields;
 442         } upper;
 443 };
 444
 445 /* Offload Context Descriptor */
 446 struct e1000_context_desc {
 447         union {
 448                 __le32 ip_config;
 449                 struct {
 450                         u8 ipcss;  /* IP checksum start */
 451                         u8 ipcso;  /* IP checksum offset */
 452                         __le16 ipcse;  /* IP checksum end */
 453                 } ip_fields;
 454         } lower_setup;
 455         union {
 456                 __le32 tcp_config;
 457                 struct {
 458                         u8 tucss;  /* TCP checksum start */
 459                         u8 tucso;  /* TCP checksum offset */
 460                         __le16 tucse;  /* TCP checksum end */
 461                 } tcp_fields;
 462         } upper_setup;
 463         __le32 cmd_and_length;
 464         union {
 465                 __le32 data;
 466                 struct {
 467                         u8 status;  /* Descriptor status */
 468                         u8 hdr_len;  /* Header length */
 469                         __le16 mss;  /* Maximum segment size */
 470                 } fields;
 471         } tcp_seg_setup;
 472 };
 473
 474 /* Offload data descriptor */
 475 struct e1000_data_desc {
 476         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 477         union {
 478                 __le32 data;
 479                 struct {
 480                         __le16 length;  /* Data buffer length */
 481                         u8 typ_len_ext;
 482                         u8 cmd;
 483                 } flags;
 484         } lower;
 485         union {
 486                 __le32 data;
 487                 struct {
 488                         u8 status;  /* Descriptor status */
 489                         u8 popts;  /* Packet Options */
 490                         __le16 special;
 491                 } fields;
 492         } upper;
 493 };
 494
 495 /* Statistics counters collected by the MAC */
 496 struct e1000_hw_stats {
 497         u64 crcerrs;
 498         u64 algnerrc;
 499         u64 symerrs;
 500         u64 rxerrc;
 501         u64 mpc;
 502         u64 scc;
 503         u64 ecol;
 504         u64 mcc;
 505         u64 latecol;
 506         u64 colc;
 507         u64 dc;
 508         u64 tncrs;
 509         u64 sec;
 510         u64 cexterr;
 511         u64 rlec;
 512         u64 xonrxc;
 513         u64 xontxc;
 514         u64 xoffrxc;
 515         u64 xofftxc;
 516         u64 fcruc;
 517         u64 prc64;
 518         u64 prc127;
 519         u64 prc255;
 520         u64 prc511;
 521         u64 prc1023;
 522         u64 prc1522;
 523         u64 gprc;
 524         u64 bprc;
 525         u64 mprc;
 526         u64 gptc;
 527         u64 gorc;
 528         u64 gotc;
 529         u64 rnbc;
 530         u64 ruc;
 531         u64 rfc;
 532         u64 roc;
 533         u64 rjc;
 534         u64 mgprc;
 535         u64 mgpdc;
 536         u64 mgptc;
 537         u64 tor;
 538         u64 tot;
 539         u64 tpr;
 540         u64 tpt;
 541         u64 ptc64;
 542         u64 ptc127;
 543         u64 ptc255;
 544         u64 ptc511;
 545         u64 ptc1023;
 546         u64 ptc1522;
 547         u64 mptc;
 548         u64 bptc;
 549         u64 tsctc;
 550         u64 tsctfc;
 551         u64 iac;
 552         u64 icrxptc;
 553         u64 icrxatc;
 554         u64 ictxptc;
 555         u64 ictxatc;
 556         u64 ictxqec;
 557         u64 ictxqmtc;
 558         u64 icrxdmtc;
 559         u64 icrxoc;
 560         u64 cbtmpc;
 561         u64 htdpmc;
 562         u64 cbrdpc;
 563         u64 cbrmpc;
 564         u64 rpthc;
 565         u64 hgptc;
 566         u64 htcbdpc;
 567         u64 hgorc;
 568         u64 hgotc;
 569         u64 lenerrs;
 570         u64 scvpc;
 571         u64 hrmpc;
 572         u64 doosync;
 573         u64 o2bgptc;
 574         u64 o2bspc;
 575         u64 b2ospc;
 576         u64 b2ogprc;
 577 };
 578
 579 struct e1000_vf_stats {
 580         u64 base_gprc;
 581         u64 base_gptc;
 582         u64 base_gorc;
 583         u64 base_gotc;
 584         u64 base_mprc;
 585         u64 base_gotlbc;
 586         u64 base_gptlbc;
 587         u64 base_gorlbc;
 588         u64 base_gprlbc;
 589
 590         u32 last_gprc;
 591         u32 last_gptc;
 592         u32 last_gorc;
 593         u32 last_gotc;
 594         u32 last_mprc;
 595         u32 last_gotlbc;
 596         u32 last_gptlbc;
 597         u32 last_gorlbc;
 598         u32 last_gprlbc;
 599
 600         u64 gprc;
 601         u64 gptc;
 602         u64 gorc;
 603         u64 gotc;
 604         u64 mprc;
 605         u64 gotlbc;
 606         u64 gptlbc;
 607         u64 gorlbc;
 608         u64 gprlbc;
 609 };
 610
 611 struct e1000_phy_stats {
 612         u32 idle_errors;
 613         u32 receive_errors;
 614 };
 615
 616 struct e1000_host_mng_dhcp_cookie {
 617         u32 signature;
 618         u8  status;
 619         u8  reserved0;
 620         u16 vlan_id;
 621         u32 reserved1;
 622         u16 reserved2;
 623         u8  reserved3;
 624         u8  checksum;
 625 };
 626
 627 /* Host Interface "Rev 1" */
 628 struct e1000_host_command_header {
 629         u8 command_id;
 630         u8 command_length;
 631         u8 command_options;
 632         u8 checksum;
 633 };
 634
 635 #define E1000_HI_MAX_DATA_LENGTH        252
 636 struct e1000_host_command_info {
 637         struct e1000_host_command_header command_header;
 638         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 639 };
 640
 641 /* Host Interface "Rev 2" */
 642 struct e1000_host_mng_command_header {
 643         u8  command_id;
 644         u8  checksum;
 645         u16 reserved1;
 646         u16 reserved2;
 647         u16 command_length;
 648 };
 649
 650 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 651 struct e1000_host_mng_command_info {
 652         struct e1000_host_mng_command_header command_header;
 653         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 654 };
 655
 656 #include "e1000_mac.h"
 657 #include "e1000_phy.h"
 658 #include "e1000_nvm.h"
 659 #include "e1000_manage.h"
 660 #include "e1000_mbx.h"
 661
 662 /* Function pointers for the MAC. */
 663 struct e1000_mac_operations {
 664         s32  (*init_params)(struct e1000_hw *);
 665         s32  (*id_led_init)(struct e1000_hw *);
 666         s32  (*blink_led)(struct e1000_hw *);
 667         bool (*check_mng_mode)(struct e1000_hw *);
 668         s32  (*check_for_link)(struct e1000_hw *);
 669         s32  (*cleanup_led)(struct e1000_hw *);
 670         void (*clear_hw_cntrs)(struct e1000_hw *);
 671         void (*clear_vfta)(struct e1000_hw *);
 672         s32  (*get_bus_info)(struct e1000_hw *);
 673         void (*set_lan_id)(struct e1000_hw *);
 674         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 675         s32  (*led_on)(struct e1000_hw *);
 676         s32  (*led_off)(struct e1000_hw *);
 677         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 678         s32  (*reset_hw)(struct e1000_hw *);
 679         s32  (*init_hw)(struct e1000_hw *);
 680         void (*shutdown_serdes)(struct e1000_hw *);
 681         void (*power_up_serdes)(struct e1000_hw *);
 682         s32  (*setup_link)(struct e1000_hw *);
 683         s32  (*setup_physical_interface)(struct e1000_hw *);
 684         s32  (*setup_led)(struct e1000_hw *);
 685         void (*write_vfta)(struct e1000_hw *, u32, u32);
 686         void (*config_collision_dist)(struct e1000_hw *);
 687         void (*rar_set)(struct e1000_hw *, u8*, u32);
 688         s32  (*read_mac_addr)(struct e1000_hw *);
 689         s32  (*validate_mdi_setting)(struct e1000_hw *);
 690         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 691         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 692         void (*release_swfw_sync)(struct e1000_hw *, u16);
 693 };
 694
 695 /* When to use various PHY register access functions:
 696  *
 697  *                 Func   Caller
 698  *   Function      Does   Does    When to use
 699  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 700  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 701  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 702  *                                on different pages
 703  *   X_reg_page    A      L,P     for multiple accesses of different regs
 704  *                                on the same page
 705  *
 706  * Where X=[read|write], L=locking, P=sets page, A=register access
 707  *
 708  */
 709 struct e1000_phy_operations {
 710         s32  (*init_params)(struct e1000_hw *);
 711         s32  (*acquire)(struct e1000_hw *);
 712         s32  (*cfg_on_link_up)(struct e1000_hw *);
 713         s32  (*check_polarity)(struct e1000_hw *);
 714         s32  (*check_reset_block)(struct e1000_hw *);
 715         s32  (*commit)(struct e1000_hw *);
 716         s32  (*force_speed_duplex)(struct e1000_hw *);
 717         s32  (*get_cfg_done)(struct e1000_hw *hw);
 718         s32  (*get_cable_length)(struct e1000_hw *);
 719         s32  (*get_info)(struct e1000_hw *);
 720         s32  (*set_page)(struct e1000_hw *, u16);
 721         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 722         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 723         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 724         void (*release)(struct e1000_hw *);
 725         s32  (*reset)(struct e1000_hw *);
 726         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 727         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 728         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 729         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 730         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 731         void (*power_up)(struct e1000_hw *);
 732         void (*power_down)(struct e1000_hw *);
 733         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 734         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 735 };
 736
 737 /* Function pointers for the NVM. */
 738 struct e1000_nvm_operations {
 739         s32  (*init_params)(struct e1000_hw *);
 740         s32  (*acquire)(struct e1000_hw *);
 741         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 742         void (*release)(struct e1000_hw *);
 743         void (*reload)(struct e1000_hw *);
 744         s32  (*update)(struct e1000_hw *);
 745         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 746         s32  (*validate)(struct e1000_hw *);
 747         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 748 };
 749
 750 struct e1000_mac_info {
 751         struct e1000_mac_operations ops;
 752         u8 addr[ETH_ADDR_LEN];
 753         u8 perm_addr[ETH_ADDR_LEN];
 754
 755         enum e1000_mac_type type;
 756
 757         u32 collision_delta;
 758         u32 ledctl_default;
 759         u32 ledctl_mode1;
 760         u32 ledctl_mode2;
 761         u32 mc_filter_type;
 762         u32 tx_packet_delta;
 763         u32 txcw;
 764
 765         u16 current_ifs_val;
 766         u16 ifs_max_val;
 767         u16 ifs_min_val;
 768         u16 ifs_ratio;
 769         u16 ifs_step_size;
 770         u16 mta_reg_count;
 771         u16 uta_reg_count;
 772
 773         /* Maximum size of the MTA register table in all supported adapters */
 774         #define MAX_MTA_REG 128
 775         u32 mta_shadow[MAX_MTA_REG];
 776         u16 rar_entry_count;
 777
 778         u8  forced_speed_duplex;
 779
 780         bool adaptive_ifs;
 781         bool has_fwsm;
 782         bool arc_subsystem_valid;
 783         bool asf_firmware_present;
 784         bool autoneg;
 785         bool autoneg_failed;
 786         bool get_link_status;
 787         bool in_ifs_mode;
 788         bool report_tx_early;
 789         enum e1000_serdes_link_state serdes_link_state;
 790         bool serdes_has_link;
 791         bool tx_pkt_filtering;
 792         u32 max_frame_size;
 793 };
 794
 795 struct e1000_phy_info {
 796         struct e1000_phy_operations ops;
 797         enum e1000_phy_type type;
 798
 799         enum e1000_1000t_rx_status local_rx;
 800         enum e1000_1000t_rx_status remote_rx;
 801         enum e1000_ms_type ms_type;
 802         enum e1000_ms_type original_ms_type;
 803         enum e1000_rev_polarity cable_polarity;
 804         enum e1000_smart_speed smart_speed;
 805
 806         u32 addr;
 807         u32 id;
 808         u32 reset_delay_us; /* in usec */
 809         u32 revision;
 810
 811         enum e1000_media_type media_type;
 812
 813         u16 autoneg_advertised;
 814         u16 autoneg_mask;
 815         u16 cable_length;
 816         u16 max_cable_length;
 817         u16 min_cable_length;
 818
 819         u8 mdix;
 820
 821         bool disable_polarity_correction;
 822         bool is_mdix;
 823         bool polarity_correction;
 824         bool speed_downgraded;
 825         bool autoneg_wait_to_complete;
 826 };
 827
 828 struct e1000_nvm_info {
 829         struct e1000_nvm_operations ops;
 830         enum e1000_nvm_type type;
 831         enum e1000_nvm_override override;
 832
 833         u32 flash_bank_size;
 834         u32 flash_base_addr;
 835
 836         u16 word_size;
 837         u16 delay_usec;
 838         u16 address_bits;
 839         u16 opcode_bits;
 840         u16 page_size;
 841 };
 842
 843 struct e1000_bus_info {
 844         enum e1000_bus_type type;
 845         enum e1000_bus_speed speed;
 846         enum e1000_bus_width width;
 847
 848         u16 func;
 849         u16 pci_cmd_word;
 850 };
 851
 852 struct e1000_fc_info {
 853         u32 high_water;  /* Flow control high-water mark */
 854         u32 low_water;  /* Flow control low-water mark */
 855         u16 pause_time;  /* Flow control pause timer */
 856         u16 refresh_time;  /* Flow control refresh timer */
 857         bool send_xon;  /* Flow control send XON */
 858         bool strict_ieee;  /* Strict IEEE mode */
 859         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 860         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 861 };
 862
 863 struct e1000_mbx_operations {
 864         s32 (*init_params)(struct e1000_hw *hw);
 865         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 866         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 867         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 868         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 869         s32 (*check_for_msg)(struct e1000_hw *, u16);
 870         s32 (*check_for_ack)(struct e1000_hw *, u16);
 871         s32 (*check_for_rst)(struct e1000_hw *, u16);
 872 };
 873
 874 struct e1000_mbx_stats {
 875         u32 msgs_tx;
 876         u32 msgs_rx;
 877
 878         u32 acks;
 879         u32 reqs;
 880         u32 rsts;
 881 };
 882
 883 struct e1000_mbx_info {
 884         struct e1000_mbx_operations ops;
 885         struct e1000_mbx_stats stats;
 886         u32 timeout;
 887         u32 usec_delay;
 888         u16 size;
 889 };
 890
 891 struct e1000_dev_spec_82541 {
 892         enum e1000_dsp_config dsp_config;
 893         enum e1000_ffe_config ffe_config;
 894         u16 spd_default;
 895         bool phy_init_script;
 896 };
 897
 898 struct e1000_dev_spec_82542 {
 899         bool dma_fairness;
 900 };
 901
 902 struct e1000_dev_spec_82543 {
 903         u32  tbi_compatibility;
 904         bool dma_fairness;
 905         bool init_phy_disabled;
 906 };
 907
 908 struct e1000_dev_spec_82571 {
 909         bool laa_is_present;
 910         u32 smb_counter;
 911         E1000_MUTEX swflag_mutex;
 912 };
 913
 914 struct e1000_dev_spec_80003es2lan {
 915         bool  mdic_wa_enable;
 916 };
 917
 918 struct e1000_shadow_ram {
 919         u16  value;
 920         bool modified;
 921 };
 922
 923 #define E1000_SHADOW_RAM_WORDS          2048
 924
 925 struct e1000_dev_spec_ich8lan {
 926         bool kmrn_lock_loss_workaround_enabled;
 927         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 928         E1000_MUTEX nvm_mutex;
 929         E1000_MUTEX swflag_mutex;
 930         bool nvm_k1_enabled;
 931         bool eee_disable;
 932         u16 eee_lp_ability;
 933 };
 934
 935 struct e1000_dev_spec_82575 {
 936         bool sgmii_active;
 937         bool global_device_reset;
 938         bool eee_disable;
 939         bool module_plugged;
 940         bool clear_semaphore_once;
 941         u32 mtu;
 942         struct sfp_e1000_flags eth_flags;
 943 };
 944
 945 struct e1000_dev_spec_vf {
 946         u32 vf_number;
 947         u32 v2p_mailbox;
 948 };
 949
 950 struct e1000_hw {
 951         void *back;
 952
 953         u8 *hw_addr;
 954         u8 *flash_address;
 955         unsigned long io_base;
 956
 957         struct e1000_mac_info  mac;
 958         struct e1000_fc_info   fc;
 959         struct e1000_phy_info  phy;
 960         struct e1000_nvm_info  nvm;
 961         struct e1000_bus_info  bus;
 962         struct e1000_mbx_info mbx;
 963         struct e1000_host_mng_dhcp_cookie mng_cookie;
 964
 965         union {
 966                 struct e1000_dev_spec_82541 _82541;
 967                 struct e1000_dev_spec_82542 _82542;
 968                 struct e1000_dev_spec_82543 _82543;
 969                 struct e1000_dev_spec_82571 _82571;
 970                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 971                 struct e1000_dev_spec_ich8lan ich8lan;
 972                 struct e1000_dev_spec_82575 _82575;
 973                 struct e1000_dev_spec_vf vf;
 974         } dev_spec;
 975
 976         u16 device_id;
 977         u16 subsystem_vendor_id;
 978         u16 subsystem_device_id;
 979         u16 vendor_id;
 980
 981         u8  revision_id;
 982 };
 983
 984 #include "e1000_82541.h"
 985 #include "e1000_82543.h"
 986 #include "e1000_82571.h"
 987 #include "e1000_80003es2lan.h"
 988 #include "e1000_ich8lan.h"
 989 #include "e1000_82575.h"
 990 #include "e1000_i210.h"
 991
 992 /* These functions must be implemented by drivers */
 993 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 994 void e1000_pci_set_mwi(struct e1000_hw *hw);
 995 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 996 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 997 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 998 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 999
1000 #endif