1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
40 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
43 * e1000_init_mac_ops_generic - Initialize MAC function pointers
44 * @hw: pointer to the HW structure
46 * Setups up the function pointers to no-op functions
48 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
50 struct e1000_mac_info *mac = &hw->mac;
51 DEBUGFUNC("e1000_init_mac_ops_generic");
54 mac->ops.init_params = e1000_null_ops_generic;
55 mac->ops.init_hw = e1000_null_ops_generic;
56 mac->ops.reset_hw = e1000_null_ops_generic;
57 mac->ops.setup_physical_interface = e1000_null_ops_generic;
58 mac->ops.get_bus_info = e1000_null_ops_generic;
59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
64 mac->ops.cleanup_led = e1000_null_ops_generic;
65 mac->ops.setup_led = e1000_null_ops_generic;
66 mac->ops.blink_led = e1000_null_ops_generic;
67 mac->ops.led_on = e1000_null_ops_generic;
68 mac->ops.led_off = e1000_null_ops_generic;
70 mac->ops.setup_link = e1000_null_ops_generic;
71 mac->ops.get_link_up_info = e1000_null_link_info;
72 mac->ops.check_for_link = e1000_null_ops_generic;
73 mac->ops.set_obff_timer = e1000_null_set_obff_timer;
75 mac->ops.check_mng_mode = e1000_null_mng_mode;
77 mac->ops.update_mc_addr_list = e1000_null_update_mc;
78 mac->ops.clear_vfta = e1000_null_mac_generic;
79 mac->ops.write_vfta = e1000_null_write_vfta;
80 mac->ops.rar_set = e1000_rar_set_generic;
81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
85 * e1000_null_ops_generic - No-op function, returns 0
86 * @hw: pointer to the HW structure
88 s32 e1000_null_ops_generic(struct e1000_hw *hw)
90 DEBUGFUNC("e1000_null_ops_generic");
95 * e1000_null_mac_generic - No-op function, return void
96 * @hw: pointer to the HW structure
98 void e1000_null_mac_generic(struct e1000_hw *hw)
100 DEBUGFUNC("e1000_null_mac_generic");
105 * e1000_null_link_info - No-op function, return 0
106 * @hw: pointer to the HW structure
108 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
110 DEBUGFUNC("e1000_null_link_info");
111 return E1000_SUCCESS;
115 * e1000_null_mng_mode - No-op function, return FALSE
116 * @hw: pointer to the HW structure
118 bool e1000_null_mng_mode(struct e1000_hw *hw) {
119 DEBUGFUNC("e1000_null_mng_mode");
124 * e1000_null_update_mc - No-op function, return void
125 * @hw: pointer to the HW structure
127 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
129 DEBUGFUNC("e1000_null_update_mc");
134 * e1000_null_write_vfta - No-op function, return void
135 * @hw: pointer to the HW structure
137 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
139 DEBUGFUNC("e1000_null_write_vfta");
144 * e1000_null_rar_set - No-op function, return void
145 * @hw: pointer to the HW structure
147 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
149 DEBUGFUNC("e1000_null_rar_set");
154 * e1000_null_set_obff_timer - No-op function, return 0
155 * @hw: pointer to the HW structure
157 s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a)
159 DEBUGFUNC("e1000_null_set_obff_timer");
160 return E1000_SUCCESS;
164 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
165 * @hw: pointer to the HW structure
167 * Determines and stores the system bus information for a particular
168 * network interface. The following bus information is determined and stored:
169 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
171 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
173 struct e1000_mac_info *mac = &hw->mac;
174 struct e1000_bus_info *bus = &hw->bus;
175 u32 status = E1000_READ_REG(hw, E1000_STATUS);
176 s32 ret_val = E1000_SUCCESS;
178 DEBUGFUNC("e1000_get_bus_info_pci_generic");
181 bus->type = (status & E1000_STATUS_PCIX_MODE)
182 ? e1000_bus_type_pcix
183 : e1000_bus_type_pci;
186 if (bus->type == e1000_bus_type_pci) {
187 bus->speed = (status & E1000_STATUS_PCI66)
189 : e1000_bus_speed_33;
191 switch (status & E1000_STATUS_PCIX_SPEED) {
192 case E1000_STATUS_PCIX_SPEED_66:
193 bus->speed = e1000_bus_speed_66;
195 case E1000_STATUS_PCIX_SPEED_100:
196 bus->speed = e1000_bus_speed_100;
198 case E1000_STATUS_PCIX_SPEED_133:
199 bus->speed = e1000_bus_speed_133;
202 bus->speed = e1000_bus_speed_reserved;
208 bus->width = (status & E1000_STATUS_BUS64)
210 : e1000_bus_width_32;
212 /* Which PCI(-X) function? */
213 mac->ops.set_lan_id(hw);
219 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
220 * @hw: pointer to the HW structure
222 * Determines and stores the system bus information for a particular
223 * network interface. The following bus information is determined and stored:
224 * bus speed, bus width, type (PCIe), and PCIe function.
226 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
228 struct e1000_mac_info *mac = &hw->mac;
229 struct e1000_bus_info *bus = &hw->bus;
231 u16 pcie_link_status;
233 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
235 bus->type = e1000_bus_type_pci_express;
237 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
240 bus->width = e1000_bus_width_unknown;
241 bus->speed = e1000_bus_speed_unknown;
243 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
244 case PCIE_LINK_SPEED_2500:
245 bus->speed = e1000_bus_speed_2500;
247 case PCIE_LINK_SPEED_5000:
248 bus->speed = e1000_bus_speed_5000;
251 bus->speed = e1000_bus_speed_unknown;
255 bus->width = (enum e1000_bus_width)((pcie_link_status &
256 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
259 mac->ops.set_lan_id(hw);
261 return E1000_SUCCESS;
265 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
267 * @hw: pointer to the HW structure
269 * Determines the LAN function id by reading memory-mapped registers
270 * and swaps the port value if requested.
272 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
274 struct e1000_bus_info *bus = &hw->bus;
277 /* The status register reports the correct function number
278 * for the device regardless of function swap state.
280 reg = E1000_READ_REG(hw, E1000_STATUS);
281 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
285 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
286 * @hw: pointer to the HW structure
288 * Determines the LAN function id by reading PCI config space.
290 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
292 struct e1000_bus_info *bus = &hw->bus;
296 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
297 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
298 status = E1000_READ_REG(hw, E1000_STATUS);
299 bus->func = (status & E1000_STATUS_FUNC_MASK)
300 >> E1000_STATUS_FUNC_SHIFT;
307 * e1000_set_lan_id_single_port - Set LAN id for a single port device
308 * @hw: pointer to the HW structure
310 * Sets the LAN function id to zero for a single port device.
312 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
314 struct e1000_bus_info *bus = &hw->bus;
320 * e1000_clear_vfta_generic - Clear VLAN filter table
321 * @hw: pointer to the HW structure
323 * Clears the register array which contains the VLAN filter table by
324 * setting all the values to 0.
326 void e1000_clear_vfta_generic(struct e1000_hw *hw)
330 DEBUGFUNC("e1000_clear_vfta_generic");
332 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
333 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
334 E1000_WRITE_FLUSH(hw);
339 * e1000_write_vfta_generic - Write value to VLAN filter table
340 * @hw: pointer to the HW structure
341 * @offset: register offset in VLAN filter table
342 * @value: register value written to VLAN filter table
344 * Writes value at the given offset in the register array which stores
345 * the VLAN filter table.
347 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
349 DEBUGFUNC("e1000_write_vfta_generic");
351 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
352 E1000_WRITE_FLUSH(hw);
356 * e1000_init_rx_addrs_generic - Initialize receive address's
357 * @hw: pointer to the HW structure
358 * @rar_count: receive address registers
360 * Setup the receive address registers by setting the base receive address
361 * register to the devices MAC address and clearing all the other receive
362 * address registers to 0.
364 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
367 u8 mac_addr[ETH_ADDR_LEN] = {0};
369 DEBUGFUNC("e1000_init_rx_addrs_generic");
371 /* Setup the receive address */
372 DEBUGOUT("Programming MAC Address into RAR[0]\n");
374 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
376 /* Zero out the other (rar_entry_count - 1) receive addresses */
377 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
378 for (i = 1; i < rar_count; i++)
379 hw->mac.ops.rar_set(hw, mac_addr, i);
383 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
384 * @hw: pointer to the HW structure
386 * Checks the nvm for an alternate MAC address. An alternate MAC address
387 * can be setup by pre-boot software and must be treated like a permanent
388 * address and must override the actual permanent MAC address. If an
389 * alternate MAC address is found it is programmed into RAR0, replacing
390 * the permanent address that was installed into RAR0 by the Si on reset.
391 * This function will return SUCCESS unless it encounters an error while
392 * reading the EEPROM.
394 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
398 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
399 u8 alt_mac_addr[ETH_ADDR_LEN];
401 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
403 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
407 /* not supported on older hardware or 82573 */
408 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
409 return E1000_SUCCESS;
411 /* Alternate MAC address is handled by the option ROM for 82580
412 * and newer. SW support not required.
414 if (hw->mac.type >= e1000_82580)
415 return E1000_SUCCESS;
417 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
418 &nvm_alt_mac_addr_offset);
420 DEBUGOUT("NVM Read Error\n");
424 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
425 (nvm_alt_mac_addr_offset == 0x0000))
426 /* There is no Alternate MAC Address */
427 return E1000_SUCCESS;
429 if (hw->bus.func == E1000_FUNC_1)
430 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
431 if (hw->bus.func == E1000_FUNC_2)
432 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
434 if (hw->bus.func == E1000_FUNC_3)
435 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
436 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
437 offset = nvm_alt_mac_addr_offset + (i >> 1);
438 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
440 DEBUGOUT("NVM Read Error\n");
444 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
445 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
448 /* if multicast bit is set, the alternate address will not be used */
449 if (alt_mac_addr[0] & 0x01) {
450 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
451 return E1000_SUCCESS;
454 /* We have a valid alternate MAC address, and we want to treat it the
455 * same as the normal permanent MAC address stored by the HW into the
456 * RAR. Do this by mapping this address into RAR0.
458 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
460 return E1000_SUCCESS;
464 * e1000_rar_set_generic - Set receive address register
465 * @hw: pointer to the HW structure
466 * @addr: pointer to the receive address
467 * @index: receive address array register
469 * Sets the receive address array register at index to the address passed
472 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
474 u32 rar_low, rar_high;
476 DEBUGFUNC("e1000_rar_set_generic");
478 /* HW expects these in little endian so we reverse the byte order
479 * from network order (big endian) to little endian
481 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
482 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
484 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
486 /* If MAC address zero, no need to set the AV bit */
487 if (rar_low || rar_high)
488 rar_high |= E1000_RAH_AV;
490 /* Some bridges will combine consecutive 32-bit writes into
491 * a single burst write, which will malfunction on some parts.
492 * The flushes avoid this.
494 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
495 E1000_WRITE_FLUSH(hw);
496 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
497 E1000_WRITE_FLUSH(hw);
501 * e1000_hash_mc_addr_generic - Generate a multicast hash value
502 * @hw: pointer to the HW structure
503 * @mc_addr: pointer to a multicast address
505 * Generates a multicast address hash value which is used to determine
506 * the multicast filter table array address and new table value.
508 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
510 u32 hash_value, hash_mask;
513 DEBUGFUNC("e1000_hash_mc_addr_generic");
515 /* Register count multiplied by bits per register */
516 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
518 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
519 * where 0xFF would still fall within the hash mask.
521 while (hash_mask >> bit_shift != 0xFF)
524 /* The portion of the address that is used for the hash table
525 * is determined by the mc_filter_type setting.
526 * The algorithm is such that there is a total of 8 bits of shifting.
527 * The bit_shift for a mc_filter_type of 0 represents the number of
528 * left-shifts where the MSB of mc_addr[5] would still fall within
529 * the hash_mask. Case 0 does this exactly. Since there are a total
530 * of 8 bits of shifting, then mc_addr[4] will shift right the
531 * remaining number of bits. Thus 8 - bit_shift. The rest of the
532 * cases are a variation of this algorithm...essentially raising the
533 * number of bits to shift mc_addr[5] left, while still keeping the
534 * 8-bit shifting total.
536 * For example, given the following Destination MAC Address and an
537 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
538 * we can see that the bit_shift for case 0 is 4. These are the hash
539 * values resulting from each mc_filter_type...
540 * [0] [1] [2] [3] [4] [5]
544 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
545 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
546 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
547 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
549 switch (hw->mac.mc_filter_type) {
564 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
565 (((u16) mc_addr[5]) << bit_shift)));
571 * e1000_update_mc_addr_list_generic - Update Multicast addresses
572 * @hw: pointer to the HW structure
573 * @mc_addr_list: array of multicast addresses to program
574 * @mc_addr_count: number of multicast addresses to program
576 * Updates entire Multicast Table Array.
577 * The caller must have a packed mc_addr_list of multicast addresses.
579 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
580 u8 *mc_addr_list, u32 mc_addr_count)
582 u32 hash_value, hash_bit, hash_reg;
585 DEBUGFUNC("e1000_update_mc_addr_list_generic");
587 /* clear mta_shadow */
588 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
590 /* update mta_shadow from mc_addr_list */
591 for (i = 0; (u32) i < mc_addr_count; i++) {
592 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
594 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
595 hash_bit = hash_value & 0x1F;
597 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
598 mc_addr_list += (ETH_ADDR_LEN);
601 /* replace the entire MTA table */
602 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
603 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
604 E1000_WRITE_FLUSH(hw);
608 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
609 * @hw: pointer to the HW structure
611 * In certain situations, a system BIOS may report that the PCIx maximum
612 * memory read byte count (MMRBC) value is higher than than the actual
613 * value. We check the PCIx command register with the current PCIx status
616 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
620 u16 pcix_stat_hi_word;
623 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
625 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
626 if (hw->bus.type != e1000_bus_type_pcix)
629 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
630 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
631 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
632 PCIX_COMMAND_MMRBC_SHIFT;
633 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
634 PCIX_STATUS_HI_MMRBC_SHIFT;
635 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
636 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
637 if (cmd_mmrbc > stat_mmrbc) {
638 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
639 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
640 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
645 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
646 * @hw: pointer to the HW structure
648 * Clears the base hardware counters by reading the counter registers.
650 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
652 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
654 E1000_READ_REG(hw, E1000_CRCERRS);
655 E1000_READ_REG(hw, E1000_SYMERRS);
656 E1000_READ_REG(hw, E1000_MPC);
657 E1000_READ_REG(hw, E1000_SCC);
658 E1000_READ_REG(hw, E1000_ECOL);
659 E1000_READ_REG(hw, E1000_MCC);
660 E1000_READ_REG(hw, E1000_LATECOL);
661 E1000_READ_REG(hw, E1000_COLC);
662 E1000_READ_REG(hw, E1000_DC);
663 E1000_READ_REG(hw, E1000_SEC);
664 E1000_READ_REG(hw, E1000_RLEC);
665 E1000_READ_REG(hw, E1000_XONRXC);
666 E1000_READ_REG(hw, E1000_XONTXC);
667 E1000_READ_REG(hw, E1000_XOFFRXC);
668 E1000_READ_REG(hw, E1000_XOFFTXC);
669 E1000_READ_REG(hw, E1000_FCRUC);
670 E1000_READ_REG(hw, E1000_GPRC);
671 E1000_READ_REG(hw, E1000_BPRC);
672 E1000_READ_REG(hw, E1000_MPRC);
673 E1000_READ_REG(hw, E1000_GPTC);
674 E1000_READ_REG(hw, E1000_GORCL);
675 E1000_READ_REG(hw, E1000_GORCH);
676 E1000_READ_REG(hw, E1000_GOTCL);
677 E1000_READ_REG(hw, E1000_GOTCH);
678 E1000_READ_REG(hw, E1000_RNBC);
679 E1000_READ_REG(hw, E1000_RUC);
680 E1000_READ_REG(hw, E1000_RFC);
681 E1000_READ_REG(hw, E1000_ROC);
682 E1000_READ_REG(hw, E1000_RJC);
683 E1000_READ_REG(hw, E1000_TORL);
684 E1000_READ_REG(hw, E1000_TORH);
685 E1000_READ_REG(hw, E1000_TOTL);
686 E1000_READ_REG(hw, E1000_TOTH);
687 E1000_READ_REG(hw, E1000_TPR);
688 E1000_READ_REG(hw, E1000_TPT);
689 E1000_READ_REG(hw, E1000_MPTC);
690 E1000_READ_REG(hw, E1000_BPTC);
694 * e1000_check_for_copper_link_generic - Check for link (Copper)
695 * @hw: pointer to the HW structure
697 * Checks to see of the link status of the hardware has changed. If a
698 * change in link status has been detected, then we read the PHY registers
699 * to get the current speed/duplex if link exists.
701 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
703 struct e1000_mac_info *mac = &hw->mac;
707 DEBUGFUNC("e1000_check_for_copper_link");
709 /* We only want to go out to the PHY registers to see if Auto-Neg
710 * has completed and/or if our link status has changed. The
711 * get_link_status flag is set upon receiving a Link Status
712 * Change or Rx Sequence Error interrupt.
714 if (!mac->get_link_status)
715 return E1000_SUCCESS;
717 /* First we want to see if the MII Status Register reports
718 * link. If so, then we want to get the current speed/duplex
721 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
726 return E1000_SUCCESS; /* No link detected */
728 mac->get_link_status = FALSE;
730 /* Check if there was DownShift, must be checked
731 * immediately after link-up
733 e1000_check_downshift_generic(hw);
735 /* If we are forcing speed/duplex, then we simply return since
736 * we have already determined whether we have link or not.
739 return -E1000_ERR_CONFIG;
741 /* Auto-Neg is enabled. Auto Speed Detection takes care
742 * of MAC speed/duplex configuration. So we only need to
743 * configure Collision Distance in the MAC.
745 mac->ops.config_collision_dist(hw);
747 /* Configure Flow Control now that Auto-Neg has completed.
748 * First, we need to restore the desired flow control
749 * settings because we may have had to re-autoneg with a
750 * different link partner.
752 ret_val = e1000_config_fc_after_link_up_generic(hw);
754 DEBUGOUT("Error configuring flow control\n");
760 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
761 * @hw: pointer to the HW structure
763 * Checks for link up on the hardware. If link is not up and we have
764 * a signal, then we need to force link up.
766 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
768 struct e1000_mac_info *mac = &hw->mac;
774 DEBUGFUNC("e1000_check_for_fiber_link_generic");
776 ctrl = E1000_READ_REG(hw, E1000_CTRL);
777 status = E1000_READ_REG(hw, E1000_STATUS);
778 rxcw = E1000_READ_REG(hw, E1000_RXCW);
780 /* If we don't have link (auto-negotiation failed or link partner
781 * cannot auto-negotiate), the cable is plugged in (we have signal),
782 * and our link partner is not trying to auto-negotiate with us (we
783 * are receiving idles or data), we need to force link up. We also
784 * need to give auto-negotiation time to complete, in case the cable
785 * was just plugged in. The autoneg_failed flag does this.
787 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
788 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
789 !(rxcw & E1000_RXCW_C)) {
790 if (!mac->autoneg_failed) {
791 mac->autoneg_failed = TRUE;
792 return E1000_SUCCESS;
794 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
796 /* Disable auto-negotiation in the TXCW register */
797 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
799 /* Force link-up and also force full-duplex. */
800 ctrl = E1000_READ_REG(hw, E1000_CTRL);
801 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
802 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
804 /* Configure Flow Control after forcing link up. */
805 ret_val = e1000_config_fc_after_link_up_generic(hw);
807 DEBUGOUT("Error configuring flow control\n");
810 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
811 /* If we are forcing link and we are receiving /C/ ordered
812 * sets, re-enable auto-negotiation in the TXCW register
813 * and disable forced link in the Device Control register
814 * in an attempt to auto-negotiate with our link partner.
816 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
817 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
818 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
820 mac->serdes_has_link = TRUE;
823 return E1000_SUCCESS;
827 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
828 * @hw: pointer to the HW structure
830 * Checks for link up on the hardware. If link is not up and we have
831 * a signal, then we need to force link up.
833 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
835 struct e1000_mac_info *mac = &hw->mac;
841 DEBUGFUNC("e1000_check_for_serdes_link_generic");
843 ctrl = E1000_READ_REG(hw, E1000_CTRL);
844 status = E1000_READ_REG(hw, E1000_STATUS);
845 rxcw = E1000_READ_REG(hw, E1000_RXCW);
847 /* If we don't have link (auto-negotiation failed or link partner
848 * cannot auto-negotiate), and our link partner is not trying to
849 * auto-negotiate with us (we are receiving idles or data),
850 * we need to force link up. We also need to give auto-negotiation
853 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
854 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
855 if (!mac->autoneg_failed) {
856 mac->autoneg_failed = TRUE;
857 return E1000_SUCCESS;
859 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
861 /* Disable auto-negotiation in the TXCW register */
862 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
864 /* Force link-up and also force full-duplex. */
865 ctrl = E1000_READ_REG(hw, E1000_CTRL);
866 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
867 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
869 /* Configure Flow Control after forcing link up. */
870 ret_val = e1000_config_fc_after_link_up_generic(hw);
872 DEBUGOUT("Error configuring flow control\n");
875 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
876 /* If we are forcing link and we are receiving /C/ ordered
877 * sets, re-enable auto-negotiation in the TXCW register
878 * and disable forced link in the Device Control register
879 * in an attempt to auto-negotiate with our link partner.
881 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
882 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
883 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
885 mac->serdes_has_link = TRUE;
886 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
887 /* If we force link for non-auto-negotiation switch, check
888 * link status based on MAC synchronization for internal
891 /* SYNCH bit and IV bit are sticky. */
893 rxcw = E1000_READ_REG(hw, E1000_RXCW);
894 if (rxcw & E1000_RXCW_SYNCH) {
895 if (!(rxcw & E1000_RXCW_IV)) {
896 mac->serdes_has_link = TRUE;
897 DEBUGOUT("SERDES: Link up - forced.\n");
900 mac->serdes_has_link = FALSE;
901 DEBUGOUT("SERDES: Link down - force failed.\n");
905 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
906 status = E1000_READ_REG(hw, E1000_STATUS);
907 if (status & E1000_STATUS_LU) {
908 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
910 rxcw = E1000_READ_REG(hw, E1000_RXCW);
911 if (rxcw & E1000_RXCW_SYNCH) {
912 if (!(rxcw & E1000_RXCW_IV)) {
913 mac->serdes_has_link = TRUE;
914 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
916 mac->serdes_has_link = FALSE;
917 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
920 mac->serdes_has_link = FALSE;
921 DEBUGOUT("SERDES: Link down - no sync.\n");
924 mac->serdes_has_link = FALSE;
925 DEBUGOUT("SERDES: Link down - autoneg failed\n");
929 return E1000_SUCCESS;
933 * e1000_set_default_fc_generic - Set flow control default values
934 * @hw: pointer to the HW structure
936 * Read the EEPROM for the default values for flow control and store the
939 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
944 DEBUGFUNC("e1000_set_default_fc_generic");
946 /* Read and store word 0x0F of the EEPROM. This word contains bits
947 * that determine the hardware's default PAUSE (flow control) mode,
948 * a bit that determines whether the HW defaults to enabling or
949 * disabling auto-negotiation, and the direction of the
950 * SW defined pins. If there is no SW over-ride of the flow
951 * control setting, then the variable hw->fc will
952 * be initialized based on a value in the EEPROM.
954 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
957 DEBUGOUT("NVM Read Error\n");
961 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
962 hw->fc.requested_mode = e1000_fc_none;
963 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
965 hw->fc.requested_mode = e1000_fc_tx_pause;
967 hw->fc.requested_mode = e1000_fc_full;
969 return E1000_SUCCESS;
973 * e1000_setup_link_generic - Setup flow control and link settings
974 * @hw: pointer to the HW structure
976 * Determines which flow control settings to use, then configures flow
977 * control. Calls the appropriate media-specific link configuration
978 * function. Assuming the adapter has a valid link partner, a valid link
979 * should be established. Assumes the hardware has previously been reset
980 * and the transmitter and receiver are not enabled.
982 s32 e1000_setup_link_generic(struct e1000_hw *hw)
986 DEBUGFUNC("e1000_setup_link_generic");
988 /* In the case of the phy reset being blocked, we already have a link.
989 * We do not need to set it up again.
991 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
992 return E1000_SUCCESS;
994 /* If requested flow control is set to default, set flow control
995 * based on the EEPROM flow control settings.
997 if (hw->fc.requested_mode == e1000_fc_default) {
998 ret_val = e1000_set_default_fc_generic(hw);
1003 /* Save off the requested flow control mode for use later. Depending
1004 * on the link partner's capabilities, we may or may not use this mode.
1006 hw->fc.current_mode = hw->fc.requested_mode;
1008 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1009 hw->fc.current_mode);
1011 /* Call the necessary media_type subroutine to configure the link. */
1012 ret_val = hw->mac.ops.setup_physical_interface(hw);
1016 /* Initialize the flow control address, type, and PAUSE timer
1017 * registers to their default values. This is done even if flow
1018 * control is disabled, because it does not hurt anything to
1019 * initialize these registers.
1021 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1022 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1023 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1024 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1026 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1028 return e1000_set_fc_watermarks_generic(hw);
1032 * e1000_commit_fc_settings_generic - Configure flow control
1033 * @hw: pointer to the HW structure
1035 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1036 * base on the flow control settings in e1000_mac_info.
1038 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1040 struct e1000_mac_info *mac = &hw->mac;
1043 DEBUGFUNC("e1000_commit_fc_settings_generic");
1045 /* Check for a software override of the flow control settings, and
1046 * setup the device accordingly. If auto-negotiation is enabled, then
1047 * software will have to set the "PAUSE" bits to the correct value in
1048 * the Transmit Config Word Register (TXCW) and re-start auto-
1049 * negotiation. However, if auto-negotiation is disabled, then
1050 * software will have to manually configure the two flow control enable
1051 * bits in the CTRL register.
1053 * The possible values of the "fc" parameter are:
1054 * 0: Flow control is completely disabled
1055 * 1: Rx flow control is enabled (we can receive pause frames,
1056 * but not send pause frames).
1057 * 2: Tx flow control is enabled (we can send pause frames but we
1058 * do not support receiving pause frames).
1059 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1061 switch (hw->fc.current_mode) {
1063 /* Flow control completely disabled by a software over-ride. */
1064 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1066 case e1000_fc_rx_pause:
1067 /* Rx Flow control is enabled and Tx Flow control is disabled
1068 * by a software over-ride. Since there really isn't a way to
1069 * advertise that we are capable of Rx Pause ONLY, we will
1070 * advertise that we support both symmetric and asymmetric Rx
1071 * PAUSE. Later, we will disable the adapter's ability to send
1074 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1076 case e1000_fc_tx_pause:
1077 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1078 * by a software over-ride.
1080 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1083 /* Flow control (both Rx and Tx) is enabled by a software
1086 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1089 DEBUGOUT("Flow control param set incorrectly\n");
1090 return -E1000_ERR_CONFIG;
1094 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1097 return E1000_SUCCESS;
1101 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1102 * @hw: pointer to the HW structure
1104 * Polls for link up by reading the status register, if link fails to come
1105 * up with auto-negotiation, then the link is forced if a signal is detected.
1107 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1109 struct e1000_mac_info *mac = &hw->mac;
1113 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1115 /* If we have a signal (the cable is plugged in, or assumed TRUE for
1116 * serdes media) then poll for a "Link-Up" indication in the Device
1117 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1118 * seconds (Auto-negotiation should complete in less than 500
1119 * milliseconds even if the other end is doing it in SW).
1121 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1123 status = E1000_READ_REG(hw, E1000_STATUS);
1124 if (status & E1000_STATUS_LU)
1127 if (i == FIBER_LINK_UP_LIMIT) {
1128 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1129 mac->autoneg_failed = TRUE;
1130 /* AutoNeg failed to achieve a link, so we'll call
1131 * mac->check_for_link. This routine will force the
1132 * link up if we detect a signal. This will allow us to
1133 * communicate with non-autonegotiating link partners.
1135 ret_val = mac->ops.check_for_link(hw);
1137 DEBUGOUT("Error while checking for link\n");
1140 mac->autoneg_failed = FALSE;
1142 mac->autoneg_failed = FALSE;
1143 DEBUGOUT("Valid Link Found\n");
1146 return E1000_SUCCESS;
1150 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1151 * @hw: pointer to the HW structure
1153 * Configures collision distance and flow control for fiber and serdes
1154 * links. Upon successful setup, poll for link.
1156 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1161 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1163 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1165 /* Take the link out of reset */
1166 ctrl &= ~E1000_CTRL_LRST;
1168 hw->mac.ops.config_collision_dist(hw);
1170 ret_val = e1000_commit_fc_settings_generic(hw);
1174 /* Since auto-negotiation is enabled, take the link out of reset (the
1175 * link will be in reset, because we previously reset the chip). This
1176 * will restart auto-negotiation. If auto-negotiation is successful
1177 * then the link-up status bit will be set and the flow control enable
1178 * bits (RFCE and TFCE) will be set according to their negotiated value.
1180 DEBUGOUT("Auto-negotiation enabled\n");
1182 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1183 E1000_WRITE_FLUSH(hw);
1186 /* For these adapters, the SW definable pin 1 is set when the optics
1187 * detect a signal. If we have a signal, then poll for a "Link-Up"
1190 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1191 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1192 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1194 DEBUGOUT("No signal detected\n");
1201 * e1000_config_collision_dist_generic - Configure collision distance
1202 * @hw: pointer to the HW structure
1204 * Configures the collision distance to the default value and is used
1205 * during link setup.
1207 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1211 DEBUGFUNC("e1000_config_collision_dist_generic");
1213 tctl = E1000_READ_REG(hw, E1000_TCTL);
1215 tctl &= ~E1000_TCTL_COLD;
1216 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1218 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1219 E1000_WRITE_FLUSH(hw);
1223 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1224 * @hw: pointer to the HW structure
1226 * Sets the flow control high/low threshold (watermark) registers. If
1227 * flow control XON frame transmission is enabled, then set XON frame
1228 * transmission as well.
1230 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1232 u32 fcrtl = 0, fcrth = 0;
1234 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1236 /* Set the flow control receive threshold registers. Normally,
1237 * these registers will be set to a default threshold that may be
1238 * adjusted later by the driver's runtime code. However, if the
1239 * ability to transmit pause frames is not enabled, then these
1240 * registers will be set to 0.
1242 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1243 /* We need to set up the Receive Threshold high and low water
1244 * marks as well as (optionally) enabling the transmission of
1247 fcrtl = hw->fc.low_water;
1248 if (hw->fc.send_xon)
1249 fcrtl |= E1000_FCRTL_XONE;
1251 fcrth = hw->fc.high_water;
1253 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1254 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1256 return E1000_SUCCESS;
1260 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1261 * @hw: pointer to the HW structure
1263 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1264 * device control register to reflect the adapter settings. TFCE and RFCE
1265 * need to be explicitly set by software when a copper PHY is used because
1266 * autonegotiation is managed by the PHY rather than the MAC. Software must
1267 * also configure these bits when link is forced on a fiber connection.
1269 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1273 DEBUGFUNC("e1000_force_mac_fc_generic");
1275 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1277 /* Because we didn't get link via the internal auto-negotiation
1278 * mechanism (we either forced link or we got link via PHY
1279 * auto-neg), we have to manually enable/disable transmit an
1280 * receive flow control.
1282 * The "Case" statement below enables/disable flow control
1283 * according to the "hw->fc.current_mode" parameter.
1285 * The possible values of the "fc" parameter are:
1286 * 0: Flow control is completely disabled
1287 * 1: Rx flow control is enabled (we can receive pause
1288 * frames but not send pause frames).
1289 * 2: Tx flow control is enabled (we can send pause frames
1290 * frames but we do not receive pause frames).
1291 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1292 * other: No other values should be possible at this point.
1294 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1296 switch (hw->fc.current_mode) {
1298 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1300 case e1000_fc_rx_pause:
1301 ctrl &= (~E1000_CTRL_TFCE);
1302 ctrl |= E1000_CTRL_RFCE;
1304 case e1000_fc_tx_pause:
1305 ctrl &= (~E1000_CTRL_RFCE);
1306 ctrl |= E1000_CTRL_TFCE;
1309 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1312 DEBUGOUT("Flow control param set incorrectly\n");
1313 return -E1000_ERR_CONFIG;
1316 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1318 return E1000_SUCCESS;
1322 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1323 * @hw: pointer to the HW structure
1325 * Checks the status of auto-negotiation after link up to ensure that the
1326 * speed and duplex were not forced. If the link needed to be forced, then
1327 * flow control needs to be forced also. If auto-negotiation is enabled
1328 * and did not fail, then we configure flow control based on our link
1331 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1333 struct e1000_mac_info *mac = &hw->mac;
1334 s32 ret_val = E1000_SUCCESS;
1335 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1336 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1339 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1341 /* Check for the case where we have fiber media and auto-neg failed
1342 * so we had to force link. In this case, we need to force the
1343 * configuration of the MAC to match the "fc" parameter.
1345 if (mac->autoneg_failed) {
1346 if (hw->phy.media_type == e1000_media_type_fiber ||
1347 hw->phy.media_type == e1000_media_type_internal_serdes)
1348 ret_val = e1000_force_mac_fc_generic(hw);
1350 if (hw->phy.media_type == e1000_media_type_copper)
1351 ret_val = e1000_force_mac_fc_generic(hw);
1355 DEBUGOUT("Error forcing flow control settings\n");
1359 /* Check for the case where we have copper media and auto-neg is
1360 * enabled. In this case, we need to check and see if Auto-Neg
1361 * has completed, and if so, how the PHY and link partner has
1362 * flow control configured.
1364 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1365 /* Read the MII Status Register and check to see if AutoNeg
1366 * has completed. We read this twice because this reg has
1367 * some "sticky" (latched) bits.
1369 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1372 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1376 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1377 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1381 /* The AutoNeg process has completed, so we now need to
1382 * read both the Auto Negotiation Advertisement
1383 * Register (Address 4) and the Auto_Negotiation Base
1384 * Page Ability Register (Address 5) to determine how
1385 * flow control was negotiated.
1387 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1391 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1392 &mii_nway_lp_ability_reg);
1396 /* Two bits in the Auto Negotiation Advertisement Register
1397 * (Address 4) and two bits in the Auto Negotiation Base
1398 * Page Ability Register (Address 5) determine flow control
1399 * for both the PHY and the link partner. The following
1400 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1401 * 1999, describes these PAUSE resolution bits and how flow
1402 * control is determined based upon these settings.
1403 * NOTE: DC = Don't Care
1405 * LOCAL DEVICE | LINK PARTNER
1406 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1407 *-------|---------|-------|---------|--------------------
1408 * 0 | 0 | DC | DC | e1000_fc_none
1409 * 0 | 1 | 0 | DC | e1000_fc_none
1410 * 0 | 1 | 1 | 0 | e1000_fc_none
1411 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1412 * 1 | 0 | 0 | DC | e1000_fc_none
1413 * 1 | DC | 1 | DC | e1000_fc_full
1414 * 1 | 1 | 0 | 0 | e1000_fc_none
1415 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1417 * Are both PAUSE bits set to 1? If so, this implies
1418 * Symmetric Flow Control is enabled at both ends. The
1419 * ASM_DIR bits are irrelevant per the spec.
1421 * For Symmetric Flow Control:
1423 * LOCAL DEVICE | LINK PARTNER
1424 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1425 *-------|---------|-------|---------|--------------------
1426 * 1 | DC | 1 | DC | E1000_fc_full
1429 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1430 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1431 /* Now we need to check if the user selected Rx ONLY
1432 * of pause frames. In this case, we had to advertise
1433 * FULL flow control because we could not advertise Rx
1434 * ONLY. Hence, we must now check to see if we need to
1435 * turn OFF the TRANSMISSION of PAUSE frames.
1437 if (hw->fc.requested_mode == e1000_fc_full) {
1438 hw->fc.current_mode = e1000_fc_full;
1439 DEBUGOUT("Flow Control = FULL.\n");
1441 hw->fc.current_mode = e1000_fc_rx_pause;
1442 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1445 /* For receiving PAUSE frames ONLY.
1447 * LOCAL DEVICE | LINK PARTNER
1448 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1449 *-------|---------|-------|---------|--------------------
1450 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1452 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1453 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1454 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1455 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1456 hw->fc.current_mode = e1000_fc_tx_pause;
1457 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1459 /* For transmitting PAUSE frames ONLY.
1461 * LOCAL DEVICE | LINK PARTNER
1462 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1463 *-------|---------|-------|---------|--------------------
1464 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1466 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1467 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1468 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1469 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1470 hw->fc.current_mode = e1000_fc_rx_pause;
1471 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1473 /* Per the IEEE spec, at this point flow control
1474 * should be disabled.
1476 hw->fc.current_mode = e1000_fc_none;
1477 DEBUGOUT("Flow Control = NONE.\n");
1480 /* Now we need to do one last check... If we auto-
1481 * negotiated to HALF DUPLEX, flow control should not be
1482 * enabled per IEEE 802.3 spec.
1484 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1486 DEBUGOUT("Error getting link speed and duplex\n");
1490 if (duplex == HALF_DUPLEX)
1491 hw->fc.current_mode = e1000_fc_none;
1493 /* Now we call a subroutine to actually force the MAC
1494 * controller to use the correct flow control settings.
1496 ret_val = e1000_force_mac_fc_generic(hw);
1498 DEBUGOUT("Error forcing flow control settings\n");
1503 /* Check for the case where we have SerDes media and auto-neg is
1504 * enabled. In this case, we need to check and see if Auto-Neg
1505 * has completed, and if so, how the PHY and link partner has
1506 * flow control configured.
1508 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1510 /* Read the PCS_LSTS and check to see if AutoNeg
1513 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1515 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1516 DEBUGOUT("PCS Auto Neg has not completed.\n");
1520 /* The AutoNeg process has completed, so we now need to
1521 * read both the Auto Negotiation Advertisement
1522 * Register (PCS_ANADV) and the Auto_Negotiation Base
1523 * Page Ability Register (PCS_LPAB) to determine how
1524 * flow control was negotiated.
1526 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1527 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1529 /* Two bits in the Auto Negotiation Advertisement Register
1530 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1531 * Page Ability Register (PCS_LPAB) determine flow control
1532 * for both the PHY and the link partner. The following
1533 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1534 * 1999, describes these PAUSE resolution bits and how flow
1535 * control is determined based upon these settings.
1536 * NOTE: DC = Don't Care
1538 * LOCAL DEVICE | LINK PARTNER
1539 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1540 *-------|---------|-------|---------|--------------------
1541 * 0 | 0 | DC | DC | e1000_fc_none
1542 * 0 | 1 | 0 | DC | e1000_fc_none
1543 * 0 | 1 | 1 | 0 | e1000_fc_none
1544 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1545 * 1 | 0 | 0 | DC | e1000_fc_none
1546 * 1 | DC | 1 | DC | e1000_fc_full
1547 * 1 | 1 | 0 | 0 | e1000_fc_none
1548 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1550 * Are both PAUSE bits set to 1? If so, this implies
1551 * Symmetric Flow Control is enabled at both ends. The
1552 * ASM_DIR bits are irrelevant per the spec.
1554 * For Symmetric Flow Control:
1556 * LOCAL DEVICE | LINK PARTNER
1557 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1558 *-------|---------|-------|---------|--------------------
1559 * 1 | DC | 1 | DC | e1000_fc_full
1562 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1563 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1564 /* Now we need to check if the user selected Rx ONLY
1565 * of pause frames. In this case, we had to advertise
1566 * FULL flow control because we could not advertise Rx
1567 * ONLY. Hence, we must now check to see if we need to
1568 * turn OFF the TRANSMISSION of PAUSE frames.
1570 if (hw->fc.requested_mode == e1000_fc_full) {
1571 hw->fc.current_mode = e1000_fc_full;
1572 DEBUGOUT("Flow Control = FULL.\n");
1574 hw->fc.current_mode = e1000_fc_rx_pause;
1575 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1578 /* For receiving PAUSE frames ONLY.
1580 * LOCAL DEVICE | LINK PARTNER
1581 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1582 *-------|---------|-------|---------|--------------------
1583 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1585 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1586 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1587 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1588 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1589 hw->fc.current_mode = e1000_fc_tx_pause;
1590 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1592 /* For transmitting PAUSE frames ONLY.
1594 * LOCAL DEVICE | LINK PARTNER
1595 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1596 *-------|---------|-------|---------|--------------------
1597 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1599 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1600 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1601 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1602 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1603 hw->fc.current_mode = e1000_fc_rx_pause;
1604 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1606 /* Per the IEEE spec, at this point flow control
1607 * should be disabled.
1609 hw->fc.current_mode = e1000_fc_none;
1610 DEBUGOUT("Flow Control = NONE.\n");
1613 /* Now we call a subroutine to actually force the MAC
1614 * controller to use the correct flow control settings.
1616 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1617 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1618 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1620 ret_val = e1000_force_mac_fc_generic(hw);
1622 DEBUGOUT("Error forcing flow control settings\n");
1627 return E1000_SUCCESS;
1631 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1632 * @hw: pointer to the HW structure
1633 * @speed: stores the current speed
1634 * @duplex: stores the current duplex
1636 * Read the status register for the current speed/duplex and store the current
1637 * speed and duplex for copper connections.
1639 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1644 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1646 status = E1000_READ_REG(hw, E1000_STATUS);
1647 if (status & E1000_STATUS_SPEED_1000) {
1648 *speed = SPEED_1000;
1649 DEBUGOUT("1000 Mbs, ");
1650 } else if (status & E1000_STATUS_SPEED_100) {
1652 DEBUGOUT("100 Mbs, ");
1655 DEBUGOUT("10 Mbs, ");
1658 if (status & E1000_STATUS_FD) {
1659 *duplex = FULL_DUPLEX;
1660 DEBUGOUT("Full Duplex\n");
1662 *duplex = HALF_DUPLEX;
1663 DEBUGOUT("Half Duplex\n");
1666 return E1000_SUCCESS;
1670 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1671 * @hw: pointer to the HW structure
1672 * @speed: stores the current speed
1673 * @duplex: stores the current duplex
1675 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1676 * for fiber/serdes links.
1678 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1679 u16 *speed, u16 *duplex)
1681 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1683 *speed = SPEED_1000;
1684 *duplex = FULL_DUPLEX;
1686 return E1000_SUCCESS;
1690 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1691 * @hw: pointer to the HW structure
1693 * Acquire the HW semaphore to access the PHY or NVM
1695 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1698 s32 timeout = hw->nvm.word_size + 1;
1701 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1703 /* Get the SW semaphore */
1704 while (i < timeout) {
1705 swsm = E1000_READ_REG(hw, E1000_SWSM);
1706 if (!(swsm & E1000_SWSM_SMBI))
1714 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1715 return -E1000_ERR_NVM;
1718 /* Get the FW semaphore. */
1719 for (i = 0; i < timeout; i++) {
1720 swsm = E1000_READ_REG(hw, E1000_SWSM);
1721 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1723 /* Semaphore acquired if bit latched */
1724 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1731 /* Release semaphores */
1732 e1000_put_hw_semaphore_generic(hw);
1733 DEBUGOUT("Driver can't access the NVM\n");
1734 return -E1000_ERR_NVM;
1737 return E1000_SUCCESS;
1741 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1742 * @hw: pointer to the HW structure
1744 * Release hardware semaphore used to access the PHY or NVM
1746 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1750 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1752 swsm = E1000_READ_REG(hw, E1000_SWSM);
1754 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1756 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1760 * e1000_get_auto_rd_done_generic - Check for auto read completion
1761 * @hw: pointer to the HW structure
1763 * Check EEPROM for Auto Read done bit.
1765 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1769 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1771 while (i < AUTO_READ_DONE_TIMEOUT) {
1772 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1778 if (i == AUTO_READ_DONE_TIMEOUT) {
1779 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1780 return -E1000_ERR_RESET;
1783 return E1000_SUCCESS;
1787 * e1000_valid_led_default_generic - Verify a valid default LED config
1788 * @hw: pointer to the HW structure
1789 * @data: pointer to the NVM (EEPROM)
1791 * Read the EEPROM for the current default LED configuration. If the
1792 * LED configuration is not valid, set to a valid LED configuration.
1794 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1798 DEBUGFUNC("e1000_valid_led_default_generic");
1800 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1802 DEBUGOUT("NVM Read Error\n");
1806 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1807 *data = ID_LED_DEFAULT;
1809 return E1000_SUCCESS;
1813 * e1000_id_led_init_generic -
1814 * @hw: pointer to the HW structure
1817 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1819 struct e1000_mac_info *mac = &hw->mac;
1821 const u32 ledctl_mask = 0x000000FF;
1822 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1823 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1825 const u16 led_mask = 0x0F;
1827 DEBUGFUNC("e1000_id_led_init_generic");
1829 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1833 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1834 mac->ledctl_mode1 = mac->ledctl_default;
1835 mac->ledctl_mode2 = mac->ledctl_default;
1837 for (i = 0; i < 4; i++) {
1838 temp = (data >> (i << 2)) & led_mask;
1840 case ID_LED_ON1_DEF2:
1841 case ID_LED_ON1_ON2:
1842 case ID_LED_ON1_OFF2:
1843 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1844 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1846 case ID_LED_OFF1_DEF2:
1847 case ID_LED_OFF1_ON2:
1848 case ID_LED_OFF1_OFF2:
1849 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1850 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1857 case ID_LED_DEF1_ON2:
1858 case ID_LED_ON1_ON2:
1859 case ID_LED_OFF1_ON2:
1860 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1861 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1863 case ID_LED_DEF1_OFF2:
1864 case ID_LED_ON1_OFF2:
1865 case ID_LED_OFF1_OFF2:
1866 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1867 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1875 return E1000_SUCCESS;
1879 * e1000_setup_led_generic - Configures SW controllable LED
1880 * @hw: pointer to the HW structure
1882 * This prepares the SW controllable LED for use and saves the current state
1883 * of the LED so it can be later restored.
1885 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1889 DEBUGFUNC("e1000_setup_led_generic");
1891 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1892 return -E1000_ERR_CONFIG;
1894 if (hw->phy.media_type == e1000_media_type_fiber) {
1895 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1896 hw->mac.ledctl_default = ledctl;
1898 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1899 E1000_LEDCTL_LED0_MODE_MASK);
1900 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1901 E1000_LEDCTL_LED0_MODE_SHIFT);
1902 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1903 } else if (hw->phy.media_type == e1000_media_type_copper) {
1904 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1907 return E1000_SUCCESS;
1911 * e1000_cleanup_led_generic - Set LED config to default operation
1912 * @hw: pointer to the HW structure
1914 * Remove the current LED configuration and set the LED configuration
1915 * to the default value, saved from the EEPROM.
1917 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1919 DEBUGFUNC("e1000_cleanup_led_generic");
1921 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1922 return E1000_SUCCESS;
1926 * e1000_blink_led_generic - Blink LED
1927 * @hw: pointer to the HW structure
1929 * Blink the LEDs which are set to be on.
1931 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1933 u32 ledctl_blink = 0;
1936 DEBUGFUNC("e1000_blink_led_generic");
1938 if (hw->phy.media_type == e1000_media_type_fiber) {
1939 /* always blink LED0 for PCI-E fiber */
1940 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1941 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1943 /* Set the blink bit for each LED that's "on" (0x0E)
1944 * (or "off" if inverted) in ledctl_mode2. The blink
1945 * logic in hardware only works when mode is set to "on"
1946 * so it must be changed accordingly when the mode is
1947 * "off" and inverted.
1949 ledctl_blink = hw->mac.ledctl_mode2;
1950 for (i = 0; i < 32; i += 8) {
1951 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1952 E1000_LEDCTL_LED0_MODE_MASK;
1953 u32 led_default = hw->mac.ledctl_default >> i;
1955 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1956 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1957 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1958 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1960 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1961 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1962 E1000_LEDCTL_MODE_LED_ON) << i;
1967 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1969 return E1000_SUCCESS;
1973 * e1000_led_on_generic - Turn LED on
1974 * @hw: pointer to the HW structure
1978 s32 e1000_led_on_generic(struct e1000_hw *hw)
1982 DEBUGFUNC("e1000_led_on_generic");
1984 switch (hw->phy.media_type) {
1985 case e1000_media_type_fiber:
1986 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1987 ctrl &= ~E1000_CTRL_SWDPIN0;
1988 ctrl |= E1000_CTRL_SWDPIO0;
1989 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1991 case e1000_media_type_copper:
1992 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1998 return E1000_SUCCESS;
2002 * e1000_led_off_generic - Turn LED off
2003 * @hw: pointer to the HW structure
2007 s32 e1000_led_off_generic(struct e1000_hw *hw)
2011 DEBUGFUNC("e1000_led_off_generic");
2013 switch (hw->phy.media_type) {
2014 case e1000_media_type_fiber:
2015 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2016 ctrl |= E1000_CTRL_SWDPIN0;
2017 ctrl |= E1000_CTRL_SWDPIO0;
2018 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2020 case e1000_media_type_copper:
2021 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2027 return E1000_SUCCESS;
2031 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2032 * @hw: pointer to the HW structure
2033 * @no_snoop: bitmap of snoop events
2035 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2037 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2041 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2043 if (hw->bus.type != e1000_bus_type_pci_express)
2047 gcr = E1000_READ_REG(hw, E1000_GCR);
2048 gcr &= ~(PCIE_NO_SNOOP_ALL);
2050 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2055 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2056 * @hw: pointer to the HW structure
2058 * Returns E1000_SUCCESS if successful, else returns -10
2059 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2060 * the master requests to be disabled.
2062 * Disables PCI-Express master access and verifies there are no pending
2065 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2068 s32 timeout = MASTER_DISABLE_TIMEOUT;
2070 DEBUGFUNC("e1000_disable_pcie_master_generic");
2072 if (hw->bus.type != e1000_bus_type_pci_express)
2073 return E1000_SUCCESS;
2075 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2076 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2080 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2081 E1000_STATUS_GIO_MASTER_ENABLE))
2088 DEBUGOUT("Master requests are pending.\n");
2089 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2092 return E1000_SUCCESS;
2096 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2097 * @hw: pointer to the HW structure
2099 * Reset the Adaptive Interframe Spacing throttle to default values.
2101 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2103 struct e1000_mac_info *mac = &hw->mac;
2105 DEBUGFUNC("e1000_reset_adaptive_generic");
2107 if (!mac->adaptive_ifs) {
2108 DEBUGOUT("Not in Adaptive IFS mode!\n");
2112 mac->current_ifs_val = 0;
2113 mac->ifs_min_val = IFS_MIN;
2114 mac->ifs_max_val = IFS_MAX;
2115 mac->ifs_step_size = IFS_STEP;
2116 mac->ifs_ratio = IFS_RATIO;
2118 mac->in_ifs_mode = FALSE;
2119 E1000_WRITE_REG(hw, E1000_AIT, 0);
2123 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2124 * @hw: pointer to the HW structure
2126 * Update the Adaptive Interframe Spacing Throttle value based on the
2127 * time between transmitted packets and time between collisions.
2129 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2131 struct e1000_mac_info *mac = &hw->mac;
2133 DEBUGFUNC("e1000_update_adaptive_generic");
2135 if (!mac->adaptive_ifs) {
2136 DEBUGOUT("Not in Adaptive IFS mode!\n");
2140 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2141 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2142 mac->in_ifs_mode = TRUE;
2143 if (mac->current_ifs_val < mac->ifs_max_val) {
2144 if (!mac->current_ifs_val)
2145 mac->current_ifs_val = mac->ifs_min_val;
2147 mac->current_ifs_val +=
2149 E1000_WRITE_REG(hw, E1000_AIT,
2150 mac->current_ifs_val);
2154 if (mac->in_ifs_mode &&
2155 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2156 mac->current_ifs_val = 0;
2157 mac->in_ifs_mode = FALSE;
2158 E1000_WRITE_REG(hw, E1000_AIT, 0);
2164 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2165 * @hw: pointer to the HW structure
2167 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2168 * set, which is forced to MDI mode only.
2170 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2172 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2174 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2175 DEBUGOUT("Invalid MDI setting detected\n");
2177 return -E1000_ERR_CONFIG;
2180 return E1000_SUCCESS;
2184 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2185 * @hw: pointer to the HW structure
2187 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2190 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw)
2192 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2194 return E1000_SUCCESS;
2198 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2199 * @hw: pointer to the HW structure
2200 * @reg: 32bit register offset such as E1000_SCTL
2201 * @offset: register offset to write to
2202 * @data: data to write at register offset
2204 * Writes an address/data control type register. There are several of these
2205 * and they all have the format address << 8 | data and bit 31 is polled for
2208 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2209 u32 offset, u8 data)
2211 u32 i, regvalue = 0;
2213 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2215 /* Set up the address and data */
2216 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2217 E1000_WRITE_REG(hw, reg, regvalue);
2219 /* Poll the ready bit to see if the MDI read completed */
2220 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2222 regvalue = E1000_READ_REG(hw, reg);
2223 if (regvalue & E1000_GEN_CTL_READY)
2226 if (!(regvalue & E1000_GEN_CTL_READY)) {
2227 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2228 return -E1000_ERR_PHY;
2231 return E1000_SUCCESS;