2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
72 #include <machine/resource.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <dev/fxp/if_fxpreg.h>
81 #include <dev/fxp/if_fxpvar.h>
82 #include <dev/fxp/rcvbundl.h>
84 MODULE_DEPEND(fxp, pci, 1, 1, 1);
85 MODULE_DEPEND(fxp, ether, 1, 1, 1);
86 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
87 #include "miibus_if.h"
90 * NOTE! On !x86 we typically have an alignment constraint. The
91 * card DMAs the packet immediately following the RFA. However,
92 * the first thing in the packet is a 14-byte Ethernet header.
93 * This means that the packet is misaligned. To compensate,
94 * we actually offset the RFA 2 bytes into the cluster. This
95 * alignes the packet after the Ethernet header at a 32-bit
96 * boundary. HOWEVER! This means that the RFA is misaligned!
98 #define RFA_ALIGNMENT_FUDGE 2
101 * Set initial transmit threshold at 64 (512 bytes). This is
102 * increased by 64 (512 bytes) at a time, to maximum of 192
103 * (1536 bytes), if an underrun occurs.
105 static int tx_threshold = 64;
108 * The configuration byte map has several undefined fields which
109 * must be one or must be zero. Set up a template for these bits.
110 * The actual configuration is performed in fxp_init_body.
112 * See struct fxp_cb_config for the bit definitions.
114 static const u_char fxp_cb_config_template[] = {
115 0x0, 0x0, /* cb_status */
116 0x0, 0x0, /* cb_command */
117 0x0, 0x0, 0x0, 0x0, /* link_addr */
153 * Claim various Intel PCI device identifiers for this driver. The
154 * sub-vendor and sub-device field are extensively used to identify
155 * particular variants, but we don't currently differentiate between
158 static const struct fxp_ident fxp_ident_table[] = {
159 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
160 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
161 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
162 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
163 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
164 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
170 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
171 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
172 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
175 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
176 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
177 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
178 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
179 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
180 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
181 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
182 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
183 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
184 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
185 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
186 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
187 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
188 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
189 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
191 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
192 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
193 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
194 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
196 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
197 { 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
198 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
199 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
200 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
201 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
202 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
203 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
207 #ifdef FXP_IP_CSUM_WAR
208 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
210 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
213 static int fxp_probe(device_t dev);
214 static int fxp_attach(device_t dev);
215 static int fxp_detach(device_t dev);
216 static int fxp_shutdown(device_t dev);
217 static int fxp_suspend(device_t dev);
218 static int fxp_resume(device_t dev);
220 static const struct fxp_ident *fxp_find_ident(device_t dev);
221 static void fxp_intr(void *xsc);
222 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
223 struct mbuf *m, uint16_t status, int pos);
224 static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
225 uint8_t statack, int count);
226 static void fxp_init(void *xsc);
227 static void fxp_init_body(struct fxp_softc *sc, int);
228 static void fxp_tick(void *xsc);
229 static void fxp_start(struct ifnet *ifp);
230 static void fxp_start_body(struct ifnet *ifp);
231 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
232 static void fxp_txeof(struct fxp_softc *sc);
233 static void fxp_stop(struct fxp_softc *sc);
234 static void fxp_release(struct fxp_softc *sc);
235 static int fxp_ioctl(struct ifnet *ifp, u_long command,
237 static void fxp_watchdog(struct fxp_softc *sc);
238 static void fxp_add_rfabuf(struct fxp_softc *sc,
240 static void fxp_discard_rfabuf(struct fxp_softc *sc,
242 static int fxp_new_rfabuf(struct fxp_softc *sc,
244 static int fxp_mc_addrs(struct fxp_softc *sc);
245 static void fxp_mc_setup(struct fxp_softc *sc);
246 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
248 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
250 static void fxp_autosize_eeprom(struct fxp_softc *sc);
251 static void fxp_load_eeprom(struct fxp_softc *sc);
252 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
253 int offset, int words);
254 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
255 int offset, int words);
256 static int fxp_ifmedia_upd(struct ifnet *ifp);
257 static void fxp_ifmedia_sts(struct ifnet *ifp,
258 struct ifmediareq *ifmr);
259 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
260 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
261 struct ifmediareq *ifmr);
262 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
263 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
265 static void fxp_miibus_statchg(device_t dev);
266 static void fxp_load_ucode(struct fxp_softc *sc);
267 static void fxp_update_stats(struct fxp_softc *sc);
268 static void fxp_sysctl_node(struct fxp_softc *sc);
269 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
271 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
272 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
273 static void fxp_scb_wait(struct fxp_softc *sc);
274 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
275 static void fxp_dma_wait(struct fxp_softc *sc,
276 volatile uint16_t *status, bus_dma_tag_t dmat,
279 static device_method_t fxp_methods[] = {
280 /* Device interface */
281 DEVMETHOD(device_probe, fxp_probe),
282 DEVMETHOD(device_attach, fxp_attach),
283 DEVMETHOD(device_detach, fxp_detach),
284 DEVMETHOD(device_shutdown, fxp_shutdown),
285 DEVMETHOD(device_suspend, fxp_suspend),
286 DEVMETHOD(device_resume, fxp_resume),
289 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
290 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
291 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
296 static driver_t fxp_driver = {
299 sizeof(struct fxp_softc),
302 static devclass_t fxp_devclass;
304 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL,
306 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
308 static struct resource_spec fxp_res_spec_mem[] = {
309 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
310 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
314 static struct resource_spec fxp_res_spec_io[] = {
315 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
316 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
321 * Wait for the previous command to be accepted (but not necessarily
325 fxp_scb_wait(struct fxp_softc *sc)
333 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
336 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
337 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
338 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
339 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
340 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
341 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
346 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
349 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
350 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
353 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
357 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
358 bus_dma_tag_t dmat, bus_dmamap_t map)
362 for (i = 10000; i > 0; i--) {
364 bus_dmamap_sync(dmat, map,
365 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
366 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
370 device_printf(sc->dev, "DMA timeout\n");
373 static const struct fxp_ident *
374 fxp_find_ident(device_t dev)
378 const struct fxp_ident *ident;
380 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
381 devid = pci_get_device(dev);
382 revid = pci_get_revid(dev);
383 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
384 if (ident->devid == devid &&
385 (ident->revid == revid || ident->revid == -1)) {
394 * Return identification string if this device is ours.
397 fxp_probe(device_t dev)
399 const struct fxp_ident *ident;
401 ident = fxp_find_ident(dev);
403 device_set_desc(dev, ident->name);
404 return (BUS_PROBE_DEFAULT);
410 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
417 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
419 *addr = segs->ds_addr;
423 fxp_attach(device_t dev)
425 struct fxp_softc *sc;
426 struct fxp_cb_tx *tcbp;
432 u_char eaddr[ETHER_ADDR_LEN];
433 int error, flags, i, pmc, prefer_iomap;
436 sc = device_get_softc(dev);
438 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
440 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
441 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
442 fxp_serial_ifmedia_sts);
444 ifp = sc->ifp = if_alloc(IFT_ETHER);
446 device_printf(dev, "can not if_alloc()\n");
452 * Enable bus mastering.
454 pci_enable_busmaster(dev);
455 val = pci_read_config(dev, PCIR_COMMAND, 2);
458 * Figure out which we should try first - memory mapping or i/o mapping?
459 * We default to memory mapping. Then we accept an override from the
460 * command line. Then we check to see which one is enabled.
463 resource_int_value(device_get_name(dev), device_get_unit(dev),
464 "prefer_iomap", &prefer_iomap);
466 sc->fxp_spec = fxp_res_spec_io;
468 sc->fxp_spec = fxp_res_spec_mem;
470 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
472 if (sc->fxp_spec == fxp_res_spec_mem)
473 sc->fxp_spec = fxp_res_spec_io;
475 sc->fxp_spec = fxp_res_spec_mem;
476 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
479 device_printf(dev, "could not allocate resources\n");
485 device_printf(dev, "using %s space register mapping\n",
486 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
490 * Put CU/RU idle state and prepare full reset.
492 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
494 /* Full reset and disable interrupts. */
495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
497 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
500 * Find out how large of an SEEPROM we have.
502 fxp_autosize_eeprom(sc);
506 * Find out the chip revision; lump all 82557 revs together.
508 sc->ident = fxp_find_ident(dev);
509 if (sc->ident->ich > 0) {
510 /* Assume ICH controllers are 82559. */
511 sc->revision = FXP_REV_82559_A0;
513 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
514 if ((data >> 8) == 1)
515 sc->revision = FXP_REV_82557;
517 sc->revision = pci_get_revid(dev);
521 * Check availability of WOL. 82559ER does not support WOL.
523 if (sc->revision >= FXP_REV_82558_A4 &&
524 sc->revision != FXP_REV_82559S_A) {
525 data = sc->eeprom[FXP_EEPROM_MAP_ID];
526 if ((data & 0x20) != 0 &&
527 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
528 sc->flags |= FXP_FLAG_WOLCAP;
531 if (sc->revision == FXP_REV_82550_C) {
533 * 82550C with server extension requires microcode to
534 * receive fragmented UDP datagrams. However if the
535 * microcode is used for client-only featured 82550C
536 * it locks up controller.
538 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
539 if ((data & 0x0400) == 0)
540 sc->flags |= FXP_FLAG_NO_UCODE;
543 /* Receiver lock-up workaround detection. */
544 if (sc->revision < FXP_REV_82558_A4) {
545 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
546 if ((data & 0x03) != 0x03) {
547 sc->flags |= FXP_FLAG_RXBUG;
548 device_printf(dev, "Enabling Rx lock-up workaround\n");
553 * Determine whether we must use the 503 serial interface.
555 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
556 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
557 && (data & FXP_PHY_SERIAL_ONLY))
558 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
562 * Enable workarounds for certain chip revision deficiencies.
564 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
565 * some systems based a normal 82559 design, have a defect where
566 * the chip can cause a PCI protocol violation if it receives
567 * a CU_RESUME command when it is entering the IDLE state. The
568 * workaround is to disable Dynamic Standby Mode, so the chip never
569 * deasserts CLKRUN#, and always remains in an active state.
571 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
573 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
574 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
575 data = sc->eeprom[FXP_EEPROM_MAP_ID];
576 if (data & 0x02) { /* STB enable */
581 "Disabling dynamic standby mode in EEPROM\n");
583 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
584 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
585 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
587 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
588 cksum += sc->eeprom[i];
589 i = (1 << sc->eeprom_size) - 1;
590 cksum = 0xBABA - cksum;
591 fxp_write_eeprom(sc, &cksum, i, 1);
593 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
594 i, sc->eeprom[i], cksum);
595 sc->eeprom[i] = cksum;
597 * If the user elects to continue, try the software
598 * workaround, as it is better than nothing.
600 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
605 * If we are not a 82557 chip, we can enable extended features.
607 if (sc->revision != FXP_REV_82557) {
609 * If MWI is enabled in the PCI configuration, and there
610 * is a valid cacheline size (8 or 16 dwords), then tell
611 * the board to turn on MWI.
613 if (val & PCIM_CMD_MWRICEN &&
614 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
615 sc->flags |= FXP_FLAG_MWI_ENABLE;
617 /* turn on the extended TxCB feature */
618 sc->flags |= FXP_FLAG_EXT_TXCB;
620 /* enable reception of long frames for VLAN */
621 sc->flags |= FXP_FLAG_LONG_PKT_EN;
623 /* a hack to get long VLAN frames on a 82557 */
624 sc->flags |= FXP_FLAG_SAVE_BAD;
627 /* For 82559 or later chips, Rx checksum offload is supported. */
628 if (sc->revision >= FXP_REV_82559_A0) {
629 /* 82559ER does not support Rx checksum offloading. */
630 if (sc->ident->devid != 0x1209)
631 sc->flags |= FXP_FLAG_82559_RXCSUM;
634 * Enable use of extended RFDs and TCBs for 82550
635 * and later chips. Note: we need extended TXCB support
636 * too, but that's already enabled by the code above.
637 * Be careful to do this only on the right devices.
639 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
640 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
641 || sc->revision == FXP_REV_82551_10) {
642 sc->rfa_size = sizeof (struct fxp_rfa);
643 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
644 sc->flags |= FXP_FLAG_EXT_RFA;
645 /* Use extended RFA instead of 82559 checksum mode. */
646 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
648 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
649 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
653 * Allocate DMA tags and DMA safe memory.
655 sc->maxtxseg = FXP_NTXSEG;
656 sc->maxsegsize = MCLBYTES;
657 if (sc->flags & FXP_FLAG_EXT_RFA) {
659 sc->maxsegsize = FXP_TSO_SEGSIZE;
661 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
662 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
663 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
664 sc->maxtxseg, sc->maxsegsize, 0,
665 busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
667 device_printf(dev, "could not create TX DMA tag\n");
671 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
672 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
673 MCLBYTES, 1, MCLBYTES, 0,
674 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
676 device_printf(dev, "could not create RX DMA tag\n");
680 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
681 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
682 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
683 busdma_lock_mutex, &Giant, &sc->fxp_stag);
685 device_printf(dev, "could not create stats DMA tag\n");
689 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
690 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
692 device_printf(dev, "could not allocate stats DMA memory\n");
695 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
696 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
699 device_printf(dev, "could not load the stats DMA buffer\n");
703 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
704 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
705 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
706 busdma_lock_mutex, &Giant, &sc->cbl_tag);
708 device_printf(dev, "could not create TxCB DMA tag\n");
712 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
713 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
715 device_printf(dev, "could not allocate TxCB DMA memory\n");
719 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
720 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
721 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
723 device_printf(dev, "could not load TxCB DMA buffer\n");
727 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
728 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
729 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
730 busdma_lock_mutex, &Giant, &sc->mcs_tag);
733 "could not create multicast setup DMA tag\n");
737 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
738 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
741 "could not allocate multicast setup DMA memory\n");
744 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
745 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
749 "can't load the multicast setup DMA buffer\n");
754 * Pre-allocate the TX DMA maps and setup the pointers to
755 * the TX command blocks.
757 txp = sc->fxp_desc.tx_list;
758 tcbp = sc->fxp_desc.cbl_list;
759 for (i = 0; i < FXP_NTXCB; i++) {
760 txp[i].tx_cb = tcbp + i;
761 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
763 device_printf(dev, "can't create DMA map for TX\n");
767 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
769 device_printf(dev, "can't create spare DMA map\n");
774 * Pre-allocate our receive buffers.
776 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
777 for (i = 0; i < FXP_NRFABUFS; i++) {
778 rxp = &sc->fxp_desc.rx_list[i];
779 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
781 device_printf(dev, "can't create DMA map for RX\n");
784 if (fxp_new_rfabuf(sc, rxp) != 0) {
788 fxp_add_rfabuf(sc, rxp);
794 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
795 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
796 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
797 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
798 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
799 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
801 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
802 pci_get_vendor(dev), pci_get_device(dev),
803 pci_get_subvendor(dev), pci_get_subdevice(dev),
805 device_printf(dev, "Dynamic Standby mode is %s\n",
806 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
811 * If this is only a 10Mbps device, then there is no MII, and
812 * the PHY will use a serial interface instead.
814 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
815 * doesn't have a programming interface of any sort. The
816 * media is sensed automatically based on how the link partner
817 * is configured. This is, in essence, manual configuration.
819 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
820 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
821 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
824 * i82557 wedge when isolating all of their PHYs.
826 flags = MIIF_NOISOLATE;
827 if (sc->revision >= FXP_REV_82558_A4)
828 flags |= MIIF_DOPAUSE;
829 error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd,
830 fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
831 MII_OFFSET_ANY, flags);
833 device_printf(dev, "attaching PHYs failed\n");
838 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
839 ifp->if_init = fxp_init;
841 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
842 ifp->if_ioctl = fxp_ioctl;
843 ifp->if_start = fxp_start;
845 ifp->if_capabilities = ifp->if_capenable = 0;
847 /* Enable checksum offload/TSO for 82550 or better chips */
848 if (sc->flags & FXP_FLAG_EXT_RFA) {
849 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
850 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
851 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
854 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
855 ifp->if_capabilities |= IFCAP_RXCSUM;
856 ifp->if_capenable |= IFCAP_RXCSUM;
859 if (sc->flags & FXP_FLAG_WOLCAP) {
860 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
861 ifp->if_capenable |= IFCAP_WOL_MAGIC;
864 #ifdef DEVICE_POLLING
865 /* Inform the world we support polling. */
866 ifp->if_capabilities |= IFCAP_POLLING;
870 * Attach the interface.
872 ether_ifattach(ifp, eaddr);
875 * Tell the upper layer(s) we support long frames.
876 * Must appear after the call to ether_ifattach() because
877 * ether_ifattach() sets ifi_hdrlen to the default value.
879 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
880 ifp->if_capabilities |= IFCAP_VLAN_MTU;
881 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
882 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
883 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
884 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
885 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
886 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
890 * Let the system queue as many packets as we have available
893 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
894 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
895 IFQ_SET_READY(&ifp->if_snd);
898 * Hook our interrupt after all initialization is complete.
900 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
901 NULL, fxp_intr, sc, &sc->ih);
903 device_printf(dev, "could not setup irq\n");
904 ether_ifdetach(sc->ifp);
909 * Configure hardware to reject magic frames otherwise
910 * system will hang on recipt of magic frames.
912 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
914 /* Clear wakeup events. */
915 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
916 fxp_init_body(sc, 0);
928 * Release all resources. The softc lock should not be held and the
929 * interrupt should already be torn down.
932 fxp_release(struct fxp_softc *sc)
938 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
939 KASSERT(sc->ih == NULL,
940 ("fxp_release() called with intr handle still active"));
942 device_delete_child(sc->dev, sc->miibus);
943 bus_generic_detach(sc->dev);
944 ifmedia_removeall(&sc->sc_media);
945 if (sc->fxp_desc.cbl_list) {
946 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
947 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
951 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
952 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
955 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
956 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
958 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
959 if (sc->fxp_rxmtag) {
960 for (i = 0; i < FXP_NRFABUFS; i++) {
961 rxp = &sc->fxp_desc.rx_list[i];
962 if (rxp->rx_mbuf != NULL) {
963 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
964 BUS_DMASYNC_POSTREAD);
965 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
966 m_freem(rxp->rx_mbuf);
968 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
970 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
971 bus_dma_tag_destroy(sc->fxp_rxmtag);
973 if (sc->fxp_txmtag) {
974 for (i = 0; i < FXP_NTXCB; i++) {
975 txp = &sc->fxp_desc.tx_list[i];
976 if (txp->tx_mbuf != NULL) {
977 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
978 BUS_DMASYNC_POSTWRITE);
979 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
980 m_freem(txp->tx_mbuf);
982 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
984 bus_dma_tag_destroy(sc->fxp_txmtag);
987 bus_dma_tag_destroy(sc->fxp_stag);
989 bus_dma_tag_destroy(sc->cbl_tag);
991 bus_dma_tag_destroy(sc->mcs_tag);
995 mtx_destroy(&sc->sc_mtx);
1002 fxp_detach(device_t dev)
1004 struct fxp_softc *sc = device_get_softc(dev);
1006 #ifdef DEVICE_POLLING
1007 if (sc->ifp->if_capenable & IFCAP_POLLING)
1008 ether_poll_deregister(sc->ifp);
1013 * Stop DMA and drop transmit queue, but disable interrupts first.
1015 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1018 callout_drain(&sc->stat_ch);
1021 * Close down routes etc.
1023 ether_ifdetach(sc->ifp);
1026 * Unhook interrupt before dropping lock. This is to prevent
1027 * races with fxp_intr().
1029 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1032 /* Release our allocated resources. */
1038 * Device shutdown routine. Called at system shutdown after sync. The
1039 * main purpose of this routine is to shut off receiver DMA so that
1040 * kernel memory doesn't get clobbered during warmboot.
1043 fxp_shutdown(device_t dev)
1047 * Make sure that DMA is disabled prior to reboot. Not doing
1048 * do could allow DMA to corrupt kernel memory during the
1049 * reboot before the driver initializes.
1051 return (fxp_suspend(dev));
1055 * Device suspend routine. Stop the interface and save some PCI
1056 * settings in case the BIOS doesn't restore them properly on
1060 fxp_suspend(device_t dev)
1062 struct fxp_softc *sc = device_get_softc(dev);
1070 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1071 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1072 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1073 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1075 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1076 sc->flags |= FXP_FLAG_WOL;
1077 /* Reconfigure hardware to accept magic frames. */
1078 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1079 fxp_init_body(sc, 0);
1081 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1092 * Device resume routine. re-enable busmastering, and restart the interface if
1096 fxp_resume(device_t dev)
1098 struct fxp_softc *sc = device_get_softc(dev);
1099 struct ifnet *ifp = sc->ifp;
1105 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1106 sc->flags &= ~FXP_FLAG_WOL;
1107 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1108 /* Disable PME and clear PME status. */
1109 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1110 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1111 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1112 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1113 CSR_READ_1(sc, FXP_CSR_PMDR));
1116 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1119 /* reinitialize interface if necessary */
1120 if (ifp->if_flags & IFF_UP)
1121 fxp_init_body(sc, 1);
1130 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1138 for (x = 1 << (length - 1); x; x >>= 1) {
1140 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1142 reg = FXP_EEPROM_EECS;
1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1153 * Read from the serial EEPROM. Basically, you manually shift in
1154 * the read opcode (one bit at a time) and then shift in the address,
1155 * and then you shift out the data (all of this one bit at a time).
1156 * The word size is 16 bits, so you have to provide the address for
1157 * every 16 bits of data.
1160 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1167 * Shift in read opcode.
1169 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1174 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1176 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1178 reg = FXP_EEPROM_EECS;
1179 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1183 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1185 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1187 if (autosize && reg == 0) {
1188 sc->eeprom_size = data;
1196 reg = FXP_EEPROM_EECS;
1197 for (x = 1 << 15; x; x >>= 1) {
1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1200 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1202 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1212 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1217 * Erase/write enable.
1219 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1220 fxp_eeprom_shiftin(sc, 0x4, 3);
1221 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1225 * Shift in write opcode, address, data.
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1228 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1229 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1230 fxp_eeprom_shiftin(sc, data, 16);
1231 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1234 * Wait for EEPROM to finish up.
1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1238 for (i = 0; i < 1000; i++) {
1239 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1243 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1246 * Erase/write disable.
1248 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1249 fxp_eeprom_shiftin(sc, 0x4, 3);
1250 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1251 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1258 * Figure out EEPROM size.
1260 * 559's can have either 64-word or 256-word EEPROMs, the 558
1261 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1262 * talks about the existance of 16 to 256 word EEPROMs.
1264 * The only known sizes are 64 and 256, where the 256 version is used
1265 * by CardBus cards to store CIS information.
1267 * The address is shifted in msb-to-lsb, and after the last
1268 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1269 * after which follows the actual data. We try to detect this zero, by
1270 * probing the data-out bit in the EEPROM control register just after
1271 * having shifted in a bit. If the bit is zero, we assume we've
1272 * shifted enough address bits. The data-out should be tri-state,
1273 * before this, which should translate to a logical one.
1276 fxp_autosize_eeprom(struct fxp_softc *sc)
1279 /* guess maximum size of 256 words */
1280 sc->eeprom_size = 8;
1283 (void) fxp_eeprom_getword(sc, 0, 1);
1287 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1291 for (i = 0; i < words; i++)
1292 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1296 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1300 for (i = 0; i < words; i++)
1301 fxp_eeprom_putword(sc, offset + i, data[i]);
1305 fxp_load_eeprom(struct fxp_softc *sc)
1310 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1312 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1313 cksum += sc->eeprom[i];
1314 cksum = 0xBABA - cksum;
1315 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1316 device_printf(sc->dev,
1317 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1318 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1322 * Grab the softc lock and call the real fxp_start_body() routine
1325 fxp_start(struct ifnet *ifp)
1327 struct fxp_softc *sc = ifp->if_softc;
1330 fxp_start_body(ifp);
1335 * Start packet transmission on the interface.
1336 * This routine must be called with the softc lock held, and is an
1337 * internal entry point only.
1340 fxp_start_body(struct ifnet *ifp)
1342 struct fxp_softc *sc = ifp->if_softc;
1343 struct mbuf *mb_head;
1346 FXP_LOCK_ASSERT(sc, MA_OWNED);
1348 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1352 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1355 * We're finished if there is nothing more to add to the list or if
1356 * we're all filled up with buffers to transmit.
1357 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1358 * a NOP command when needed.
1361 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1362 sc->tx_queued < FXP_NTXCB - 1) {
1365 * Grab a packet to transmit.
1367 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1368 if (mb_head == NULL)
1371 if (fxp_encap(sc, &mb_head)) {
1372 if (mb_head == NULL)
1374 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1375 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1379 * Pass packet to bpf if there is a listener.
1381 BPF_MTAP(ifp, mb_head);
1385 * We're finished. If we added to the list, issue a RESUME to get DMA
1386 * going again if suspended.
1389 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1392 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1394 * Set a 5 second timer just in case we don't hear
1395 * from the card again.
1397 sc->watchdog_timer = 5;
1402 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1407 struct fxp_cb_tx *cbp;
1409 bus_dma_segment_t segs[FXP_NTXSEG];
1410 int error, i, nseg, tcp_payload;
1412 FXP_LOCK_ASSERT(sc, MA_OWNED);
1418 * Get pointer to next available tx desc.
1420 txp = sc->fxp_desc.tx_last->tx_next;
1423 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1424 * Ethernet Controller Family Open Source Software
1425 * Developer Manual says:
1426 * Using software parsing is only allowed with legal
1427 * TCP/IP or UDP/IP packets.
1429 * For all other datagrams, hardware parsing must
1431 * Software parsing appears to truncate ICMP and
1432 * fragmented UDP packets that contain one to three
1433 * bytes in the second (and final) mbuf of the packet.
1435 if (sc->flags & FXP_FLAG_EXT_RFA)
1436 txp->tx_cb->ipcb_ip_activation_high =
1437 FXP_IPCB_HARDWAREPARSING_ENABLE;
1440 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1442 * 82550/82551 requires ethernet/IP/TCP headers must be
1443 * contained in the first active transmit buffer.
1445 struct ether_header *eh;
1447 uint32_t ip_off, poff;
1449 if (M_WRITABLE(*m_head) == 0) {
1450 /* Get a writable copy. */
1451 m = m_dup(*m_head, M_NOWAIT);
1459 ip_off = sizeof(struct ether_header);
1460 m = m_pullup(*m_head, ip_off);
1465 eh = mtod(m, struct ether_header *);
1466 /* Check the existence of VLAN tag. */
1467 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1468 ip_off = sizeof(struct ether_vlan_header);
1469 m = m_pullup(m, ip_off);
1475 m = m_pullup(m, ip_off + sizeof(struct ip));
1480 ip = (struct ip *)(mtod(m, char *) + ip_off);
1481 poff = ip_off + (ip->ip_hl << 2);
1482 m = m_pullup(m, poff + sizeof(struct tcphdr));
1487 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1488 m = m_pullup(m, poff + (tcp->th_off << 2));
1495 * Since 82550/82551 doesn't modify IP length and pseudo
1496 * checksum in the first frame driver should compute it.
1498 ip = (struct ip *)(mtod(m, char *) + ip_off);
1499 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1501 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1502 (tcp->th_off << 2));
1503 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1504 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1505 m->m_pkthdr.tso_segsz));
1506 /* Compute total TCP payload. */
1507 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1508 tcp_payload -= tcp->th_off << 2;
1510 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1512 * Deal with TCP/IP checksum offload. Note that
1513 * in order for TCP checksum offload to work,
1514 * the pseudo header checksum must have already
1515 * been computed and stored in the checksum field
1516 * in the TCP header. The stack should have
1517 * already done this for us.
1519 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1520 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1521 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1523 #ifdef FXP_IP_CSUM_WAR
1525 * XXX The 82550 chip appears to have trouble
1526 * dealing with IP header checksums in very small
1527 * datagrams, namely fragments from 1 to 3 bytes
1528 * in size. For example, say you want to transmit
1529 * a UDP packet of 1473 bytes. The packet will be
1530 * fragmented over two IP datagrams, the latter
1531 * containing only one byte of data. The 82550 will
1532 * botch the header checksum on the 1-byte fragment.
1533 * As long as the datagram contains 4 or more bytes
1534 * of data, you're ok.
1536 * The following code attempts to work around this
1537 * problem: if the datagram is less than 38 bytes
1538 * in size (14 bytes ether header, 20 bytes IP header,
1539 * plus 4 bytes of data), we punt and compute the IP
1540 * header checksum by hand. This workaround doesn't
1541 * work very well, however, since it can be fooled
1542 * by things like VLAN tags and IP options that make
1543 * the header sizes/offsets vary.
1546 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1547 if (m->m_pkthdr.len < 38) {
1549 m->m_data += ETHER_HDR_LEN;
1550 ip = mtod(m, struct ip *);
1551 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1552 m->m_data -= ETHER_HDR_LEN;
1553 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1555 txp->tx_cb->ipcb_ip_activation_high =
1556 FXP_IPCB_HARDWAREPARSING_ENABLE;
1557 txp->tx_cb->ipcb_ip_schedule |=
1558 FXP_IPCB_IP_CHECKSUM_ENABLE;
1564 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1566 if (error == EFBIG) {
1567 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1574 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1575 *m_head, segs, &nseg, 0);
1581 } else if (error != 0)
1589 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1590 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1593 for (i = 0; i < nseg; i++) {
1595 * If this is an 82550/82551, then we're using extended
1596 * TxCBs _and_ we're using checksum offload. This means
1597 * that the TxCB is really an IPCB. One major difference
1598 * between the two is that with plain extended TxCBs,
1599 * the bottom half of the TxCB contains two entries from
1600 * the TBD array, whereas IPCBs contain just one entry:
1601 * one entry (8 bytes) has been sacrificed for the TCP/IP
1602 * checksum offload control bits. So to make things work
1603 * right, we have to start filling in the TBD array
1604 * starting from a different place depending on whether
1605 * the chip is an 82550/82551 or not.
1607 if (sc->flags & FXP_FLAG_EXT_RFA) {
1608 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1609 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1611 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1612 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1615 if (sc->flags & FXP_FLAG_EXT_RFA) {
1616 /* Configure dynamic TBD for 82550/82551. */
1617 cbp->tbd_number = 0xFF;
1618 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1620 cbp->tbd_number = nseg;
1621 /* Configure TSO. */
1622 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1623 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1624 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1625 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1626 FXP_IPCB_IP_CHECKSUM_ENABLE |
1627 FXP_IPCB_TCP_PACKET |
1628 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1630 /* Configure VLAN hardware tag insertion. */
1631 if ((m->m_flags & M_VLANTAG) != 0) {
1632 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1633 txp->tx_cb->ipcb_ip_activation_high |=
1634 FXP_IPCB_INSERTVLAN_ENABLE;
1638 txp->tx_cb->cb_status = 0;
1639 txp->tx_cb->byte_count = 0;
1640 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1641 txp->tx_cb->cb_command =
1642 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1645 txp->tx_cb->cb_command =
1646 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1647 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1648 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1649 txp->tx_cb->tx_threshold = tx_threshold;
1652 * Advance the end of list forward.
1654 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1655 sc->fxp_desc.tx_last = txp;
1658 * Advance the beginning of the list forward if there are
1659 * no other packets queued (when nothing is queued, tx_first
1660 * sits on the last TxCB that was sent out).
1662 if (sc->tx_queued == 0)
1663 sc->fxp_desc.tx_first = txp;
1670 #ifdef DEVICE_POLLING
1671 static poll_handler_t fxp_poll;
1674 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1676 struct fxp_softc *sc = ifp->if_softc;
1681 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1686 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1688 if (cmd == POLL_AND_CHECK_STATUS) {
1691 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1692 if (tmp == 0xff || tmp == 0) {
1694 return (rx_npkts); /* nothing to do */
1697 /* ack what we can */
1699 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1702 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1706 #endif /* DEVICE_POLLING */
1709 * Process interface interrupts.
1714 struct fxp_softc *sc = xsc;
1715 struct ifnet *ifp = sc->ifp;
1719 if (sc->suspended) {
1724 #ifdef DEVICE_POLLING
1725 if (ifp->if_capenable & IFCAP_POLLING) {
1730 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1732 * It should not be possible to have all bits set; the
1733 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1734 * all bits are set, this may indicate that the card has
1735 * been physically ejected, so ignore it.
1737 if (statack == 0xff) {
1743 * First ACK all the interrupts in this pass.
1745 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1746 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1747 fxp_intr_body(sc, ifp, statack, -1);
1753 fxp_txeof(struct fxp_softc *sc)
1759 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1760 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1761 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1762 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1763 txp = txp->tx_next) {
1764 if (txp->tx_mbuf != NULL) {
1765 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1766 BUS_DMASYNC_POSTWRITE);
1767 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1768 m_freem(txp->tx_mbuf);
1769 txp->tx_mbuf = NULL;
1770 /* clear this to reset csum offload bits */
1771 txp->tx_cb->tbd[0].tb_addr = 0;
1774 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1776 sc->fxp_desc.tx_first = txp;
1777 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1778 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1779 if (sc->tx_queued == 0)
1780 sc->watchdog_timer = 0;
1784 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1785 uint16_t status, int pos)
1787 struct ether_header *eh;
1790 int32_t hlen, len, pktlen, temp32;
1791 uint16_t csum, *opts;
1793 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1794 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1795 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1796 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1797 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1798 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1799 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1800 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1801 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1803 m->m_pkthdr.csum_data = 0xffff;
1809 pktlen = m->m_pkthdr.len;
1810 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1812 eh = mtod(m, struct ether_header *);
1813 if (eh->ether_type != htons(ETHERTYPE_IP))
1815 ip = (struct ip *)(eh + 1);
1816 if (ip->ip_v != IPVERSION)
1819 hlen = ip->ip_hl << 2;
1820 pktlen -= sizeof(struct ether_header);
1821 if (hlen < sizeof(struct ip))
1823 if (ntohs(ip->ip_len) < hlen)
1825 if (ntohs(ip->ip_len) != pktlen)
1827 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1828 return; /* can't handle fragmented packet */
1832 if (pktlen < (hlen + sizeof(struct tcphdr)))
1836 if (pktlen < (hlen + sizeof(struct udphdr)))
1838 uh = (struct udphdr *)((caddr_t)ip + hlen);
1839 if (uh->uh_sum == 0)
1840 return; /* no checksum */
1845 /* Extract computed checksum. */
1846 csum = be16dec(mtod(m, char *) + pos);
1847 /* checksum fixup for IP options */
1848 len = hlen - sizeof(struct ip);
1850 opts = (uint16_t *)(ip + 1);
1851 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1852 temp32 = csum - *opts;
1853 temp32 = (temp32 >> 16) + (temp32 & 65535);
1854 csum = temp32 & 65535;
1857 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1858 m->m_pkthdr.csum_data = csum;
1862 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1867 struct fxp_rfa *rfa;
1868 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1873 FXP_LOCK_ASSERT(sc, MA_OWNED);
1877 #ifdef DEVICE_POLLING
1878 /* Pick up a deferred RNR condition if `count' ran out last time. */
1879 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1880 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1886 * Free any finished transmit mbuf chains.
1888 * Handle the CNA event likt a CXTNO event. It used to
1889 * be that this event (control unit not ready) was not
1890 * encountered, but it is now with the SMPng modifications.
1891 * The exact sequence of events that occur when the interface
1892 * is brought up are different now, and if this event
1893 * goes unhandled, the configuration/rxfilter setup sequence
1894 * can stall for several seconds. The result is that no
1895 * packets go out onto the wire for about 5 to 10 seconds
1896 * after the interface is ifconfig'ed for the first time.
1898 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1902 * Try to start more packets transmitting.
1904 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1905 fxp_start_body(ifp);
1908 * Just return if nothing happened on the receive side.
1910 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1914 * Process receiver interrupts. If a no-resource (RNR)
1915 * condition exists, get whatever packets we can and
1916 * re-start the receiver.
1918 * When using polling, we do not process the list to completion,
1919 * so when we get an RNR interrupt we must defer the restart
1920 * until we hit the last buffer with the C bit set.
1921 * If we run out of cycles and rfa_headm has the C bit set,
1922 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1923 * that the info will be used in the subsequent polling cycle.
1926 rxp = sc->fxp_desc.rx_head;
1928 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1929 RFA_ALIGNMENT_FUDGE);
1930 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1931 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1933 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1934 if (count >= 0 && count-- == 0) {
1936 /* Defer RNR processing until the next time. */
1937 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1942 #endif /* DEVICE_POLLING */
1944 status = le16toh(rfa->rfa_status);
1945 if ((status & FXP_RFA_STATUS_C) == 0)
1948 if ((status & FXP_RFA_STATUS_RNR) != 0)
1951 * Advance head forward.
1953 sc->fxp_desc.rx_head = rxp->rx_next;
1956 * Add a new buffer to the receive chain.
1957 * If this fails, the old buffer is recycled
1960 if (fxp_new_rfabuf(sc, rxp) == 0) {
1964 * Fetch packet length (the top 2 bits of
1965 * actual_size are flags set by the controller
1966 * upon completion), and drop the packet in case
1967 * of bogus length or CRC errors.
1969 total_len = le16toh(rfa->actual_size) & 0x3fff;
1970 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1971 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1972 /* Adjust for appended checksum bytes. */
1975 if (total_len < (int)sizeof(struct ether_header) ||
1976 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1978 status & (FXP_RFA_STATUS_CRC |
1979 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1981 fxp_add_rfabuf(sc, rxp);
1985 m->m_pkthdr.len = m->m_len = total_len;
1986 m->m_pkthdr.rcvif = ifp;
1988 /* Do IP checksum checking. */
1989 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1990 fxp_rxcsum(sc, ifp, m, status, total_len);
1991 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1992 (status & FXP_RFA_STATUS_VLAN) != 0) {
1993 m->m_pkthdr.ether_vtag =
1994 ntohs(rfa->rfax_vlan_id);
1995 m->m_flags |= M_VLANTAG;
1998 * Drop locks before calling if_input() since it
1999 * may re-enter fxp_start() in the netisr case.
2000 * This would result in a lock reversal. Better
2001 * performance might be obtained by chaining all
2002 * packets received, dropping the lock, and then
2003 * calling if_input() on each one.
2006 (*ifp->if_input)(ifp, m);
2009 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2012 /* Reuse RFA and loaded DMA map. */
2014 fxp_discard_rfabuf(sc, rxp);
2016 fxp_add_rfabuf(sc, rxp);
2020 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2021 sc->fxp_desc.rx_head->rx_addr);
2022 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2028 fxp_update_stats(struct fxp_softc *sc)
2030 struct ifnet *ifp = sc->ifp;
2031 struct fxp_stats *sp = sc->fxp_stats;
2032 struct fxp_hwstats *hsp;
2035 FXP_LOCK_ASSERT(sc, MA_OWNED);
2037 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2038 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2039 /* Update statistical counters. */
2040 if (sc->revision >= FXP_REV_82559_A0)
2041 status = &sp->completion_status;
2042 else if (sc->revision >= FXP_REV_82558_A4)
2043 status = (uint32_t *)&sp->tx_tco;
2045 status = &sp->tx_pause;
2046 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2047 hsp = &sc->fxp_hwstats;
2048 hsp->tx_good += le32toh(sp->tx_good);
2049 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2050 hsp->tx_latecols += le32toh(sp->tx_latecols);
2051 hsp->tx_underruns += le32toh(sp->tx_underruns);
2052 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2053 hsp->tx_deffered += le32toh(sp->tx_deffered);
2054 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2055 hsp->tx_multiple_collisions +=
2056 le32toh(sp->tx_multiple_collisions);
2057 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2058 hsp->rx_good += le32toh(sp->rx_good);
2059 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2060 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2061 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2062 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2063 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2064 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2065 hsp->tx_pause += le32toh(sp->tx_pause);
2066 hsp->rx_pause += le32toh(sp->rx_pause);
2067 hsp->rx_controls += le32toh(sp->rx_controls);
2068 hsp->tx_tco += le16toh(sp->tx_tco);
2069 hsp->rx_tco += le16toh(sp->rx_tco);
2071 ifp->if_opackets += le32toh(sp->tx_good);
2072 ifp->if_collisions += le32toh(sp->tx_total_collisions);
2074 ifp->if_ipackets += le32toh(sp->rx_good);
2075 sc->rx_idle_secs = 0;
2076 } else if (sc->flags & FXP_FLAG_RXBUG) {
2078 * Receiver's been idle for another second.
2083 le32toh(sp->rx_crc_errors) +
2084 le32toh(sp->rx_alignment_errors) +
2085 le32toh(sp->rx_rnr_errors) +
2086 le32toh(sp->rx_overrun_errors);
2088 * If any transmit underruns occured, bump up the transmit
2089 * threshold by another 512 bytes (64 * 8).
2091 if (sp->tx_underruns) {
2092 ifp->if_oerrors += le32toh(sp->tx_underruns);
2093 if (tx_threshold < 192)
2097 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2098 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2103 * Update packet in/out/collision statistics. The i82557 doesn't
2104 * allow you to access these counters without doing a fairly
2105 * expensive DMA to get _all_ of the statistics it maintains, so
2106 * we do this operation here only once per second. The statistics
2107 * counters in the kernel are updated from the previous dump-stats
2108 * DMA and then a new dump-stats DMA is started. The on-chip
2109 * counters are zeroed when the DMA completes. If we can't start
2110 * the DMA immediately, we don't wait - we just prepare to read
2111 * them again next time.
2116 struct fxp_softc *sc = xsc;
2117 struct ifnet *ifp = sc->ifp;
2119 FXP_LOCK_ASSERT(sc, MA_OWNED);
2121 /* Update statistical counters. */
2122 fxp_update_stats(sc);
2125 * Release any xmit buffers that have completed DMA. This isn't
2126 * strictly necessary to do here, but it's advantagous for mbufs
2127 * with external storage to be released in a timely manner rather
2128 * than being defered for a potentially long time. This limits
2129 * the delay to a maximum of one second.
2134 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2135 * then assume the receiver has locked up and attempt to clear
2136 * the condition by reprogramming the multicast filter. This is
2137 * a work-around for a bug in the 82557 where the receiver locks
2138 * up if it gets certain types of garbage in the syncronization
2139 * bits prior to the packet header. This bug is supposed to only
2140 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2141 * mode as well (perhaps due to a 10/100 speed transition).
2143 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2144 sc->rx_idle_secs = 0;
2145 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2146 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2147 fxp_init_body(sc, 1);
2152 * If there is no pending command, start another stats
2153 * dump. Otherwise punt for now.
2155 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2157 * Start another stats dump.
2159 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2161 if (sc->miibus != NULL)
2162 mii_tick(device_get_softc(sc->miibus));
2165 * Check that chip hasn't hung.
2170 * Schedule another timeout one second from now.
2172 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2176 * Stop the interface. Cancels the statistics updater and resets
2180 fxp_stop(struct fxp_softc *sc)
2182 struct ifnet *ifp = sc->ifp;
2186 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2187 sc->watchdog_timer = 0;
2190 * Cancel stats updater.
2192 callout_stop(&sc->stat_ch);
2195 * Preserve PCI configuration, configure, IA/multicast
2196 * setup and put RU and CU into idle state.
2198 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2200 /* Disable interrupts. */
2201 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2203 fxp_update_stats(sc);
2206 * Release any xmit buffers.
2208 txp = sc->fxp_desc.tx_list;
2210 for (i = 0; i < FXP_NTXCB; i++) {
2211 if (txp[i].tx_mbuf != NULL) {
2212 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2213 BUS_DMASYNC_POSTWRITE);
2214 bus_dmamap_unload(sc->fxp_txmtag,
2216 m_freem(txp[i].tx_mbuf);
2217 txp[i].tx_mbuf = NULL;
2218 /* clear this to reset csum offload bits */
2219 txp[i].tx_cb->tbd[0].tb_addr = 0;
2223 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2229 * Watchdog/transmission transmit timeout handler. Called when a
2230 * transmission is started on the interface, but no interrupt is
2231 * received before the timeout. This usually indicates that the
2232 * card has wedged for some reason.
2235 fxp_watchdog(struct fxp_softc *sc)
2238 FXP_LOCK_ASSERT(sc, MA_OWNED);
2240 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2243 device_printf(sc->dev, "device timeout\n");
2244 sc->ifp->if_oerrors++;
2246 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2247 fxp_init_body(sc, 1);
2251 * Acquire locks and then call the real initialization function. This
2252 * is necessary because ether_ioctl() calls if_init() and this would
2253 * result in mutex recursion if the mutex was held.
2258 struct fxp_softc *sc = xsc;
2261 fxp_init_body(sc, 1);
2266 * Perform device initialization. This routine must be called with the
2270 fxp_init_body(struct fxp_softc *sc, int setmedia)
2272 struct ifnet *ifp = sc->ifp;
2273 struct mii_data *mii;
2274 struct fxp_cb_config *cbp;
2275 struct fxp_cb_ias *cb_ias;
2276 struct fxp_cb_tx *tcbp;
2280 FXP_LOCK_ASSERT(sc, MA_OWNED);
2282 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2286 * Cancel any pending I/O
2291 * Issue software reset, which also unloads the microcode.
2293 sc->flags &= ~FXP_FLAG_UCODE;
2294 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2297 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2300 * Initialize base of CBL and RFA memory. Loading with zero
2301 * sets it up for regular linear addressing.
2303 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2304 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2307 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2310 * Initialize base of dump-stats buffer.
2313 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2314 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2315 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2316 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2317 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2320 * Attempt to load microcode if requested.
2321 * For ICH based controllers do not load microcode.
2323 if (sc->ident->ich == 0) {
2324 if (ifp->if_flags & IFF_LINK0 &&
2325 (sc->flags & FXP_FLAG_UCODE) == 0)
2330 * Set IFF_ALLMULTI status. It's needed in configure action
2336 * We temporarily use memory that contains the TxCB list to
2337 * construct the config CB. The TxCB list memory is rebuilt
2340 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2343 * This bcopy is kind of disgusting, but there are a bunch of must be
2344 * zero and must be one bits in this structure and this is the easiest
2345 * way to initialize them all to proper values.
2347 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2350 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2352 cbp->link_addr = 0xffffffff; /* (no) next command */
2353 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2354 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2355 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2356 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2357 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2358 cbp->type_enable = 0; /* actually reserved */
2359 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2360 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2361 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2362 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2363 cbp->dma_mbce = 0; /* (disable) dma max counters */
2364 cbp->late_scb = 0; /* (don't) defer SCB update */
2365 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2366 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2367 cbp->ci_int = 1; /* interrupt on CU idle */
2368 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2369 cbp->ext_stats_dis = 1; /* disable extended counters */
2370 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2371 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2372 cbp->disc_short_rx = !prm; /* discard short packets */
2373 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2374 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2375 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2376 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2377 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2378 cbp->csma_dis = 0; /* (don't) disable link */
2379 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2380 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2381 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2382 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2383 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2384 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2385 cbp->nsai = 1; /* (don't) disable source addr insert */
2386 cbp->preamble_length = 2; /* (7 byte) preamble */
2387 cbp->loopback = 0; /* (don't) loopback */
2388 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2389 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2390 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2391 cbp->promiscuous = prm; /* promiscuous mode */
2392 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2393 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2394 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2395 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2396 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2398 cbp->stripping = !prm; /* truncate rx packet to byte count */
2399 cbp->padding = 1; /* (do) pad short tx packets */
2400 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2401 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2402 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2403 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2404 cbp->force_fdx = 0; /* (don't) force full duplex */
2405 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2406 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2407 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm;
2408 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2409 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2410 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2412 if (sc->revision == FXP_REV_82557) {
2414 * The 82557 has no hardware flow control, the values
2415 * below are the defaults for the chip.
2417 cbp->fc_delay_lsb = 0;
2418 cbp->fc_delay_msb = 0x40;
2419 cbp->pri_fc_thresh = 3;
2421 cbp->rx_fc_restop = 0;
2422 cbp->rx_fc_restart = 0;
2424 cbp->pri_fc_loc = 1;
2426 /* Set pause RX FIFO threshold to 1KB. */
2427 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2428 /* Set pause time. */
2429 cbp->fc_delay_lsb = 0xff;
2430 cbp->fc_delay_msb = 0xff;
2431 cbp->pri_fc_thresh = 3;
2432 mii = device_get_softc(sc->miibus);
2433 if ((IFM_OPTIONS(mii->mii_media_active) &
2434 IFM_ETH_TXPAUSE) != 0)
2435 /* enable transmit FC */
2438 /* disable transmit FC */
2440 if ((IFM_OPTIONS(mii->mii_media_active) &
2441 IFM_ETH_RXPAUSE) != 0) {
2442 /* enable FC restart/restop frames */
2443 cbp->rx_fc_restart = 1;
2444 cbp->rx_fc_restop = 1;
2446 /* disable FC restart/restop frames */
2447 cbp->rx_fc_restart = 0;
2448 cbp->rx_fc_restop = 0;
2450 cbp->fc_filter = !prm; /* drop FC frames to host */
2451 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2454 /* Enable 82558 and 82559 extended statistics functionality. */
2455 if (sc->revision >= FXP_REV_82558_A4) {
2456 if (sc->revision >= FXP_REV_82559_A0) {
2458 * Extend configuration table size to 32
2459 * to include TCO configuration.
2461 cbp->byte_count = 32;
2462 cbp->ext_stats_dis = 1;
2463 /* Enable TCO stats. */
2464 cbp->tno_int_or_tco_en = 1;
2467 cbp->ext_stats_dis = 0;
2471 * Start the config command/DMA.
2474 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2475 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2476 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2477 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2478 /* ...and wait for it to complete. */
2479 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2482 * Now initialize the station address. Temporarily use the TxCB
2483 * memory area like we did above for the config CB.
2485 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2486 cb_ias->cb_status = 0;
2487 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2488 cb_ias->link_addr = 0xffffffff;
2489 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2492 * Start the IAS (Individual Address Setup) command/DMA.
2495 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2497 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2498 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2499 /* ...and wait for it to complete. */
2500 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2503 * Initialize the multicast address list.
2508 * Initialize transmit control block (TxCB) list.
2510 txp = sc->fxp_desc.tx_list;
2511 tcbp = sc->fxp_desc.cbl_list;
2512 bzero(tcbp, FXP_TXCB_SZ);
2513 for (i = 0; i < FXP_NTXCB; i++) {
2514 txp[i].tx_mbuf = NULL;
2515 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2516 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2517 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2518 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2519 if (sc->flags & FXP_FLAG_EXT_TXCB)
2520 tcbp[i].tbd_array_addr =
2521 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2523 tcbp[i].tbd_array_addr =
2524 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2525 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2528 * Set the suspend flag on the first TxCB and start the control
2529 * unit. It will execute the NOP and then suspend.
2531 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2532 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2533 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2534 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2538 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2539 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2542 * Initialize receiver buffer area - RFA.
2545 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2546 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2548 if (sc->miibus != NULL && setmedia != 0)
2549 mii_mediachg(device_get_softc(sc->miibus));
2551 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2552 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2555 * Enable interrupts.
2557 #ifdef DEVICE_POLLING
2559 * ... but only do that if we are not polling. And because (presumably)
2560 * the default is interrupts on, we need to disable them explicitly!
2562 if (ifp->if_capenable & IFCAP_POLLING )
2563 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2565 #endif /* DEVICE_POLLING */
2566 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2569 * Start stats updater.
2571 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2575 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2582 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2585 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2589 * Change media according to request.
2592 fxp_ifmedia_upd(struct ifnet *ifp)
2594 struct fxp_softc *sc = ifp->if_softc;
2595 struct mii_data *mii;
2596 struct mii_softc *miisc;
2598 mii = device_get_softc(sc->miibus);
2600 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2608 * Notify the world which media we're using.
2611 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2613 struct fxp_softc *sc = ifp->if_softc;
2614 struct mii_data *mii;
2616 mii = device_get_softc(sc->miibus);
2619 ifmr->ifm_active = mii->mii_media_active;
2620 ifmr->ifm_status = mii->mii_media_status;
2625 * Add a buffer to the end of the RFA buffer list.
2626 * Return 0 if successful, 1 for failure. A failure results in
2627 * reusing the RFA buffer.
2628 * The RFA struct is stuck at the beginning of mbuf cluster and the
2629 * data pointer is fixed up to point just past it.
2632 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2635 struct fxp_rfa *rfa;
2636 bus_dmamap_t tmp_map;
2639 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2644 * Move the data pointer up so that the incoming data packet
2645 * will be 32-bit aligned.
2647 m->m_data += RFA_ALIGNMENT_FUDGE;
2650 * Get a pointer to the base of the mbuf cluster and move
2651 * data start past it.
2653 rfa = mtod(m, struct fxp_rfa *);
2654 m->m_data += sc->rfa_size;
2655 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2657 rfa->rfa_status = 0;
2658 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2659 rfa->actual_size = 0;
2660 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2664 * Initialize the rest of the RFA. Note that since the RFA
2665 * is misaligned, we cannot store values directly. We're thus
2666 * using the le32enc() function which handles endianness and
2667 * is also alignment-safe.
2669 le32enc(&rfa->link_addr, 0xffffffff);
2670 le32enc(&rfa->rbd_addr, 0xffffffff);
2672 /* Map the RFA into DMA memory. */
2673 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2674 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2675 &rxp->rx_addr, BUS_DMA_NOWAIT);
2681 if (rxp->rx_mbuf != NULL)
2682 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2683 tmp_map = sc->spare_map;
2684 sc->spare_map = rxp->rx_map;
2685 rxp->rx_map = tmp_map;
2688 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2689 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2694 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2696 struct fxp_rfa *p_rfa;
2697 struct fxp_rx *p_rx;
2700 * If there are other buffers already on the list, attach this
2701 * one to the end by fixing up the tail to point to this one.
2703 if (sc->fxp_desc.rx_head != NULL) {
2704 p_rx = sc->fxp_desc.rx_tail;
2705 p_rfa = (struct fxp_rfa *)
2706 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2707 p_rx->rx_next = rxp;
2708 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2709 p_rfa->rfa_control = 0;
2710 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2713 rxp->rx_next = NULL;
2714 sc->fxp_desc.rx_head = rxp;
2716 sc->fxp_desc.rx_tail = rxp;
2720 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2723 struct fxp_rfa *rfa;
2726 m->m_data = m->m_ext.ext_buf;
2728 * Move the data pointer up so that the incoming data packet
2729 * will be 32-bit aligned.
2731 m->m_data += RFA_ALIGNMENT_FUDGE;
2734 * Get a pointer to the base of the mbuf cluster and move
2735 * data start past it.
2737 rfa = mtod(m, struct fxp_rfa *);
2738 m->m_data += sc->rfa_size;
2739 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2741 rfa->rfa_status = 0;
2742 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2743 rfa->actual_size = 0;
2746 * Initialize the rest of the RFA. Note that since the RFA
2747 * is misaligned, we cannot store values directly. We're thus
2748 * using the le32enc() function which handles endianness and
2749 * is also alignment-safe.
2751 le32enc(&rfa->link_addr, 0xffffffff);
2752 le32enc(&rfa->rbd_addr, 0xffffffff);
2754 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2759 fxp_miibus_readreg(device_t dev, int phy, int reg)
2761 struct fxp_softc *sc = device_get_softc(dev);
2765 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2766 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2768 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2773 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2775 return (value & 0xffff);
2779 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2781 struct fxp_softc *sc = device_get_softc(dev);
2784 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2785 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2788 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2793 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2798 fxp_miibus_statchg(device_t dev)
2800 struct fxp_softc *sc;
2801 struct mii_data *mii;
2804 sc = device_get_softc(dev);
2805 mii = device_get_softc(sc->miibus);
2807 if (mii == NULL || ifp == NULL ||
2808 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
2809 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2810 (IFM_AVALID | IFM_ACTIVE))
2813 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2814 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2815 sc->cu_resume_bug = 1;
2817 sc->cu_resume_bug = 0;
2819 * Call fxp_init_body in order to adjust the flow control settings.
2820 * Note that the 82557 doesn't support hardware flow control.
2822 if (sc->revision == FXP_REV_82557)
2824 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2825 fxp_init_body(sc, 0);
2829 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2831 struct fxp_softc *sc = ifp->if_softc;
2832 struct ifreq *ifr = (struct ifreq *)data;
2833 struct mii_data *mii;
2834 int flag, mask, error = 0, reinit;
2840 * If interface is marked up and not running, then start it.
2841 * If it is marked down and running, stop it.
2842 * XXX If it's up then re-initialize it. This is so flags
2843 * such as IFF_PROMISC are handled.
2845 if (ifp->if_flags & IFF_UP) {
2846 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2847 ((ifp->if_flags ^ sc->if_flags) &
2848 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2849 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2850 fxp_init_body(sc, 0);
2851 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2852 fxp_init_body(sc, 1);
2854 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2857 sc->if_flags = ifp->if_flags;
2864 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2865 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2866 fxp_init_body(sc, 0);
2873 if (sc->miibus != NULL) {
2874 mii = device_get_softc(sc->miibus);
2875 error = ifmedia_ioctl(ifp, ifr,
2876 &mii->mii_media, command);
2878 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2884 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2885 #ifdef DEVICE_POLLING
2886 if (mask & IFCAP_POLLING) {
2887 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2888 error = ether_poll_register(fxp_poll, ifp);
2892 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2893 FXP_SCB_INTR_DISABLE);
2894 ifp->if_capenable |= IFCAP_POLLING;
2897 error = ether_poll_deregister(ifp);
2898 /* Enable interrupts in any case */
2900 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2901 ifp->if_capenable &= ~IFCAP_POLLING;
2907 if ((mask & IFCAP_TXCSUM) != 0 &&
2908 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2909 ifp->if_capenable ^= IFCAP_TXCSUM;
2910 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2911 ifp->if_hwassist |= FXP_CSUM_FEATURES;
2913 ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2915 if ((mask & IFCAP_RXCSUM) != 0 &&
2916 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2917 ifp->if_capenable ^= IFCAP_RXCSUM;
2918 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2921 if ((mask & IFCAP_TSO4) != 0 &&
2922 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2923 ifp->if_capenable ^= IFCAP_TSO4;
2924 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2925 ifp->if_hwassist |= CSUM_TSO;
2927 ifp->if_hwassist &= ~CSUM_TSO;
2929 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2930 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2931 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2932 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2933 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2934 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2935 if (sc->revision != FXP_REV_82557)
2936 flag = FXP_FLAG_LONG_PKT_EN;
2937 else /* a hack to get long frames on the old chip */
2938 flag = FXP_FLAG_SAVE_BAD;
2940 if (ifp->if_flags & IFF_UP)
2943 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2944 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2945 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2946 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2947 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2948 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2949 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2950 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2951 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2952 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2953 ifp->if_capenable &=
2954 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2957 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2958 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2959 fxp_init_body(sc, 0);
2962 VLAN_CAPABILITIES(ifp);
2966 error = ether_ioctl(ifp, command, data);
2972 * Fill in the multicast address list and return number of entries.
2975 fxp_mc_addrs(struct fxp_softc *sc)
2977 struct fxp_cb_mcs *mcsp = sc->mcsp;
2978 struct ifnet *ifp = sc->ifp;
2979 struct ifmultiaddr *ifma;
2983 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2984 if_maddr_rlock(ifp);
2985 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2986 if (ifma->ifma_addr->sa_family != AF_LINK)
2988 if (nmcasts >= MAXMCADDR) {
2989 ifp->if_flags |= IFF_ALLMULTI;
2993 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2994 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2997 if_maddr_runlock(ifp);
2999 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
3004 * Program the multicast filter.
3006 * We have an artificial restriction that the multicast setup command
3007 * must be the first command in the chain, so we take steps to ensure
3008 * this. By requiring this, it allows us to keep up the performance of
3009 * the pre-initialized command ring (esp. link pointers) by not actually
3010 * inserting the mcsetup command in the ring - i.e. its link pointer
3011 * points to the TxCB ring, but the mcsetup descriptor itself is not part
3012 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3013 * lead into the regular TxCB ring when it completes.
3016 fxp_mc_setup(struct fxp_softc *sc)
3018 struct fxp_cb_mcs *mcsp;
3021 FXP_LOCK_ASSERT(sc, MA_OWNED);
3024 mcsp->cb_status = 0;
3025 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3026 mcsp->link_addr = 0xffffffff;
3030 * Wait until command unit is idle. This should never be the
3031 * case when nothing is queued, but make sure anyway.
3034 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3035 FXP_SCB_CUS_IDLE && --count)
3038 device_printf(sc->dev, "command queue timeout\n");
3043 * Start the multicast setup command.
3046 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3048 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3049 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3050 /* ...and wait for it to complete. */
3051 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3054 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3055 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3056 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3057 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3058 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3059 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3060 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3062 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3064 static const struct ucode {
3068 u_short int_delay_offset;
3069 u_short bundle_max_offset;
3071 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3072 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3073 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3074 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3075 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3076 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3077 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3078 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3079 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3080 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3081 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3082 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3083 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3084 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3085 { 0, NULL, 0, 0, 0 }
3089 fxp_load_ucode(struct fxp_softc *sc)
3091 const struct ucode *uc;
3092 struct fxp_cb_ucode *cbp;
3095 if (sc->flags & FXP_FLAG_NO_UCODE)
3098 for (uc = ucode_table; uc->ucode != NULL; uc++)
3099 if (sc->revision == uc->revision)
3101 if (uc->ucode == NULL)
3103 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3105 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3106 cbp->link_addr = 0xffffffff; /* (no) next command */
3107 for (i = 0; i < uc->length; i++)
3108 cbp->ucode[i] = htole32(uc->ucode[i]);
3109 if (uc->int_delay_offset)
3110 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3111 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3112 if (uc->bundle_max_offset)
3113 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3114 htole16(sc->tunable_bundle_max);
3116 * Download the ucode to the chip.
3119 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3120 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3121 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3122 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3123 /* ...and wait for it to complete. */
3124 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3125 device_printf(sc->dev,
3126 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3127 sc->tunable_int_delay,
3128 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3129 sc->flags |= FXP_FLAG_UCODE;
3130 bzero(cbp, FXP_TXCB_SZ);
3133 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3134 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3137 fxp_sysctl_node(struct fxp_softc *sc)
3139 struct sysctl_ctx_list *ctx;
3140 struct sysctl_oid_list *child, *parent;
3141 struct sysctl_oid *tree;
3142 struct fxp_hwstats *hsp;
3144 ctx = device_get_sysctl_ctx(sc->dev);
3145 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3147 SYSCTL_ADD_PROC(ctx, child,
3148 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3149 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3150 "FXP driver receive interrupt microcode bundling delay");
3151 SYSCTL_ADD_PROC(ctx, child,
3152 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3153 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3154 "FXP driver receive interrupt microcode bundle size limit");
3155 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3159 * Pull in device tunables.
3161 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3162 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3163 (void) resource_int_value(device_get_name(sc->dev),
3164 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3165 (void) resource_int_value(device_get_name(sc->dev),
3166 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3169 hsp = &sc->fxp_hwstats;
3170 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3171 NULL, "FXP statistics");
3172 parent = SYSCTL_CHILDREN(tree);
3174 /* Rx MAC statistics. */
3175 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3176 NULL, "Rx MAC statistics");
3177 child = SYSCTL_CHILDREN(tree);
3178 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3179 &hsp->rx_good, "Good frames");
3180 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3181 &hsp->rx_crc_errors, "CRC errors");
3182 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3183 &hsp->rx_alignment_errors, "Alignment errors");
3184 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3185 &hsp->rx_rnr_errors, "RNR errors");
3186 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3187 &hsp->rx_overrun_errors, "Overrun errors");
3188 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3189 &hsp->rx_cdt_errors, "Collision detect errors");
3190 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3191 &hsp->rx_shortframes, "Short frame errors");
3192 if (sc->revision >= FXP_REV_82558_A4) {
3193 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3194 &hsp->rx_pause, "Pause frames");
3195 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3196 &hsp->rx_controls, "Unsupported control frames");
3198 if (sc->revision >= FXP_REV_82559_A0)
3199 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3200 &hsp->rx_tco, "TCO frames");
3202 /* Tx MAC statistics. */
3203 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3204 NULL, "Tx MAC statistics");
3205 child = SYSCTL_CHILDREN(tree);
3206 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3207 &hsp->tx_good, "Good frames");
3208 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3209 &hsp->tx_maxcols, "Maximum collisions errors");
3210 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3211 &hsp->tx_latecols, "Late collisions errors");
3212 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3213 &hsp->tx_underruns, "Underrun errors");
3214 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3215 &hsp->tx_lostcrs, "Lost carrier sense");
3216 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3217 &hsp->tx_deffered, "Deferred");
3218 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3219 &hsp->tx_single_collisions, "Single collisions");
3220 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3221 &hsp->tx_multiple_collisions, "Multiple collisions");
3222 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3223 &hsp->tx_total_collisions, "Total collisions");
3224 if (sc->revision >= FXP_REV_82558_A4)
3225 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3226 &hsp->tx_pause, "Pause frames");
3227 if (sc->revision >= FXP_REV_82559_A0)
3228 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3229 &hsp->tx_tco, "TCO frames");
3232 #undef FXP_SYSCTL_STAT_ADD
3235 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3239 value = *(int *)arg1;
3240 error = sysctl_handle_int(oidp, &value, 0, req);
3241 if (error || !req->newptr)
3243 if (value < low || value > high)
3245 *(int *)arg1 = value;
3250 * Interrupt delay is expressed in microseconds, a multiplier is used
3251 * to convert this to the appropriate clock ticks before using.
3254 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3257 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3261 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3264 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
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