2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/apicvar.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/md_var.h>
45 #include <machine/specialreg.h>
47 #define CORE_CPUID_REQUEST 0xA
48 #define CORE_CPUID_REQUEST_SIZE 0x4
49 #define CORE_CPUID_EAX 0x0
50 #define CORE_CPUID_EBX 0x1
51 #define CORE_CPUID_ECX 0x2
52 #define CORE_CPUID_EDX 0x3
54 #define IAF_PMC_CAPS \
55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
56 PMC_CAP_USER | PMC_CAP_SYSTEM)
57 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
59 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
64 * "Architectural" events defined by Intel. The values of these
65 * symbols correspond to positions in the bitmask returned by
66 * the CPUID.0AH instruction.
68 enum core_arch_events {
69 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
70 CORE_AE_BRANCH_MISSES_RETIRED = 6,
71 CORE_AE_INSTRUCTION_RETIRED = 1,
72 CORE_AE_LLC_MISSES = 4,
73 CORE_AE_LLC_REFERENCE = 3,
74 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
75 CORE_AE_UNHALTED_CORE_CYCLES = 0
78 static enum pmc_cputype core_cputype;
81 volatile uint32_t pc_resync;
82 volatile uint32_t pc_iafctrl; /* Fixed function control. */
83 volatile uint64_t pc_globalctrl; /* Global control register. */
84 struct pmc_hw pc_corepmcs[];
87 static struct core_cpu **core_pcpu;
89 static uint32_t core_architectural_events;
90 static uint64_t core_pmcmask;
92 static int core_iaf_ri; /* relative index of fixed counters */
93 static int core_iaf_width;
94 static int core_iaf_npmc;
96 static int core_iap_width;
97 static int core_iap_npmc;
100 core_pcpu_noop(struct pmc_mdep *md, int cpu)
108 core_pcpu_init(struct pmc_mdep *md, int cpu)
113 int core_ri, n, npmc;
115 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
116 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
118 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
120 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
121 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
123 if (core_cputype != PMC_CPU_INTEL_CORE)
124 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
126 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
127 M_PMC, M_WAITOK | M_ZERO);
132 KASSERT(pc != NULL && cc != NULL,
133 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
135 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
136 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
137 PMC_PHW_CPU_TO_STATE(cpu) |
138 PMC_PHW_INDEX_TO_STATE(n + core_ri);
140 pc->pc_hwpmcs[n + core_ri] = phw;
147 core_pcpu_fini(struct pmc_mdep *md, int cpu)
149 int core_ri, n, npmc;
154 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
155 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
157 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
159 if ((cc = core_pcpu[cpu]) == NULL)
162 core_pcpu[cpu] = NULL;
166 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
169 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
170 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
172 for (n = 0; n < npmc; n++) {
173 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
174 wrmsr(IAP_EVSEL0 + n, msr);
177 if (core_cputype != PMC_CPU_INTEL_CORE) {
178 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
179 wrmsr(IAF_CTRL, msr);
180 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
183 for (n = 0; n < npmc; n++)
184 pc->pc_hwpmcs[n + core_ri] = NULL;
192 * Fixed function counters.
196 iaf_perfctr_value_to_reload_count(pmc_value_t v)
198 v &= (1ULL << core_iaf_width) - 1;
199 return (1ULL << core_iaf_width) - v;
203 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
205 return (1ULL << core_iaf_width) - rlc;
209 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
210 const struct pmc_op_pmcallocate *a)
213 uint32_t caps, flags, validflags;
215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
216 ("[core,%d] illegal CPU %d", __LINE__, cpu));
218 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
220 if (ri < 0 || ri > core_iaf_npmc)
225 if (a->pm_class != PMC_CLASS_IAF ||
226 (caps & IAF_PMC_CAPS) != caps)
230 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
233 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
237 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
240 flags = a->pm_md.pm_iaf.pm_iaf_flags;
242 validflags = IAF_MASK;
244 if (core_cputype != PMC_CPU_INTEL_ATOM)
245 validflags &= ~IAF_ANY;
247 if ((flags & ~validflags) != 0)
250 if (caps & PMC_CAP_INTERRUPT)
252 if (caps & PMC_CAP_SYSTEM)
254 if (caps & PMC_CAP_USER)
256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
257 flags |= (IAF_OS | IAF_USR);
259 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
261 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
262 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
268 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
271 ("[core,%d] illegal CPU %d", __LINE__, cpu));
273 KASSERT(ri >= 0 && ri < core_iaf_npmc,
274 ("[core,%d] illegal row-index %d", __LINE__, ri));
276 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
281 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
287 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
291 char iaf_name[PMC_NAME_MAX];
293 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
295 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
296 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
300 pi->pm_class = PMC_CLASS_IAF;
302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
303 pi->pm_enabled = TRUE;
304 *ppmc = phw->phw_pmc;
306 pi->pm_enabled = FALSE;
314 iaf_get_config(int cpu, int ri, struct pmc **ppm)
316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
322 iaf_get_msr(int ri, uint32_t *msr)
324 KASSERT(ri >= 0 && ri < core_iaf_npmc,
325 ("[iaf,%d] ri %d out of range", __LINE__, ri));
327 *msr = IAF_RI_TO_MSR(ri);
333 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
339 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
340 KASSERT(ri >= 0 && ri < core_iaf_npmc,
341 ("[core,%d] illegal row-index %d", __LINE__, ri));
343 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
346 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
347 ri, ri + core_iaf_ri));
349 tmp = rdpmc(IAF_RI_TO_MSR(ri));
351 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
352 *v = iaf_perfctr_value_to_reload_count(tmp);
356 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
357 IAF_RI_TO_MSR(ri), *v);
363 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
365 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
367 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
368 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
369 KASSERT(ri >= 0 && ri < core_iaf_npmc,
370 ("[core,%d] illegal row-index %d", __LINE__, ri));
372 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
373 ("[core,%d] PHW pmc non-NULL", __LINE__));
379 iaf_start_pmc(int cpu, int ri)
382 struct core_cpu *iafc;
385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
386 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
387 KASSERT(ri >= 0 && ri < core_iaf_npmc,
388 ("[core,%d] illegal row-index %d", __LINE__, ri));
390 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
392 iafc = core_pcpu[cpu];
393 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
395 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
397 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
398 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
402 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
403 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
404 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
405 IAF_GLOBAL_CTRL_MASK));
406 } while (iafc->pc_resync != 0);
408 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
409 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
410 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
416 iaf_stop_pmc(int cpu, int ri)
419 struct core_cpu *iafc;
422 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
424 iafc = core_pcpu[cpu];
426 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
427 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
428 KASSERT(ri >= 0 && ri < core_iaf_npmc,
429 ("[core,%d] illegal row-index %d", __LINE__, ri));
431 fc = (IAF_MASK << (ri * 4));
433 if (core_cputype != PMC_CPU_INTEL_ATOM)
436 iafc->pc_iafctrl &= ~fc;
438 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
439 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
440 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
444 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
445 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
446 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
447 IAF_GLOBAL_CTRL_MASK));
448 } while (iafc->pc_resync != 0);
450 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
451 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
452 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
458 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
465 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
466 KASSERT(ri >= 0 && ri < core_iaf_npmc,
467 ("[core,%d] illegal row-index %d", __LINE__, ri));
470 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
473 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
475 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
476 v = iaf_reload_count_to_perfctr_value(v);
478 /* Turn off fixed counters */
479 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
480 wrmsr(IAF_CTRL, msr);
482 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
484 /* Turn on fixed counters */
485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
486 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
488 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
489 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
490 (uintmax_t) rdmsr(IAF_CTRL),
491 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
498 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
500 struct pmc_classdep *pcd;
502 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
504 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
506 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
508 pcd->pcd_caps = IAF_PMC_CAPS;
509 pcd->pcd_class = PMC_CLASS_IAF;
511 pcd->pcd_ri = md->pmd_npmc;
512 pcd->pcd_width = pmcwidth;
514 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
515 pcd->pcd_config_pmc = iaf_config_pmc;
516 pcd->pcd_describe = iaf_describe;
517 pcd->pcd_get_config = iaf_get_config;
518 pcd->pcd_get_msr = iaf_get_msr;
519 pcd->pcd_pcpu_fini = core_pcpu_noop;
520 pcd->pcd_pcpu_init = core_pcpu_noop;
521 pcd->pcd_read_pmc = iaf_read_pmc;
522 pcd->pcd_release_pmc = iaf_release_pmc;
523 pcd->pcd_start_pmc = iaf_start_pmc;
524 pcd->pcd_stop_pmc = iaf_stop_pmc;
525 pcd->pcd_write_pmc = iaf_write_pmc;
527 md->pmd_npmc += npmc;
531 * Intel programmable PMCs.
535 * Event descriptor tables.
537 * For each event id, we track:
539 * 1. The CPUs that the event is valid for.
541 * 2. If the event uses a fixed UMASK, the value of the umask field.
542 * If the event doesn't use a fixed UMASK, a mask of legal bits
546 struct iap_event_descr {
547 enum pmc_event iap_ev;
548 unsigned char iap_evcode;
549 unsigned char iap_umask;
550 unsigned int iap_flags;
553 #define IAP_F_CC (1 << 0) /* CPU: Core */
554 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
555 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
556 #define IAP_F_CA (1 << 3) /* CPU: Atom */
557 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
558 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
559 #define IAP_F_WM (1 << 5) /* CPU: Westmere */
560 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */
561 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */
562 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */
563 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */
564 #define IAP_F_HW (1 << 10) /* CPU: Haswell */
565 #define IAP_F_FM (1 << 11) /* Fixed mask */
567 #define IAP_F_ALLCPUSCORE2 \
568 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
570 /* Sub fields of UMASK that this event supports. */
571 #define IAP_M_CORE (1 << 0) /* Core specificity */
572 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
573 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
574 #define IAP_M_MESI (1 << 3) /* MESI */
575 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
576 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
577 #define IAP_M_TRANSITION (1 << 6) /* Transition */
579 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
580 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
581 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
582 #define IAP_F_MESI (0xF << 8) /* MESI */
583 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
584 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
585 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
587 #define IAP_PREFETCH_RESERVED (0x2 << 12)
588 #define IAP_CORE_THIS (0x1 << 14)
589 #define IAP_CORE_ALL (0x3 << 14)
590 #define IAP_F_CMASK 0xFF000000
592 static struct iap_event_descr iap_events[] = {
594 #define IAPDESCR(N,EV,UM,FLAGS) { \
595 .iap_ev = PMC_EV_IAP_EVENT_##N, \
596 .iap_evcode = (EV), \
598 .iap_flags = (FLAGS) \
601 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
602 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
604 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
605 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
607 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
608 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
609 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
610 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
612 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
614 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
616 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
617 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
618 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
619 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
620 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
622 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
623 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
624 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
625 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB |
626 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
627 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
629 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
630 IAP_F_CC2E | IAP_F_CA),
631 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
632 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
633 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
634 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
635 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
637 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
638 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
639 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
641 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
642 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
643 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
644 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB |
647 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
648 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
649 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
650 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
651 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
652 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
653 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
654 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
655 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
656 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
657 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
658 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW),
659 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
660 IAP_F_SBX | IAP_F_HW),
661 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
662 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
663 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW),
664 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
665 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
666 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
667 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
669 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
670 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
671 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
672 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
674 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
675 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
676 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
678 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
680 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
681 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
683 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
684 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
686 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
687 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
688 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
689 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
690 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
691 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
693 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
694 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
695 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
696 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
697 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
698 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
700 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
701 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
702 IAP_F_WM | IAP_F_SB | IAP_F_SBX),
703 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
704 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
705 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
706 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
708 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
710 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
712 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
714 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
716 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
717 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB |
719 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
720 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
722 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
723 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
724 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
725 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
726 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
727 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
728 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
729 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
730 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
732 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
733 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
735 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
736 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
737 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
739 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
740 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
741 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
742 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
744 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
747 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
748 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
750 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
751 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
752 IAP_F_I7 | IAP_F_WM),
753 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
755 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
756 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
757 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
759 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
761 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
762 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
763 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
764 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
766 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
767 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
768 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
769 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
770 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
771 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
772 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
773 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
774 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
775 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
776 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
777 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
778 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
779 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
780 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
781 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
782 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW),
783 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW),
784 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW),
785 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW),
786 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
787 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
788 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
789 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
790 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW),
791 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW),
792 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW),
793 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW),
794 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
795 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
796 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
797 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
798 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW),
799 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW),
800 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW),
801 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW),
802 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
803 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW),
804 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW),
805 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
807 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
809 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
810 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
811 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
812 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
813 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
814 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
815 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
816 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
817 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
818 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
819 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
820 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
822 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
823 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
824 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
825 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
826 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
828 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
829 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
830 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
831 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
832 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
833 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
834 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
835 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
836 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW),
837 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
838 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
839 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
841 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
842 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
843 IAP_F_SBX | IAP_F_IBX),
844 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX),
845 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
846 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
847 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
848 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
849 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
850 IAP_F_SBX | IAP_F_IBX),
852 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
853 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
854 IAP_F_CA | IAP_F_CC2),
855 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
856 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
858 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
860 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
861 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
862 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
863 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
864 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
865 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
867 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
869 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
870 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
872 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
873 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
875 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
877 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
878 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
880 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
881 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
883 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
885 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
887 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
888 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
889 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
890 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
891 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
892 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
893 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
895 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
896 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
897 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
898 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
899 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
900 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
901 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
903 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
904 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
905 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
906 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
907 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
908 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
910 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
912 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
913 IAP_F_CC2 | IAP_F_I7),
915 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
917 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
919 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
920 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
922 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
923 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
924 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
925 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
927 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
928 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
929 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
931 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
932 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
934 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB |
935 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
936 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW),
937 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
938 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
939 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
940 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
941 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW),
942 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW),
944 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
945 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
946 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
947 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
948 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
950 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
951 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
952 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
953 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
954 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
956 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
958 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
959 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
960 IAP_F_SB | IAP_F_SBX),
961 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
962 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
964 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
965 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
966 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
967 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
968 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
970 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
971 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
972 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
973 IAP_F_SB | IAP_F_SBX),
974 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
975 IAP_F_SB | IAP_F_SBX),
976 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
977 IAP_F_SB | IAP_F_SBX),
979 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
981 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
983 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
984 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
985 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
986 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
988 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
989 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
990 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
992 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
993 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
994 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
995 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
997 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
998 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
999 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1000 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1002 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1003 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1005 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB),
1006 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX),
1008 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1009 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1010 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1011 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1012 IAP_F_IBX | IAP_F_HW),
1013 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1014 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1015 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1016 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1018 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1019 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
1021 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
1022 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
1024 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
1025 IAP_F_CA | IAP_F_CC2),
1026 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
1027 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1028 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1029 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1030 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1032 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1033 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
1035 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
1036 IAP_F_CA | IAP_F_CC2),
1037 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
1039 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1041 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1042 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
1044 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1045 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1046 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1047 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1049 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1050 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1052 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1053 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
1055 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1056 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
1058 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1059 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
1061 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1062 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
1064 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
1065 IAP_F_CA | IAP_F_CC2),
1066 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
1068 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
1069 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
1071 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1072 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1073 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1074 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1075 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1076 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1077 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1078 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1079 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1080 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1081 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1082 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1083 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1084 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1085 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1087 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1089 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1091 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1093 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1094 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
1096 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1098 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1099 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1100 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1101 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1102 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1104 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1106 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1107 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
1108 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
1110 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1111 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1112 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
1113 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1114 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
1115 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
1117 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
1118 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1120 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
1121 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1122 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1123 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1124 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1125 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1126 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1127 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW),
1128 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
1129 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1130 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1131 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1132 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW),
1133 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1135 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1137 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1138 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1139 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1140 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1141 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1142 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1143 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1144 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1146 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1147 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1148 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1149 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1150 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1151 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1152 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1153 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1154 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1155 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1156 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1157 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1158 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1159 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1160 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1161 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1162 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1163 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1164 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1165 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1166 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1167 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1169 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1170 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1171 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1172 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1173 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1174 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1175 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1176 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1177 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1178 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1179 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1180 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1181 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1182 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1183 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1184 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1185 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1186 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1187 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1188 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1189 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1191 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1192 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1193 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1194 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1195 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1196 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1198 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1199 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1200 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1201 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1202 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1204 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1205 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1207 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1208 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1209 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1211 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1212 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1213 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1214 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1215 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1216 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1217 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1219 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1220 IAP_F_SBX | IAP_F_IBX),
1221 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1222 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1223 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1224 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1225 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1226 IAP_F_SBX | IAP_F_IBX),
1227 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1228 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1229 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1230 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1232 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1233 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1234 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1235 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1236 IAP_F_SB | IAP_F_SBX),
1237 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1239 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1240 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1241 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1242 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1243 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1244 IAP_F_SB | IAP_F_SBX),
1245 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1246 IAP_F_SB | IAP_F_SBX),
1247 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1248 IAP_F_SB | IAP_F_SBX),
1250 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1251 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1252 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1253 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW),
1254 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1256 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1257 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1258 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1260 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1261 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1262 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1263 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1265 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1266 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1267 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1268 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1270 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1271 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1272 IAP_F_SBX | IAP_F_IBX),
1273 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1275 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1276 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1278 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1279 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1280 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1281 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1282 IAP_F_IBX | IAP_F_HW),
1283 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1284 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1285 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1286 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1287 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1288 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1289 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1290 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1292 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1293 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1294 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1295 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1296 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1297 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1298 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1299 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1300 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1301 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1302 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1303 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1304 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1307 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1308 IAP_F_SB | IAP_F_SBX),
1310 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1311 IAP_F_WM | IAP_F_I7O),
1312 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1313 IAP_F_WM | IAP_F_I7O),
1314 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1315 IAP_F_WM | IAP_F_I7O),
1316 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1317 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1318 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1319 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1320 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1321 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1322 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1323 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1324 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1326 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1327 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1328 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1330 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1332 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1333 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1335 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1336 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1337 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1339 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1340 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1342 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1343 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1345 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW),
1346 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW),
1347 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW),
1348 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW),
1349 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW),
1350 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW),
1351 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW),
1352 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW),
1354 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1355 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1356 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1357 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1359 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1361 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1362 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1363 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1364 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1365 IAP_F_IBX | IAP_F_HW),
1366 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1367 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1368 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1369 IAP_F_I7 | IAP_F_WM),
1370 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1372 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1373 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1374 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1375 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1376 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1377 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1378 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1379 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1380 IAP_F_SBX | IAP_F_IBX),
1381 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW),
1382 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1384 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1385 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1386 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1387 IAP_F_IBX | IAP_F_HW),
1388 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1389 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1390 IAP_F_IBX | IAP_F_HW),
1391 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1392 IAP_F_I7 | IAP_F_WM),
1393 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1394 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1395 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1396 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1398 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1399 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1400 IAP_F_I7 | IAP_F_WM),
1401 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1402 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1403 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1404 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1405 IAP_F_IBX | IAP_F_HW),
1406 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1407 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1408 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1410 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1411 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1412 IAP_F_IBX | IAP_F_HW),
1413 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1414 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1415 IAP_F_IBX | IAP_F_HW),
1416 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1417 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1418 IAP_F_IBX | IAP_F_HW),
1419 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1420 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1421 IAP_F_IBX | IAP_F_HW),
1422 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1423 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1424 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1425 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1426 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1427 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1428 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1429 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1430 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1431 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1433 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1434 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1435 IAP_F_IBX | IAP_F_HW),
1436 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1437 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1438 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1439 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1440 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1441 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1442 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1443 IAP_F_SBX | IAP_F_IBX),
1444 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1445 IAP_F_SBX | IAP_F_IBX),
1447 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1448 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1449 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1451 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1452 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1453 IAP_F_I7 | IAP_F_WM),
1454 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1455 IAP_F_I7 | IAP_F_WM),
1456 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1457 IAP_F_I7 | IAP_F_WM),
1458 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1459 IAP_F_I7 | IAP_F_WM),
1460 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1461 IAP_F_I7 | IAP_F_WM),
1462 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1464 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1465 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1467 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1469 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1470 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1471 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1472 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1473 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1474 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1475 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1477 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1478 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1479 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1480 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1482 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1483 IAP_F_I7 | IAP_F_WM),
1484 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1485 IAP_F_I7 | IAP_F_WM),
1486 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1487 IAP_F_I7 | IAP_F_WM),
1488 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1489 IAP_F_I7 | IAP_F_WM),
1490 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1492 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1493 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1495 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1496 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1497 IAP_F_I7 | IAP_F_WM),
1498 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1499 IAP_F_I7 | IAP_F_WM),
1500 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1501 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1502 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1504 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1505 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1506 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1507 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1508 IAP_F_SBX | IAP_F_IBX),
1510 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1511 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1513 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1514 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1515 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1516 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1517 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1518 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1519 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1520 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1521 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1522 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1523 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1524 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1525 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1527 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1528 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1529 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1530 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1531 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1532 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1533 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1534 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW),
1535 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1536 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1537 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1539 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1540 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1541 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1542 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1543 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1544 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1545 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1546 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1547 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1548 IAP_F_I7 | IAP_F_WM),
1549 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1551 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX |
1552 IAP_F_IBX | IAP_F_HW),
1553 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1554 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX),
1555 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX),
1557 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1558 IAP_F_I7 | IAP_F_WM),
1559 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1560 IAP_F_SB | IAP_F_SBX),
1561 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1562 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1563 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1565 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1566 IAP_F_I7 | IAP_F_WM),
1567 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1568 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1569 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1570 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1572 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1574 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1575 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1576 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1577 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1578 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1580 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1581 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1582 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1583 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1585 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1586 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1587 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1589 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1590 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1592 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1593 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1594 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1595 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1596 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1597 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1599 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1600 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1603 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1605 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1606 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1608 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1610 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1611 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1612 IAP_F_WM | IAP_F_SBX),
1613 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1614 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1616 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1617 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1618 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O),
1620 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1622 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1623 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1624 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1625 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1626 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1627 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1628 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1629 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1630 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1631 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1632 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1633 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1634 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1635 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1636 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1637 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1638 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1640 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1641 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1642 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1643 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1644 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1645 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1646 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1647 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1649 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1650 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1651 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1652 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1653 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1654 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1655 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW),
1656 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW),
1657 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1658 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1659 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1661 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1663 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1664 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1665 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1666 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1667 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1668 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1670 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1671 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1672 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1673 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1674 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1675 IAP_F_SB | IAP_F_SBX),
1677 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1679 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1680 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1681 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1683 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1684 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1686 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1687 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1688 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1689 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1690 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1691 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1692 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1695 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1698 iap_perfctr_value_to_reload_count(pmc_value_t v)
1700 v &= (1ULL << core_iap_width) - 1;
1701 return (1ULL << core_iap_width) - v;
1705 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1707 return (1ULL << core_iap_width) - rlc;
1711 iap_pmc_has_overflowed(int ri)
1716 * We treat a Core (i.e., Intel architecture v1) PMC as has
1717 * having overflowed if its MSB is zero.
1720 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1724 * Check an event against the set of supported architectural events.
1726 * Returns 1 if the event is architectural and unsupported on this
1727 * CPU. Returns 0 otherwise.
1731 iap_architectural_event_is_unsupported(enum pmc_event pe)
1733 enum core_arch_events ae;
1736 case PMC_EV_IAP_EVENT_3CH_00H:
1737 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1739 case PMC_EV_IAP_EVENT_C0H_00H:
1740 ae = CORE_AE_INSTRUCTION_RETIRED;
1742 case PMC_EV_IAP_EVENT_3CH_01H:
1743 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1745 case PMC_EV_IAP_EVENT_2EH_4FH:
1746 ae = CORE_AE_LLC_REFERENCE;
1748 case PMC_EV_IAP_EVENT_2EH_41H:
1749 ae = CORE_AE_LLC_MISSES;
1751 case PMC_EV_IAP_EVENT_C4H_00H:
1752 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1754 case PMC_EV_IAP_EVENT_C5H_00H:
1755 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1758 default: /* Non architectural event. */
1762 return ((core_architectural_events & (1 << ae)) == 0);
1766 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1772 * Events valid only on counter 0, 1.
1774 case PMC_EV_IAP_EVENT_40H_01H:
1775 case PMC_EV_IAP_EVENT_40H_02H:
1776 case PMC_EV_IAP_EVENT_40H_04H:
1777 case PMC_EV_IAP_EVENT_40H_08H:
1778 case PMC_EV_IAP_EVENT_40H_0FH:
1779 case PMC_EV_IAP_EVENT_41H_02H:
1780 case PMC_EV_IAP_EVENT_41H_04H:
1781 case PMC_EV_IAP_EVENT_41H_08H:
1782 case PMC_EV_IAP_EVENT_42H_01H:
1783 case PMC_EV_IAP_EVENT_42H_02H:
1784 case PMC_EV_IAP_EVENT_42H_04H:
1785 case PMC_EV_IAP_EVENT_42H_08H:
1786 case PMC_EV_IAP_EVENT_43H_01H:
1787 case PMC_EV_IAP_EVENT_43H_02H:
1788 case PMC_EV_IAP_EVENT_51H_01H:
1789 case PMC_EV_IAP_EVENT_51H_02H:
1790 case PMC_EV_IAP_EVENT_51H_04H:
1791 case PMC_EV_IAP_EVENT_51H_08H:
1792 case PMC_EV_IAP_EVENT_63H_01H:
1793 case PMC_EV_IAP_EVENT_63H_02H:
1798 mask = ~0; /* Any row index is ok. */
1801 return (mask & (1 << ri));
1805 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1811 * Events valid only on counter 0.
1813 case PMC_EV_IAP_EVENT_60H_01H:
1814 case PMC_EV_IAP_EVENT_60H_02H:
1815 case PMC_EV_IAP_EVENT_60H_04H:
1816 case PMC_EV_IAP_EVENT_60H_08H:
1817 case PMC_EV_IAP_EVENT_B3H_01H:
1818 case PMC_EV_IAP_EVENT_B3H_02H:
1819 case PMC_EV_IAP_EVENT_B3H_04H:
1824 * Events valid only on counter 0, 1.
1826 case PMC_EV_IAP_EVENT_4CH_01H:
1827 case PMC_EV_IAP_EVENT_4EH_01H:
1828 case PMC_EV_IAP_EVENT_4EH_02H:
1829 case PMC_EV_IAP_EVENT_4EH_04H:
1830 case PMC_EV_IAP_EVENT_51H_01H:
1831 case PMC_EV_IAP_EVENT_51H_02H:
1832 case PMC_EV_IAP_EVENT_51H_04H:
1833 case PMC_EV_IAP_EVENT_51H_08H:
1834 case PMC_EV_IAP_EVENT_63H_01H:
1835 case PMC_EV_IAP_EVENT_63H_02H:
1840 mask = ~0; /* Any row index is ok. */
1843 return (mask & (1 << ri));
1847 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri)
1852 /* Events valid only on counter 0. */
1853 case PMC_EV_IAP_EVENT_B7H_01H:
1856 /* Events valid only on counter 1. */
1857 case PMC_EV_IAP_EVENT_C0H_01H:
1860 /* Events valid only on counter 2. */
1861 case PMC_EV_IAP_EVENT_48H_01H:
1862 case PMC_EV_IAP_EVENT_A2H_02H:
1865 /* Events valid only on counter 3. */
1866 case PMC_EV_IAP_EVENT_A3H_08H:
1867 case PMC_EV_IAP_EVENT_BBH_01H:
1868 case PMC_EV_IAP_EVENT_CDH_01H:
1869 case PMC_EV_IAP_EVENT_CDH_02H:
1873 mask = ~0; /* Any row index is ok. */
1876 return (mask & (1 << ri));
1880 iap_event_ok_on_counter(enum pmc_event pe, int ri)
1886 * Events valid only on counter 0.
1888 case PMC_EV_IAP_EVENT_10H_00H:
1889 case PMC_EV_IAP_EVENT_14H_00H:
1890 case PMC_EV_IAP_EVENT_18H_00H:
1891 case PMC_EV_IAP_EVENT_B3H_01H:
1892 case PMC_EV_IAP_EVENT_B3H_02H:
1893 case PMC_EV_IAP_EVENT_B3H_04H:
1894 case PMC_EV_IAP_EVENT_C1H_00H:
1895 case PMC_EV_IAP_EVENT_CBH_01H:
1896 case PMC_EV_IAP_EVENT_CBH_02H:
1901 * Events valid only on counter 1.
1903 case PMC_EV_IAP_EVENT_11H_00H:
1904 case PMC_EV_IAP_EVENT_12H_00H:
1905 case PMC_EV_IAP_EVENT_13H_00H:
1910 mask = ~0; /* Any row index is ok. */
1913 return (mask & (1 << ri));
1917 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1918 const struct pmc_op_pmcallocate *a)
1922 struct iap_event_descr *ie;
1923 uint32_t c, caps, config, cpuflag, evsel, mask;
1925 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1926 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1927 KASSERT(ri >= 0 && ri < core_iap_npmc,
1928 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1930 /* check requested capabilities */
1932 if ((IAP_PMC_CAPS & caps) != caps)
1937 if (iap_architectural_event_is_unsupported(ev))
1938 return (EOPNOTSUPP);
1941 * A small number of events are not supported in all the
1942 * processors based on a given microarchitecture.
1944 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) {
1945 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
1946 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)
1950 switch (core_cputype) {
1951 case PMC_CPU_INTEL_COREI7:
1952 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1955 case PMC_CPU_INTEL_SANDYBRIDGE:
1956 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
1957 case PMC_CPU_INTEL_IVYBRIDGE:
1958 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
1959 case PMC_CPU_INTEL_HASWELL:
1960 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
1963 case PMC_CPU_INTEL_WESTMERE:
1964 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1968 if (iap_event_ok_on_counter(ev, ri) == 0)
1973 * Look for an event descriptor with matching CPU and event id
1977 switch (core_cputype) {
1979 case PMC_CPU_INTEL_ATOM:
1982 case PMC_CPU_INTEL_CORE:
1985 case PMC_CPU_INTEL_CORE2:
1986 cpuflag = IAP_F_CC2;
1988 case PMC_CPU_INTEL_CORE2EXTREME:
1989 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
1991 case PMC_CPU_INTEL_COREI7:
1994 case PMC_CPU_INTEL_HASWELL:
1997 case PMC_CPU_INTEL_IVYBRIDGE:
2000 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2001 cpuflag = IAP_F_IBX;
2003 case PMC_CPU_INTEL_SANDYBRIDGE:
2006 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2007 cpuflag = IAP_F_SBX;
2009 case PMC_CPU_INTEL_WESTMERE:
2014 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
2015 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
2018 if (n == niap_events)
2022 * A matching event descriptor has been found, so start
2023 * assembling the contents of the event select register.
2025 evsel = ie->iap_evcode;
2027 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
2030 * If the event uses a fixed umask value, reject any umask
2031 * bits set by the user.
2033 if (ie->iap_flags & IAP_F_FM) {
2035 if (IAP_UMASK(config) != 0)
2038 evsel |= (ie->iap_umask << 8);
2043 * Otherwise, the UMASK value needs to be taken from
2044 * the MD fields of the allocation request. Reject
2045 * requests that specify reserved bits.
2050 if (ie->iap_umask & IAP_M_CORE) {
2051 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
2057 if (ie->iap_umask & IAP_M_AGENT)
2058 mask |= IAP_F_AGENT;
2060 if (ie->iap_umask & IAP_M_PREFETCH) {
2062 if ((c = (config & IAP_F_PREFETCH)) ==
2063 IAP_PREFETCH_RESERVED)
2066 mask |= IAP_F_PREFETCH;
2069 if (ie->iap_umask & IAP_M_MESI)
2072 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
2073 mask |= IAP_F_SNOOPRESPONSE;
2075 if (ie->iap_umask & IAP_M_SNOOPTYPE)
2076 mask |= IAP_F_SNOOPTYPE;
2078 if (ie->iap_umask & IAP_M_TRANSITION)
2079 mask |= IAP_F_TRANSITION;
2082 * If bits outside of the allowed set of umask bits
2083 * are set, reject the request.
2088 evsel |= (config & mask);
2093 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
2095 if (core_cputype == PMC_CPU_INTEL_ATOM ||
2096 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2097 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON)
2098 evsel |= (config & IAP_ANY);
2099 else if (config & IAP_ANY)
2103 * Check offcore response configuration.
2105 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
2106 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
2107 ev != PMC_EV_IAP_EVENT_BBH_01H)
2109 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
2110 ev == PMC_EV_IAP_EVENT_BBH_01H)
2112 if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
2113 core_cputype == PMC_CPU_INTEL_WESTMERE) &&
2114 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
2116 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2117 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
2118 core_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
2119 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) &&
2120 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
2122 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
2125 if (caps & PMC_CAP_THRESHOLD)
2126 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
2127 if (caps & PMC_CAP_USER)
2129 if (caps & PMC_CAP_SYSTEM)
2131 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
2132 evsel |= (IAP_OS | IAP_USR);
2133 if (caps & PMC_CAP_EDGE)
2135 if (caps & PMC_CAP_INVERT)
2137 if (caps & PMC_CAP_INTERRUPT)
2140 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
2146 iap_config_pmc(int cpu, int ri, struct pmc *pm)
2148 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2149 ("[core,%d] illegal CPU %d", __LINE__, cpu));
2151 KASSERT(ri >= 0 && ri < core_iap_npmc,
2152 ("[core,%d] illegal row-index %d", __LINE__, ri));
2154 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
2156 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
2159 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
2165 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
2169 char iap_name[PMC_NAME_MAX];
2171 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
2173 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
2174 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
2178 pi->pm_class = PMC_CLASS_IAP;
2180 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
2181 pi->pm_enabled = TRUE;
2182 *ppmc = phw->phw_pmc;
2184 pi->pm_enabled = FALSE;
2192 iap_get_config(int cpu, int ri, struct pmc **ppm)
2194 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2200 iap_get_msr(int ri, uint32_t *msr)
2202 KASSERT(ri >= 0 && ri < core_iap_npmc,
2203 ("[iap,%d] ri %d out of range", __LINE__, ri));
2211 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
2216 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2217 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2218 KASSERT(ri >= 0 && ri < core_iap_npmc,
2219 ("[core,%d] illegal row-index %d", __LINE__, ri));
2221 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2224 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
2228 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2229 *v = iap_perfctr_value_to_reload_count(tmp);
2231 *v = tmp & ((1ULL << core_iap_width) - 1);
2233 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
2240 iap_release_pmc(int cpu, int ri, struct pmc *pm)
2244 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
2247 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2248 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2249 KASSERT(ri >= 0 && ri < core_iap_npmc,
2250 ("[core,%d] illegal row-index %d", __LINE__, ri));
2252 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
2253 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
2259 iap_start_pmc(int cpu, int ri)
2263 struct core_cpu *cc;
2265 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2266 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2267 KASSERT(ri >= 0 && ri < core_iap_npmc,
2268 ("[core,%d] illegal row-index %d", __LINE__, ri));
2270 cc = core_pcpu[cpu];
2271 pm = cc->pc_corepmcs[ri].phw_pmc;
2274 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
2275 __LINE__, cpu, ri));
2277 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
2279 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
2281 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
2282 cpu, ri, IAP_EVSEL0 + ri, evsel);
2284 /* Event specific configuration. */
2285 switch (pm->pm_event) {
2286 case PMC_EV_IAP_EVENT_B7H_01H:
2287 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
2289 case PMC_EV_IAP_EVENT_BBH_01H:
2290 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
2296 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
2298 if (core_cputype == PMC_CPU_INTEL_CORE)
2303 cc->pc_globalctrl |= (1ULL << ri);
2304 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2305 } while (cc->pc_resync != 0);
2311 iap_stop_pmc(int cpu, int ri)
2314 struct core_cpu *cc;
2317 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2318 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2319 KASSERT(ri >= 0 && ri < core_iap_npmc,
2320 ("[core,%d] illegal row index %d", __LINE__, ri));
2322 cc = core_pcpu[cpu];
2323 pm = cc->pc_corepmcs[ri].phw_pmc;
2326 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2329 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
2331 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2332 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
2334 if (core_cputype == PMC_CPU_INTEL_CORE)
2340 cc->pc_globalctrl &= ~(1ULL << ri);
2341 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2342 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2343 } while (cc->pc_resync != 0);
2349 iap_write_pmc(int cpu, int ri, pmc_value_t v)
2352 struct core_cpu *cc;
2354 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2355 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2356 KASSERT(ri >= 0 && ri < core_iap_npmc,
2357 ("[core,%d] illegal row index %d", __LINE__, ri));
2359 cc = core_pcpu[cpu];
2360 pm = cc->pc_corepmcs[ri].phw_pmc;
2363 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2366 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
2369 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2370 v = iap_reload_count_to_perfctr_value(v);
2373 * Write the new value to the counter. The counter will be in
2374 * a stopped state when the pcd_write() entry point is called.
2377 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
2384 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
2387 struct pmc_classdep *pcd;
2389 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
2391 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
2393 /* Remember the set of architectural events supported. */
2394 core_architectural_events = ~flags;
2396 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
2398 pcd->pcd_caps = IAP_PMC_CAPS;
2399 pcd->pcd_class = PMC_CLASS_IAP;
2400 pcd->pcd_num = npmc;
2401 pcd->pcd_ri = md->pmd_npmc;
2402 pcd->pcd_width = pmcwidth;
2404 pcd->pcd_allocate_pmc = iap_allocate_pmc;
2405 pcd->pcd_config_pmc = iap_config_pmc;
2406 pcd->pcd_describe = iap_describe;
2407 pcd->pcd_get_config = iap_get_config;
2408 pcd->pcd_get_msr = iap_get_msr;
2409 pcd->pcd_pcpu_fini = core_pcpu_fini;
2410 pcd->pcd_pcpu_init = core_pcpu_init;
2411 pcd->pcd_read_pmc = iap_read_pmc;
2412 pcd->pcd_release_pmc = iap_release_pmc;
2413 pcd->pcd_start_pmc = iap_start_pmc;
2414 pcd->pcd_stop_pmc = iap_stop_pmc;
2415 pcd->pcd_write_pmc = iap_write_pmc;
2417 md->pmd_npmc += npmc;
2421 core_intr(int cpu, struct trapframe *tf)
2425 struct core_cpu *cc;
2426 int error, found_interrupt, ri;
2429 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2430 TRAPF_USERMODE(tf));
2432 found_interrupt = 0;
2433 cc = core_pcpu[cpu];
2435 for (ri = 0; ri < core_iap_npmc; ri++) {
2437 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2438 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2441 if (!iap_pmc_has_overflowed(ri))
2444 found_interrupt = 1;
2446 if (pm->pm_state != PMC_STATE_RUNNING)
2449 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2450 TRAPF_USERMODE(tf));
2452 v = pm->pm_sc.pm_reloadcount;
2453 v = iaf_reload_count_to_perfctr_value(v);
2456 * Stop the counter, reload it but only restart it if
2457 * the PMC is not stalled.
2459 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2460 wrmsr(IAP_EVSEL0 + ri, msr);
2461 wrmsr(IAP_PMC0 + ri, v);
2466 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2470 if (found_interrupt)
2471 lapic_reenable_pmc();
2473 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2474 &pmc_stats.pm_intr_ignored, 1);
2476 return (found_interrupt);
2480 core2_intr(int cpu, struct trapframe *tf)
2482 int error, found_interrupt, n;
2483 uint64_t flag, intrstatus, intrenable, msr;
2485 struct core_cpu *cc;
2488 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2489 TRAPF_USERMODE(tf));
2492 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2493 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2494 * the current set of interrupting PMCs and process these
2495 * after stopping them.
2497 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2498 intrenable = intrstatus & core_pmcmask;
2500 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2501 (uintmax_t) intrstatus);
2503 found_interrupt = 0;
2504 cc = core_pcpu[cpu];
2506 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2508 cc->pc_globalctrl &= ~intrenable;
2509 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2512 * Stop PMCs and clear overflow status bits.
2514 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2515 wrmsr(IA_GLOBAL_CTRL, msr);
2516 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2517 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2518 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2521 * Look for interrupts from fixed function PMCs.
2523 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2526 if ((intrstatus & flag) == 0)
2529 found_interrupt = 1;
2531 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2532 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2533 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2536 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2537 TRAPF_USERMODE(tf));
2539 intrenable &= ~flag;
2541 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2543 /* Reload sampling count. */
2544 wrmsr(IAF_CTR0 + n, v);
2546 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
2547 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2551 * Process interrupts from the programmable counters.
2553 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2554 if ((intrstatus & flag) == 0)
2557 found_interrupt = 1;
2559 pm = cc->pc_corepmcs[n].phw_pmc;
2560 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2561 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2564 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2565 TRAPF_USERMODE(tf));
2567 intrenable &= ~flag;
2569 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2571 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2574 /* Reload sampling count. */
2575 wrmsr(IAP_PMC0 + n, v);
2579 * Reenable all non-stalled PMCs.
2581 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2582 (uintmax_t) intrenable);
2584 cc->pc_globalctrl |= intrenable;
2586 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2588 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2589 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2590 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2591 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2592 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2594 if (found_interrupt)
2595 lapic_reenable_pmc();
2597 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2598 &pmc_stats.pm_intr_ignored, 1);
2600 return (found_interrupt);
2604 pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2606 int cpuid[CORE_CPUID_REQUEST_SIZE];
2607 int ipa_version, flags, nflags;
2609 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2611 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2613 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2614 md->pmd_cputype, maxcpu, ipa_version);
2616 if (ipa_version < 1 || ipa_version > 3) {
2617 /* Unknown PMC architecture. */
2618 printf("hwpc_core: unknown PMC architecture: %d\n",
2620 return (EPROGMISMATCH);
2623 core_cputype = md->pmd_cputype;
2628 * Initialize programmable counters.
2630 KASSERT(ipa_version >= 1,
2631 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2633 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2634 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2636 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2638 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2639 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2641 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2644 * Initialize fixed function counters, if present.
2646 if (core_cputype != PMC_CPU_INTEL_CORE) {
2647 KASSERT(ipa_version >= 2,
2648 ("[core,%d] ipa_version %d too small", __LINE__,
2651 core_iaf_ri = core_iap_npmc;
2652 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2653 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2655 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2656 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2659 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2662 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2666 * Choose the appropriate interrupt handler.
2668 if (ipa_version == 1)
2669 md->pmd_intr = core_intr;
2671 md->pmd_intr = core2_intr;
2673 md->pmd_pcpu_fini = NULL;
2674 md->pmd_pcpu_init = NULL;
2680 pmc_core_finalize(struct pmc_mdep *md)
2682 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2684 free(core_pcpu, M_PMC);