sys/dev/isci/scil/scic_sds_controller_registers.h

   1 /*-
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
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  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
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  25  *
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  34  *     notice, this list of conditions and the following disclaimer.
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  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *
  40  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  41  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  42  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  43  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  44  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  48  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  50  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  51  *
  52  * $FreeBSD$
  53  */
  54 #ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
  55 #define _SCIC_SDS_CONTROLLER_REGISTERS_H_
  56
  57 /**
  58  * @file
  59  *
  60  * @brief This file contains macros used to perform the register reads/writes
  61  *        to the SCU hardware.
  62  */
  63
  64 #ifdef __cplusplus
  65 extern "C" {
  66 #endif // __cplusplus
  67
  68 #include <dev/isci/scil/scu_registers.h>
  69 #include <dev/isci/scil/scic_sds_controller.h>
  70
  71 /**
  72  * @name SMU_REGISTER_ACCESS_MACROS
  73  */
  74 /*@{*/
  75 #define scic_sds_controller_smu_register_read(controller, reg) \
  76    smu_register_read( \
  77       (controller), \
  78       (controller)->smu_registers->reg \
  79    )
  80
  81 #define scic_sds_controller_smu_register_write(controller, reg, value) \
  82    smu_register_write( \
  83       (controller), \
  84       (controller)->smu_registers->reg, \
  85       (value) \
  86    )
  87 /*@}*/
  88
  89 /**
  90  * @name AFE_REGISTER_ACCESS_MACROS
  91  */
  92 /*@{*/
  93 #define scu_afe_register_write(controller, reg, value) \
  94    scu_register_write( \
  95       (controller), \
  96       (controller)->scu_registers->afe.reg, \
  97       (value) \
  98    )
  99
 100 #define scu_afe_register_read(controller, reg) \
 101    scu_register_read( \
 102       (controller), \
 103       (controller)->scu_registers->afe.reg \
 104    )
 105 /*@}*/
 106
 107 /**
 108  * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS
 109  */
 110 /*@{*/
 111 #define scu_sgpio_peg0_register_read(controller, reg) \
 112    scu_register_read( \
 113       (controller), \
 114       (controller)->scu_registers->peg0.sgpio.reg \
 115    )
 116
 117 #define scu_sgpio_peg0_register_write(controller, reg, value) \
 118    scu_register_write( \
 119       (controller), \
 120       (controller)->scu_registers->peg0.sgpio.reg, \
 121       (value) \
 122    )
 123 /*@}*/
 124
 125 /**
 126  * @name VIIT_REGISTER_ACCESS_MACROS
 127  */
 128 /*@{*/
 129 #define scu_controller_viit_register_write(controller, index, reg, value) \
 130    scu_register_write( \
 131       (controller), \
 132       (controller)->scu_registers->peg0.viit[index].reg, \
 133       value \
 134    )
 135 /*@}*/
 136
 137 /**
 138  * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS
 139  */
 140 /*@{*/
 141 // Scratch RAM access may be needed before the scu_registers pointer
 142 //  has been initialized.  So instead, explicitly cast BAR1 to a
 143 //  SCU_REGISTERS_T data structure.
 144
 145 // Scratch RAM is stored in the Zoning Permission Table for OROM use.
 146 #define scu_controller_scratch_ram_register_write(controller, index, value) \
 147    scu_register_write( \
 148       (controller), \
 149       ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \
 150       value \
 151    )
 152
 153 #define scu_controller_scratch_ram_register_read(controller, index) \
 154    scu_register_read( \
 155       (controller), \
 156       ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \
 157    )
 158
 159 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \
 160    scu_register_write( \
 161       (controller), \
 162       ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \
 163       value \
 164    )
 165
 166 #define scu_controller_scratch_ram_register_read_ext(controller, index) \
 167    scu_register_read( \
 168       (controller), \
 169       ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \
 170    )
 171 /*@}*/
 172
 173
 174 //*****************************************************************************
 175 //* SMU REGISTERS
 176 //*****************************************************************************
 177
 178 /**
 179  * @name SMU_REGISTERS
 180  */
 181 /*@{*/
 182 #define SMU_PCP_WRITE(controller, value) \
 183     scic_sds_controller_smu_register_write( \
 184        controller, post_context_port, value \
 185     )
 186
 187 #define SMU_TCR_READ(controller, value) \
 188     scic_sds_controller_smu_register_read( \
 189        controller, task_context_range \
 190     )
 191
 192 #define SMU_TCR_WRITE(controller, value) \
 193     scic_sds_controller_smu_register_write( \
 194        controller, task_context_range, value \
 195     )
 196
 197 #define SMU_HTTBAR_WRITE(controller, address) \
 198 { \
 199    scic_sds_controller_smu_register_write( \
 200       controller, \
 201       host_task_table_lower, \
 202       sci_cb_physical_address_lower(address) \
 203    );\
 204    scic_sds_controller_smu_register_write( \
 205       controller, \
 206       host_task_table_upper, \
 207       sci_cb_physical_address_upper(address) \
 208    ); \
 209 }
 210
 211 #define SMU_CQBAR_WRITE(controller, address) \
 212 { \
 213    scic_sds_controller_smu_register_write( \
 214       controller, \
 215       completion_queue_lower, \
 216       sci_cb_physical_address_lower(address) \
 217    ); \
 218    scic_sds_controller_smu_register_write( \
 219       controller, \
 220       completion_queue_upper, \
 221       sci_cb_physical_address_upper(address) \
 222    ); \
 223 }
 224
 225 #define SMU_CQGR_WRITE(controller, value) \
 226     scic_sds_controller_smu_register_write( \
 227        controller, completion_queue_get, value \
 228     )
 229
 230 #define SMU_CQGR_READ(controller, value) \
 231     scic_sds_controller_smu_register_read( \
 232        controller, completion_queue_get \
 233     )
 234
 235 #define SMU_CQPR_WRITE(controller, value) \
 236     scic_sds_controller_smu_register_write( \
 237        controller, completion_queue_put, value \
 238     )
 239
 240 #define SMU_RNCBAR_WRITE(controller, address) \
 241 { \
 242    scic_sds_controller_smu_register_write( \
 243       controller, \
 244       remote_node_context_lower, \
 245       sci_cb_physical_address_lower(address) \
 246    ); \
 247    scic_sds_controller_smu_register_write( \
 248       controller, \
 249       remote_node_context_upper, \
 250       sci_cb_physical_address_upper(address) \
 251    ); \
 252 }
 253
 254 #define SMU_AMR_READ(controller) \
 255    scic_sds_controller_smu_register_read( \
 256       controller, address_modifier \
 257    )
 258
 259 #define SMU_IMR_READ(controller) \
 260    scic_sds_controller_smu_register_read( \
 261       controller, interrupt_mask \
 262    )
 263
 264 #define SMU_IMR_WRITE(controller, mask) \
 265    scic_sds_controller_smu_register_write( \
 266       controller, interrupt_mask, mask \
 267    )
 268
 269 #define SMU_ISR_READ(controller) \
 270    scic_sds_controller_smu_register_read( \
 271       controller, interrupt_status \
 272    )
 273
 274 #define SMU_ISR_WRITE(controller, status) \
 275    scic_sds_controller_smu_register_write( \
 276       controller, interrupt_status, status \
 277    )
 278
 279 #define SMU_ICC_READ(controller) \
 280    scic_sds_controller_smu_register_read( \
 281       controller, interrupt_coalesce_control \
 282    )
 283
 284 #define SMU_ICC_WRITE(controller, value) \
 285    scic_sds_controller_smu_register_write( \
 286       controller, interrupt_coalesce_control, value \
 287    )
 288
 289 #define SMU_CQC_WRITE(controller, value) \
 290     scic_sds_controller_smu_register_write( \
 291        controller, completion_queue_control, value \
 292     )
 293
 294 #define SMU_SMUSRCR_WRITE(controller, value) \
 295    scic_sds_controller_smu_register_write( \
 296       controller, soft_reset_control, value \
 297    )
 298
 299 #define SMU_TCA_WRITE(controller, index, value) \
 300     scic_sds_controller_smu_register_write( \
 301        controller, task_context_assignment[index], value \
 302     )
 303
 304 #define SMU_TCA_READ(controller, index) \
 305     scic_sds_controller_smu_register_read( \
 306        controller, task_context_assignment[index] \
 307     )
 308
 309 #define SMU_DCC_READ(controller) \
 310    scic_sds_controller_smu_register_read( \
 311       controller, device_context_capacity \
 312    )
 313
 314 #define SMU_DFC_READ(controller) \
 315    scic_sds_controller_smu_register_read( \
 316       controller, device_function_capacity \
 317    )
 318
 319 #define SMU_SMUCSR_READ(controller) \
 320    scic_sds_controller_smu_register_read( \
 321       controller, control_status \
 322    )
 323
 324 #define SMU_CGUCR_READ(controller) \
 325    scic_sds_controller_smu_register_read( \
 326       controller, clock_gating_control \
 327    )
 328
 329 #define SMU_CGUCR_WRITE(controller, value) \
 330    scic_sds_controller_smu_register_write( \
 331       controller, clock_gating_control, value \
 332    )
 333
 334 #define SMU_CQPR_READ(controller) \
 335     scic_sds_controller_smu_register_read( \
 336        controller, completion_queue_put \
 337     )
 338
 339 /*@}*/
 340
 341 /**
 342  * @name SCU_REGISTER_ACCESS_MACROS
 343  */
 344 /*@{*/
 345 #define scic_sds_controller_scu_register_read(controller, reg) \
 346    scu_register_read( \
 347       (controller), \
 348       (controller)->scu_registers->reg \
 349    )
 350
 351 #define scic_sds_controller_scu_register_write(controller, reg, value) \
 352    scu_register_write( \
 353       (controller), \
 354       (controller)->scu_registers->reg, \
 355       (value) \
 356    )
 357 /*@}*/
 358
 359
 360 //****************************************************************************
 361 //*  SCU SDMA REGISTERS
 362 //****************************************************************************
 363
 364 /**
 365  * @name SCU_SDMA_REGISTER_ACCESS_MACROS
 366  */
 367 /*@{*/
 368 #define scu_sdma_register_read(controller, reg) \
 369    scu_register_read( \
 370       (controller), \
 371       (controller)->scu_registers->sdma.reg \
 372    )
 373
 374 #define scu_sdma_register_write(controller, reg, value) \
 375    scu_register_write( \
 376       (controller), \
 377       (controller)->scu_registers->sdma.reg, \
 378       (value) \
 379    )
 380 /*@}*/
 381
 382 /**
 383  * @name SCU_SDMA_REGISTERS
 384  */
 385 /*@{*/
 386 #define SCU_PUFATHAR_WRITE(controller, address) \
 387 { \
 388    scu_sdma_register_write( \
 389       controller, \
 390       uf_address_table_lower, \
 391       sci_cb_physical_address_lower(address) \
 392    ); \
 393    scu_sdma_register_write( \
 394       controller, \
 395       uf_address_table_upper, \
 396       sci_cb_physical_address_upper(address) \
 397    ); \
 398 }
 399
 400 #define SCU_UFHBAR_WRITE(controller, address) \
 401 { \
 402    scu_sdma_register_write( \
 403       controller, \
 404       uf_header_base_address_lower, \
 405       sci_cb_physical_address_lower(address) \
 406    ); \
 407    scu_sdma_register_write( \
 408       controller, \
 409       uf_header_base_address_upper, \
 410       sci_cb_physical_address_upper(address) \
 411    ); \
 412 }
 413
 414 #define SCU_UFQC_READ(controller) \
 415     scu_sdma_register_read( \
 416        controller,  \
 417        unsolicited_frame_queue_control \
 418     )
 419
 420 #define SCU_UFQC_WRITE(controller, value) \
 421     scu_sdma_register_write( \
 422        controller, \
 423        unsolicited_frame_queue_control, \
 424        value \
 425     )
 426
 427 #define SCU_UFQPP_READ(controller) \
 428     scu_sdma_register_read( \
 429        controller, \
 430        unsolicited_frame_put_pointer \
 431     )
 432
 433 #define SCU_UFQPP_WRITE(controller, value) \
 434    scu_sdma_register_write( \
 435       controller, \
 436       unsolicited_frame_put_pointer, \
 437       value \
 438    )
 439
 440 #define SCU_UFQGP_WRITE(controller, value) \
 441    scu_sdma_register_write( \
 442       controller, \
 443       unsolicited_frame_get_pointer, \
 444       value \
 445    )
 446
 447 #define SCU_PDMACR_READ(controller) \
 448    scu_sdma_register_read( \
 449       controller, \
 450       pdma_configuration \
 451    )
 452
 453 #define SCU_PDMACR_WRITE(controller, value) \
 454    scu_sdma_register_write( \
 455       controller, \
 456       pdma_configuration, \
 457       value \
 458    )
 459
 460 #define SCU_CDMACR_READ(controller) \
 461    scu_sdma_register_read( \
 462      controller, \
 463      cdma_configuration \
 464    )
 465
 466 #define SCU_CDMACR_WRITE(controller, value) \
 467    scu_sdma_register_write( \
 468       controller, \
 469       cdma_configuration, \
 470       value \
 471    )
 472 /*@}*/
 473
 474 //*****************************************************************************
 475 //* SCU CRAM AND FBRAM Registers
 476 //*****************************************************************************
 477 /**
 478  * @name SCU_CRAM_REGISTER_ACCESS_MACROS
 479  */
 480 /*@{*/
 481 #define scu_cram_register_read(controller, reg) \
 482    scu_register_read( \
 483       (controller), \
 484       (controller)->scu_registers->cram.reg \
 485    )
 486
 487 #define scu_cram_register_write(controller, reg, value) \
 488    scu_register_write( \
 489       (controller), \
 490       (controller)->scu_registers->cram.reg, \
 491       (value) \
 492    )
 493 /*@}*/
 494
 495 /**
 496  * @name SCU_FBRAM_REGISTER_ACCESS_MACROS
 497  */
 498 /*@{*/
 499 #define scu_fbram_register_read(controller, reg) \
 500    scu_register_read( \
 501       (controller), \
 502       (controller)->scu_registers->fbram.reg \
 503    )
 504
 505 #define scu_fbram_register_write(controller, reg, value) \
 506    scu_register_write( \
 507       (controller), \
 508       (controller)->scu_registers->fbram.reg, \
 509       (value) \
 510    )
 511 /*@}*/
 512
 513
 514 /**
 515  * @name SCU_CRAM_REGISTERS
 516  */
 517 /*@{*/
 518
 519 // SRAM ECC CONTROL REGISTER BITS
 520 #define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001
 521 #define MULTI_BIT_ERROR_REPORTING_ENABLE   0x00000002
 522 #define SINGLE_BIT_ERROR_REPORTING_ENABLE  0x00000004
 523
 524 //SRAM ECC control register (SECR0)
 525 #define SCU_SECR0_WRITE(controller, value) \
 526     scu_cram_register_write( \
 527       controller, \
 528       sram_ecc_control_0, \
 529       value \
 530    )
 531 /*@}*/
 532
 533 /**
 534  * @name SCU_FBRAM_REGISTERS
 535  */
 536 /*@{*/
 537
 538 //SRAM ECC control register (SECR1)
 539 #define SCU_SECR1_WRITE(controller, value) \
 540     scu_fbram_register_write( \
 541       controller, \
 542       sram_ecc_control_1, \
 543       value \
 544    )
 545 /*@}*/
 546
 547
 548 //*****************************************************************************
 549 //* SCU Port Task Scheduler Group Registers
 550 //*****************************************************************************
 551
 552 /**
 553  * @name SCU_PTSG_REGISTER_ACCESS_MACROS
 554  */
 555 /*@{*/
 556 #define scu_ptsg_register_read(controller, reg) \
 557    scu_register_read( \
 558       (controller), \
 559       (controller)->scu_registers->peg0.ptsg.reg \
 560    )
 561
 562 #define scu_ptsg_register_write(controller, reg, value) \
 563    scu_register_write( \
 564       (controller), \
 565       (controller)->scu_registers->peg0.ptsg.reg, \
 566       (value) \
 567    )
 568 /*@}*/
 569
 570 /**
 571  * @name SCU_PTSG_REGISTERS
 572  */
 573 /*@{*/
 574 #define SCU_PTSGCR_READ(controller) \
 575     scu_ptsg_register_read( \
 576        (controller), \
 577        control \
 578     )
 579
 580 #define SCU_PTSGCR_WRITE(controller, value) \
 581     scu_ptsg_register_write( \
 582        (controller), \
 583        control, \
 584        value \
 585     )
 586
 587 #define SCU_PTSGRTC_READ(controller) \
 588     scu_ptsg_register_read( \
 589        contoller, \
 590        real_time_clock \
 591     )
 592 /*@}*/
 593
 594 #ifdef __cplusplus
 595 }
 596 #endif // __cplusplus
 597
 598 #endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_