sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int serdes_flags;       /* Keeps track of the serdes type used */
  72 #define BRGPHY_5706S            0x0001
  73 #define BRGPHY_5708S            0x0002
  74 #define BRGPHY_NOANWAIT         0x0004
  75 #define BRGPHY_5709S            0x0008
  76         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  77 };
  78
  79 static device_method_t brgphy_methods[] = {
  80         /* device interface */
  81         DEVMETHOD(device_probe,         brgphy_probe),
  82         DEVMETHOD(device_attach,        brgphy_attach),
  83         DEVMETHOD(device_detach,        mii_phy_detach),
  84         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  85         DEVMETHOD_END
  86 };
  87
  88 static devclass_t brgphy_devclass;
  89
  90 static driver_t brgphy_driver = {
  91         "brgphy",
  92         brgphy_methods,
  93         sizeof(struct brgphy_softc)
  94 };
  95
  96 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
  97
  98 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
  99 static void     brgphy_setmedia(struct mii_softc *, int);
 100 static void     brgphy_status(struct mii_softc *);
 101 static void     brgphy_mii_phy_auto(struct mii_softc *, int);
 102 static void     brgphy_reset(struct mii_softc *);
 103 static void     brgphy_enable_loopback(struct mii_softc *);
 104 static void     bcm5401_load_dspcode(struct mii_softc *);
 105 static void     bcm5411_load_dspcode(struct mii_softc *);
 106 static void     bcm54k2_load_dspcode(struct mii_softc *);
 107 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 108 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 109 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 110 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 111 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 113 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 114 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 115
 116 static const struct mii_phydesc brgphys[] = {
 117         MII_PHY_DESC(BROADCOM, BCM5400),
 118         MII_PHY_DESC(BROADCOM, BCM5401),
 119         MII_PHY_DESC(BROADCOM, BCM5411),
 120         MII_PHY_DESC(BROADCOM, BCM54K2),
 121         MII_PHY_DESC(BROADCOM, BCM5701),
 122         MII_PHY_DESC(BROADCOM, BCM5703),
 123         MII_PHY_DESC(BROADCOM, BCM5704),
 124         MII_PHY_DESC(BROADCOM, BCM5705),
 125         MII_PHY_DESC(BROADCOM, BCM5706),
 126         MII_PHY_DESC(BROADCOM, BCM5714),
 127         MII_PHY_DESC(BROADCOM, BCM5421),
 128         MII_PHY_DESC(BROADCOM, BCM5750),
 129         MII_PHY_DESC(BROADCOM, BCM5752),
 130         MII_PHY_DESC(BROADCOM, BCM5780),
 131         MII_PHY_DESC(BROADCOM, BCM5708C),
 132         MII_PHY_DESC(BROADCOM2, BCM5482),
 133         MII_PHY_DESC(BROADCOM2, BCM5708S),
 134         MII_PHY_DESC(BROADCOM2, BCM5709C),
 135         MII_PHY_DESC(BROADCOM2, BCM5709S),
 136         MII_PHY_DESC(BROADCOM2, BCM5709CAX),
 137         MII_PHY_DESC(BROADCOM2, BCM5722),
 138         MII_PHY_DESC(BROADCOM2, BCM5755),
 139         MII_PHY_DESC(BROADCOM2, BCM5754),
 140         MII_PHY_DESC(BROADCOM2, BCM5761),
 141         MII_PHY_DESC(BROADCOM2, BCM5784),
 142 #ifdef notyet   /* better handled by ukphy(4) until WARs are implemented */
 143         MII_PHY_DESC(BROADCOM2, BCM5785),
 144 #endif
 145         MII_PHY_DESC(BROADCOM3, BCM5717C),
 146         MII_PHY_DESC(BROADCOM3, BCM5719C),
 147         MII_PHY_DESC(BROADCOM3, BCM5720C),
 148         MII_PHY_DESC(BROADCOM3, BCM57765),
 149         MII_PHY_DESC(BROADCOM3, BCM57780),
 150         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
 151         MII_PHY_END
 152 };
 153
 154 static const struct mii_phy_funcs brgphy_funcs = {
 155         brgphy_service,
 156         brgphy_status,
 157         brgphy_reset
 158 };
 159
 160 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
 161 #define HS21_BCM_CHIPID 0x57081021
 162
 163 static int
 164 detect_hs21(struct bce_softc *bce_sc)
 165 {
 166         char *sysenv;
 167         int found;
 168
 169         found = 0;
 170         if (bce_sc->bce_chipid == HS21_BCM_CHIPID) {
 171                 sysenv = getenv("smbios.system.product");
 172                 if (sysenv != NULL) {
 173                         if (strncmp(sysenv, HS21_PRODUCT_ID,
 174                             strlen(HS21_PRODUCT_ID)) == 0)
 175                                 found = 1;
 176                         freeenv(sysenv);
 177                 }
 178         }
 179         return (found);
 180 }
 181
 182 /* Search for our PHY in the list of known PHYs */
 183 static int
 184 brgphy_probe(device_t dev)
 185 {
 186
 187         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 188 }
 189
 190 /* Attach the PHY to the MII bus */
 191 static int
 192 brgphy_attach(device_t dev)
 193 {
 194         struct brgphy_softc *bsc;
 195         struct bge_softc *bge_sc = NULL;
 196         struct bce_softc *bce_sc = NULL;
 197         struct mii_softc *sc;
 198         struct ifnet *ifp;
 199
 200         bsc = device_get_softc(dev);
 201         sc = &bsc->mii_sc;
 202
 203         mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
 204             &brgphy_funcs, 0);
 205
 206         bsc->serdes_flags = 0;
 207         ifp = sc->mii_pdata->mii_ifp;
 208
 209         /* Find the MAC driver associated with this PHY. */
 210         if (strcmp(ifp->if_dname, "bge") == 0)
 211                 bge_sc = ifp->if_softc;
 212         else if (strcmp(ifp->if_dname, "bce") == 0)
 213                 bce_sc = ifp->if_softc;
 214
 215         /* Handle any special cases based on the PHY ID */
 216         switch (sc->mii_mpd_oui) {
 217         case MII_OUI_BROADCOM:
 218                 switch (sc->mii_mpd_model) {
 219                 case MII_MODEL_BROADCOM_BCM5706:
 220                 case MII_MODEL_BROADCOM_BCM5714:
 221                         /*
 222                          * The 5464 PHY used in the 5706 supports both copper
 223                          * and fiber interfaces over GMII.  Need to check the
 224                          * shadow registers to see which mode is actually
 225                          * in effect, and therefore whether we have 5706C or
 226                          * 5706S.
 227                          */
 228                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 229                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 230                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 231                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 232                                 bsc->serdes_flags |= BRGPHY_5706S;
 233                                 sc->mii_flags |= MIIF_HAVEFIBER;
 234                         }
 235                         break;
 236                 }
 237                 break;
 238         case MII_OUI_BROADCOM2:
 239                 switch (sc->mii_mpd_model) {
 240                 case MII_MODEL_BROADCOM2_BCM5708S:
 241                         bsc->serdes_flags |= BRGPHY_5708S;
 242                         sc->mii_flags |= MIIF_HAVEFIBER;
 243                         break;
 244                 case MII_MODEL_BROADCOM2_BCM5709S:
 245                         /*
 246                          * XXX
 247                          * 5720S and 5709S shares the same PHY id.
 248                          * Assume 5720S PHY if parent device is bge(4).
 249                          */
 250                         if (bge_sc != NULL)
 251                                 bsc->serdes_flags |= BRGPHY_5708S;
 252                         else
 253                                 bsc->serdes_flags |= BRGPHY_5709S;
 254                         sc->mii_flags |= MIIF_HAVEFIBER;
 255                         break;
 256                 }
 257                 break;
 258         }
 259
 260         PHY_RESET(sc);
 261
 262         /* Read the PHY's capabilities. */
 263         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
 264         if (sc->mii_capabilities & BMSR_EXTSTAT)
 265                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 266         device_printf(dev, " ");
 267
 268 #define ADD(m, c)       ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL)
 269
 270         /* Add the supported media types */
 271         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 272                 mii_phy_add_media(sc);
 273                 printf("\n");
 274         } else {
 275                 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 276                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 277                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 278                 printf("1000baseSX-FDX, ");
 279                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 280                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 281                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 282                         printf("2500baseSX-FDX, ");
 283                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 284                     (detect_hs21(bce_sc) != 0)) {
 285                         /*
 286                          * There appears to be certain silicon revision
 287                          * in IBM HS21 blades that is having issues with
 288                          * this driver wating for the auto-negotiation to
 289                          * complete. This happens with a specific chip id
 290                          * only and when the 1000baseSX-FDX is the only
 291                          * mode. Workaround this issue since it's unlikely
 292                          * to be ever addressed.
 293                          */
 294                         printf("auto-neg workaround, ");
 295                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 296                 }
 297                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 298                 printf("auto\n");
 299         }
 300
 301 #undef ADD
 302         MIIBUS_MEDIAINIT(sc->mii_dev);
 303         return (0);
 304 }
 305
 306 static int
 307 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 308 {
 309         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 310         int val;
 311
 312         switch (cmd) {
 313         case MII_POLLSTAT:
 314                 break;
 315         case MII_MEDIACHG:
 316                 /* If the interface is not up, don't do anything. */
 317                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 318                         break;
 319
 320                 /* Todo: Why is this here?  Is it really needed? */
 321                 PHY_RESET(sc);  /* XXX hardware bug work-around */
 322
 323                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 324                 case IFM_AUTO:
 325                         brgphy_mii_phy_auto(sc, ife->ifm_media);
 326                         break;
 327                 case IFM_2500_SX:
 328                 case IFM_1000_SX:
 329                 case IFM_1000_T:
 330                 case IFM_100_TX:
 331                 case IFM_10_T:
 332                         brgphy_setmedia(sc, ife->ifm_media);
 333                         break;
 334                 default:
 335                         return (EINVAL);
 336                 }
 337                 break;
 338         case MII_TICK:
 339                 /* Bail if the interface isn't up. */
 340                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 341                         return (0);
 342
 343
 344                 /* Bail if autoneg isn't in process. */
 345                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 346                         sc->mii_ticks = 0;
 347                         break;
 348                 }
 349
 350                 /*
 351                  * Check to see if we have link.  If we do, we don't
 352                  * need to restart the autonegotiation process.
 353                  */
 354                 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 355                 if (val & BMSR_LINK) {
 356                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 357                         break;
 358                 }
 359
 360                 /* Announce link loss right after it happens. */
 361                 if (sc->mii_ticks++ == 0)
 362                         break;
 363
 364                 /* Only retry autonegotiation every mii_anegticks seconds. */
 365                 if (sc->mii_ticks <= sc->mii_anegticks)
 366                         break;
 367
 368
 369                 /* Retry autonegotiation */
 370                 sc->mii_ticks = 0;
 371                 brgphy_mii_phy_auto(sc, ife->ifm_media);
 372                 break;
 373         }
 374
 375         /* Update the media status. */
 376         PHY_STATUS(sc);
 377
 378         /*
 379          * Callback if something changed. Note that we need to poke
 380          * the DSP on the Broadcom PHYs if the media changes.
 381          */
 382         if (sc->mii_media_active != mii->mii_media_active ||
 383             sc->mii_media_status != mii->mii_media_status ||
 384             cmd == MII_MEDIACHG) {
 385                 switch (sc->mii_mpd_oui) {
 386                 case MII_OUI_BROADCOM:
 387                         switch (sc->mii_mpd_model) {
 388                         case MII_MODEL_BROADCOM_BCM5400:
 389                                 bcm5401_load_dspcode(sc);
 390                                 break;
 391                         case MII_MODEL_BROADCOM_BCM5401:
 392                                 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 393                                         bcm5401_load_dspcode(sc);
 394                                 break;
 395                         case MII_MODEL_BROADCOM_BCM5411:
 396                                 bcm5411_load_dspcode(sc);
 397                                 break;
 398                         case MII_MODEL_BROADCOM_BCM54K2:
 399                                 bcm54k2_load_dspcode(sc);
 400                                 break;
 401                         }
 402                         break;
 403                 }
 404         }
 405         mii_phy_update(sc, cmd);
 406         return (0);
 407 }
 408
 409 /****************************************************************************/
 410 /* Sets the PHY link speed.                                                 */
 411 /*                                                                          */
 412 /* Returns:                                                                 */
 413 /*   None                                                                   */
 414 /****************************************************************************/
 415 static void
 416 brgphy_setmedia(struct mii_softc *sc, int media)
 417 {
 418         int bmcr = 0, gig;
 419
 420         switch (IFM_SUBTYPE(media)) {
 421         case IFM_2500_SX:
 422                 break;
 423         case IFM_1000_SX:
 424         case IFM_1000_T:
 425                 bmcr = BRGPHY_S1000;
 426                 break;
 427         case IFM_100_TX:
 428                 bmcr = BRGPHY_S100;
 429                 break;
 430         case IFM_10_T:
 431         default:
 432                 bmcr = BRGPHY_S10;
 433                 break;
 434         }
 435
 436         if ((media & IFM_FDX) != 0) {
 437                 bmcr |= BRGPHY_BMCR_FDX;
 438                 gig = BRGPHY_1000CTL_AFD;
 439         } else {
 440                 gig = BRGPHY_1000CTL_AHD;
 441         }
 442
 443         /* Force loopback to disconnect PHY from Ethernet medium. */
 444         brgphy_enable_loopback(sc);
 445
 446         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 447         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 448
 449         if (IFM_SUBTYPE(media) != IFM_1000_T &&
 450             IFM_SUBTYPE(media) != IFM_1000_SX) {
 451                 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 452                 return;
 453         }
 454
 455         if (IFM_SUBTYPE(media) == IFM_1000_T) {
 456                 gig |= BRGPHY_1000CTL_MSE;
 457                 if ((media & IFM_ETH_MASTER) != 0)
 458                         gig |= BRGPHY_1000CTL_MSC;
 459         }
 460         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 461         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 462             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 463 }
 464
 465 /****************************************************************************/
 466 /* Set the media status based on the PHY settings.                          */
 467 /*                                                                          */
 468 /* Returns:                                                                 */
 469 /*   None                                                                   */
 470 /****************************************************************************/
 471 static void
 472 brgphy_status(struct mii_softc *sc)
 473 {
 474         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 475         struct mii_data *mii = sc->mii_pdata;
 476         int aux, bmcr, bmsr, val, xstat;
 477         u_int flowstat;
 478
 479         mii->mii_media_status = IFM_AVALID;
 480         mii->mii_media_active = IFM_ETHER;
 481
 482         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 483         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 484
 485         if (bmcr & BRGPHY_BMCR_LOOP) {
 486                 mii->mii_media_active |= IFM_LOOP;
 487         }
 488
 489         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 490             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 491             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 492                 /* Erg, still trying, I guess... */
 493                 mii->mii_media_active |= IFM_NONE;
 494                 return;
 495         }
 496
 497         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 498                 /*
 499                  * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
 500                  * wedges at least the PHY of BCM5704 (but not others).
 501                  */
 502                 flowstat = mii_phy_flowstatus(sc);
 503                 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
 504                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 505
 506                 /* If copper link is up, get the negotiated speed/duplex. */
 507                 if (aux & BRGPHY_AUXSTS_LINK) {
 508                         mii->mii_media_status |= IFM_ACTIVE;
 509                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 510                         case BRGPHY_RES_1000FD:
 511                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 512                         case BRGPHY_RES_1000HD:
 513                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 514                         case BRGPHY_RES_100FD:
 515                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 516                         case BRGPHY_RES_100T4:
 517                                 mii->mii_media_active |= IFM_100_T4; break;
 518                         case BRGPHY_RES_100HD:
 519                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 520                         case BRGPHY_RES_10FD:
 521                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 522                         case BRGPHY_RES_10HD:
 523                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 524                         default:
 525                                 mii->mii_media_active |= IFM_NONE; break;
 526                         }
 527
 528                         if ((mii->mii_media_active & IFM_FDX) != 0)
 529                                 mii->mii_media_active |= flowstat;
 530
 531                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
 532                             (xstat & BRGPHY_1000STS_MSR) != 0)
 533                                 mii->mii_media_active |= IFM_ETH_MASTER;
 534                 }
 535         } else {
 536                 /* Todo: Add support for flow control. */
 537                 /* If serdes link is up, get the negotiated speed/duplex. */
 538                 if (bmsr & BRGPHY_BMSR_LINK) {
 539                         mii->mii_media_status |= IFM_ACTIVE;
 540                 }
 541
 542                 /* Check the link speed/duplex based on the PHY type. */
 543                 if (bsc->serdes_flags & BRGPHY_5706S) {
 544                         mii->mii_media_active |= IFM_1000_SX;
 545
 546                         /* If autoneg enabled, read negotiated duplex settings */
 547                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 548                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 549                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 550                                         mii->mii_media_active |= IFM_FDX;
 551                                 else
 552                                         mii->mii_media_active |= IFM_HDX;
 553                         }
 554                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 555                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 556                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 557
 558                         /* Check for MRBE auto-negotiated speed results. */
 559                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 560                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 561                                 mii->mii_media_active |= IFM_10_FL; break;
 562                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 563                                 mii->mii_media_active |= IFM_100_FX; break;
 564                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 565                                 mii->mii_media_active |= IFM_1000_SX; break;
 566                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 567                                 mii->mii_media_active |= IFM_2500_SX; break;
 568                         }
 569
 570                         /* Check for MRBE auto-negotiated duplex results. */
 571                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 572                                 mii->mii_media_active |= IFM_FDX;
 573                         else
 574                                 mii->mii_media_active |= IFM_HDX;
 575                 } else if (bsc->serdes_flags & BRGPHY_5709S) {
 576                         /* Select GP Status Block of the AN MMD, get autoneg results. */
 577                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 578                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 579
 580                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 581                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 582
 583                         /* Check for MRBE auto-negotiated speed results. */
 584                         switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 585                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 586                                         mii->mii_media_active |= IFM_10_FL; break;
 587                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 588                                         mii->mii_media_active |= IFM_100_FX; break;
 589                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 590                                         mii->mii_media_active |= IFM_1000_SX; break;
 591                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 592                                         mii->mii_media_active |= IFM_2500_SX; break;
 593                         }
 594
 595                         /* Check for MRBE auto-negotiated duplex results. */
 596                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 597                                 mii->mii_media_active |= IFM_FDX;
 598                         else
 599                                 mii->mii_media_active |= IFM_HDX;
 600                 }
 601         }
 602 }
 603
 604 static void
 605 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
 606 {
 607         int anar, ktcr = 0;
 608
 609         PHY_RESET(sc);
 610
 611         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 612                 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
 613                 if ((media & IFM_FLOW) != 0 ||
 614                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 615                         anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
 616                 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
 617                 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 618                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
 619                         ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 620                 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 621                 PHY_READ(sc, BRGPHY_MII_1000CTL);
 622         } else {
 623                 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
 624                 if ((media & IFM_FLOW) != 0 ||
 625                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 626                         anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
 627                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
 628         }
 629
 630         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
 631             BRGPHY_BMCR_STARTNEG);
 632         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 633 }
 634
 635 /* Enable loopback to force the link down. */
 636 static void
 637 brgphy_enable_loopback(struct mii_softc *sc)
 638 {
 639         int i;
 640
 641         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 642         for (i = 0; i < 15000; i++) {
 643                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 644                         break;
 645                 DELAY(10);
 646         }
 647 }
 648
 649 /* Turn off tap power management on 5401. */
 650 static void
 651 bcm5401_load_dspcode(struct mii_softc *sc)
 652 {
 653         static const struct {
 654                 int             reg;
 655                 uint16_t        val;
 656         } dspcode[] = {
 657                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 658                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 659                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 660                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 661                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 662                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 663                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 664                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 665                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 666                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 667                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 668                 { 0,                            0 },
 669         };
 670         int i;
 671
 672         for (i = 0; dspcode[i].reg != 0; i++)
 673                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 674         DELAY(40);
 675 }
 676
 677 static void
 678 bcm5411_load_dspcode(struct mii_softc *sc)
 679 {
 680         static const struct {
 681                 int             reg;
 682                 uint16_t        val;
 683         } dspcode[] = {
 684                 { 0x1c,                         0x8c23 },
 685                 { 0x1c,                         0x8ca3 },
 686                 { 0x1c,                         0x8c23 },
 687                 { 0,                            0 },
 688         };
 689         int i;
 690
 691         for (i = 0; dspcode[i].reg != 0; i++)
 692                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 693 }
 694
 695 void
 696 bcm54k2_load_dspcode(struct mii_softc *sc)
 697 {
 698         static const struct {
 699                 int             reg;
 700                 uint16_t        val;
 701         } dspcode[] = {
 702                 { 4,                            0x01e1 },
 703                 { 9,                            0x0300 },
 704                 { 0,                            0 },
 705         };
 706         int i;
 707
 708         for (i = 0; dspcode[i].reg != 0; i++)
 709                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 710
 711 }
 712
 713 static void
 714 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 715 {
 716         static const struct {
 717                 int             reg;
 718                 uint16_t        val;
 719         } dspcode[] = {
 720                 { 0x1c,                         0x8d68 },
 721                 { 0x1c,                         0x8d68 },
 722                 { 0,                            0 },
 723         };
 724         int i;
 725
 726         for (i = 0; dspcode[i].reg != 0; i++)
 727                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 728 }
 729
 730 static void
 731 brgphy_fixup_adc_bug(struct mii_softc *sc)
 732 {
 733         static const struct {
 734                 int             reg;
 735                 uint16_t        val;
 736         } dspcode[] = {
 737                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 738                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 739                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 740                 { 0,                            0 },
 741         };
 742         int i;
 743
 744         for (i = 0; dspcode[i].reg != 0; i++)
 745                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 746 }
 747
 748 static void
 749 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 750 {
 751         static const struct {
 752                 int             reg;
 753                 uint16_t        val;
 754         } dspcode[] = {
 755                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 756                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 757                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 758                 { BRGPHY_MII_TEST1,                     0x0014 },
 759                 { BRGPHY_MII_AUXCTL,            0x0400 },
 760                 { 0,                            0 },
 761         };
 762         int i;
 763
 764         for (i = 0; dspcode[i].reg != 0; i++)
 765                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 766 }
 767
 768 static void
 769 brgphy_fixup_ber_bug(struct mii_softc *sc)
 770 {
 771         static const struct {
 772                 int             reg;
 773                 uint16_t        val;
 774         } dspcode[] = {
 775                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 776                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 777                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 778                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 779                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 780                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 781                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 782                 { BRGPHY_MII_AUXCTL,            0x0400 },
 783                 { 0,                            0 },
 784         };
 785         int i;
 786
 787         for (i = 0; dspcode[i].reg != 0; i++)
 788                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 789 }
 790
 791 static void
 792 brgphy_fixup_crc_bug(struct mii_softc *sc)
 793 {
 794         static const struct {
 795                 int             reg;
 796                 uint16_t        val;
 797         } dspcode[] = {
 798                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 799                 { 0x1c,                         0x8c68 },
 800                 { 0x1c,                         0x8d68 },
 801                 { 0x1c,                         0x8c68 },
 802                 { 0,                            0 },
 803         };
 804         int i;
 805
 806         for (i = 0; dspcode[i].reg != 0; i++)
 807                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 808 }
 809
 810 static void
 811 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 812 {
 813         static const struct {
 814                 int             reg;
 815                 uint16_t        val;
 816         } dspcode[] = {
 817                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 818                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 819                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 820                 { BRGPHY_MII_AUXCTL,            0x0400 },
 821                 { 0,                            0 },
 822         };
 823         int i;
 824
 825         for (i = 0; dspcode[i].reg != 0; i++)
 826                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 827 }
 828
 829 static void
 830 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 831 {
 832         uint32_t val;
 833
 834         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 835         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 836         val &= ~(1 << 8);
 837         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 838
 839 }
 840
 841 static void
 842 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 843 {
 844         uint32_t        val;
 845
 846         /* Enable Ethernet@WireSpeed. */
 847         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 848         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 849         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 850 }
 851
 852 static void
 853 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 854 {
 855         uint32_t        val;
 856
 857         /* Set or clear jumbo frame settings in the PHY. */
 858         if (mtu > ETHER_MAX_LEN) {
 859                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
 860                         /* BCM5401 PHY cannot read-modify-write. */
 861                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 862                 } else {
 863                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 864                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 865                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 866                             val | BRGPHY_AUXCTL_LONG_PKT);
 867                 }
 868
 869                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 870                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 871                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 872         } else {
 873                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 874                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 875                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 876                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 877
 878                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 879                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 880                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 881         }
 882 }
 883
 884 static void
 885 brgphy_reset(struct mii_softc *sc)
 886 {
 887         struct bge_softc *bge_sc = NULL;
 888         struct bce_softc *bce_sc = NULL;
 889         struct ifnet *ifp;
 890         int i, val;
 891
 892         /*
 893          * Perform a reset.  Note that at least some Broadcom PHYs default to
 894          * being powered down as well as isolated after a reset but don't work
 895          * if one or both of these bits are cleared.  However, they just work
 896          * fine if both bits remain set, so we don't use mii_phy_reset() here.
 897          */
 898         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
 899
 900         /* Wait 100ms for it to complete. */
 901         for (i = 0; i < 100; i++) {
 902                 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
 903                         break;
 904                 DELAY(1000);
 905         }
 906
 907         /* Handle any PHY specific procedures following the reset. */
 908         switch (sc->mii_mpd_oui) {
 909         case MII_OUI_BROADCOM:
 910                 switch (sc->mii_mpd_model) {
 911                 case MII_MODEL_BROADCOM_BCM5400:
 912                         bcm5401_load_dspcode(sc);
 913                         break;
 914                 case MII_MODEL_BROADCOM_BCM5401:
 915                         if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 916                                 bcm5401_load_dspcode(sc);
 917                         break;
 918                 case MII_MODEL_BROADCOM_BCM5411:
 919                         bcm5411_load_dspcode(sc);
 920                         break;
 921                 case MII_MODEL_BROADCOM_BCM54K2:
 922                         bcm54k2_load_dspcode(sc);
 923                         break;
 924                 }
 925                 break;
 926         case MII_OUI_BROADCOM3:
 927                 switch (sc->mii_mpd_model) {
 928                 case MII_MODEL_BROADCOM3_BCM5717C:
 929                 case MII_MODEL_BROADCOM3_BCM5719C:
 930                 case MII_MODEL_BROADCOM3_BCM5720C:
 931                 case MII_MODEL_BROADCOM3_BCM57765:
 932                         return;
 933                 }
 934                 break;
 935         }
 936
 937         ifp = sc->mii_pdata->mii_ifp;
 938
 939         /* Find the driver associated with this PHY. */
 940         if (strcmp(ifp->if_dname, "bge") == 0)  {
 941                 bge_sc = ifp->if_softc;
 942         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 943                 bce_sc = ifp->if_softc;
 944         }
 945
 946         if (bge_sc) {
 947                 /* Fix up various bugs */
 948                 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
 949                         brgphy_fixup_5704_a0_bug(sc);
 950                 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
 951                         brgphy_fixup_adc_bug(sc);
 952                 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
 953                         brgphy_fixup_adjust_trim(sc);
 954                 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
 955                         brgphy_fixup_ber_bug(sc);
 956                 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
 957                         brgphy_fixup_crc_bug(sc);
 958                 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
 959                         brgphy_fixup_jitter_bug(sc);
 960
 961                 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
 962                         brgphy_jumbo_settings(sc, ifp->if_mtu);
 963
 964                 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
 965                         brgphy_ethernet_wirespeed(sc);
 966
 967                 /* Enable Link LED on Dell boxes */
 968                 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
 969                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 970                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 971                             ~BRGPHY_PHY_EXTCTL_3_LED);
 972                 }
 973
 974                 /* Adjust output voltage (From Linux driver) */
 975                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 976                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 977         } else if (bce_sc) {
 978                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 979                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
 980
 981                         /* Store autoneg capabilities/results in digital block (Page 0) */
 982                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 983                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 984                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
 985                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 986
 987                         /* Enable fiber mode and autodetection */
 988                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
 989                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
 990                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
 991                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
 992
 993                         /* Enable parallel detection */
 994                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
 995                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
 996                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
 997
 998                         /* Advertise 2.5G support through next page during autoneg */
 999                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1000                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1001                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1002                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1003
1004                         /* Increase TX signal amplitude */
1005                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1006                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1007                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1008                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1009                                         BRGPHY_5708S_TX_MISC_PG5);
1010                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1011                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1012                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1013                                         BRGPHY_5708S_DIG_PG0);
1014                         }
1015
1016                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1017                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1018                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1019                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1020                                                 BRGPHY_5708S_TX_MISC_PG5);
1021                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1022                                                 bce_sc->bce_port_hw_cfg &
1023                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1024                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1025                                                 BRGPHY_5708S_DIG_PG0);
1026                         }
1027                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1028                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1029
1030                         /* Select the SerDes Digital block of the AN MMD. */
1031                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1032                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1033                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1034                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1035                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1036
1037                         /* Select the Over 1G block of the AN MMD. */
1038                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1039
1040                         /* Enable autoneg "Next Page" to advertise 2.5G support. */
1041                         val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1042                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1043                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1044                         else
1045                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1046                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1047
1048                         /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1049                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1050
1051                         /* Enable MRBE speed autoneg. */
1052                         val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1053                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1054                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1055                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1056
1057                         /* Select the Clause 73 User B0 block of the AN MMD. */
1058                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1059
1060                         /* Enable MRBE speed autoneg. */
1061                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1062                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1063                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1064                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1065
1066                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1067                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1068         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1069                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1070                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1071                                 brgphy_fixup_disable_early_dac(sc);
1072
1073                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1074                         brgphy_ethernet_wirespeed(sc);
1075                 } else {
1076                         brgphy_fixup_ber_bug(sc);
1077                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1078                         brgphy_ethernet_wirespeed(sc);
1079                 }
1080         }
1081 }