sys/dev/nxge/include/xgehal-regs.h

   1 /*-
   2  * Copyright (c) 2002-2007 Neterion, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef XGE_HAL_REGS_H
  30 #define XGE_HAL_REGS_H
  31
  32 __EXTERN_BEGIN_DECLS
  33
  34 typedef struct {
  35
  36 /* General Control-Status Registers */
  37         u64 general_int_status;
  38 #define XGE_HAL_GEN_INTR_TXPIC             BIT(0)
  39 #define XGE_HAL_GEN_INTR_TXDMA             BIT(1)
  40 #define XGE_HAL_GEN_INTR_TXMAC             BIT(2)
  41 #define XGE_HAL_GEN_INTR_TXXGXS            BIT(3)
  42 #define XGE_HAL_GEN_INTR_TXTRAFFIC         BIT(8)
  43 #define XGE_HAL_GEN_INTR_RXPIC             BIT(32)
  44 #define XGE_HAL_GEN_INTR_RXDMA             BIT(33)
  45 #define XGE_HAL_GEN_INTR_RXMAC             BIT(34)
  46 #define XGE_HAL_GEN_INTR_MC                BIT(35)
  47 #define XGE_HAL_GEN_INTR_RXXGXS            BIT(36)
  48 #define XGE_HAL_GEN_INTR_RXTRAFFIC         BIT(40)
  49 #define XGE_HAL_GEN_ERROR_INTR             (XGE_HAL_GEN_INTR_TXPIC  | \
  50                          XGE_HAL_GEN_INTR_RXPIC  | \
  51                          XGE_HAL_GEN_INTR_TXDMA  | \
  52                          XGE_HAL_GEN_INTR_RXDMA  | \
  53                          XGE_HAL_GEN_INTR_TXMAC  | \
  54                          XGE_HAL_GEN_INTR_RXMAC  | \
  55                          XGE_HAL_GEN_INTR_TXXGXS | \
  56                          XGE_HAL_GEN_INTR_RXXGXS | \
  57                          XGE_HAL_GEN_INTR_MC)
  58
  59         u64 general_int_mask;
  60
  61         u8 unused0[0x100 - 0x10];
  62
  63         u64 sw_reset;
  64
  65 /* XGXS must be removed from reset only once. */
  66 #define XGE_HAL_SW_RESET_XENA              vBIT(0xA5,0,8)
  67 #define XGE_HAL_SW_RESET_FLASH             vBIT(0xA5,8,8)
  68 #define XGE_HAL_SW_RESET_EOI               vBIT(0xA5,16,8)
  69 #define XGE_HAL_SW_RESET_XGXS              vBIT(0xA5,24,8)
  70 #define XGE_HAL_SW_RESET_ALL               (XGE_HAL_SW_RESET_XENA  | \
  71                             XGE_HAL_SW_RESET_FLASH | \
  72                             XGE_HAL_SW_RESET_EOI | \
  73                             XGE_HAL_SW_RESET_XGXS)
  74
  75 /* The SW_RESET register must read this value after a successful reset. */
  76 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
  77 #define XGE_HAL_SW_RESET_RAW_VAL_XENA           0xA500000000ULL
  78 #define XGE_HAL_SW_RESET_RAW_VAL_HERC           0xA5A500000000ULL
  79 #else
  80 #define XGE_HAL_SW_RESET_RAW_VAL_XENA           0xA5000000ULL
  81 #define XGE_HAL_SW_RESET_RAW_VAL_HERC           0xA5A50000ULL
  82 #endif
  83
  84
  85         u64 adapter_status;
  86 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY          BIT(0)
  87 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY          BIT(1)
  88 #define XGE_HAL_ADAPTER_STATUS_PFC_READY           BIT(2)
  89 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY      BIT(3)
  90 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT       BIT(5)
  91 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT   BIT(6)
  92 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT    BIT(7)
  93 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE       vBIT(0xFF,8,8)
  94 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE     vBIT(0x0F,8,8)
  95 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR            vBIT(0x0F,0,8)
  96
  97 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT    vBIT(0xFF,16,8)
  98 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY       BIT(24)
  99 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY     BIT(25)
 100 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK          BIT(30)
 101 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK          BIT(31)
 102
 103         u64 adapter_control;
 104 #define XGE_HAL_ADAPTER_CNTL_EN                    BIT(7)
 105 #define XGE_HAL_ADAPTER_EOI_TX_ON                  BIT(15)
 106 #define XGE_HAL_ADAPTER_LED_ON                     BIT(23)
 107 #define XGE_HAL_ADAPTER_UDPI(val)                  vBIT(val,36,4)
 108 #define XGE_HAL_ADAPTER_WAIT_INT                   BIT(48)
 109 #define XGE_HAL_ADAPTER_ECC_EN                     BIT(55)
 110
 111         u64 serr_source;
 112 #define XGE_HAL_SERR_SOURCE_PIC                 BIT(0)
 113 #define XGE_HAL_SERR_SOURCE_TXDMA               BIT(1)
 114 #define XGE_HAL_SERR_SOURCE_RXDMA               BIT(2)
 115 #define XGE_HAL_SERR_SOURCE_MAC         BIT(3)
 116 #define XGE_HAL_SERR_SOURCE_MC          BIT(4)
 117 #define XGE_HAL_SERR_SOURCE_XGXS             BIT(5)
 118 #define XGE_HAL_SERR_SOURCE_ANY     (XGE_HAL_SERR_SOURCE_PIC   | \
 119                          XGE_HAL_SERR_SOURCE_TXDMA | \
 120                          XGE_HAL_SERR_SOURCE_RXDMA | \
 121                          XGE_HAL_SERR_SOURCE_MAC   | \
 122                          XGE_HAL_SERR_SOURCE_MC    | \
 123                          XGE_HAL_SERR_SOURCE_XGXS)
 124
 125         u64 pci_info;
 126 #define XGE_HAL_PCI_INFO            vBIT(0xF,0,4)
 127 #define XGE_HAL_PCI_32_BIT          BIT(8)
 128
 129         u8 unused0_1[0x160 - 0x128];
 130
 131         u64 ric_status;
 132
 133         u8  unused0_2[0x558 - 0x168];
 134
 135         u64 mbist_status;
 136
 137         u8  unused0_3[0x800 - 0x560];
 138
 139 /* PCI-X Controller registers */
 140         u64 pic_int_status;
 141         u64 pic_int_mask;
 142 #define XGE_HAL_PIC_INT_TX                     BIT(0)
 143 #define XGE_HAL_PIC_INT_FLSH                   BIT(1)
 144 #define XGE_HAL_PIC_INT_MDIO                   BIT(2)
 145 #define XGE_HAL_PIC_INT_IIC                    BIT(3)
 146 #define XGE_HAL_PIC_INT_MISC                   BIT(4)
 147 #define XGE_HAL_PIC_INT_RX                     BIT(32)
 148
 149         u64 txpic_int_reg;
 150 #define XGE_HAL_TXPIC_INT_SCHED_INTR            BIT(42)
 151         u64 txpic_int_mask;
 152 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR                BIT(0)
 153 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR                BIT(1)
 154 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR          BIT(8)
 155 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR          BIT(9)
 156 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR           BIT(10)
 157 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR           BIT(11)
 158 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR              BIT(13)
 159 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR              BIT(14)
 160 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR             BIT(15)
 161 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR      BIT(21)
 162 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR       BIT(23)
 163 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR           BIT(48)
 164 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR            BIT(50)
 165 /*
 166 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR      BIT(52)
 167 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR       BIT(54)
 168 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR     BIT(58)
 169 */
 170         u64 txpic_alarms;
 171         u64 rxpic_int_reg;
 172 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY               BIT(0)
 173 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR       BIT(44)
 174 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR                BIT(55)
 175         u64 rxpic_int_mask;
 176         u64 rxpic_alarms;
 177
 178         u64 flsh_int_reg;
 179         u64 flsh_int_mask;
 180 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR          BIT(63)
 181 #define XGE_HAL_PIC_FLSH_INT_REG_ERR                    BIT(62)
 182         u64 flash_alarms;
 183
 184         u64 mdio_int_reg;
 185         u64 mdio_int_mask;
 186 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR              BIT(0)
 187 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR               BIT(8)
 188 #define XGE_HAL_MDIO_INT_REG_LASI                      BIT(39)
 189         u64 mdio_alarms;
 190
 191         u64 iic_int_reg;
 192         u64 iic_int_mask;
 193 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR                BIT(4)
 194 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR                BIT(5)
 195 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR              BIT(6)
 196 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR                BIT(7)
 197 #define XGE_HAL_IIC_INT_REG_ACK_ERR                    BIT(8)
 198         u64 iic_alarms;
 199
 200         u64 msi_pending_reg;
 201
 202         u64 misc_int_reg;
 203 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT         BIT(0)
 204 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT      BIT(1)
 205 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT        BIT(2)
 206         u64 misc_int_mask;
 207         u64 misc_alarms;
 208
 209         u64 msi_triggered_reg;
 210
 211         u64 xfp_gpio_int_reg;
 212         u64 xfp_gpio_int_mask;
 213         u64 xfp_alarms;
 214
 215         u8  unused5[0x8E0 - 0x8C8];
 216
 217         u64 tx_traffic_int;
 218 #define XGE_HAL_TX_TRAFFIC_INT_n(n)                     BIT(n)
 219         u64 tx_traffic_mask;
 220
 221         u64 rx_traffic_int;
 222 #define XGE_HAL_RX_TRAFFIC_INT_n(n)                     BIT(n)
 223         u64 rx_traffic_mask;
 224
 225 /* PIC Control registers */
 226         u64 pic_control;
 227 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1                BIT(0)
 228 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT                 BIT(1)
 229 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n)              vBIT(n,11,4)
 230
 231         u64 swapper_ctrl;
 232 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE                  BIT(0)
 233 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE                  BIT(1)
 234 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE                  BIT(8)
 235 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE                  BIT(9)
 236 #define XGE_HAL_SWAPPER_CTRL_RTH_FE                    BIT(10)
 237 #define XGE_HAL_SWAPPER_CTRL_RTH_SE                    BIT(11)
 238 #define XGE_HAL_SWAPPER_CTRL_TXP_FE                    BIT(16)
 239 #define XGE_HAL_SWAPPER_CTRL_TXP_SE                    BIT(17)
 240 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE                  BIT(18)
 241 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE                  BIT(19)
 242 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE                  BIT(20)
 243 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE                  BIT(21)
 244 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE                  BIT(22)
 245 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE                  BIT(23)
 246 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE                  BIT(32)
 247 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE                  BIT(33)
 248 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE                  BIT(34)
 249 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE                  BIT(35)
 250 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE                  BIT(36)
 251 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE                  BIT(37)
 252 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE                   BIT(40)
 253 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE                   BIT(41)
 254 #define XGE_HAL_SWAPPER_CTRL_STATS_FE                  BIT(48)
 255 #define XGE_HAL_SWAPPER_CTRL_STATS_SE                  BIT(49)
 256
 257         u64 pif_rd_swapper_fb;
 258 #define XGE_HAL_IF_RD_SWAPPER_FB   0x0123456789ABCDEFULL
 259
 260         u64 scheduled_int_ctrl;
 261 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN                BIT(0)
 262 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT                BIT(1)
 263 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val)      vBIT(val,10,6)
 264 #define XGE_HAL_SCHED_INT_PERIOD(val)            vBIT(val,32,32)
 265 #define XGE_HAL_SCHED_INT_PERIOD_MASK            0xFFFFFFFF00000000ULL
 266
 267
 268         u64 txreqtimeout;
 269 #define XGE_HAL_TXREQTO_VAL(val)        vBIT(val,0,32)
 270 #define XGE_HAL_TXREQTO_EN          BIT(63)
 271
 272         u64 statsreqtimeout;
 273 #define XGE_HAL_STATREQTO_VAL(n)                  TBD
 274 #define XGE_HAL_STATREQTO_EN                      BIT(63)
 275
 276         u64 read_retry_delay;
 277         u64 read_retry_acceleration;
 278         u64 write_retry_delay;
 279         u64 write_retry_acceleration;
 280
 281         u64 xmsi_control;
 282 #define XGE_HAL_XMSI_EN             BIT(0)
 283 #define XGE_HAL_XMSI_DIS_TINT_SERR      BIT(1)
 284 #define XGE_HAL_XMSI_BYTE_COUNT(val)        vBIT(val,13,3)
 285
 286         u64 xmsi_access;
 287 #define XGE_HAL_XMSI_WR_RDN         BIT(7)
 288 #define XGE_HAL_XMSI_STROBE         BIT(15)
 289 #define XGE_HAL_XMSI_NO(val)            vBIT(val,26,6)
 290
 291         u64 xmsi_address;
 292         u64 xmsi_data;
 293
 294         u64 rx_mat;
 295 #define XGE_HAL_SET_RX_MAT(ring, msi)   vBIT(msi, (8 * ring), 8)
 296
 297         u8 unused6[0x8];
 298
 299         u64 tx_mat[8];
 300 #define XGE_HAL_SET_TX_MAT(fifo, msi)   vBIT(msi, (8 * fifo), 8)
 301
 302         u64 xmsi_mask_reg;
 303
 304         /* Automated statistics collection */
 305         u64 stat_byte_cnt;
 306         u64 stat_cfg;
 307 #define XGE_HAL_STAT_CFG_STAT_EN           BIT(0)
 308 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN       BIT(1)
 309 #define XGE_HAL_STAT_CFG_STAT_NS_EN        BIT(8)
 310 #define XGE_HAL_STAT_CFG_STAT_RO           BIT(9)
 311 #define XGE_HAL_XENA_PER_SEC               0x208d5
 312 #define XGE_HAL_SET_UPDT_PERIOD(n)     vBIT(n,32,32)
 313
 314         u64 stat_addr;
 315
 316         /* General Configuration */
 317         u64 mdio_control;
 318 #define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n)   vBIT(n,0,16)
 319 #define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n)    vBIT(n,19,5)
 320 #define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n)    vBIT(n,27,5)
 321 #define XGE_HAL_MDIO_CONTROL_MMD_DATA(n)    vBIT(n,32,16)
 322 #define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n)    vBIT(n,56,4)
 323 #define XGE_HAL_MDIO_CONTROL_MMD_OP(n)      vBIT(n,60,2)
 324 #define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n)    ((n>>16)&0xFFFF)
 325 #define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR       0x01
 326 #define XGE_HAL_MDIO_DOM_REG_ADDR       0xA100
 327 #define XGE_HAL_MDIO_ALARM_FLAGS_ADDR       0xA070
 328 #define XGE_HAL_MDIO_WARN_FLAGS_ADDR        0xA074
 329 #define XGE_HAL_MDIO_CTRL_START         0xE
 330 #define XGE_HAL_MDIO_OP_ADDRESS         0x0
 331 #define XGE_HAL_MDIO_OP_WRITE           0x1
 332 #define XGE_HAL_MDIO_OP_READ            0x3
 333 #define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2
 334 #define XGE_HAL_MDIO_ALARM_TEMPHIGH     0x0080
 335 #define XGE_HAL_MDIO_ALARM_TEMPLOW      0x0040
 336 #define XGE_HAL_MDIO_ALARM_BIASHIGH     0x0008
 337 #define XGE_HAL_MDIO_ALARM_BIASLOW      0x0004
 338 #define XGE_HAL_MDIO_ALARM_POUTPUTHIGH      0x0002
 339 #define XGE_HAL_MDIO_ALARM_POUTPUTLOW       0x0001
 340 #define XGE_HAL_MDIO_WARN_TEMPHIGH      0x0080
 341 #define XGE_HAL_MDIO_WARN_TEMPLOW       0x0040
 342 #define XGE_HAL_MDIO_WARN_BIASHIGH      0x0008
 343 #define XGE_HAL_MDIO_WARN_BIASLOW       0x0004
 344 #define XGE_HAL_MDIO_WARN_POUTPUTHIGH       0x0002
 345 #define XGE_HAL_MDIO_WARN_POUTPUTLOW        0x0001
 346
 347         u64 dtx_control;
 348
 349         u64 i2c_control;
 350 #define XGE_HAL_I2C_CONTROL_DEV_ID(id)      vBIT(id,1,3)
 351 #define XGE_HAL_I2C_CONTROL_ADDR(addr)      vBIT(addr,5,11)
 352 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt)   vBIT(cnt,22,2)
 353 #define XGE_HAL_I2C_CONTROL_READ        BIT(24)
 354 #define XGE_HAL_I2C_CONTROL_NACK        BIT(25)
 355 #define XGE_HAL_I2C_CONTROL_CNTL_START      vBIT(0xE,28,4)
 356 #define XGE_HAL_I2C_CONTROL_CNTL_END(val)   (val & vBIT(0x1,28,4))
 357 #define XGE_HAL_I2C_CONTROL_GET_DATA(val)   (u32)(val & 0xFFFFFFFF)
 358 #define XGE_HAL_I2C_CONTROL_SET_DATA(val)   vBIT(val,32,32)
 359
 360         u64 beacon_control;
 361         u64 misc_control;
 362 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3)
 363 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN     BIT(1)
 364 #define XGE_HAL_MISC_CONTROL_LINK_FAULT     BIT(0)
 365
 366         u64 xfb_control;
 367         u64 gpio_control;
 368 #define XGE_HAL_GPIO_CTRL_GPIO_0            BIT(8)
 369
 370         u64 txfifo_dw_mask;
 371         u64 split_table_line_no;
 372         u64 sc_timeout;
 373         u64 pic_control_2;
 374 #define XGE_HAL_TXD_WRITE_BC(n)                 vBIT(n, 13, 3)
 375         u64 ini_dperr_ctrl;
 376         u64 wreq_split_mask;
 377         u64 qw_per_rxd;
 378         u8  unused7[0x300 - 0x250];
 379
 380         u64 pic_status;
 381         u64 txp_status;
 382         u64 txp_err_context;
 383         u64 spdm_bir_offset;
 384 #define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset)   \
 385                     (u8)(spdm_bir_offset >> 61)
 386 #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \
 387                     (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF)
 388         u64 spdm_overwrite;
 389 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite)  \
 390                     (u8)((spdm_overwrite >> 48) & 0xff)
 391 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite)  \
 392                     (u8)((spdm_overwrite >> 40) & 0x3)
 393 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite)  \
 394                     (u8)((spdm_overwrite >> 32) & 0x7)
 395         u64 cfg_addr_on_dperr;
 396         u64 pif_addr_on_dperr;
 397         u64 tags_in_use;
 398         u64 rd_req_types;
 399         u64 split_table_line;
 400         u64 unxp_split_add_ph;
 401         u64 unexp_split_attr_ph;
 402         u64 split_message;
 403         u64 spdm_structure;
 404 #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure)  (u16)(spdm_structure >> 48)
 405 #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure)  \
 406                     (u8)((spdm_structure >> 40) & 0xff)
 407 #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure)  \
 408                     (u8)((spdm_structure >> 32) & 0xff)
 409
 410         u64 txdw_ptr_cnt_0;
 411         u64 txdw_ptr_cnt_1;
 412         u64 txdw_ptr_cnt_2;
 413         u64 txdw_ptr_cnt_3;
 414         u64 txdw_ptr_cnt_4;
 415         u64 txdw_ptr_cnt_5;
 416         u64 txdw_ptr_cnt_6;
 417         u64 txdw_ptr_cnt_7;
 418         u64 rxdw_cnt_ring_0;
 419         u64 rxdw_cnt_ring_1;
 420         u64 rxdw_cnt_ring_2;
 421         u64 rxdw_cnt_ring_3;
 422         u64 rxdw_cnt_ring_4;
 423         u64 rxdw_cnt_ring_5;
 424         u64 rxdw_cnt_ring_6;
 425         u64 rxdw_cnt_ring_7;
 426
 427         u8  unused8[0x410];
 428
 429 /* TxDMA registers */
 430         u64 txdma_int_status;
 431         u64 txdma_int_mask;
 432 #define XGE_HAL_TXDMA_PFC_INT           BIT(0)
 433 #define XGE_HAL_TXDMA_TDA_INT           BIT(1)
 434 #define XGE_HAL_TXDMA_PCC_INT           BIT(2)
 435 #define XGE_HAL_TXDMA_TTI_INT           BIT(3)
 436 #define XGE_HAL_TXDMA_LSO_INT           BIT(4)
 437 #define XGE_HAL_TXDMA_TPA_INT           BIT(5)
 438 #define XGE_HAL_TXDMA_SM_INT            BIT(6)
 439         u64 pfc_err_reg;
 440 #define XGE_HAL_PFC_ECC_SG_ERR          BIT(7)
 441 #define XGE_HAL_PFC_ECC_DB_ERR          BIT(15)
 442 #define XGE_HAL_PFC_SM_ERR_ALARM        BIT(23)
 443 #define XGE_HAL_PFC_MISC_0_ERR          BIT(31)
 444 #define XGE_HAL_PFC_MISC_1_ERR          BIT(32)
 445 #define XGE_HAL_PFC_PCIX_ERR            BIT(39)
 446         u64 pfc_err_mask;
 447         u64 pfc_err_alarm;
 448
 449         u64 tda_err_reg;
 450 #define XGE_HAL_TDA_Fn_ECC_SG_ERR       vBIT(0xff,0,8)
 451 #define XGE_HAL_TDA_Fn_ECC_DB_ERR       vBIT(0xff,8,8)
 452 #define XGE_HAL_TDA_SM0_ERR_ALARM       BIT(22)
 453 #define XGE_HAL_TDA_SM1_ERR_ALARM       BIT(23)
 454 #define XGE_HAL_TDA_PCIX_ERR            BIT(39)
 455         u64 tda_err_mask;
 456         u64 tda_err_alarm;
 457
 458         u64 pcc_err_reg;
 459 #define XGE_HAL_PCC_FB_ECC_SG_ERR       vBIT(0xFF,0,8)
 460 #define XGE_HAL_PCC_TXB_ECC_SG_ERR      vBIT(0xFF,8,8)
 461 #define XGE_HAL_PCC_FB_ECC_DB_ERR       vBIT(0xFF,16, 8)
 462 #define XGE_HAL_PCC_TXB_ECC_DB_ERR      vBIT(0xff,24,8)
 463 #define XGE_HAL_PCC_SM_ERR_ALARM        vBIT(0xff,32,8)
 464 #define XGE_HAL_PCC_WR_ERR_ALARM        vBIT(0xff,40,8)
 465 #define XGE_HAL_PCC_N_SERR          vBIT(0xff,48,8)
 466 #define XGE_HAL_PCC_ENABLE_FOUR         vBIT(0x0F,0,8)
 467 #define XGE_HAL_PCC_6_COF_OV_ERR        BIT(56)
 468 #define XGE_HAL_PCC_7_COF_OV_ERR        BIT(57)
 469 #define XGE_HAL_PCC_6_LSO_OV_ERR        BIT(58)
 470 #define XGE_HAL_PCC_7_LSO_OV_ERR        BIT(59)
 471         u64 pcc_err_mask;
 472         u64 pcc_err_alarm;
 473
 474         u64 tti_err_reg;
 475 #define XGE_HAL_TTI_ECC_SG_ERR          BIT(7)
 476 #define XGE_HAL_TTI_ECC_DB_ERR          BIT(15)
 477 #define XGE_HAL_TTI_SM_ERR_ALARM        BIT(23)
 478         u64 tti_err_mask;
 479         u64 tti_err_alarm;
 480
 481         u64 lso_err_reg;
 482 #define XGE_HAL_LSO6_SEND_OFLOW         BIT(12)
 483 #define XGE_HAL_LSO7_SEND_OFLOW         BIT(13)
 484 #define XGE_HAL_LSO6_ABORT          BIT(14)
 485 #define XGE_HAL_LSO7_ABORT          BIT(15)
 486 #define XGE_HAL_LSO6_SM_ERR_ALARM       BIT(22)
 487 #define XGE_HAL_LSO7_SM_ERR_ALARM       BIT(23)
 488         u64 lso_err_mask;
 489         u64 lso_err_alarm;
 490
 491         u64 tpa_err_reg;
 492 #define XGE_HAL_TPA_TX_FRM_DROP         BIT(7)
 493 #define XGE_HAL_TPA_SM_ERR_ALARM        BIT(23)
 494         u64 tpa_err_mask;
 495         u64 tpa_err_alarm;
 496
 497         u64 sm_err_reg;
 498 #define XGE_HAL_SM_SM_ERR_ALARM         BIT(15)
 499         u64 sm_err_mask;
 500         u64 sm_err_alarm;
 501
 502         u8 unused9[0x100 - 0xB8];
 503
 504 /* TxDMA arbiter */
 505         u64 tx_dma_wrap_stat;
 506
 507 /* Tx FIFO controller */
 508 #define XGE_HAL_X_MAX_FIFOS                        8
 509 #define XGE_HAL_X_FIFO_MAX_LEN                     0x1FFF   /*8191 */
 510         u64 tx_fifo_partition_0;
 511 #define XGE_HAL_TX_FIFO_PARTITION_EN               BIT(0)
 512 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val)       vBIT(val,5,3)
 513 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val)       vBIT(val,19,13)
 514 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val)       vBIT(val,37,3)
 515 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val)       vBIT(val,51,13  )
 516
 517         u64 tx_fifo_partition_1;
 518 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val)       vBIT(val,5,3)
 519 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val)       vBIT(val,19,13)
 520 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val)       vBIT(val,37,3)
 521 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val)       vBIT(val,51,13)
 522
 523         u64 tx_fifo_partition_2;
 524 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val)       vBIT(val,5,3)
 525 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val)       vBIT(val,19,13)
 526 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val)       vBIT(val,37,3)
 527 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val)       vBIT(val,51,13)
 528
 529         u64 tx_fifo_partition_3;
 530 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val)       vBIT(val,5,3)
 531 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val)       vBIT(val,19,13)
 532 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val)       vBIT(val,37,3)
 533 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val)       vBIT(val,51,13)
 534
 535 #define XGE_HAL_TX_FIFO_PARTITION_PRI_0            0    /* highest */
 536 #define XGE_HAL_TX_FIFO_PARTITION_PRI_1            1
 537 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2            2
 538 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3            3
 539 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4            4
 540 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5            5
 541 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6            6
 542 #define XGE_HAL_TX_FIFO_PARTITION_PRI_7            7    /* lowest */
 543
 544         u64 tx_w_round_robin_0;
 545         u64 tx_w_round_robin_1;
 546         u64 tx_w_round_robin_2;
 547         u64 tx_w_round_robin_3;
 548         u64 tx_w_round_robin_4;
 549
 550         u64 tti_command_mem;
 551 #define XGE_HAL_TTI_CMD_MEM_WE                     BIT(7)
 552 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD         BIT(15)
 553 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED  BIT(15)
 554 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n)              vBIT(n,26,6)
 555
 556         u64 tti_data1_mem;
 557 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n)      vBIT(n,6,26)
 558 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n)    vBIT(n,38,2)
 559 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN       BIT(38)
 560 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN       BIT(39)
 561 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n)         vBIT(n,41,7)
 562 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n)         vBIT(n,49,7)
 563 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n)         vBIT(n,57,7)
 564
 565         u64 tti_data2_mem;
 566 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n)          vBIT(n,0,16)
 567 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n)          vBIT(n,16,16)
 568 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n)          vBIT(n,32,16)
 569 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n)          vBIT(n,48,16)
 570
 571 /* Tx Protocol assist */
 572         u64 tx_pa_cfg;
 573 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR           BIT(1)
 574 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI          BIT(2)
 575 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL          BIT(3)
 576 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR      BIT(6)
 577
 578 /* Recent add, used only debug purposes. */
 579         u64 pcc_enable;
 580
 581         u64 pfc_monitor_0;
 582         u64 pfc_monitor_1;
 583         u64 pfc_monitor_2;
 584         u64 pfc_monitor_3;
 585         u64 txd_ownership_ctrl;
 586         u64 pfc_read_cntrl;
 587         u64 pfc_read_data;
 588
 589         u8  unused10[0x1700 - 0x11B0];
 590
 591         u64 txdma_debug_ctrl;
 592
 593         u8 unused11[0x1800 - 0x1708];
 594
 595 /* RxDMA Registers */
 596         u64 rxdma_int_status;
 597 #define XGE_HAL_RXDMA_RC_INT                   BIT(0)
 598 #define XGE_HAL_RXDMA_RPA_INT                  BIT(1)
 599 #define XGE_HAL_RXDMA_RDA_INT                  BIT(2)
 600 #define XGE_HAL_RXDMA_RTI_INT                  BIT(3)
 601
 602         u64 rxdma_int_mask;
 603 #define XGE_HAL_RXDMA_INT_RC_INT_M             BIT(0)
 604 #define XGE_HAL_RXDMA_INT_RPA_INT_M            BIT(1)
 605 #define XGE_HAL_RXDMA_INT_RDA_INT_M            BIT(2)
 606 #define XGE_HAL_RXDMA_INT_RTI_INT_M            BIT(3)
 607
 608         u64 rda_err_reg;
 609 #define XGE_HAL_RDA_RXDn_ECC_SG_ERR     vBIT(0xFF,0,8)
 610 #define XGE_HAL_RDA_RXDn_ECC_DB_ERR     vBIT(0xFF,8,8)
 611 #define XGE_HAL_RDA_FRM_ECC_SG_ERR      BIT(23)
 612 #define XGE_HAL_RDA_FRM_ECC_DB_N_AERR       BIT(31)
 613 #define XGE_HAL_RDA_SM1_ERR_ALARM       BIT(38)
 614 #define XGE_HAL_RDA_SM0_ERR_ALARM       BIT(39)
 615 #define XGE_HAL_RDA_MISC_ERR            BIT(47)
 616 #define XGE_HAL_RDA_PCIX_ERR            BIT(55)
 617 #define XGE_HAL_RDA_RXD_ECC_DB_SERR     BIT(63)
 618         u64 rda_err_mask;
 619         u64 rda_err_alarm;
 620
 621         u64 rc_err_reg;
 622 #define XGE_HAL_RC_PRCn_ECC_SG_ERR      vBIT(0xFF,0,8)
 623 #define XGE_HAL_RC_PRCn_ECC_DB_ERR      vBIT(0xFF,8,8)
 624 #define XGE_HAL_RC_FTC_ECC_SG_ERR       BIT(23)
 625 #define XGE_HAL_RC_FTC_ECC_DB_ERR       BIT(31)
 626 #define XGE_HAL_RC_PRCn_SM_ERR_ALARM        vBIT(0xFF,32,8)
 627 #define XGE_HAL_RC_FTC_SM_ERR_ALARM     BIT(47)
 628 #define XGE_HAL_RC_RDA_FAIL_WR_Rn       vBIT(0xFF,48,8)
 629         u64 rc_err_mask;
 630         u64 rc_err_alarm;
 631
 632         u64 prc_pcix_err_reg;
 633 #define XGE_HAL_PRC_PCI_AB_RD_Rn        vBIT(0xFF,0,8)
 634 #define XGE_HAL_PRC_PCI_DP_RD_Rn        vBIT(0xFF,8,8)
 635 #define XGE_HAL_PRC_PCI_AB_WR_Rn        vBIT(0xFF,16,8)
 636 #define XGE_HAL_PRC_PCI_DP_WR_Rn        vBIT(0xFF,24,8)
 637 #define XGE_HAL_PRC_PCI_AB_F_WR_Rn      vBIT(0xFF,32,8)
 638 #define XGE_HAL_PRC_PCI_DP_F_WR_Rn      vBIT(0xFF,40,8)
 639         u64 prc_pcix_err_mask;
 640         u64 prc_pcix_err_alarm;
 641
 642         u64 rpa_err_reg;
 643 #define XGE_HAL_RPA_ECC_SG_ERR          BIT(7)
 644 #define XGE_HAL_RPA_ECC_DB_ERR          BIT(15)
 645 #define XGE_HAL_RPA_FLUSH_REQUEST       BIT(22)
 646 #define XGE_HAL_RPA_SM_ERR_ALARM        BIT(23)
 647 #define XGE_HAL_RPA_CREDIT_ERR          BIT(31)
 648         u64 rpa_err_mask;
 649         u64 rpa_err_alarm;
 650
 651         u64 rti_err_reg;
 652 #define XGE_HAL_RTI_ECC_SG_ERR          BIT(7)
 653 #define XGE_HAL_RTI_ECC_DB_ERR          BIT(15)
 654 #define XGE_HAL_RTI_SM_ERR_ALARM        BIT(23)
 655         u64 rti_err_mask;
 656         u64 rti_err_alarm;
 657
 658         u8 unused12[0x100 - 0x88];
 659
 660 /* DMA arbiter */
 661         u64 rx_queue_priority;
 662 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val)       vBIT(val,5,3)
 663 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val)       vBIT(val,13,3)
 664 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val)       vBIT(val,21,3)
 665 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val)       vBIT(val,29,3)
 666 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val)       vBIT(val,37,3)
 667 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val)       vBIT(val,45,3)
 668 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val)       vBIT(val,53,3)
 669 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val)       vBIT(val,61,3)
 670
 671 #define XGE_HAL_RX_QUEUE_PRI_0                 0    /* highest */
 672 #define XGE_HAL_RX_QUEUE_PRI_1                 1
 673 #define XGE_HAL_RX_QUEUE_PRI_2                 2
 674 #define XGE_HAL_RX_QUEUE_PRI_3                 3
 675 #define XGE_HAL_RX_QUEUE_PRI_4                 4
 676 #define XGE_HAL_RX_QUEUE_PRI_5                 5
 677 #define XGE_HAL_RX_QUEUE_PRI_6                 6
 678 #define XGE_HAL_RX_QUEUE_PRI_7                 7    /* lowest */
 679
 680         u64 rx_w_round_robin_0;
 681         u64 rx_w_round_robin_1;
 682         u64 rx_w_round_robin_2;
 683         u64 rx_w_round_robin_3;
 684         u64 rx_w_round_robin_4;
 685
 686         /* Per-ring controller regs */
 687 #define XGE_HAL_RX_MAX_RINGS                8
 688         u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS];
 689         u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS];
 690 #define XGE_HAL_PRC_CTRL_RC_ENABLED                    BIT(7)
 691 #define XGE_HAL_PRC_CTRL_RING_MODE                     (BIT(14)|BIT(15))
 692 #define XGE_HAL_PRC_CTRL_RING_MODE_1                   vBIT(0,14,2)
 693 #define XGE_HAL_PRC_CTRL_RING_MODE_3                   vBIT(1,14,2)
 694 #define XGE_HAL_PRC_CTRL_RING_MODE_5                   vBIT(2,14,2)
 695 #define XGE_HAL_PRC_CTRL_RING_MODE_x                   vBIT(3,14,2)
 696 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n)                   vBIT(n,22,2)
 697 #define XGE_HAL_PRC_CTRL_RTH_DISABLE                   BIT(31)
 698 #define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT             BIT(37)
 699 #define XGE_HAL_PRC_CTRL_GROUP_READS                   BIT(38)
 700 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val)     vBIT(val,40,24)
 701
 702         u64 prc_alarm_action;
 703 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP            BIT(3)
 704 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP            BIT(7)
 705 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP            BIT(11)
 706 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP            BIT(15)
 707 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP            BIT(19)
 708 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP            BIT(23)
 709 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP            BIT(27)
 710 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP            BIT(31)
 711 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP            BIT(35)
 712 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP            BIT(39)
 713 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP            BIT(43)
 714 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP            BIT(47)
 715 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP            BIT(51)
 716 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP            BIT(55)
 717 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP            BIT(59)
 718 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP            BIT(63)
 719
 720 /* Receive traffic interrupts */
 721         u64 rti_command_mem;
 722 #define XGE_HAL_RTI_CMD_MEM_WE                          BIT(7)
 723 #define XGE_HAL_RTI_CMD_MEM_STROBE                      BIT(15)
 724 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD              BIT(15)
 725 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED   BIT(15)
 726 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n)                   vBIT(n,29,3)
 727
 728         u64 rti_data1_mem;
 729 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n)      vBIT(n,3,29)
 730 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN       BIT(38)
 731 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN       BIT(39)
 732 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n)         vBIT(n,41,7)
 733 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n)         vBIT(n,49,7)
 734 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n)         vBIT(n,57,7)
 735
 736         u64 rti_data2_mem;
 737 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n)          vBIT(n,0,16)
 738 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n)          vBIT(n,16,16)
 739 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n)          vBIT(n,32,16)
 740 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n)          vBIT(n,48,16)
 741
 742         u64 rx_pa_cfg;
 743 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR           BIT(1)
 744 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI          BIT(2)
 745 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL          BIT(3)
 746 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n)          vBIT(n,6,1)
 747 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n)   vBIT(n,15,1)
 748
 749         u8 unused13_0[0x8];
 750
 751         u64 ring_bump_counter1;
 752         u64 ring_bump_counter2;
 753 #define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4))))
 754
 755         u8 unused13[0x700 - 0x1f0];
 756
 757         u64 rxdma_debug_ctrl;
 758
 759         u8 unused14[0x2000 - 0x1f08];
 760
 761 /* Media Access Controller Register */
 762         u64 mac_int_status;
 763         u64 mac_int_mask;
 764 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT            BIT(0)
 765 #define XGE_HAL_MAC_INT_STATUS_RMAC_INT            BIT(1)
 766
 767         u64 mac_tmac_err_reg;
 768 #define XGE_HAL_TMAC_ECC_DB_ERR         BIT(15)
 769 #define XGE_HAL_TMAC_TX_BUF_OVRN        BIT(23)
 770 #define XGE_HAL_TMAC_TX_CRI_ERR         BIT(31)
 771 #define XGE_HAL_TMAC_TX_SM_ERR          BIT(39)
 772         u64 mac_tmac_err_mask;
 773         u64 mac_tmac_err_alarm;
 774
 775         u64 mac_rmac_err_reg;
 776 #define XGE_HAL_RMAC_RX_BUFF_OVRN       BIT(0)
 777 #define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR    BIT(0)
 778 #define XGE_HAL_RMAC_RTS_ECC_DB_ERR     BIT(0)
 779 #define XGE_HAL_RMAC_ECC_DB_ERR         BIT(0)
 780 #define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR    BIT(0)
 781 #define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT  BIT(0)
 782 #define XGE_HAL_RMAC_RX_SM_ERR          BIT(39)
 783         u64 mac_rmac_err_mask;
 784         u64 mac_rmac_err_alarm;
 785
 786         u8 unused15[0x100 - 0x40];
 787
 788         u64 mac_cfg;
 789 #define XGE_HAL_MAC_CFG_TMAC_ENABLE             BIT(0)
 790 #define XGE_HAL_MAC_CFG_RMAC_ENABLE             BIT(1)
 791 #define XGE_HAL_MAC_CFG_LAN_NOT_WAN             BIT(2)
 792 #define XGE_HAL_MAC_CFG_TMAC_LOOPBACK           BIT(3)
 793 #define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD         BIT(4)
 794 #define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS          BIT(5)
 795 #define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD          BIT(6)
 796 #define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE        BIT(7)
 797 #define XGE_HAL_MAC_RMAC_DISCARD_PFRM           BIT(8)
 798 #define XGE_HAL_MAC_RMAC_BCAST_ENABLE           BIT(9)
 799 #define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE        BIT(10)
 800 #define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val)     vBIT(val,16,8)
 801
 802         u64 tmac_avg_ipg;
 803 #define XGE_HAL_TMAC_AVG_IPG(val)           vBIT(val,0,8)
 804
 805         u64 rmac_max_pyld_len;
 806 #define XGE_HAL_RMAC_MAX_PYLD_LEN(val)      vBIT(val,2,14)
 807
 808         u64 rmac_err_cfg;
 809 #define XGE_HAL_RMAC_ERR_FCS                    BIT(0)
 810 #define XGE_HAL_RMAC_ERR_FCS_ACCEPT             BIT(1)
 811 #define XGE_HAL_RMAC_ERR_TOO_LONG               BIT(1)
 812 #define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT        BIT(1)
 813 #define XGE_HAL_RMAC_ERR_RUNT                   BIT(2)
 814 #define XGE_HAL_RMAC_ERR_RUNT_ACCEPT            BIT(2)
 815 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH           BIT(3)
 816 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT    BIT(3)
 817
 818         u64 rmac_cfg_key;
 819 #define XGE_HAL_RMAC_CFG_KEY(val)               vBIT(val,0,16)
 820
 821 #define XGE_HAL_MAX_MAC_ADDRESSES               64
 822 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET       63
 823 #define XGE_HAL_MAX_MAC_ADDRESSES_HERC          256
 824 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC  255
 825
 826         u64 rmac_addr_cmd_mem;
 827 #define XGE_HAL_RMAC_ADDR_CMD_MEM_WE                    BIT(7)
 828 #define XGE_HAL_RMAC_ADDR_CMD_MEM_RD                    0
 829 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD        BIT(15)
 830 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING  BIT(15)
 831 #define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n)             vBIT(n,26,6)
 832
 833         u64 rmac_addr_data0_mem;
 834 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n)    vBIT(n,0,48)
 835 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER       BIT(48)
 836
 837         u64 rmac_addr_data1_mem;
 838 #define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n)    vBIT(n,0,48)
 839
 840         u8 unused16[0x8];
 841
 842 /*
 843             u64 rmac_addr_cfg;
 844 #define XGE_HAL_RMAC_ADDR_UCASTn_EN(n)     mBIT(0)_n(n)
 845 #define XGE_HAL_RMAC_ADDR_MCASTn_EN(n)     mBIT(0)_n(n)
 846 #define XGE_HAL_RMAC_ADDR_BCAST_EN         vBIT(0)_48
 847 #define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN      vBIT(0)_49
 848 */
 849         u64 tmac_ipg_cfg;
 850
 851         u64 rmac_pause_cfg;
 852 #define XGE_HAL_RMAC_PAUSE_GEN_EN          BIT(0)
 853 #define XGE_HAL_RMAC_PAUSE_RCV_EN          BIT(1)
 854 #define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF    vBIT(0xFFFF,16,16)
 855 #define XGE_HAL_RMAC_PAUSE_HG_PTIME(val)    vBIT(val,16,16)
 856
 857         u64 rmac_red_cfg;
 858
 859         u64 rmac_red_rate_q0q3;
 860         u64 rmac_red_rate_q4q7;
 861
 862         u64 mac_link_util;
 863 #define XGE_HAL_MAC_TX_LINK_UTIL           vBIT(0xFE,1,7)
 864 #define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE   vBIT(0xF, 8,4)
 865 #define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n )  vBIT(n,8,4)
 866 #define XGE_HAL_MAC_RX_LINK_UTIL           vBIT(0xFE,33,7)
 867 #define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE   vBIT(0xF,40,4)
 868 #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n )  vBIT(n,40,4)
 869
 870 #define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \
 871                            XGE_HAL_MAC_RX_LINK_UTIL_DISABLE)
 872
 873         u64 rmac_invalid_ipg;
 874
 875 /* rx traffic steering */
 876 #define XGE_HAL_MAC_RTS_FRM_LEN_SET(len)    vBIT(len,2,14)
 877         u64 rts_frm_len_n[8];
 878
 879         u64 rts_qos_steering;
 880
 881 #define XGE_HAL_MAX_DIX_MAP                         4
 882         u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP];
 883 #define XGE_HAL_RTS_DIX_MAP_ETYPE(val)             vBIT(val,0,16)
 884 #define XGE_HAL_RTS_DIX_MAP_SCW(val)               BIT(val,21)
 885
 886         u64 rts_q_alternates;
 887         u64 rts_default_q;
 888 #define XGE_HAL_RTS_DEFAULT_Q(n)           vBIT(n,5,3)
 889
 890         u64 rts_ctrl;
 891 #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI           BIT(2)
 892 #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL           BIT(3)
 893 #define XGE_HAL_RTS_CTRL_ENHANCED_MODE         BIT(7)
 894
 895         u64 rts_pn_cam_ctrl;
 896 #define XGE_HAL_RTS_PN_CAM_CTRL_WE                 BIT(7)
 897 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD     BIT(15)
 898 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED   BIT(15)
 899 #define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n)          vBIT(n,24,8)
 900         u64 rts_pn_cam_data;
 901 #define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT         BIT(7)
 902 #define XGE_HAL_RTS_PN_CAM_DATA_PORT(val)          vBIT(val,8,16)
 903 #define XGE_HAL_RTS_PN_CAM_DATA_SCW(val)           vBIT(val,24,8)
 904
 905         u64 rts_ds_mem_ctrl;
 906 #define XGE_HAL_RTS_DS_MEM_CTRL_WE                 BIT(7)
 907 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD     BIT(15)
 908 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED   BIT(15)
 909 #define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n)          vBIT(n,26,6)
 910         u64 rts_ds_mem_data;
 911 #define XGE_HAL_RTS_DS_MEM_DATA(n)                 vBIT(n,0,8)
 912
 913         u8  unused16_1[0x308 - 0x220];
 914
 915         u64 rts_vid_mem_ctrl;
 916         u64 rts_vid_mem_data;
 917         u64 rts_p0_p3_map;
 918         u64 rts_p4_p7_map;
 919         u64 rts_p8_p11_map;
 920         u64 rts_p12_p15_map;
 921
 922         u64 rts_mac_cfg;
 923 #define XGE_HAL_RTS_MAC_SECT0_EN                    BIT(0)
 924 #define XGE_HAL_RTS_MAC_SECT1_EN                    BIT(1)
 925 #define XGE_HAL_RTS_MAC_SECT2_EN                    BIT(2)
 926 #define XGE_HAL_RTS_MAC_SECT3_EN                    BIT(3)
 927 #define XGE_HAL_RTS_MAC_SECT4_EN                    BIT(4)
 928 #define XGE_HAL_RTS_MAC_SECT5_EN                    BIT(5)
 929 #define XGE_HAL_RTS_MAC_SECT6_EN                    BIT(6)
 930 #define XGE_HAL_RTS_MAC_SECT7_EN                    BIT(7)
 931
 932         u8 unused16_2[0x380 - 0x340];
 933
 934         u64 rts_rth_cfg;
 935 #define XGE_HAL_RTS_RTH_EN                         BIT(3)
 936 #define XGE_HAL_RTS_RTH_BUCKET_SIZE(n)             vBIT(n,4,4)
 937 #define XGE_HAL_RTS_RTH_ALG_SEL_MS                 BIT(11)
 938 #define XGE_HAL_RTS_RTH_TCP_IPV4_EN                BIT(15)
 939 #define XGE_HAL_RTS_RTH_UDP_IPV4_EN                BIT(19)
 940 #define XGE_HAL_RTS_RTH_IPV4_EN                    BIT(23)
 941 #define XGE_HAL_RTS_RTH_TCP_IPV6_EN                BIT(27)
 942 #define XGE_HAL_RTS_RTH_UDP_IPV6_EN                BIT(31)
 943 #define XGE_HAL_RTS_RTH_IPV6_EN                    BIT(35)
 944 #define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN             BIT(39)
 945 #define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN             BIT(43)
 946 #define XGE_HAL_RTS_RTH_IPV6_EX_EN                 BIT(47)
 947
 948         u64 rts_rth_map_mem_ctrl;
 949 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE            BIT(7)
 950 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE        BIT(15)
 951 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n)     vBIT(n,24,8)
 952
 953         u64 rts_rth_map_mem_data;
 954 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN      BIT(3)
 955 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n)            vBIT(n,5,3)
 956
 957         u64 rts_rth_spdm_mem_ctrl;
 958 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE       BIT(15)
 959 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n)  vBIT(n,21,3)
 960 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n)    vBIT(n,24,8)
 961
 962         u64 rts_rth_spdm_mem_data;
 963
 964         u64 rts_rth_jhash_cfg;
 965 #define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n)            vBIT(n,0,32)
 966 #define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n)          vBIT(n,32,32)
 967
 968         u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */
 969         u64 rts_rth_hash_mask_5;
 970 #define XGE_HAL_RTH_HASH_MASK_5(n)                 vBIT(n,0,32)
 971
 972         u64 rts_rth_status;
 973 #define XGE_HAL_RTH_STATUS_SPDM_USE_L4             BIT(3)
 974
 975         u8  unused17[0x400 - 0x3E8];
 976
 977         u64 rmac_red_fine_q0q3;
 978         u64 rmac_red_fine_q4q7;
 979         u64 rmac_pthresh_cross;
 980         u64 rmac_rthresh_cross;
 981         u64 rmac_pnum_range[32];
 982
 983         u64 rmac_mp_crc_0;
 984         u64 rmac_mp_mask_a_0;
 985         u64 rmac_mp_mask_b_0;
 986
 987         u64 rmac_mp_crc_1;
 988         u64 rmac_mp_mask_a_1;
 989         u64 rmac_mp_mask_b_1;
 990
 991         u64 rmac_mp_crc_2;
 992         u64 rmac_mp_mask_a_2;
 993         u64 rmac_mp_mask_b_2;
 994
 995         u64 rmac_mp_crc_3;
 996         u64 rmac_mp_mask_a_3;
 997         u64 rmac_mp_mask_b_3;
 998
 999         u64 rmac_mp_crc_4;
1000         u64 rmac_mp_mask_a_4;
1001         u64 rmac_mp_mask_b_4;
1002
1003         u64 rmac_mp_crc_5;
1004         u64 rmac_mp_mask_a_5;
1005         u64 rmac_mp_mask_b_5;
1006
1007         u64 rmac_mp_crc_6;
1008         u64 rmac_mp_mask_a_6;
1009         u64 rmac_mp_mask_b_6;
1010
1011         u64 rmac_mp_crc_7;
1012         u64 rmac_mp_mask_a_7;
1013         u64 rmac_mp_mask_b_7;
1014
1015         u64 mac_ctrl;
1016         u64 activity_control;
1017
1018         u8  unused17_2[0x700 - 0x5F0];
1019
1020         u64 mac_debug_ctrl;
1021 #define XGE_HAL_MAC_DBG_ACTIVITY_VALUE         0x411040400000000ULL
1022
1023         u8 unused18[0x2800 - 0x2708];
1024
1025 /* memory controller registers */
1026         u64 mc_int_status;
1027 #define XGE_HAL_MC_INT_STATUS_MC_INT               BIT(0)
1028         u64 mc_int_mask;
1029 #define XGE_HAL_MC_INT_MASK_MC_INT                 BIT(0)
1030
1031         u64 mc_err_reg;
1032 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L        BIT(2) /* non-Xena */
1033 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U        BIT(3) /* non-Xena */
1034 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L        BIT(4) /* non-Xena */
1035 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U        BIT(5) /* non-Xena */
1036 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L        BIT(6)
1037 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U        BIT(7)
1038 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L        BIT(10) /* non-Xena */
1039 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U        BIT(11) /* non-Xena */
1040 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L        BIT(12) /* non-Xena */
1041 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U        BIT(13) /* non-Xena */
1042 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L        BIT(14)
1043 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U        BIT(15)
1044 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0       BIT(17)
1045 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0       BIT(18) /* Xena: reset */
1046 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1       BIT(19)
1047 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1       BIT(20) /* Xena: reset */
1048 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0          BIT(22)
1049 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1          BIT(23)
1050 #define XGE_HAL_MC_ERR_REG_SM_ERR                  BIT(31)
1051 #define XGE_HAL_MC_ERR_REG_PL_LOCK_N               BIT(39)
1052
1053         u64 mc_err_mask;
1054         u64 mc_err_alarm;
1055
1056         u8 unused19[0x100 - 0x28];
1057
1058 /* MC configuration */
1059         u64 rx_queue_cfg;
1060 #define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n)              vBIT(n,0,8)
1061 #define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n)              vBIT(n,8,8)
1062 #define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n)              vBIT(n,16,8)
1063 #define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n)              vBIT(n,24,8)
1064 #define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n)              vBIT(n,32,8)
1065 #define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n)              vBIT(n,40,8)
1066 #define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n)              vBIT(n,48,8)
1067 #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n)              vBIT(n,56,8)
1068
1069         u64 mc_rldram_mrs;
1070 #define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
1071 #define XGE_HAL_MC_RLDRAM_MRS_ENABLE        BIT(47)
1072
1073         u64 mc_rldram_interleave;
1074
1075         u64 mc_pause_thresh_q0q3;
1076         u64 mc_pause_thresh_q4q7;
1077
1078         u64 mc_red_thresh_q[8];
1079
1080         u8 unused20[0x200 - 0x168];
1081         u64 mc_rldram_ref_per;
1082         u8 unused21[0x220 - 0x208];
1083         u64 mc_rldram_test_ctrl;
1084 #define XGE_HAL_MC_RLDRAM_TEST_MODE     BIT(47)
1085 #define XGE_HAL_MC_RLDRAM_TEST_WRITE        BIT(7)
1086 #define XGE_HAL_MC_RLDRAM_TEST_GO       BIT(15)
1087 #define XGE_HAL_MC_RLDRAM_TEST_DONE     BIT(23)
1088 #define XGE_HAL_MC_RLDRAM_TEST_PASS     BIT(31)
1089
1090         u8 unused22[0x240 - 0x228];
1091         u64 mc_rldram_test_add;
1092         u8 unused23[0x260 - 0x248];
1093         u64 mc_rldram_test_d0;
1094         u8 unused24[0x280 - 0x268];
1095         u64 mc_rldram_test_d1;
1096         u8 unused25[0x300 - 0x288];
1097         u64 mc_rldram_test_d2;
1098         u8  unused26_1[0x2C00 - 0x2B08];
1099         u64 mc_rldram_test_read_d0;
1100         u8  unused26_2[0x20 - 0x8];
1101         u64 mc_rldram_test_read_d1;
1102         u8  unused26_3[0x40 - 0x28];
1103         u64 mc_rldram_test_read_d2;
1104         u8  unused26_4[0x60 - 0x48];
1105         u64 mc_rldram_test_add_bkg;
1106         u8  unused26_5[0x80 - 0x68];
1107         u64 mc_rldram_test_d0_bkg;
1108         u8  unused26_6[0xD00 - 0xC88];
1109         u64 mc_rldram_test_d1_bkg;
1110         u8  unused26_7[0x20 - 0x8];
1111         u64 mc_rldram_test_d2_bkg;
1112         u8  unused26_8[0x40 - 0x28];
1113         u64 mc_rldram_test_read_d0_bkg;
1114         u8  unused26_9[0x60 - 0x48];
1115         u64 mc_rldram_test_read_d1_bkg;
1116         u8  unused26_10[0x80 - 0x68];
1117         u64 mc_rldram_test_read_d2_bkg;
1118         u8  unused26_11[0xE00 - 0xD88];
1119         u64 mc_rldram_generation;
1120         u8  unused26_12[0x20 - 0x8];
1121         u64 mc_driver;
1122         u8  unused26_13[0x40 - 0x28];
1123         u64 mc_rldram_ref_per_herc;
1124 #define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n)   vBIT(n, 0, 16)
1125         u8 unused26_14[0x660 - 0x648];
1126         u64 mc_rldram_mrs_herc;
1127 #define XGE_HAL_MC_RLDRAM_MRS(n)              vBIT(n, 14, 17)
1128         u8 unused26_15[0x700 - 0x668];
1129         u64 mc_debug_ctrl;
1130
1131         u8 unused27[0x3000 - 0x2f08];
1132
1133 /* XGXG */
1134         /* XGXS control registers */
1135
1136         u64 xgxs_int_status;
1137 #define XGE_HAL_XGXS_INT_STATUS_TXGXS              BIT(0)
1138 #define XGE_HAL_XGXS_INT_STATUS_RXGXS              BIT(1)
1139         u64 xgxs_int_mask;
1140 #define XGE_HAL_XGXS_INT_MASK_TXGXS                BIT(0)
1141 #define XGE_HAL_XGXS_INT_MASK_RXGXS                BIT(1)
1142
1143         u64 xgxs_txgxs_err_reg;
1144 #define XGE_HAL_TXGXS_ECC_SG_ERR            BIT(7)
1145 #define XGE_HAL_TXGXS_ECC_DB_ERR            BIT(15)
1146 #define XGE_HAL_TXGXS_ESTORE_UFLOW          BIT(31)
1147 #define XGE_HAL_TXGXS_TX_SM_ERR             BIT(39)
1148         u64 xgxs_txgxs_err_mask;
1149         u64 xgxs_txgxs_err_alarm;
1150
1151         u64 xgxs_rxgxs_err_reg;
1152 #define XGE_HAL_RXGXS_ESTORE_OFLOW          BIT(7)
1153 #define XGE_HAL_RXGXS_RX_SM_ERR             BIT(39)
1154         u64 xgxs_rxgxs_err_mask;
1155         u64 xgxs_rxgxs_err_alarm;
1156
1157         u64 spi_err_reg;
1158         u64 spi_err_mask;
1159         u64 spi_err_alarm;
1160
1161         u8 unused28[0x100 - 0x58];
1162
1163         u64 xgxs_cfg;
1164         u64 xgxs_status;
1165
1166         u64 xgxs_cfg_key;
1167         u64 xgxs_efifo_cfg; /* CHANGED */
1168         u64 rxgxs_ber_0;    /* CHANGED */
1169         u64 rxgxs_ber_1;    /* CHANGED */
1170
1171         u64 spi_control;
1172         u64 spi_data;
1173         u64 spi_write_protect;
1174
1175         u8  unused29[0x80 - 0x48];
1176
1177         u64 xgxs_cfg_1;
1178 } xge_hal_pci_bar0_t;
1179
1180 /* Using this strcture to calculate offsets */
1181 typedef struct xge_hal_pci_config_le_t {
1182         u16     vendor_id;              // 0x00
1183         u16     device_id;              // 0x02
1184
1185         u16     command;                // 0x04
1186         u16     status;                 // 0x06
1187
1188         u8      revision;               // 0x08
1189         u8      pciClass[3];            // 0x09
1190
1191         u8      cache_line_size;        // 0x0c
1192         u8      latency_timer;          // 0x0d
1193         u8      header_type;            // 0x0e
1194         u8      bist;                   // 0x0f
1195
1196         u32     base_addr0_lo;          // 0x10
1197         u32     base_addr0_hi;          // 0x14
1198
1199         u32     base_addr1_lo;          // 0x18
1200         u32     base_addr1_hi;          // 0x1C
1201
1202         u32     not_Implemented1;       // 0x20
1203         u32     not_Implemented2;       // 0x24
1204
1205         u32     cardbus_cis_pointer;    // 0x28
1206
1207         u16     subsystem_vendor_id;    // 0x2c
1208         u16     subsystem_id;           // 0x2e
1209
1210         u32     rom_base;               // 0x30
1211         u8      capabilities_pointer;   // 0x34
1212         u8      rsvd_35[3];             // 0x35
1213         u32     rsvd_38;                // 0x38
1214
1215         u8      interrupt_line;         // 0x3c
1216         u8      interrupt_pin;          // 0x3d
1217         u8      min_grant;              // 0x3e
1218         u8      max_latency;            // 0x3f
1219
1220         u8      msi_cap_id;             // 0x40
1221         u8      msi_next_ptr;           // 0x41
1222         u16     msi_control;            // 0x42
1223         u32     msi_lower_address;      // 0x44
1224         u32     msi_higher_address;     // 0x48
1225         u16     msi_data;               // 0x4c
1226         u16     msi_unused;             // 0x4e
1227
1228         u8      vpd_cap_id;             // 0x50
1229         u8      vpd_next_cap;           // 0x51
1230         u16     vpd_addr;               // 0x52
1231         u32     vpd_data;               // 0x54
1232
1233         u8      rsvd_b0[8];             // 0x58
1234
1235         u8      pcix_cap;               // 0x60
1236         u8      pcix_next_cap;          // 0x61
1237         u16     pcix_command;           // 0x62
1238
1239         u32     pcix_status;            // 0x64
1240
1241         u8      rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68];
1242 } xge_hal_pci_config_le_t;              // 0x100
1243
1244 typedef struct xge_hal_pci_config_t {
1245 #ifdef XGE_OS_HOST_BIG_ENDIAN
1246         u16     device_id;              // 0x02
1247         u16     vendor_id;              // 0x00
1248
1249         u16     status;                 // 0x06
1250         u16     command;                // 0x04
1251
1252         u8      pciClass[3];            // 0x09
1253         u8      revision;               // 0x08
1254
1255         u8      bist;                   // 0x0f
1256         u8      header_type;            // 0x0e
1257         u8      latency_timer;          // 0x0d
1258         u8      cache_line_size;        // 0x0c
1259
1260         u32     base_addr0_lo;           // 0x10
1261         u32     base_addr0_hi;           // 0x14
1262
1263         u32     base_addr1_lo;          // 0x18
1264         u32     base_addr1_hi;          // 0x1C
1265
1266         u32     not_Implemented1;       // 0x20
1267         u32     not_Implemented2;       // 0x24
1268
1269         u32     cardbus_cis_pointer;    // 0x28
1270
1271         u16     subsystem_id;           // 0x2e
1272         u16     subsystem_vendor_id;    // 0x2c
1273
1274         u32     rom_base;               // 0x30
1275         u8      rsvd_35[3];             // 0x35
1276         u8      capabilities_pointer;   // 0x34
1277         u32     rsvd_38;                // 0x38
1278
1279         u8      max_latency;            // 0x3f
1280         u8      min_grant;              // 0x3e
1281         u8      interrupt_pin;          // 0x3d
1282         u8      interrupt_line;         // 0x3c
1283
1284         u16     msi_control;            // 0x42
1285         u8      msi_next_ptr;           // 0x41
1286         u8      msi_cap_id;             // 0x40
1287         u32     msi_lower_address;      // 0x44
1288         u32     msi_higher_address;     // 0x48
1289         u16     msi_unused;             // 0x4e
1290         u16     msi_data;               // 0x4c
1291
1292         u16     vpd_addr;               // 0x52
1293         u8      vpd_next_cap;           // 0x51
1294         u8      vpd_cap_id;             // 0x50
1295         u32     vpd_data;               // 0x54
1296
1297         u8      rsvd_b0[8];             // 0x58
1298
1299         u16     pcix_command;           // 0x62
1300         u8      pcix_next_cap;          // 0x61
1301         u8      pcix_cap;               // 0x60
1302
1303         u32     pcix_status;            // 0x64
1304 #else
1305         u16     vendor_id;              // 0x00
1306         u16     device_id;              // 0x02
1307
1308         u16     command;                // 0x04
1309         u16     status;                 // 0x06
1310
1311         u8      revision;               // 0x08
1312         u8      pciClass[3];            // 0x09
1313
1314         u8      cache_line_size;        // 0x0c
1315         u8      latency_timer;          // 0x0d
1316         u8      header_type;            // 0x0e
1317         u8      bist;                   // 0x0f
1318
1319         u32     base_addr0_lo;          // 0x10
1320         u32     base_addr0_hi;          // 0x14
1321
1322         u32     base_addr1_lo;          // 0x18
1323         u32     base_addr1_hi;          // 0x1C
1324
1325         u32     not_Implemented1;       // 0x20
1326         u32     not_Implemented2;       // 0x24
1327
1328         u32     cardbus_cis_pointer;    // 0x28
1329
1330         u16     subsystem_vendor_id;    // 0x2c
1331         u16     subsystem_id;           // 0x2e
1332
1333         u32     rom_base;               // 0x30
1334         u8      capabilities_pointer;   // 0x34
1335         u8      rsvd_35[3];             // 0x35
1336         u32     rsvd_38;                // 0x38
1337
1338         u8      interrupt_line;         // 0x3c
1339         u8      interrupt_pin;          // 0x3d
1340         u8      min_grant;              // 0x3e
1341         u8      max_latency;            // 0x3f
1342
1343         u8      msi_cap_id;             // 0x40
1344         u8      msi_next_ptr;           // 0x41
1345         u16     msi_control;            // 0x42
1346         u32     msi_lower_address;      // 0x44
1347         u32     msi_higher_address;     // 0x48
1348         u16     msi_data;               // 0x4c
1349         u16     msi_unused;             // 0x4e
1350
1351         u8      vpd_cap_id;             // 0x50
1352         u8      vpd_next_cap;           // 0x51
1353         u16     vpd_addr;               // 0x52
1354         u32     vpd_data;               // 0x54
1355
1356         u8      rsvd_b0[8];             // 0x58
1357
1358         u8      pcix_cap;               // 0x60
1359         u8      pcix_next_cap;          // 0x61
1360         u16     pcix_command;           // 0x62
1361
1362         u32     pcix_status;            // 0x64
1363
1364 #endif
1365         u8      rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68];
1366 } xge_hal_pci_config_t;               // 0x100
1367
1368 #define XGE_HAL_REG_SPACE   sizeof(xge_hal_pci_bar0_t)
1369 #define XGE_HAL_EEPROM_SIZE (0x01 << 11)
1370
1371 __EXTERN_END_DECLS
1372
1373 #endif /* XGE_HAL_REGS_H */