sys/dev/oce/oce_hw.h

   1 /*-
   2  * Copyright (C) 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the Emulex Corporation nor the names of its
  16  *    contributors may be used to endorse or promote products derived from
  17  *    this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Contact Information:
  32  * freebsd-drivers@emulex.com
  33  *
  34  * Emulex
  35  * 3333 Susan Street
  36  * Costa Mesa, CA 92626
  37  */
  38
  39 /* $FreeBSD$ */
  40
  41 #include <sys/types.h>
  42
  43 #undef _BIG_ENDIAN /* TODO */
  44 #pragma pack(1)
  45
  46 #define OC_CNA_GEN2                     0x2
  47 #define OC_CNA_GEN3                     0x3
  48 #define DEVID_TIGERSHARK                0x700
  49 #define DEVID_TOMCAT                    0x710
  50
  51 /* PCI CSR offsets */
  52 #define PCICFG_F1_CSR                   0x0     /* F1 for NIC */
  53 #define PCICFG_SEMAPHORE                0xbc
  54 #define PCICFG_SOFT_RESET               0x5c
  55 #define PCICFG_UE_STATUS_HI_MASK        0xac
  56 #define PCICFG_UE_STATUS_LO_MASK        0xa8
  57 #define PCICFG_ONLINE0                  0xb0
  58 #define PCICFG_ONLINE1                  0xb4
  59 #define INTR_EN                         0x20000000
  60 #define IMAGE_TRANSFER_SIZE             (32 * 1024)     /* 32K at a time */
  61
  62 /* CSR register offsets */
  63 #define MPU_EP_CONTROL                  0
  64 #define MPU_EP_SEMAPHORE_BE3            0xac
  65 #define MPU_EP_SEMAPHORE_XE201          0x400
  66 #define MPU_EP_SEMAPHORE_SH             0x94
  67 #define PCICFG_INTR_CTRL                0xfc
  68 #define HOSTINTR_MASK                   (1 << 29)
  69 #define HOSTINTR_PFUNC_SHIFT            26
  70 #define HOSTINTR_PFUNC_MASK             7
  71
  72 /* POST status reg struct */
  73 #define POST_STAGE_POWER_ON_RESET       0x00
  74 #define POST_STAGE_AWAITING_HOST_RDY    0x01
  75 #define POST_STAGE_HOST_RDY             0x02
  76 #define POST_STAGE_CHIP_RESET           0x03
  77 #define POST_STAGE_ARMFW_READY          0xc000
  78 #define POST_STAGE_ARMFW_UE             0xf000
  79
  80 /* DOORBELL registers */
  81 #define PD_RXULP_DB                     0x0100
  82 #define PD_TXULP_DB                     0x0060
  83 #define DB_RQ_ID_MASK                   0x3FF
  84
  85 #define PD_CQ_DB                        0x0120
  86 #define PD_EQ_DB                        PD_CQ_DB
  87 #define PD_MPU_MBOX_DB                  0x0160
  88 #define PD_MQ_DB                        0x0140
  89
  90 /* EQE completion types */
  91 #define EQ_MINOR_CODE_COMPLETION        0x00
  92 #define EQ_MINOR_CODE_OTHER             0x01
  93 #define EQ_MAJOR_CODE_COMPLETION        0x00
  94
  95 /* Link Status field values */
  96 #define PHY_LINK_FAULT_NONE             0x0
  97 #define PHY_LINK_FAULT_LOCAL            0x01
  98 #define PHY_LINK_FAULT_REMOTE           0x02
  99
 100 #define PHY_LINK_SPEED_ZERO             0x0     /* No link */
 101 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
 102 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
 103 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
 104 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
 105
 106 #define PHY_LINK_DUPLEX_NONE            0x0
 107 #define PHY_LINK_DUPLEX_HALF            0x1
 108 #define PHY_LINK_DUPLEX_FULL            0x2
 109
 110 #define NTWK_PORT_A                     0x0     /* (Port A) */
 111 #define NTWK_PORT_B                     0x1     /* (Port B) */
 112
 113 #define PHY_LINK_SPEED_ZERO                     0x0     /* (No link.) */
 114 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
 115 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
 116 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
 117 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
 118
 119 /* Hardware Address types */
 120 #define MAC_ADDRESS_TYPE_STORAGE        0x0     /* (Storage MAC Address) */
 121 #define MAC_ADDRESS_TYPE_NETWORK        0x1     /* (Network MAC Address) */
 122 #define MAC_ADDRESS_TYPE_PD             0x2     /* (Protection Domain MAC Addr) */
 123 #define MAC_ADDRESS_TYPE_MANAGEMENT     0x3     /* (Management MAC Address) */
 124 #define MAC_ADDRESS_TYPE_FCOE           0x4     /* (FCoE MAC Address) */
 125
 126 /* CREATE_IFACE capability and cap_en flags */
 127 #define MBX_RX_IFACE_FLAGS_RSS          0x4
 128 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS  0x8
 129 #define MBX_RX_IFACE_FLAGS_BROADCAST    0x10
 130 #define MBX_RX_IFACE_FLAGS_UNTAGGED     0x20
 131 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS     0x80
 132 #define MBX_RX_IFACE_FLAGS_VLAN         0x100
 133 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS    0x200
 134 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR  0x400
 135 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR        0x800
 136 #define MBX_RX_IFACE_FLAGS_MULTICAST    0x1000
 137 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
 138 #define MBX_RX_IFACE_FLAGS_HDS          0x4000
 139 #define MBX_RX_IFACE_FLAGS_DIRECTED     0x8000
 140 #define MBX_RX_IFACE_FLAGS_VMQ          0x10000
 141 #define MBX_RX_IFACE_FLAGS_NETQ         0x20000
 142 #define MBX_RX_IFACE_FLAGS_QGROUPS      0x40000
 143 #define MBX_RX_IFACE_FLAGS_LSO          0x80000
 144 #define MBX_RX_IFACE_FLAGS_LRO          0x100000
 145
 146 #define MQ_RING_CONTEXT_SIZE_16         0x5     /* (16 entries) */
 147 #define MQ_RING_CONTEXT_SIZE_32         0x6     /* (32 entries) */
 148 #define MQ_RING_CONTEXT_SIZE_64         0x7     /* (64 entries) */
 149 #define MQ_RING_CONTEXT_SIZE_128        0x8     /* (128 entries) */
 150
 151 #define MBX_DB_READY_BIT                0x1
 152 #define MBX_DB_HI_BIT                   0x2
 153 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
 154 #define ASYNC_EVENT_LINK_UP             0x1
 155 #define ASYNC_EVENT_LINK_DOWN           0x0
 156 #define ASYNC_EVENT_GRP5                0x5
 157 #define ASYNC_EVENT_CODE_DEBUG          0x6
 158 #define ASYNC_EVENT_PVID_STATE          0x3
 159 #define ASYNC_EVENT_DEBUG_QNQ           0x1
 160 #define ASYNC_EVENT_CODE_SLIPORT        0x11
 161 #define VLAN_VID_MASK                   0x0FFF
 162
 163 /* port link_status */
 164 #define ASYNC_EVENT_LOGICAL             0x02
 165
 166 /* Logical Link Status */
 167 #define NTWK_LOGICAL_LINK_DOWN          0
 168 #define NTWK_LOGICAL_LINK_UP            1
 169
 170 /* Rx filter bits */
 171 #define NTWK_RX_FILTER_IP_CKSUM         0x1
 172 #define NTWK_RX_FILTER_TCP_CKSUM        0x2
 173 #define NTWK_RX_FILTER_UDP_CKSUM        0x4
 174 #define NTWK_RX_FILTER_STRIP_CRC        0x8
 175
 176 /* max SGE per mbx */
 177 #define MAX_MBX_SGE                     19
 178
 179 /* Max multicast filter size*/
 180 #define OCE_MAX_MC_FILTER_SIZE          64
 181
 182 /* PCI SLI (Service Level Interface) capabilities register */
 183 #define OCE_INTF_REG_OFFSET             0x58
 184 #define OCE_INTF_VALID_SIG              6       /* register's signature */
 185 #define OCE_INTF_FUNC_RESET_REQD        1
 186 #define OCE_INTF_HINT1_NOHINT           0
 187 #define OCE_INTF_HINT1_SEMAINIT         1
 188 #define OCE_INTF_HINT1_STATCTRL         2
 189 #define OCE_INTF_IF_TYPE_0              0
 190 #define OCE_INTF_IF_TYPE_1              1
 191 #define OCE_INTF_IF_TYPE_2              2
 192 #define OCE_INTF_IF_TYPE_3              3
 193 #define OCE_INTF_SLI_REV3               3       /* not supported by driver */
 194 #define OCE_INTF_SLI_REV4               4       /* driver supports SLI-4 */
 195 #define OCE_INTF_PHYS_FUNC              0
 196 #define OCE_INTF_VIRT_FUNC              1
 197 #define OCE_INTF_FAMILY_BE2             0       /* not supported by driver */
 198 #define OCE_INTF_FAMILY_BE3             1       /* driver supports BE3 */
 199 #define OCE_INTF_FAMILY_A0_CHIP         0xA     /* Lancer A0 chip (supported) */
 200 #define OCE_INTF_FAMILY_B0_CHIP         0xB     /* Lancer B0 chip (future) */
 201
 202 #define NIC_WQE_SIZE    16
 203 #define NIC_UNICAST     0x00
 204 #define NIC_MULTICAST   0x01
 205 #define NIC_BROADCAST   0x02
 206
 207 #define NIC_HDS_NO_SPLIT        0x00
 208 #define NIC_HDS_SPLIT_L3PL      0x01
 209 #define NIC_HDS_SPLIT_L4PL      0x02
 210
 211 #define NIC_WQ_TYPE_FORWARDING          0x01
 212 #define NIC_WQ_TYPE_STANDARD            0x02
 213 #define NIC_WQ_TYPE_LOW_LATENCY         0x04
 214
 215 #define OCE_RESET_STATS         1
 216 #define OCE_RETAIN_STATS        0
 217 #define OCE_TXP_SW_SZ           48
 218
 219 typedef union pci_sli_intf_u {
 220         uint32_t dw0;
 221         struct {
 222 #ifdef _BIG_ENDIAN
 223                 uint32_t sli_valid:3;
 224                 uint32_t sli_hint2:5;
 225                 uint32_t sli_hint1:8;
 226                 uint32_t sli_if_type:4;
 227                 uint32_t sli_family:4;
 228                 uint32_t sli_rev:4;
 229                 uint32_t rsv0:3;
 230                 uint32_t sli_func_type:1;
 231 #else
 232                 uint32_t sli_func_type:1;
 233                 uint32_t rsv0:3;
 234                 uint32_t sli_rev:4;
 235                 uint32_t sli_family:4;
 236                 uint32_t sli_if_type:4;
 237                 uint32_t sli_hint1:8;
 238                 uint32_t sli_hint2:5;
 239                 uint32_t sli_valid:3;
 240 #endif
 241         } bits;
 242 } pci_sli_intf_t;
 243
 244
 245
 246 /* physical address structure to be used in MBX */
 247 struct phys_addr {
 248         /* dw0 */
 249         uint32_t lo;
 250         /* dw1 */
 251         uint32_t hi;
 252 };
 253
 254
 255
 256 typedef union pcicfg_intr_ctl_u {
 257         uint32_t dw0;
 258         struct {
 259 #ifdef _BIG_ENDIAN
 260                 uint32_t winselect:2;
 261                 uint32_t hostintr:1;
 262                 uint32_t pfnum:3;
 263                 uint32_t vf_cev_int_line_en:1;
 264                 uint32_t winaddr:23;
 265                 uint32_t membarwinen:1;
 266 #else
 267                 uint32_t membarwinen:1;
 268                 uint32_t winaddr:23;
 269                 uint32_t vf_cev_int_line_en:1;
 270                 uint32_t pfnum:3;
 271                 uint32_t hostintr:1;
 272                 uint32_t winselect:2;
 273 #endif
 274         } bits;
 275 } pcicfg_intr_ctl_t;
 276
 277
 278
 279
 280 typedef union pcicfg_semaphore_u {
 281         uint32_t dw0;
 282         struct {
 283 #ifdef _BIG_ENDIAN
 284                 uint32_t rsvd:31;
 285                 uint32_t lock:1;
 286 #else
 287                 uint32_t lock:1;
 288                 uint32_t rsvd:31;
 289 #endif
 290         } bits;
 291 } pcicfg_semaphore_t;
 292
 293
 294
 295
 296 typedef union pcicfg_soft_reset_u {
 297         uint32_t dw0;
 298         struct {
 299 #ifdef _BIG_ENDIAN
 300                 uint32_t nec_ll_rcvdetect:8;
 301                 uint32_t dbg_all_reqs_62_49:14;
 302                 uint32_t scratchpad0:1;
 303                 uint32_t exception_oe:1;
 304                 uint32_t soft_reset:1;
 305                 uint32_t rsvd0:7;
 306 #else
 307                 uint32_t rsvd0:7;
 308                 uint32_t soft_reset:1;
 309                 uint32_t exception_oe:1;
 310                 uint32_t scratchpad0:1;
 311                 uint32_t dbg_all_reqs_62_49:14;
 312                 uint32_t nec_ll_rcvdetect:8;
 313 #endif
 314         } bits;
 315 } pcicfg_soft_reset_t;
 316
 317
 318
 319
 320 typedef union pcicfg_online1_u {
 321         uint32_t dw0;
 322         struct {
 323 #ifdef _BIG_ENDIAN
 324                 uint32_t host8_online:1;
 325                 uint32_t host7_online:1;
 326                 uint32_t host6_online:1;
 327                 uint32_t host5_online:1;
 328                 uint32_t host4_online:1;
 329                 uint32_t host3_online:1;
 330                 uint32_t host2_online:1;
 331                 uint32_t ipc_online:1;
 332                 uint32_t arm_online:1;
 333                 uint32_t txp_online:1;
 334                 uint32_t xaui_online:1;
 335                 uint32_t rxpp_online:1;
 336                 uint32_t txpb_online:1;
 337                 uint32_t rr_online:1;
 338                 uint32_t pmem_online:1;
 339                 uint32_t pctl1_online:1;
 340                 uint32_t pctl0_online:1;
 341                 uint32_t pcs1online_online:1;
 342                 uint32_t mpu_iram_online:1;
 343                 uint32_t pcs0online_online:1;
 344                 uint32_t mgmt_mac_online:1;
 345                 uint32_t lpcmemhost_online:1;
 346 #else
 347                 uint32_t lpcmemhost_online:1;
 348                 uint32_t mgmt_mac_online:1;
 349                 uint32_t pcs0online_online:1;
 350                 uint32_t mpu_iram_online:1;
 351                 uint32_t pcs1online_online:1;
 352                 uint32_t pctl0_online:1;
 353                 uint32_t pctl1_online:1;
 354                 uint32_t pmem_online:1;
 355                 uint32_t rr_online:1;
 356                 uint32_t txpb_online:1;
 357                 uint32_t rxpp_online:1;
 358                 uint32_t xaui_online:1;
 359                 uint32_t txp_online:1;
 360                 uint32_t arm_online:1;
 361                 uint32_t ipc_online:1;
 362                 uint32_t host2_online:1;
 363                 uint32_t host3_online:1;
 364                 uint32_t host4_online:1;
 365                 uint32_t host5_online:1;
 366                 uint32_t host6_online:1;
 367                 uint32_t host7_online:1;
 368                 uint32_t host8_online:1;
 369 #endif
 370         } bits;
 371 } pcicfg_online1_t;
 372
 373
 374
 375 typedef union mpu_ep_semaphore_u {
 376         uint32_t dw0;
 377         struct {
 378 #ifdef _BIG_ENDIAN
 379                 uint32_t error:1;
 380                 uint32_t backup_fw:1;
 381                 uint32_t iscsi_no_ip:1;
 382                 uint32_t iscsi_ip_conflict:1;
 383                 uint32_t option_rom_installed:1;
 384                 uint32_t iscsi_drv_loaded:1;
 385                 uint32_t rsvd0:10;
 386                 uint32_t stage:16;
 387 #else
 388                 uint32_t stage:16;
 389                 uint32_t rsvd0:10;
 390                 uint32_t iscsi_drv_loaded:1;
 391                 uint32_t option_rom_installed:1;
 392                 uint32_t iscsi_ip_conflict:1;
 393                 uint32_t iscsi_no_ip:1;
 394                 uint32_t backup_fw:1;
 395                 uint32_t error:1;
 396 #endif
 397         } bits;
 398 } mpu_ep_semaphore_t;
 399
 400
 401
 402
 403 typedef union mpu_ep_control_u {
 404         uint32_t dw0;
 405         struct {
 406 #ifdef _BIG_ENDIAN
 407                 uint32_t cpu_reset:1;
 408                 uint32_t rsvd1:15;
 409                 uint32_t ep_ram_init_status:1;
 410                 uint32_t rsvd0:12;
 411                 uint32_t m2_rxpbuf:1;
 412                 uint32_t m1_rxpbuf:1;
 413                 uint32_t m0_rxpbuf:1;
 414 #else
 415                 uint32_t m0_rxpbuf:1;
 416                 uint32_t m1_rxpbuf:1;
 417                 uint32_t m2_rxpbuf:1;
 418                 uint32_t rsvd0:12;
 419                 uint32_t ep_ram_init_status:1;
 420                 uint32_t rsvd1:15;
 421                 uint32_t cpu_reset:1;
 422 #endif
 423         } bits;
 424 } mpu_ep_control_t;
 425
 426
 427
 428
 429 /* RX doorbell */
 430 typedef union pd_rxulp_db_u {
 431         uint32_t dw0;
 432         struct {
 433 #ifdef _BIG_ENDIAN
 434                 uint32_t num_posted:8;
 435                 uint32_t invalidate:1;
 436                 uint32_t rsvd1:13;
 437                 uint32_t qid:10;
 438 #else
 439                 uint32_t qid:10;
 440                 uint32_t rsvd1:13;
 441                 uint32_t invalidate:1;
 442                 uint32_t num_posted:8;
 443 #endif
 444         } bits;
 445 } pd_rxulp_db_t;
 446
 447
 448 /* TX doorbell */
 449 typedef union pd_txulp_db_u {
 450         uint32_t dw0;
 451         struct {
 452 #ifdef _BIG_ENDIAN
 453                 uint32_t rsvd1:2;
 454                 uint32_t num_posted:14;
 455                 uint32_t rsvd0:6;
 456                 uint32_t qid:10;
 457 #else
 458                 uint32_t qid:10;
 459                 uint32_t rsvd0:6;
 460                 uint32_t num_posted:14;
 461                 uint32_t rsvd1:2;
 462 #endif
 463         } bits;
 464 } pd_txulp_db_t;
 465
 466 /* CQ doorbell */
 467 typedef union cq_db_u {
 468         uint32_t dw0;
 469         struct {
 470 #ifdef _BIG_ENDIAN
 471                 uint32_t rsvd1:2;
 472                 uint32_t rearm:1;
 473                 uint32_t num_popped:13;
 474                 uint32_t rsvd0:5;
 475                 uint32_t event:1;
 476                 uint32_t qid:10;
 477 #else
 478                 uint32_t qid:10;
 479                 uint32_t event:1;
 480                 uint32_t rsvd0:5;
 481                 uint32_t num_popped:13;
 482                 uint32_t rearm:1;
 483                 uint32_t rsvd1:2;
 484 #endif
 485         } bits;
 486 } cq_db_t;
 487
 488 /* EQ doorbell */
 489 typedef union eq_db_u {
 490         uint32_t dw0;
 491         struct {
 492 #ifdef _BIG_ENDIAN
 493                 uint32_t rsvd1:2;
 494                 uint32_t rearm:1;
 495                 uint32_t num_popped:13;
 496                 uint32_t rsvd0:5;
 497                 uint32_t event:1;
 498                 uint32_t clrint:1;
 499                 uint32_t qid:9;
 500 #else
 501                 uint32_t qid:9;
 502                 uint32_t clrint:1;
 503                 uint32_t event:1;
 504                 uint32_t rsvd0:5;
 505                 uint32_t num_popped:13;
 506                 uint32_t rearm:1;
 507                 uint32_t rsvd1:2;
 508 #endif
 509         } bits;
 510 } eq_db_t;
 511
 512 /* bootstrap mbox doorbell */
 513 typedef union pd_mpu_mbox_db_u {
 514         uint32_t dw0;
 515         struct {
 516 #ifdef _BIG_ENDIAN
 517                 uint32_t address:30;
 518                 uint32_t hi:1;
 519                 uint32_t ready:1;
 520 #else
 521                 uint32_t ready:1;
 522                 uint32_t hi:1;
 523                 uint32_t address:30;
 524 #endif
 525         } bits;
 526 } pd_mpu_mbox_db_t;
 527
 528 /* MQ ring doorbell */
 529 typedef union pd_mq_db_u {
 530         uint32_t dw0;
 531         struct {
 532 #ifdef _BIG_ENDIAN
 533                 uint32_t rsvd1:2;
 534                 uint32_t num_posted:14;
 535                 uint32_t rsvd0:5;
 536                 uint32_t mq_id:11;
 537 #else
 538                 uint32_t mq_id:11;
 539                 uint32_t rsvd0:5;
 540                 uint32_t num_posted:14;
 541                 uint32_t rsvd1:2;
 542 #endif
 543         } bits;
 544 } pd_mq_db_t;
 545
 546 /*
 547  * Event Queue Entry
 548  */
 549 struct oce_eqe {
 550         uint32_t evnt;
 551 };
 552
 553 /* MQ scatter gather entry. Array of these make an SGL */
 554 struct oce_mq_sge {
 555         uint32_t pa_lo;
 556         uint32_t pa_hi;
 557         uint32_t length;
 558 };
 559
 560 /*
 561  * payload can contain an SGL or an embedded array of upto 59 dwords
 562  */
 563 struct oce_mbx_payload {
 564         union {
 565                 union {
 566                         struct oce_mq_sge sgl[MAX_MBX_SGE];
 567                         uint32_t embedded[59];
 568                 } u1;
 569                 uint32_t dw[59];
 570         } u0;
 571 };
 572
 573 /*
 574  * MQ MBX structure
 575  */
 576 struct oce_mbx {
 577         union {
 578                 struct {
 579 #ifdef _BIG_ENDIAN
 580                         uint32_t special:8;
 581                         uint32_t rsvd1:16;
 582                         uint32_t sge_count:5;
 583                         uint32_t rsvd0:2;
 584                         uint32_t embedded:1;
 585 #else
 586                         uint32_t embedded:1;
 587                         uint32_t rsvd0:2;
 588                         uint32_t sge_count:5;
 589                         uint32_t rsvd1:16;
 590                         uint32_t special:8;
 591 #endif
 592                 } s;
 593                 uint32_t dw0;
 594         } u0;
 595
 596         uint32_t payload_length;
 597         uint32_t tag[2];
 598         uint32_t rsvd2[1];
 599         struct oce_mbx_payload payload;
 600 };
 601
 602 /* completion queue entry for MQ */
 603 struct oce_mq_cqe {
 604         union {
 605                 struct {
 606 #ifdef _BIG_ENDIAN
 607                         /* dw0 */
 608                         uint32_t extended_status:16;
 609                         uint32_t completion_status:16;
 610                         /* dw1 dw2 */
 611                         uint32_t mq_tag[2];
 612                         /* dw3 */
 613                         uint32_t valid:1;
 614                         uint32_t async_event:1;
 615                         uint32_t hpi_buffer_cmpl:1;
 616                         uint32_t completed:1;
 617                         uint32_t consumed:1;
 618                         uint32_t rsvd0:3;
 619                         uint32_t async_type:8;
 620                         uint32_t event_type:8;
 621                         uint32_t rsvd1:8;
 622 #else
 623                         /* dw0 */
 624                         uint32_t completion_status:16;
 625                         uint32_t extended_status:16;
 626                         /* dw1 dw2 */
 627                         uint32_t mq_tag[2];
 628                         /* dw3 */
 629                         uint32_t rsvd1:8;
 630                         uint32_t event_type:8;
 631                         uint32_t async_type:8;
 632                         uint32_t rsvd0:3;
 633                         uint32_t consumed:1;
 634                         uint32_t completed:1;
 635                         uint32_t hpi_buffer_cmpl:1;
 636                         uint32_t async_event:1;
 637                         uint32_t valid:1;
 638 #endif
 639                 } s;
 640                 uint32_t dw[4];
 641         } u0;
 642 };
 643
 644 /* Mailbox Completion Status Codes */
 645 enum MBX_COMPLETION_STATUS {
 646         MBX_CQE_STATUS_SUCCESS = 0x00,
 647         MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
 648         MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
 649         MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
 650         MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
 651         MBX_CQE_STATUS_DMA_FAILED = 0x05
 652 };
 653
 654 struct oce_async_cqe_link_state {
 655         union {
 656                 struct {
 657 #ifdef _BIG_ENDIAN
 658                         /* dw0 */
 659                         uint8_t speed;
 660                         uint8_t duplex;
 661                         uint8_t link_status;
 662                         uint8_t phy_port;
 663                         /* dw1 */
 664                         uint16_t qos_link_speed;
 665                         uint8_t rsvd0;
 666                         uint8_t fault;
 667                         /* dw2 */
 668                         uint32_t event_tag;
 669                         /* dw3 */
 670                         uint32_t valid:1;
 671                         uint32_t async_event:1;
 672                         uint32_t rsvd2:6;
 673                         uint32_t event_type:8;
 674                         uint32_t event_code:8;
 675                         uint32_t rsvd1:8;
 676 #else
 677                         /* dw0 */
 678                         uint8_t phy_port;
 679                         uint8_t link_status;
 680                         uint8_t duplex;
 681                         uint8_t speed;
 682                         /* dw1 */
 683                         uint8_t fault;
 684                         uint8_t rsvd0;
 685                         uint16_t qos_link_speed;
 686                         /* dw2 */
 687                         uint32_t event_tag;
 688                         /* dw3 */
 689                         uint32_t rsvd1:8;
 690                         uint32_t event_code:8;
 691                         uint32_t event_type:8;
 692                         uint32_t rsvd2:6;
 693                         uint32_t async_event:1;
 694                         uint32_t valid:1;
 695 #endif
 696                 } s;
 697                 uint32_t dw[4];
 698         } u0;
 699 };
 700
 701
 702 /* PVID aync event */
 703 struct oce_async_event_grp5_pvid_state {
 704         uint8_t enabled;
 705         uint8_t rsvd0;
 706         uint16_t tag;
 707         uint32_t event_tag;
 708         uint32_t rsvd1;
 709         uint32_t code;
 710 };
 711
 712 /* async event indicating outer VLAN tag in QnQ */
 713 struct oce_async_event_qnq {
 714         uint8_t valid;       /* Indicates if outer VLAN is valid */
 715         uint8_t rsvd0;
 716         uint16_t vlan_tag;
 717         uint32_t event_tag;
 718         uint8_t rsvd1[4];
 719         uint32_t code;
 720 } ;
 721
 722
 723 typedef union oce_mq_ext_ctx_u {
 724         uint32_t dw[6];
 725         struct {
 726                 #ifdef _BIG_ENDIAN
 727                 /* dw0 */
 728                 uint32_t dw4rsvd1:16;
 729                 uint32_t num_pages:16;
 730                 /* dw1 */
 731                 uint32_t async_evt_bitmap;
 732                 /* dw2 */
 733                 uint32_t cq_id:10;
 734                 uint32_t dw5rsvd2:2;
 735                 uint32_t ring_size:4;
 736                 uint32_t dw5rsvd1:16;
 737                 /* dw3 */
 738                 uint32_t valid:1;
 739                 uint32_t dw6rsvd1:31;
 740                 /* dw4 */
 741                 uint32_t dw7rsvd1:21;
 742                 uint32_t async_cq_id:10;
 743                 uint32_t async_cq_valid:1;
 744         #else
 745                 /* dw0 */
 746                 uint32_t num_pages:16;
 747                 uint32_t dw4rsvd1:16;
 748                 /* dw1 */
 749                 uint32_t async_evt_bitmap;
 750                 /* dw2 */
 751                 uint32_t dw5rsvd1:16;
 752                 uint32_t ring_size:4;
 753                 uint32_t dw5rsvd2:2;
 754                 uint32_t cq_id:10;
 755                 /* dw3 */
 756                 uint32_t dw6rsvd1:31;
 757                 uint32_t valid:1;
 758                 /* dw4 */
 759                 uint32_t async_cq_valid:1;
 760                 uint32_t async_cq_id:10;
 761                 uint32_t dw7rsvd1:21;
 762         #endif
 763                 /* dw5 */
 764                 uint32_t dw8rsvd1;
 765         } v0;
 766                 struct {
 767         #ifdef _BIG_ENDIAN
 768                 /* dw0 */
 769                 uint32_t cq_id:16;
 770                 uint32_t num_pages:16;
 771                 /* dw1 */
 772                 uint32_t async_evt_bitmap;
 773                 /* dw2 */
 774                 uint32_t dw5rsvd2:12;
 775                 uint32_t ring_size:4;
 776                 uint32_t async_cq_id:16;
 777                 /* dw3 */
 778                 uint32_t valid:1;
 779                 uint32_t dw6rsvd1:31;
 780                 /* dw4 */
 781                 uint32_t dw7rsvd1:31;
 782                 uint32_t async_cq_valid:1;
 783         #else
 784                 /* dw0 */
 785                 uint32_t num_pages:16;
 786                 uint32_t cq_id:16;
 787                 /* dw1 */
 788                 uint32_t async_evt_bitmap;
 789                 /* dw2 */
 790                 uint32_t async_cq_id:16;
 791                 uint32_t ring_size:4;
 792                 uint32_t dw5rsvd2:12;
 793                 /* dw3 */
 794                 uint32_t dw6rsvd1:31;
 795                 uint32_t valid:1;
 796                 /* dw4 */
 797                 uint32_t async_cq_valid:1;
 798                 uint32_t dw7rsvd1:31;
 799         #endif
 800                 /* dw5 */
 801                 uint32_t dw8rsvd1;
 802         } v1;
 803
 804 } oce_mq_ext_ctx_t;
 805
 806
 807 /* MQ mailbox structure */
 808 struct oce_bmbx {
 809         struct oce_mbx mbx;
 810         struct oce_mq_cqe cqe;
 811 };
 812
 813 /* ---[ MBXs start here ]---------------------------------------------- */
 814 /* MBXs sub system codes */
 815 enum MBX_SUBSYSTEM_CODES {
 816         MBX_SUBSYSTEM_RSVD = 0,
 817         MBX_SUBSYSTEM_COMMON = 1,
 818         MBX_SUBSYSTEM_COMMON_ISCSI = 2,
 819         MBX_SUBSYSTEM_NIC = 3,
 820         MBX_SUBSYSTEM_TOE = 4,
 821         MBX_SUBSYSTEM_PXE_UNDI = 5,
 822         MBX_SUBSYSTEM_ISCSI_INI = 6,
 823         MBX_SUBSYSTEM_ISCSI_TGT = 7,
 824         MBX_SUBSYSTEM_MILI_PTL = 8,
 825         MBX_SUBSYSTEM_MILI_TMD = 9,
 826         MBX_SUBSYSTEM_RDMA = 10,
 827         MBX_SUBSYSTEM_LOWLEVEL = 11,
 828         MBX_SUBSYSTEM_LRO = 13,
 829         IOCBMBX_SUBSYSTEM_DCBX = 15,
 830         IOCBMBX_SUBSYSTEM_DIAG = 16,
 831         IOCBMBX_SUBSYSTEM_VENDOR = 17
 832 };
 833
 834 /* common ioctl opcodes */
 835 enum COMMON_SUBSYSTEM_OPCODES {
 836 /* These opcodes are common to both networking and storage PCI functions
 837  * They are used to reserve resources and configure CNA. These opcodes
 838  * all use the MBX_SUBSYSTEM_COMMON subsystem code.
 839  */
 840         OPCODE_COMMON_QUERY_IFACE_MAC = 1,
 841         OPCODE_COMMON_SET_IFACE_MAC = 2,
 842         OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
 843         OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
 844         OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
 845         OPCODE_COMMON_READ_FLASHROM = 6,
 846         OPCODE_COMMON_WRITE_FLASHROM = 7,
 847         OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
 848         OPCODE_COMMON_CREATE_CQ = 12,
 849         OPCODE_COMMON_CREATE_EQ = 13,
 850         OPCODE_COMMON_CREATE_MQ = 21,
 851         OPCODE_COMMON_GET_QOS = 27,
 852         OPCODE_COMMON_SET_QOS = 28,
 853         OPCODE_COMMON_READ_EPROM = 30,
 854         OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
 855         OPCODE_COMMON_NOP = 33,
 856         OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
 857         OPCODE_COMMON_GET_FW_VERSION = 35,
 858         OPCODE_COMMON_SET_FLOW_CONTROL = 36,
 859         OPCODE_COMMON_GET_FLOW_CONTROL = 37,
 860         OPCODE_COMMON_SET_FRAME_SIZE = 39,
 861         OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
 862         OPCODE_COMMON_CREATE_IFACE = 50,
 863         OPCODE_COMMON_DESTROY_IFACE = 51,
 864         OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
 865         OPCODE_COMMON_DESTROY_MQ = 53,
 866         OPCODE_COMMON_DESTROY_CQ = 54,
 867         OPCODE_COMMON_DESTROY_EQ = 55,
 868         OPCODE_COMMON_UPLOAD_TCP = 56,
 869         OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
 870         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
 871         OPCODE_COMMON_ADD_IFACE_MAC = 59,
 872         OPCODE_COMMON_DEL_IFACE_MAC = 60,
 873         OPCODE_COMMON_FUNCTION_RESET = 61,
 874         OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
 875         OPCODE_COMMON_GET_BOOT_CONFIG = 66,
 876         OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
 877         OPCODE_COMMON_SET_BEACON_CONFIG = 69,
 878         OPCODE_COMMON_GET_BEACON_CONFIG = 70,
 879         OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
 880         OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73,
 881         OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
 882         OPCODE_COMMON_GET_PORT_NAME = 77,
 883         OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
 884         OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
 885         OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
 886         OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
 887         OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
 888         OPCODE_COMMON_GET_RESET_NEEDED = 84,
 889         OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
 890         OPCODE_COMMON_GET_NCSI_CONFIG = 86,
 891         OPCODE_COMMON_SET_NCSI_CONFIG = 87,
 892         OPCODE_COMMON_CREATE_MQ_EXT = 90,
 893         OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
 894         OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
 895         OPCODE_COMMON_GET_PHY_CONFIG = 102,
 896         OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
 897         OPCODE_COMMON_GET_ADAPTER_ID = 110,
 898         OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
 899         OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
 900         OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
 901         OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
 902         OPCODE_COMMON_SEND_ACTIVATION = 115,
 903         OPCODE_COMMON_RESET_LICENSES = 116,
 904         OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
 905         OPCODE_COMMON_QUERY_TCB = 144,
 906         OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
 907         OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
 908         OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
 909         OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
 910         OPCODE_COMMON_MODIFY_CQ = 149,
 911         OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
 912         OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
 913         OPCODE_COMMON_GET_HSW_CONFIG = 152,
 914         OPCODE_COMMON_SET_HSW_CONFIG = 153,
 915         OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
 916         OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
 917         OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
 918         OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
 919         OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
 920         OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
 921         OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
 922         OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
 923         OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
 924         OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
 925         OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
 926         OPCODE_COMMON_GET_PROFILE_LIST = 166,
 927         OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
 928         OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
 929         OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
 930         OPCODE_COMMON_READ_OBJECT = 171,
 931         OPCODE_COMMON_WRITE_OBJECT = 172
 932 };
 933
 934 /* common ioctl header */
 935 #define OCE_MBX_VER_V2  0x0002          /* Version V2 mailbox command */
 936 #define OCE_MBX_VER_V1  0x0001          /* Version V1 mailbox command */
 937 #define OCE_MBX_VER_V0  0x0000          /* Version V0 mailbox command */
 938 struct mbx_hdr {
 939         union {
 940                 uint32_t dw[4];
 941                 struct {
 942                 #ifdef _BIG_ENDIAN
 943                         /* dw 0 */
 944                         uint32_t domain:8;
 945                         uint32_t port_number:8;
 946                         uint32_t subsystem:8;
 947                         uint32_t opcode:8;
 948                         /* dw 1 */
 949                         uint32_t timeout;
 950                         /* dw 2 */
 951                         uint32_t request_length;
 952                         /* dw 3 */
 953                         uint32_t rsvd0:24;
 954                         uint32_t version:8;
 955                 #else
 956                         /* dw 0 */
 957                         uint32_t opcode:8;
 958                         uint32_t subsystem:8;
 959                         uint32_t port_number:8;
 960                         uint32_t domain:8;
 961                         /* dw 1 */
 962                         uint32_t timeout;
 963                         /* dw 2 */
 964                         uint32_t request_length;
 965                         /* dw 3 */
 966                         uint32_t version:8;
 967                         uint32_t rsvd0:24;
 968                 #endif
 969                 } req;
 970                 struct {
 971                 #ifdef _BIG_ENDIAN
 972                         /* dw 0 */
 973                         uint32_t domain:8;
 974                         uint32_t rsvd0:8;
 975                         uint32_t subsystem:8;
 976                         uint32_t opcode:8;
 977                         /* dw 1 */
 978                         uint32_t rsvd1:16;
 979                         uint32_t additional_status:8;
 980                         uint32_t status:8;
 981                 #else
 982                         /* dw 0 */
 983                         uint32_t opcode:8;
 984                         uint32_t subsystem:8;
 985                         uint32_t rsvd0:8;
 986                         uint32_t domain:8;
 987                         /* dw 1 */
 988                         uint32_t status:8;
 989                         uint32_t additional_status:8;
 990                         uint32_t rsvd1:16;
 991                 #endif
 992                         uint32_t rsp_length;
 993                         uint32_t actual_rsp_length;
 994                 } rsp;
 995         } u0;
 996 };
 997 #define OCE_BMBX_RHDR_SZ 20
 998 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
 999 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
1000 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
1001
1002 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */
1003 struct mbx_query_common_link_config {
1004         struct mbx_hdr hdr;
1005         union {
1006                 struct {
1007                         uint32_t rsvd0;
1008                 } req;
1009
1010                 struct {
1011                         /* dw 0 */
1012                         uint8_t physical_port;
1013                         uint8_t mac_duplex;
1014                         uint8_t mac_speed;
1015                         uint8_t mac_fault;
1016                         /* dw 1 */
1017                         uint8_t mgmt_mac_duplex;
1018                         uint8_t mgmt_mac_speed;
1019                         uint16_t qos_link_speed;
1020                         uint32_t logical_link_status;
1021                 } rsp;
1022         } params;
1023 };
1024
1025 /* [57] OPCODE_COMMON_SET_LINK_SPEED */
1026 struct mbx_set_common_link_speed {
1027         struct mbx_hdr hdr;
1028         union {
1029                 struct {
1030 #ifdef _BIG_ENDIAN
1031                         uint8_t rsvd0;
1032                         uint8_t mac_speed;
1033                         uint8_t virtual_port;
1034                         uint8_t physical_port;
1035 #else
1036                         uint8_t physical_port;
1037                         uint8_t virtual_port;
1038                         uint8_t mac_speed;
1039                         uint8_t rsvd0;
1040 #endif
1041                 } req;
1042
1043                 struct {
1044                         uint32_t rsvd0;
1045                 } rsp;
1046
1047                 uint32_t dw;
1048         } params;
1049 };
1050
1051 struct mac_address_format {
1052         uint16_t size_of_struct;
1053         uint8_t mac_addr[6];
1054 };
1055
1056 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
1057 struct mbx_query_common_iface_mac {
1058         struct mbx_hdr hdr;
1059         union {
1060                 struct {
1061 #ifdef _BIG_ENDIAN
1062                         uint16_t if_id;
1063                         uint8_t permanent;
1064                         uint8_t type;
1065 #else
1066                         uint8_t type;
1067                         uint8_t permanent;
1068                         uint16_t if_id;
1069 #endif
1070
1071                 } req;
1072
1073                 struct {
1074                         struct mac_address_format mac;
1075                 } rsp;
1076         } params;
1077 };
1078
1079 /* [02] OPCODE_COMMON_SET_IFACE_MAC */
1080 struct mbx_set_common_iface_mac {
1081         struct mbx_hdr hdr;
1082         union {
1083                 struct {
1084 #ifdef _BIG_ENDIAN
1085                         /* dw 0 */
1086                         uint16_t if_id;
1087                         uint8_t invalidate;
1088                         uint8_t type;
1089 #else
1090                         /* dw 0 */
1091                         uint8_t type;
1092                         uint8_t invalidate;
1093                         uint16_t if_id;
1094 #endif
1095                         /* dw 1 */
1096                         struct mac_address_format mac;
1097                 } req;
1098
1099                 struct {
1100                         uint32_t rsvd0;
1101                 } rsp;
1102
1103                 uint32_t dw[2];
1104         } params;
1105 };
1106
1107 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
1108 struct mbx_set_common_iface_multicast {
1109         struct mbx_hdr hdr;
1110         union {
1111                 struct {
1112                         /* dw 0 */
1113                         uint16_t num_mac;
1114                         uint8_t promiscuous;
1115                         uint8_t if_id;
1116                         /* dw 1-48 */
1117                         struct {
1118                                 uint8_t byte[6];
1119                         } mac[32];
1120
1121                 } req;
1122
1123                 struct {
1124                         uint32_t rsvd0;
1125                 } rsp;
1126
1127                 uint32_t dw[49];
1128         } params;
1129 };
1130
1131 struct qinq_vlan {
1132 #ifdef _BIG_ENDIAN
1133         uint16_t inner;
1134         uint16_t outer;
1135 #else
1136         uint16_t outer;
1137         uint16_t inner;
1138 #endif
1139 };
1140
1141 struct normal_vlan {
1142         uint16_t vtag;
1143 };
1144
1145 struct ntwk_if_vlan_tag {
1146         union {
1147                 struct normal_vlan normal;
1148                 struct qinq_vlan qinq;
1149         } u0;
1150 };
1151
1152 /* [50] OPCODE_COMMON_CREATE_IFACE */
1153 struct mbx_create_common_iface {
1154         struct mbx_hdr hdr;
1155         union {
1156                 struct {
1157                         uint32_t version;
1158                         uint32_t cap_flags;
1159                         uint32_t enable_flags;
1160                         uint8_t mac_addr[6];
1161                         uint8_t rsvd0;
1162                         uint8_t mac_invalid;
1163                         struct ntwk_if_vlan_tag vlan_tag;
1164                 } req;
1165
1166                 struct {
1167                         uint32_t if_id;
1168                         uint32_t pmac_id;
1169                 } rsp;
1170                 uint32_t dw[4];
1171         } params;
1172 };
1173
1174 /* [51] OPCODE_COMMON_DESTROY_IFACE */
1175 struct mbx_destroy_common_iface {
1176         struct mbx_hdr hdr;
1177         union {
1178                 struct {
1179                         uint32_t if_id;
1180                 } req;
1181
1182                 struct {
1183                         uint32_t rsvd0;
1184                 } rsp;
1185
1186                 uint32_t dw;
1187         } params;
1188 };
1189
1190 /* event queue context structure */
1191 struct oce_eq_ctx {
1192 #ifdef _BIG_ENDIAN
1193         uint32_t dw4rsvd1:16;
1194         uint32_t num_pages:16;
1195
1196         uint32_t size:1;
1197         uint32_t dw5rsvd2:1;
1198         uint32_t valid:1;
1199         uint32_t dw5rsvd1:29;
1200
1201         uint32_t armed:1;
1202         uint32_t dw6rsvd2:2;
1203         uint32_t count:3;
1204         uint32_t dw6rsvd1:26;
1205
1206         uint32_t dw7rsvd2:9;
1207         uint32_t delay_mult:10;
1208         uint32_t dw7rsvd1:13;
1209
1210         uint32_t dw8rsvd1;
1211 #else
1212         uint32_t num_pages:16;
1213         uint32_t dw4rsvd1:16;
1214
1215         uint32_t dw5rsvd1:29;
1216         uint32_t valid:1;
1217         uint32_t dw5rsvd2:1;
1218         uint32_t size:1;
1219
1220         uint32_t dw6rsvd1:26;
1221         uint32_t count:3;
1222         uint32_t dw6rsvd2:2;
1223         uint32_t armed:1;
1224
1225         uint32_t dw7rsvd1:13;
1226         uint32_t delay_mult:10;
1227         uint32_t dw7rsvd2:9;
1228
1229         uint32_t dw8rsvd1;
1230 #endif
1231 };
1232
1233 /* [13] OPCODE_COMMON_CREATE_EQ */
1234 struct mbx_create_common_eq {
1235         struct mbx_hdr hdr;
1236         union {
1237                 struct {
1238                         struct oce_eq_ctx ctx;
1239                         struct phys_addr pages[8];
1240                 } req;
1241
1242                 struct {
1243                         uint16_t eq_id;
1244                         uint16_t rsvd0;
1245                 } rsp;
1246         } params;
1247 };
1248
1249 /* [55] OPCODE_COMMON_DESTROY_EQ */
1250 struct mbx_destroy_common_eq {
1251         struct mbx_hdr hdr;
1252         union {
1253                 struct {
1254 #ifdef _BIG_ENDIAN
1255                         uint16_t rsvd0;
1256                         uint16_t id;
1257 #else
1258                         uint16_t id;
1259                         uint16_t rsvd0;
1260 #endif
1261                 } req;
1262
1263                 struct {
1264                         uint32_t rsvd0;
1265                 } rsp;
1266         } params;
1267 };
1268
1269 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
1270 typedef union oce_cq_ctx_u {
1271         uint32_t dw[5];
1272         struct {
1273         #ifdef _BIG_ENDIAN
1274                 /* dw4 */
1275                 uint32_t dw4rsvd1:16;
1276                 uint32_t num_pages:16;
1277                 /* dw5 */
1278                 uint32_t eventable:1;
1279                 uint32_t dw5rsvd3:1;
1280                 uint32_t valid:1;
1281                 uint32_t count:2;
1282                 uint32_t dw5rsvd2:12;
1283                 uint32_t nodelay:1;
1284                 uint32_t coalesce_wm:2;
1285                 uint32_t dw5rsvd1:12;
1286                 /* dw6 */
1287                 uint32_t armed:1;
1288                 uint32_t dw6rsvd2:1;
1289                 uint32_t eq_id:8;
1290                 uint32_t dw6rsvd1:22;
1291         #else
1292                 /* dw4 */
1293                 uint32_t num_pages:16;
1294                 uint32_t dw4rsvd1:16;
1295                 /* dw5 */
1296                 uint32_t dw5rsvd1:12;
1297                 uint32_t coalesce_wm:2;
1298                 uint32_t nodelay:1;
1299                 uint32_t dw5rsvd2:12;
1300                 uint32_t count:2;
1301                 uint32_t valid:1;
1302                 uint32_t dw5rsvd3:1;
1303                 uint32_t eventable:1;
1304                 /* dw6 */
1305                 uint32_t dw6rsvd1:22;
1306                 uint32_t eq_id:8;
1307                 uint32_t dw6rsvd2:1;
1308                 uint32_t armed:1;
1309         #endif
1310                 /* dw7 */
1311                 uint32_t dw7rsvd1;
1312                 /* dw8 */
1313                 uint32_t dw8rsvd1;
1314         } v0;
1315         struct {
1316         #ifdef _BIG_ENDIAN
1317                 /* dw4 */
1318                 uint32_t dw4rsvd1:8;
1319                 uint32_t page_size:8;
1320                 uint32_t num_pages:16;
1321                 /* dw5 */
1322                 uint32_t eventable:1;
1323                 uint32_t dw5rsvd3:1;
1324                 uint32_t valid:1;
1325                 uint32_t count:2;
1326                 uint32_t dw5rsvd2:11;
1327                 uint32_t autovalid:1;
1328                 uint32_t nodelay:1;
1329                 uint32_t coalesce_wm:2;
1330                 uint32_t dw5rsvd1:12;
1331                 /* dw6 */
1332                 uint32_t armed:1;
1333                 uint32_t dw6rsvd1:15;
1334                 uint32_t eq_id:16;
1335                 /* dw7 */
1336                 uint32_t dw7rsvd1:16;
1337                 uint32_t cqe_count:16;
1338         #else
1339                 /* dw4 */
1340                 uint32_t num_pages:16;
1341                 uint32_t page_size:8;
1342                 uint32_t dw4rsvd1:8;
1343                 /* dw5 */
1344                 uint32_t dw5rsvd1:12;
1345                 uint32_t coalesce_wm:2;
1346                 uint32_t nodelay:1;
1347                 uint32_t autovalid:1;
1348                 uint32_t dw5rsvd2:11;
1349                 uint32_t count:2;
1350                 uint32_t valid:1;
1351                 uint32_t dw5rsvd3:1;
1352                 uint32_t eventable:1;
1353                 /* dw6 */
1354                 uint32_t eq_id:8;
1355                 uint32_t dw6rsvd1:15;
1356                 uint32_t armed:1;
1357                 /* dw7 */
1358                 uint32_t cqe_count:16;
1359                 uint32_t dw7rsvd1:16;
1360         #endif
1361                 /* dw8 */
1362                 uint32_t dw8rsvd1;
1363         } v2;
1364 } oce_cq_ctx_t;
1365
1366 /* [12] OPCODE_COMMON_CREATE_CQ */
1367 struct mbx_create_common_cq {
1368         struct mbx_hdr hdr;
1369         union {
1370                 struct {
1371                         oce_cq_ctx_t cq_ctx;
1372                         struct phys_addr pages[4];
1373                 } req;
1374
1375                 struct {
1376                         uint16_t cq_id;
1377                         uint16_t rsvd0;
1378                 } rsp;
1379         } params;
1380 };
1381
1382 /* [54] OPCODE_COMMON_DESTROY_CQ */
1383 struct mbx_destroy_common_cq {
1384         struct mbx_hdr hdr;
1385         union {
1386                 struct {
1387 #ifdef _BIG_ENDIAN
1388                         uint16_t rsvd0;
1389                         uint16_t id;
1390 #else
1391                         uint16_t id;
1392                         uint16_t rsvd0;
1393 #endif
1394                 } req;
1395
1396                 struct {
1397                         uint32_t rsvd0;
1398                 } rsp;
1399         } params;
1400 };
1401
1402 typedef union oce_mq_ctx_u {
1403         uint32_t dw[5];
1404         struct {
1405         #ifdef _BIG_ENDIAN
1406                 /* dw4 */
1407                 uint32_t dw4rsvd1:16;
1408                 uint32_t num_pages:16;
1409                 /* dw5 */
1410                 uint32_t cq_id:10;
1411                 uint32_t dw5rsvd2:2;
1412                 uint32_t ring_size:4;
1413                 uint32_t dw5rsvd1:16;
1414                 /* dw6 */
1415                 uint32_t valid:1;
1416                 uint32_t dw6rsvd1:31;
1417                 /* dw7 */
1418                 uint32_t dw7rsvd1:21;
1419                 uint32_t async_cq_id:10;
1420                 uint32_t async_cq_valid:1;
1421         #else
1422                 /* dw4 */
1423                 uint32_t num_pages:16;
1424                 uint32_t dw4rsvd1:16;
1425                 /* dw5 */
1426                 uint32_t dw5rsvd1:16;
1427                 uint32_t ring_size:4;
1428                 uint32_t dw5rsvd2:2;
1429                 uint32_t cq_id:10;
1430                 /* dw6 */
1431                 uint32_t dw6rsvd1:31;
1432                 uint32_t valid:1;
1433                 /* dw7 */
1434                 uint32_t async_cq_valid:1;
1435                 uint32_t async_cq_id:10;
1436                 uint32_t dw7rsvd1:21;
1437         #endif
1438                 /* dw8 */
1439                 uint32_t dw8rsvd1;
1440         } v0;
1441 } oce_mq_ctx_t;
1442
1443 /**
1444  * @brief [21] OPCODE_COMMON_CREATE_MQ
1445  * A MQ must be at least 16 entries deep (corresponding to 1 page) and
1446  * at most 128 entries deep (corresponding to 8 pages).
1447  */
1448 struct mbx_create_common_mq {
1449         struct mbx_hdr hdr;
1450         union {
1451                 struct {
1452                         oce_mq_ctx_t context;
1453                         struct phys_addr pages[8];
1454                 } req;
1455
1456                 struct {
1457                         uint32_t mq_id:16;
1458                         uint32_t rsvd0:16;
1459                 } rsp;
1460         } params;
1461 };
1462
1463 struct mbx_create_common_mq_ex {
1464         struct mbx_hdr hdr;
1465         union {
1466                 struct {
1467                         oce_mq_ext_ctx_t context;
1468                         struct phys_addr pages[8];
1469                 } req;
1470
1471                 struct {
1472                         uint32_t mq_id:16;
1473                         uint32_t rsvd0:16;
1474                 } rsp;
1475         } params;
1476 };
1477
1478
1479
1480 /* [53] OPCODE_COMMON_DESTROY_MQ */
1481 struct mbx_destroy_common_mq {
1482         struct mbx_hdr hdr;
1483         union {
1484                 struct {
1485 #ifdef _BIG_ENDIAN
1486                         uint16_t rsvd0;
1487                         uint16_t id;
1488 #else
1489                         uint16_t id;
1490                         uint16_t rsvd0;
1491 #endif
1492                 } req;
1493
1494                 struct {
1495                         uint32_t rsvd0;
1496                 } rsp;
1497         } params;
1498 };
1499
1500 /* [35] OPCODE_COMMON_GET_ FW_VERSION */
1501 struct mbx_get_common_fw_version {
1502         struct mbx_hdr hdr;
1503         union {
1504                 struct {
1505                         uint32_t rsvd0;
1506                 } req;
1507
1508                 struct {
1509                         uint8_t fw_ver_str[32];
1510                         uint8_t fw_on_flash_ver_str[32];
1511                 } rsp;
1512         } params;
1513 };
1514
1515 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1516 struct mbx_common_cev_modify_msi_messages {
1517         struct mbx_hdr hdr;
1518         union {
1519                 struct {
1520                         uint32_t num_msi_msgs;
1521                 } req;
1522
1523                 struct {
1524                         uint32_t rsvd0;
1525                 } rsp;
1526         } params;
1527 };
1528
1529 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
1530 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
1531 struct mbx_common_get_set_flow_control {
1532         struct mbx_hdr hdr;
1533 #ifdef _BIG_ENDIAN
1534         uint16_t tx_flow_control;
1535         uint16_t rx_flow_control;
1536 #else
1537         uint16_t rx_flow_control;
1538         uint16_t tx_flow_control;
1539 #endif
1540 };
1541
1542 enum e_flash_opcode {
1543         MGMT_FLASHROM_OPCODE_FLASH = 1,
1544         MGMT_FLASHROM_OPCODE_SAVE = 2
1545 };
1546
1547 /* [06] OPCODE_READ_COMMON_FLASHROM */
1548 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
1549
1550 struct mbx_common_read_write_flashrom {
1551         struct mbx_hdr hdr;
1552         uint32_t flash_op_code;
1553         uint32_t flash_op_type;
1554         uint32_t data_buffer_size;
1555         uint32_t data_offset;
1556         uint8_t  data_buffer[4];        /* + IMAGE_TRANSFER_SIZE */
1557 };
1558
1559 struct oce_phy_info {
1560         uint16_t phy_type;
1561         uint16_t interface_type;
1562         uint32_t misc_params;
1563         uint16_t ext_phy_details;
1564         uint16_t rsvd;
1565         uint16_t auto_speeds_supported;
1566         uint16_t fixed_speeds_supported;
1567         uint32_t future_use[2];
1568 };
1569
1570 struct mbx_common_phy_info {
1571         struct mbx_hdr hdr;
1572         union {
1573                 struct {
1574                         uint32_t rsvd0[4];
1575                 } req;
1576                 struct {
1577                         struct oce_phy_info phy_info;
1578                 } rsp;
1579         } params;
1580 };
1581
1582 /*Lancer firmware*/
1583
1584 struct mbx_lancer_common_write_object {
1585         union {
1586                 struct {
1587                         struct   mbx_hdr hdr;
1588                         uint32_t write_length: 24;
1589                         uint32_t rsvd: 7;
1590                         uint32_t eof: 1;
1591                         uint32_t write_offset;
1592                         uint8_t  object_name[104];
1593                         uint32_t descriptor_count;
1594                         uint32_t buffer_length;
1595                         uint32_t address_lower;
1596                         uint32_t address_upper;
1597                 } req;
1598                 struct {
1599                         uint8_t  opcode;
1600                         uint8_t  subsystem;
1601                         uint8_t  rsvd1[2];
1602                         uint8_t  status;
1603                         uint8_t  additional_status;
1604                         uint8_t  rsvd2[2];
1605                         uint32_t response_length;
1606                         uint32_t actual_response_length;
1607                         uint32_t actual_write_length;
1608                 } rsp;
1609         } params;
1610 };
1611
1612 /**
1613  * @brief MBX Common Quiery Firmaware Config
1614  * This command retrieves firmware configuration parameters and adapter
1615  * resources available to the driver originating the request. The firmware
1616  * configuration defines supported protocols by the installed adapter firmware.
1617  * This includes which ULP processors support the specified protocols and
1618  * the number of TCP connections allowed for that protocol.
1619  */
1620 struct mbx_common_query_fw_config {
1621         struct mbx_hdr hdr;
1622         union {
1623                 struct {
1624                         uint32_t rsvd0[30];
1625                 } req;
1626
1627                 struct {
1628                         uint32_t config_number;
1629                         uint32_t asic_revision;
1630                         uint32_t port_id;       /* used for stats retrieval */
1631                         uint32_t function_mode;
1632                         struct {
1633
1634                                 uint32_t ulp_mode;
1635                                 uint32_t nic_wqid_base;
1636                                 uint32_t nic_wq_tot;
1637                                 uint32_t toe_wqid_base;
1638                                 uint32_t toe_wq_tot;
1639                                 uint32_t toe_rqid_base;
1640                                 uint32_t toe_rqid_tot;
1641                                 uint32_t toe_defrqid_base;
1642                                 uint32_t toe_defrqid_count;
1643                                 uint32_t lro_rqid_base;
1644                                 uint32_t lro_rqid_tot;
1645                                 uint32_t iscsi_icd_base;
1646                                 uint32_t iscsi_icd_count;
1647                         } ulp[2];
1648                         uint32_t function_caps;
1649                         uint32_t cqid_base;
1650                         uint32_t cqid_tot;
1651                         uint32_t eqid_base;
1652                         uint32_t eqid_tot;
1653                 } rsp;
1654         } params;
1655 };
1656
1657 enum CQFW_CONFIG_NUMBER {
1658         FCN_NIC_ISCSI_Initiator = 0x0,
1659         FCN_ISCSI_Target = 0x3,
1660         FCN_FCoE = 0x7,
1661         FCN_ISCSI_Initiator_Target = 0x9,
1662         FCN_NIC_RDMA_TOE = 0xA,
1663         FCN_NIC_RDMA_FCoE = 0xB,
1664         FCN_NIC_RDMA_iSCSI = 0xC,
1665         FCN_NIC_iSCSI_FCoE = 0xD
1666 };
1667
1668 /**
1669  * @brief Function Capabilites
1670  * This field contains the flags indicating the capabilities of
1671  * the SLI Host’s PCI function.
1672  */
1673 enum CQFW_FUNCTION_CAPABILITIES {
1674         FNC_UNCLASSIFIED_STATS = 0x1,
1675         FNC_RSS = 0x2,
1676         FNC_PROMISCUOUS = 0x4,
1677         FNC_LEGACY_MODE = 0x8,
1678         FNC_HDS = 0x4000,
1679         FNC_VMQ = 0x10000,
1680         FNC_NETQ = 0x20000,
1681         FNC_QGROUPS = 0x40000,
1682         FNC_LRO = 0x100000,
1683         FNC_VLAN_OFFLOAD = 0x800000
1684 };
1685
1686 enum CQFW_ULP_MODES_SUPPORTED {
1687         ULP_TOE_MODE = 0x1,
1688         ULP_NIC_MODE = 0x2,
1689         ULP_RDMA_MODE = 0x4,
1690         ULP_ISCSI_INI_MODE = 0x10,
1691         ULP_ISCSI_TGT_MODE = 0x20,
1692         ULP_FCOE_INI_MODE = 0x40,
1693         ULP_FCOE_TGT_MODE = 0x80,
1694         ULP_DAL_MODE = 0x100,
1695         ULP_LRO_MODE = 0x200
1696 };
1697
1698 /**
1699  * @brief Function Modes Supported
1700  * Valid function modes (or protocol-types) supported on the SLI-Host’s
1701  * PCIe function.  This field is a logical OR of the following values:
1702  */
1703 enum CQFW_FUNCTION_MODES_SUPPORTED {
1704         FNM_TOE_MODE = 0x1,             /* TCP offload supported */
1705         FNM_NIC_MODE = 0x2,             /* Raw Ethernet supported */
1706         FNM_RDMA_MODE = 0x4,            /* RDMA protocol supported */
1707         FNM_VM_MODE = 0x8,              /* Virtual Machines supported  */
1708         FNM_ISCSI_INI_MODE = 0x10,      /* iSCSI initiator supported */
1709         FNM_ISCSI_TGT_MODE = 0x20,      /* iSCSI target plus initiator */
1710         FNM_FCOE_INI_MODE = 0x40,       /* FCoE Initiator supported */
1711         FNM_FCOE_TGT_MODE = 0x80,       /* FCoE target supported */
1712         FNM_DAL_MODE = 0x100,           /* DAL supported */
1713         FNM_LRO_MODE = 0x200,           /* LRO supported */
1714         FNM_FLEX10_MODE = 0x400,        /* QinQ, FLEX-10 or VNIC */
1715         FNM_NCSI_MODE = 0x800,          /* NCSI supported */
1716         FNM_IPV6_MODE = 0x1000,         /* IPV6 stack enabled */
1717         FNM_BE2_COMPAT_MODE = 0x2000,   /* BE2 compatibility (BE3 disable)*/
1718         FNM_INVALID_MODE = 0x8000,      /* Invalid */
1719         FNM_BE3_COMPAT_MODE = 0x10000,  /* BE3 features */
1720         FNM_VNIC_MODE = 0x20000,        /* Set when IBM vNIC mode is set */
1721         FNM_VNTAG_MODE = 0x40000,       /* Set when VNTAG mode is set */
1722         FNM_UMC_MODE = 0x1000000,       /* Set when UMC mode is set */
1723         FNM_UMC_DEF_EN = 0x100000,      /* Set when UMC Default is set */
1724         FNM_ONE_GB_EN = 0x200000,       /* Set when 1GB Default is set */
1725         FNM_VNIC_DEF_VALID = 0x400000,  /* Set when VNIC_DEF_EN is valid */
1726         FNM_VNIC_DEF_EN = 0x800000      /* Set when VNIC Default enabled */
1727 };
1728
1729
1730 struct mbx_common_config_vlan {
1731         struct mbx_hdr hdr;
1732         union {
1733                 struct {
1734 #ifdef _BIG_ENDIAN
1735                         uint8_t num_vlans;
1736                         uint8_t untagged;
1737                         uint8_t promisc;
1738                         uint8_t if_id;
1739 #else
1740                         uint8_t if_id;
1741                         uint8_t promisc;
1742                         uint8_t untagged;
1743                         uint8_t num_vlans;
1744 #endif
1745                         union {
1746                                 struct normal_vlan normal_vlans[64];
1747                                 struct qinq_vlan qinq_vlans[32];
1748                         } tags;
1749                 } req;
1750
1751                 struct {
1752                         uint32_t rsvd;
1753                 } rsp;
1754         } params;
1755 };
1756
1757 typedef struct iface_rx_filter_ctx {
1758         uint32_t global_flags_mask;
1759         uint32_t global_flags;
1760         uint32_t iface_flags_mask;
1761         uint32_t iface_flags;
1762         uint32_t if_id;
1763         #define IFACE_RX_NUM_MCAST_MAX          64
1764         uint32_t num_mcast;
1765         struct mbx_mcast_addr {
1766                 uint8_t byte[6];
1767         } mac[IFACE_RX_NUM_MCAST_MAX];
1768 } iface_rx_filter_ctx_t;
1769
1770 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
1771 struct mbx_set_common_iface_rx_filter {
1772         struct mbx_hdr hdr;
1773         union {
1774                 iface_rx_filter_ctx_t req;
1775                 iface_rx_filter_ctx_t rsp;
1776         } params;
1777 };
1778
1779 struct be_set_eqd {
1780         uint32_t eq_id;
1781         uint32_t phase;
1782         uint32_t dm;
1783 };
1784
1785 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1786 struct mbx_modify_common_eq_delay {
1787         struct mbx_hdr hdr;
1788         union {
1789                 struct {
1790                         uint32_t num_eq;
1791                         struct {
1792                                 uint32_t eq_id;
1793                                 uint32_t phase;
1794                                 uint32_t dm;
1795                         } delay[8];
1796                 } req;
1797
1798                 struct {
1799                         uint32_t rsvd0;
1800                 } rsp;
1801         } params;
1802 };
1803
1804 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */
1805
1806 struct mgmt_hba_attr {
1807         int8_t   flashrom_ver_str[32];
1808         int8_t   manufac_name[32];
1809         uint32_t supp_modes;
1810         int8_t   seeprom_ver_lo;
1811         int8_t   seeprom_ver_hi;
1812         int8_t   rsvd0[2];
1813         uint32_t ioctl_data_struct_ver;
1814         uint32_t ep_fw_data_struct_ver;
1815         uint8_t  ncsi_ver_str[12];
1816         uint32_t def_ext_to;
1817         int8_t   cntl_mod_num[32];
1818         int8_t   cntl_desc[64];
1819         int8_t   cntl_ser_num[32];
1820         int8_t   ip_ver_str[32];
1821         int8_t   fw_ver_str[32];
1822         int8_t   bios_ver_str[32];
1823         int8_t   redboot_ver_str[32];
1824         int8_t   drv_ver_str[32];
1825         int8_t   fw_on_flash_ver_str[32];
1826         uint32_t funcs_supp;
1827         uint16_t max_cdblen;
1828         uint8_t  asic_rev;
1829         uint8_t  gen_guid[16];
1830         uint8_t  hba_port_count;
1831         uint16_t default_link_down_timeout;
1832         uint8_t  iscsi_ver_min_max;
1833         uint8_t  multifunc_dev;
1834         uint8_t  cache_valid;
1835         uint8_t  hba_status;
1836         uint8_t  max_domains_supp;
1837         uint8_t  phy_port;
1838         uint32_t fw_post_status;
1839         uint32_t hba_mtu[8];
1840         uint8_t  iSCSI_feat;
1841         uint8_t  asic_gen;
1842         uint8_t  future_u8[2];
1843         uint32_t future_u32[3];
1844 };
1845
1846 struct mgmt_cntl_attr {
1847         struct    mgmt_hba_attr hba_attr;
1848         uint16_t  pci_vendor_id;
1849         uint16_t  pci_device_id;
1850         uint16_t  pci_sub_vendor_id;
1851         uint16_t  pci_sub_system_id;
1852         uint8_t   pci_bus_num;
1853         uint8_t   pci_dev_num;
1854         uint8_t   pci_func_num;
1855         uint8_t   interface_type;
1856         uint64_t  unique_id;
1857         uint8_t   netfilters;
1858         uint8_t   rsvd0[3];
1859         uint32_t  future_u32[4];
1860 };
1861
1862 struct mbx_common_get_cntl_attr {
1863         struct mbx_hdr hdr;
1864         union {
1865                 struct {
1866                         uint32_t rsvd0;
1867                 } req;
1868                 struct {
1869                         struct mgmt_cntl_attr cntl_attr_info;
1870                 } rsp;
1871         } params;
1872 };
1873
1874 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1875 struct mbx_add_common_iface_mac {
1876         struct mbx_hdr hdr;
1877         union {
1878                 struct {
1879                         uint32_t if_id;
1880                         uint8_t mac_address[6];
1881                         uint8_t rsvd0[2];
1882                 } req;
1883                 struct {
1884                         uint32_t pmac_id;
1885                 } rsp;
1886         } params;
1887 };
1888
1889 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1890 struct mbx_del_common_iface_mac {
1891         struct mbx_hdr hdr;
1892         union {
1893                 struct {
1894                         uint32_t if_id;
1895                         uint32_t pmac_id;
1896                 } req;
1897                 struct {
1898                         uint32_t rsvd0;
1899                 } rsp;
1900         } params;
1901 };
1902
1903 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1904 struct mbx_query_common_max_mbx_buffer_size {
1905         struct mbx_hdr hdr;
1906         struct {
1907                 uint32_t max_ioctl_bufsz;
1908         } rsp;
1909 };
1910
1911 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1912 struct ioctl_common_function_reset {
1913         struct mbx_hdr hdr;
1914 };
1915
1916 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */
1917 struct mbx_read_common_transrecv_data {
1918         struct mbx_hdr hdr;
1919         union {
1920                 struct {
1921                         uint32_t    page_num;
1922                         uint32_t    port;
1923                 } req;
1924                 struct {
1925                         uint32_t    page_num;
1926                         uint32_t    port;
1927                         uint32_t    page_data[32];
1928                 } rsp;
1929         } params;
1930
1931 };
1932
1933 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1934 struct mbx_common_func_link_cfg {
1935         struct mbx_hdr hdr;
1936         union {
1937                 struct {
1938                         uint32_t enable;
1939                 } req;
1940                 struct {
1941                         uint32_t rsvd0;
1942                 } rsp;
1943         } params;
1944 };
1945
1946 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
1947 #define CAP_SW_TIMESTAMPS       2
1948 #define CAP_BE3_NATIVE_ERX_API  4
1949
1950 struct mbx_common_set_function_cap {
1951         struct mbx_hdr hdr;
1952         union {
1953                 struct {
1954                         uint32_t valid_capability_flags;
1955                         uint32_t capability_flags;
1956                         uint8_t  sbz[212];
1957                 } req;
1958                 struct {
1959                         uint32_t valid_capability_flags;
1960                         uint32_t capability_flags;
1961                         uint8_t  sbz[212];
1962                 } rsp;
1963         } params;
1964 };
1965 struct mbx_lowlevel_test_loopback_mode {
1966         struct mbx_hdr hdr;
1967         union {
1968                 struct {
1969                         uint32_t loopback_type;
1970                         uint32_t num_pkts;
1971                         uint64_t pattern;
1972                         uint32_t src_port;
1973                         uint32_t dest_port;
1974                         uint32_t pkt_size;
1975                 }req;
1976                 struct {
1977                         uint32_t    status;
1978                         uint32_t    num_txfer;
1979                         uint32_t    num_rx;
1980                         uint32_t    miscomp_off;
1981                         uint32_t    ticks_compl;
1982                 }rsp;
1983         } params;
1984 };
1985
1986 struct mbx_lowlevel_set_loopback_mode {
1987         struct mbx_hdr hdr;
1988         union {
1989                 struct {
1990                         uint8_t src_port;
1991                         uint8_t dest_port;
1992                         uint8_t loopback_type;
1993                         uint8_t loopback_state;
1994                 } req;
1995                 struct {
1996                         uint8_t rsvd0[4];
1997                 } rsp;
1998         } params;
1999 };
2000 #define MAX_RESC_DESC                           256
2001 #define RESC_DESC_SIZE                          88
2002 #define ACTIVE_PROFILE                          2
2003 #define NIC_RESC_DESC_TYPE_V0                   0x41
2004 #define NIC_RESC_DESC_TYPE_V1                   0x51
2005 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */
2006 struct mbx_common_get_func_config {
2007         struct mbx_hdr hdr;
2008         union {
2009                 struct {
2010                         uint8_t rsvd;
2011                         uint8_t type;
2012                         uint16_t rsvd1;
2013                 } req;
2014                 struct {
2015                         uint32_t desc_count;
2016                         uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
2017                 } rsp;
2018         } params;
2019 };
2020
2021
2022 /* OPCODE_COMMON_GET_PROFILE_CONFIG */
2023
2024 struct mbx_common_get_profile_config {
2025         struct mbx_hdr hdr;
2026         union {
2027                 struct {
2028                         uint8_t rsvd;
2029                         uint8_t type;
2030                         uint16_t rsvd1;
2031                 } req;
2032                 struct {
2033                         uint32_t desc_count;
2034                         uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
2035                 } rsp;
2036         } params;
2037 };
2038
2039 struct oce_nic_resc_desc {
2040         uint8_t desc_type;
2041         uint8_t desc_len;
2042         uint8_t rsvd1;
2043         uint8_t flags;
2044         uint8_t vf_num;
2045         uint8_t rsvd2;
2046         uint8_t pf_num;
2047         uint8_t rsvd3;
2048         uint16_t unicast_mac_count;
2049         uint8_t rsvd4[6];
2050         uint16_t mcc_count;
2051         uint16_t vlan_count;
2052         uint16_t mcast_mac_count;
2053         uint16_t txq_count;
2054         uint16_t rq_count;
2055         uint16_t rssq_count;
2056         uint16_t lro_count;
2057         uint16_t cq_count;
2058         uint16_t toe_conn_count;
2059         uint16_t eq_count;
2060         uint32_t rsvd5;
2061         uint32_t cap_flags;
2062         uint8_t link_param;
2063         uint8_t rsvd6[3];
2064         uint32_t bw_min;
2065         uint32_t bw_max;
2066         uint8_t acpi_params;
2067         uint8_t wol_param;
2068         uint16_t rsvd7;
2069         uint32_t rsvd8[7];
2070
2071 };
2072
2073
2074 struct flash_file_hdr {
2075         uint8_t  sign[52];
2076         uint8_t  ufi_version[4];
2077         uint32_t file_len;
2078         uint32_t cksum;
2079         uint32_t antidote;
2080         uint32_t num_imgs;
2081         uint8_t  build[24];
2082         uint8_t  rsvd[32];
2083 };
2084
2085 struct image_hdr {
2086         uint32_t imageid;
2087         uint32_t imageoffset;
2088         uint32_t imagelength;
2089         uint32_t image_checksum;
2090         uint8_t  image_version[32];
2091 };
2092
2093 struct flash_section_hdr {
2094         uint32_t format_rev;
2095         uint32_t cksum;
2096         uint32_t antidote;
2097         uint32_t num_images;
2098         uint8_t  id_string[128];
2099         uint32_t rsvd[4];
2100 };
2101
2102 struct flash_section_entry {
2103         uint32_t type;
2104         uint32_t offset;
2105         uint32_t pad_size;
2106         uint32_t image_size;
2107         uint32_t cksum;
2108         uint32_t entry_point;
2109         uint32_t rsvd0;
2110         uint32_t rsvd1;
2111         uint8_t  ver_data[32];
2112 };
2113
2114 struct flash_sec_info {
2115         uint8_t cookie[32];
2116         struct  flash_section_hdr fsec_hdr;
2117         struct  flash_section_entry fsec_entry[32];
2118 };
2119
2120
2121 enum LOWLEVEL_SUBSYSTEM_OPCODES {
2122 /* Opcodes used for lowlevel functions common to many subystems.
2123  * Some of these opcodes are used for diagnostic functions only.
2124  * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
2125  */
2126         OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
2127         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
2128         OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
2129 };
2130
2131 enum LLDP_SUBSYSTEM_OPCODES {
2132 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
2133         OPCODE_LLDP_GET_CFG = 1,
2134         OPCODE_LLDP_SET_CFG = 2,
2135         OPCODE_LLDP_GET_STATS = 3
2136 };
2137
2138 enum DCBX_SUBSYSTEM_OPCODES {
2139 /* Opcodes used for DCBX. */
2140         OPCODE_DCBX_GET_CFG = 1,
2141         OPCODE_DCBX_SET_CFG = 2,
2142         OPCODE_DCBX_GET_MIB_INFO = 3,
2143         OPCODE_DCBX_GET_DCBX_MODE = 4,
2144         OPCODE_DCBX_SET_MODE = 5
2145 };
2146
2147 enum DMTF_SUBSYSTEM_OPCODES {
2148 /* Opcodes used for DCBX subsystem. */
2149         OPCODE_DMTF_EXEC_CLP_CMD = 1
2150 };
2151
2152 enum DIAG_SUBSYSTEM_OPCODES {
2153 /* Opcodes used for diag functions common to many subsystems. */
2154         OPCODE_DIAG_RUN_DMA_TEST = 1,
2155         OPCODE_DIAG_RUN_MDIO_TEST = 2,
2156         OPCODE_DIAG_RUN_NLB_TEST = 3,
2157         OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
2158         OPCODE_DIAG_GET_MAC = 5
2159 };
2160
2161 enum VENDOR_SUBSYSTEM_OPCODES {
2162 /* Opcodes used for Vendor subsystem. */
2163         OPCODE_VENDOR_SLI = 1
2164 };
2165
2166 /* Management Status Codes */
2167 enum MGMT_STATUS_SUCCESS {
2168         MGMT_SUCCESS = 0,
2169         MGMT_FAILED = 1,
2170         MGMT_ILLEGAL_REQUEST = 2,
2171         MGMT_ILLEGAL_FIELD = 3,
2172         MGMT_INSUFFICIENT_BUFFER = 4,
2173         MGMT_UNAUTHORIZED_REQUEST = 5,
2174         MGMT_INVALID_ISNS_ADDRESS = 10,
2175         MGMT_INVALID_IPADDR = 11,
2176         MGMT_INVALID_GATEWAY = 12,
2177         MGMT_INVALID_SUBNETMASK = 13,
2178         MGMT_INVALID_TARGET_IPADDR = 16,
2179         MGMT_TGTTBL_FULL = 20,
2180         MGMT_FLASHROM_SAVE_FAILED = 23,
2181         MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
2182         MGMT_INVALID_SESSION = 31,
2183         MGMT_INVALID_CONNECTION = 32,
2184         MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
2185         MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
2186         MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
2187         MGMT_BTL_NO_FREE_SLOT_PATH = 36,
2188         MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
2189         MGMT_POLL_IOCTL_TIMEOUT = 40,
2190         MGMT_ERROR_ACITISCSI = 41,
2191         MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
2192         MGMT_REBOOT_REQUIRED = 44,
2193         MGMT_INSUFFICIENT_TIMEOUT = 45,
2194         MGMT_IPADDR_NOT_SET = 46,
2195         MGMT_IPADDR_DUP_DETECTED = 47,
2196         MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
2197         MGMT_TARGET_BUSY = 49,
2198         MGMT_TGT_ERR_LISTEN_SOCKET = 50,
2199         MGMT_TGT_ERR_BIND_SOCKET = 51,
2200         MGMT_TGT_ERR_NO_SOCKET = 52,
2201         MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
2202         MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
2203         MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
2204         MGMT_FCF_IN_USE = 58 ,
2205         MGMT_NO_CQE = 59,
2206         MGMT_TARGET_NOT_FOUND = 65,
2207         MGMT_NOT_SUPPORTED = 66,
2208         MGMT_NO_FCF_RECORDS = 67,
2209         MGMT_FEATURE_NOT_SUPPORTED = 68,
2210         MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
2211         MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
2212         MGMT_INVALID_NON_EMBEDDED_WRB = 71,
2213         MGMT_OOR = 100,
2214         MGMT_INVALID_PD = 101,
2215         MGMT_STATUS_PD_INUSE = 102,
2216         MGMT_INVALID_CQ = 103,
2217         MGMT_INVALID_QP = 104,
2218         MGMT_INVALID_STAG = 105,
2219         MGMT_ORD_EXCEEDS = 106,
2220         MGMT_IRD_EXCEEDS = 107,
2221         MGMT_SENDQ_WQE_EXCEEDS = 108,
2222         MGMT_RECVQ_RQE_EXCEEDS = 109,
2223         MGMT_SGE_SEND_EXCEEDS = 110,
2224         MGMT_SGE_WRITE_EXCEEDS = 111,
2225         MGMT_SGE_RECV_EXCEEDS = 112,
2226         MGMT_INVALID_STATE_CHANGE = 113,
2227         MGMT_MW_BOUND = 114,
2228         MGMT_INVALID_VA = 115,
2229         MGMT_INVALID_LENGTH = 116,
2230         MGMT_INVALID_FBO = 117,
2231         MGMT_INVALID_ACC_RIGHTS = 118,
2232         MGMT_INVALID_PBE_SIZE = 119,
2233         MGMT_INVALID_PBL_ENTRY = 120,
2234         MGMT_INVALID_PBL_OFFSET = 121,
2235         MGMT_ADDR_NON_EXIST = 122,
2236         MGMT_INVALID_VLANID = 123,
2237         MGMT_INVALID_MTU = 124,
2238         MGMT_INVALID_BACKLOG = 125,
2239         MGMT_CONNECTION_INPROGRESS = 126,
2240         MGMT_INVALID_RQE_SIZE = 127,
2241         MGMT_INVALID_RQE_ENTRY = 128
2242 };
2243
2244 /* Additional Management Status Codes */
2245 enum MGMT_ADDI_STATUS {
2246         MGMT_ADDI_NO_STATUS = 0,
2247         MGMT_ADDI_INVALID_IPTYPE = 1,
2248         MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
2249         MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
2250         MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
2251         MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
2252         MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
2253         MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
2254         MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
2255         MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
2256         MGMT_ADDI_TCP_CONNECT_FAILED = 21,
2257         MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
2258         MGMT_ADDI_LINK_DOWN = 23,
2259         MGMT_ADDI_DHCP_ERROR = 24,
2260         MGMT_ADDI_CONNECTION_OFFLOADED = 25,
2261         MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
2262         MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
2263         MGMT_ADDI_REQUEST_REJECTED = 28,
2264         MGMT_ADDI_INVALID_SUBSYSTEM = 29,
2265         MGMT_ADDI_INVALID_OPCODE = 30,
2266         MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
2267         MGMT_ADDI_INVALID_KEY = 32,
2268         MGMT_ADDI_INVALID_DOMAIN = 35,
2269         MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
2270         MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
2271         MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
2272         MGMT_ADDI_LOGIN_NOT_FOUND = 46,
2273         MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
2274         MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
2275         MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
2276         MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
2277         MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
2278         MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
2279         MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
2280         MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
2281         MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
2282         MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
2283         MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
2284         MGMT_ADDI_SAME_CHAP_SECRET = 58,
2285         MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
2286         MGMT_ADDI_DUPLICATE_ENTRY = 60,
2287         MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
2288         MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
2289         MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
2290         MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
2291         MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
2292         MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
2293         MGMT_ADDI_INVALID_VLAN_RANGE = 69,
2294         MGMT_ADDI_ERR_SET_VLAN = 70,
2295         MGMT_ADDI_ERR_DEL_VLAN = 71,
2296         MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
2297         MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
2298         MGMT_ADDI_TOO_MANY_INTERFACES = 74,
2299         MGMT_ADDI_INVALID_REQUEST = 75
2300 };
2301
2302 enum NIC_SUBSYSTEM_OPCODES {
2303 /**
2304  * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
2305  * These opcodes are used for configuring the Ethernet interfaces.
2306  * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
2307  */
2308         NIC_CONFIG_RSS = 1,
2309         NIC_CONFIG_ACPI = 2,
2310         NIC_CONFIG_PROMISCUOUS = 3,
2311         NIC_GET_STATS = 4,
2312         NIC_CREATE_WQ = 7,
2313         NIC_CREATE_RQ = 8,
2314         NIC_DELETE_WQ = 9,
2315         NIC_DELETE_RQ = 10,
2316         NIC_CONFIG_ACPI_WOL_MAGIC = 12,
2317         NIC_GET_NETWORK_STATS = 13,
2318         NIC_CREATE_HDS_RQ = 16,
2319         NIC_DELETE_HDS_RQ = 17,
2320         NIC_GET_PPORT_STATS = 18,
2321         NIC_GET_VPORT_STATS = 19,
2322         NIC_GET_QUEUE_STATS = 20
2323 };
2324
2325 /* Hash option flags for RSS enable */
2326 enum RSS_ENABLE_FLAGS {
2327         RSS_ENABLE_NONE         = 0x0,  /* (No RSS) */
2328         RSS_ENABLE_IPV4         = 0x1,  /* (IPV4 HASH enabled ) */
2329         RSS_ENABLE_TCP_IPV4     = 0x2,  /* (TCP IPV4 Hash enabled) */
2330         RSS_ENABLE_IPV6         = 0x4,  /* (IPV6 HASH enabled) */
2331         RSS_ENABLE_TCP_IPV6     = 0x8,  /* (TCP IPV6 HASH */
2332         RSS_ENABLE_UDP_IPV4     = 0x10, /* UDP IPV4 HASH */
2333         RSS_ENABLE_UDP_IPV6     = 0x20  /* UDP IPV6 HASH */
2334 };
2335 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2336 #define RSS_DISABLE RSS_ENABLE_NONE
2337
2338 /* NIC header WQE */
2339 struct oce_nic_hdr_wqe {
2340         union {
2341                 struct {
2342 #ifdef _BIG_ENDIAN
2343                         /* dw0 */
2344                         uint32_t rsvd0;
2345
2346                         /* dw1 */
2347                         uint32_t last_seg_udp_len:14;
2348                         uint32_t rsvd1:18;
2349
2350                         /* dw2 */
2351                         uint32_t lso_mss:14;
2352                         uint32_t num_wqe:5;
2353                         uint32_t rsvd4:2;
2354                         uint32_t vlan:1;
2355                         uint32_t lso:1;
2356                         uint32_t tcpcs:1;
2357                         uint32_t udpcs:1;
2358                         uint32_t ipcs:1;
2359                         uint32_t rsvd3:1;
2360                         uint32_t rsvd2:1;
2361                         uint32_t forward:1;
2362                         uint32_t crc:1;
2363                         uint32_t event:1;
2364                         uint32_t complete:1;
2365
2366                         /* dw3 */
2367                         uint32_t vlan_tag:16;
2368                         uint32_t total_length:16;
2369 #else
2370                         /* dw0 */
2371                         uint32_t rsvd0;
2372
2373                         /* dw1 */
2374                         uint32_t rsvd1:18;
2375                         uint32_t last_seg_udp_len:14;
2376
2377                         /* dw2 */
2378                         uint32_t complete:1;
2379                         uint32_t event:1;
2380                         uint32_t crc:1;
2381                         uint32_t forward:1;
2382                         uint32_t rsvd2:1;
2383                         uint32_t rsvd3:1;
2384                         uint32_t ipcs:1;
2385                         uint32_t udpcs:1;
2386                         uint32_t tcpcs:1;
2387                         uint32_t lso:1;
2388                         uint32_t vlan:1;
2389                         uint32_t rsvd4:2;
2390                         uint32_t num_wqe:5;
2391                         uint32_t lso_mss:14;
2392
2393                         /* dw3 */
2394                         uint32_t total_length:16;
2395                         uint32_t vlan_tag:16;
2396 #endif
2397                 } s;
2398                 uint32_t dw[4];
2399         } u0;
2400 };
2401
2402 /* NIC fragment WQE */
2403 struct oce_nic_frag_wqe {
2404         union {
2405                 struct {
2406                         /* dw0 */
2407                         uint32_t frag_pa_hi;
2408                         /* dw1 */
2409                         uint32_t frag_pa_lo;
2410                         /* dw2 */
2411                         uint32_t rsvd0;
2412                         uint32_t frag_len;
2413                 } s;
2414                 uint32_t dw[4];
2415         } u0;
2416 };
2417
2418 /* Ethernet Tx Completion Descriptor */
2419 struct oce_nic_tx_cqe {
2420         union {
2421                 struct {
2422 #ifdef _BIG_ENDIAN
2423                         /* dw 0 */
2424                         uint32_t status:4;
2425                         uint32_t rsvd0:8;
2426                         uint32_t port:2;
2427                         uint32_t ct:2;
2428                         uint32_t wqe_index:16;
2429
2430                         /* dw 1 */
2431                         uint32_t rsvd1:5;
2432                         uint32_t cast_enc:2;
2433                         uint32_t lso:1;
2434                         uint32_t nwh_bytes:8;
2435                         uint32_t user_bytes:16;
2436
2437                         /* dw 2 */
2438                         uint32_t rsvd2;
2439
2440                         /* dw 3 */
2441                         uint32_t valid:1;
2442                         uint32_t rsvd3:4;
2443                         uint32_t wq_id:11;
2444                         uint32_t num_pkts:16;
2445 #else
2446                         /* dw 0 */
2447                         uint32_t wqe_index:16;
2448                         uint32_t ct:2;
2449                         uint32_t port:2;
2450                         uint32_t rsvd0:8;
2451                         uint32_t status:4;
2452
2453                         /* dw 1 */
2454                         uint32_t user_bytes:16;
2455                         uint32_t nwh_bytes:8;
2456                         uint32_t lso:1;
2457                         uint32_t cast_enc:2;
2458                         uint32_t rsvd1:5;
2459                         /* dw 2 */
2460                         uint32_t rsvd2;
2461
2462                         /* dw 3 */
2463                         uint32_t num_pkts:16;
2464                         uint32_t wq_id:11;
2465                         uint32_t rsvd3:4;
2466                         uint32_t valid:1;
2467 #endif
2468                 } s;
2469                 uint32_t dw[4];
2470         } u0;
2471 };
2472 #define WQ_CQE_VALID(_cqe)  (_cqe->u0.dw[3])
2473 #define WQ_CQE_INVALIDATE(_cqe)  (_cqe->u0.dw[3] = 0)
2474
2475 /* Receive Queue Entry (RQE) */
2476 struct oce_nic_rqe {
2477         union {
2478                 struct {
2479                         uint32_t frag_pa_hi;
2480                         uint32_t frag_pa_lo;
2481                 } s;
2482                 uint32_t dw[2];
2483         } u0;
2484 };
2485
2486 /* NIC Receive CQE */
2487 struct oce_nic_rx_cqe {
2488         union {
2489                 struct {
2490 #ifdef _BIG_ENDIAN
2491                         /* dw 0 */
2492                         uint32_t ip_options:1;
2493                         uint32_t port:1;
2494                         uint32_t pkt_size:14;
2495                         uint32_t vlan_tag:16;
2496
2497                         /* dw 1 */
2498                         uint32_t num_fragments:3;
2499                         uint32_t switched:1;
2500                         uint32_t ct:2;
2501                         uint32_t frag_index:10;
2502                         uint32_t rsvd0:1;
2503                         uint32_t vlan_tag_present:1;
2504                         uint32_t mac_dst:6;
2505                         uint32_t ip_ver:1;
2506                         uint32_t l4_cksum_pass:1;
2507                         uint32_t ip_cksum_pass:1;
2508                         uint32_t udpframe:1;
2509                         uint32_t tcpframe:1;
2510                         uint32_t ipframe:1;
2511                         uint32_t rss_hp:1;
2512                         uint32_t error:1;
2513
2514                         /* dw 2 */
2515                         uint32_t valid:1;
2516                         uint32_t hds_type:2;
2517                         uint32_t lro_pkt:1;
2518                         uint32_t rsvd4:1;
2519                         uint32_t hds_hdr_size:12;
2520                         uint32_t hds_hdr_frag_index:10;
2521                         uint32_t rss_bank:1;
2522                         uint32_t qnq:1;
2523                         uint32_t pkt_type:2;
2524                         uint32_t rss_flush:1;
2525
2526                         /* dw 3 */
2527                         uint32_t rss_hash_value;
2528 #else
2529                         /* dw 0 */
2530                         uint32_t vlan_tag:16;
2531                         uint32_t pkt_size:14;
2532                         uint32_t port:1;
2533                         uint32_t ip_options:1;
2534                         /* dw 1 */
2535                         uint32_t error:1;
2536                         uint32_t rss_hp:1;
2537                         uint32_t ipframe:1;
2538                         uint32_t tcpframe:1;
2539                         uint32_t udpframe:1;
2540                         uint32_t ip_cksum_pass:1;
2541                         uint32_t l4_cksum_pass:1;
2542                         uint32_t ip_ver:1;
2543                         uint32_t mac_dst:6;
2544                         uint32_t vlan_tag_present:1;
2545                         uint32_t rsvd0:1;
2546                         uint32_t frag_index:10;
2547                         uint32_t ct:2;
2548                         uint32_t switched:1;
2549                         uint32_t num_fragments:3;
2550
2551                         /* dw 2 */
2552                         uint32_t rss_flush:1;
2553                         uint32_t pkt_type:2;
2554                         uint32_t qnq:1;
2555                         uint32_t rss_bank:1;
2556                         uint32_t hds_hdr_frag_index:10;
2557                         uint32_t hds_hdr_size:12;
2558                         uint32_t rsvd4:1;
2559                         uint32_t lro_pkt:1;
2560                         uint32_t hds_type:2;
2561                         uint32_t valid:1;
2562                         /* dw 3 */
2563                         uint32_t rss_hash_value;
2564 #endif
2565                 } s;
2566                 uint32_t dw[4];
2567         } u0;
2568 };
2569 /* NIC Receive CQE_v1 */
2570 struct oce_nic_rx_cqe_v1 {
2571         union {
2572                 struct {
2573 #ifdef _BIG_ENDIAN
2574                         /* dw 0 */
2575                         uint32_t ip_options:1;
2576                         uint32_t vlan_tag_present:1;
2577                         uint32_t pkt_size:14;
2578                         uint32_t vlan_tag:16;
2579
2580                         /* dw 1 */
2581                         uint32_t num_fragments:3;
2582                         uint32_t switched:1;
2583                         uint32_t ct:2;
2584                         uint32_t frag_index:10;
2585                         uint32_t rsvd0:1;
2586                         uint32_t mac_dst:7;
2587                         uint32_t ip_ver:1;
2588                         uint32_t l4_cksum_pass:1;
2589                         uint32_t ip_cksum_pass:1;
2590                         uint32_t udpframe:1;
2591                         uint32_t tcpframe:1;
2592                         uint32_t ipframe:1;
2593                         uint32_t rss_hp:1;
2594                         uint32_t error:1;
2595
2596                         /* dw 2 */
2597                         uint32_t valid:1;
2598                         uint32_t rsvd4:13;
2599                         uint32_t hds_hdr_size:
2600                         uint32_t hds_hdr_frag_index:8;
2601                         uint32_t vlantag:1;
2602                         uint32_t port:2;
2603                         uint32_t rss_bank:1;
2604                         uint32_t qnq:1;
2605                         uint32_t pkt_type:2;
2606                         uint32_t rss_flush:1;
2607
2608                         /* dw 3 */
2609                         uint32_t rss_hash_value;
2610         #else
2611                         /* dw 0 */
2612                         uint32_t vlan_tag:16;
2613                         uint32_t pkt_size:14;
2614                         uint32_t vlan_tag_present:1;
2615                         uint32_t ip_options:1;
2616                         /* dw 1 */
2617                         uint32_t error:1;
2618                         uint32_t rss_hp:1;
2619                         uint32_t ipframe:1;
2620                         uint32_t tcpframe:1;
2621                         uint32_t udpframe:1;
2622                         uint32_t ip_cksum_pass:1;
2623                         uint32_t l4_cksum_pass:1;
2624                         uint32_t ip_ver:1;
2625                         uint32_t mac_dst:7;
2626                         uint32_t rsvd0:1;
2627                         uint32_t frag_index:10;
2628                         uint32_t ct:2;
2629                         uint32_t switched:1;
2630                         uint32_t num_fragments:3;
2631
2632                         /* dw 2 */
2633                         uint32_t rss_flush:1;
2634                         uint32_t pkt_type:2;
2635                         uint32_t qnq:1;
2636                         uint32_t rss_bank:1;
2637                         uint32_t port:2;
2638                         uint32_t vlantag:1;
2639                         uint32_t hds_hdr_frag_index:8;
2640                         uint32_t hds_hdr_size:2;
2641                         uint32_t rsvd4:13;
2642                         uint32_t valid:1;
2643                         /* dw 3 */
2644                         uint32_t rss_hash_value;
2645 #endif
2646                 } s;
2647                 uint32_t dw[4];
2648         } u0;
2649 };
2650
2651 #define RQ_CQE_VALID_MASK  0x80
2652 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
2653 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
2654
2655 struct mbx_config_nic_promiscuous {
2656         struct mbx_hdr hdr;
2657         union {
2658                 struct {
2659 #ifdef _BIG_ENDIAN
2660                         uint16_t rsvd0;
2661                         uint8_t port1_promisc;
2662                         uint8_t port0_promisc;
2663 #else
2664                         uint8_t port0_promisc;
2665                         uint8_t port1_promisc;
2666                         uint16_t rsvd0;
2667 #endif
2668                 } req;
2669
2670                 struct {
2671                         uint32_t rsvd0;
2672                 } rsp;
2673         } params;
2674 };
2675
2676 typedef union oce_wq_ctx_u {
2677                 uint32_t dw[17];
2678                 struct {
2679 #ifdef _BIG_ENDIAN
2680                         /* dw4 */
2681                         uint32_t dw4rsvd2:8;
2682                         uint32_t nic_wq_type:8;
2683                         uint32_t dw4rsvd1:8;
2684                         uint32_t num_pages:8;
2685                         /* dw5 */
2686                         uint32_t dw5rsvd2:12;
2687                         uint32_t wq_size:4;
2688                         uint32_t dw5rsvd1:16;
2689                         /* dw6 */
2690                         uint32_t valid:1;
2691                         uint32_t dw6rsvd1:31;
2692                         /* dw7 */
2693                         uint32_t dw7rsvd1:16;
2694                         uint32_t cq_id:16;
2695 #else
2696                         /* dw4 */
2697                         uint32_t num_pages:8;
2698 #if 0
2699                         uint32_t dw4rsvd1:8;
2700 #else
2701 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */
2702                         uint32_t ulp_mask:8;
2703 #endif
2704                         uint32_t nic_wq_type:8;
2705                         uint32_t dw4rsvd2:8;
2706                         /* dw5 */
2707                         uint32_t dw5rsvd1:16;
2708                         uint32_t wq_size:4;
2709                         uint32_t dw5rsvd2:12;
2710                         /* dw6 */
2711                         uint32_t dw6rsvd1:31;
2712                         uint32_t valid:1;
2713                         /* dw7 */
2714                         uint32_t cq_id:16;
2715                         uint32_t dw7rsvd1:16;
2716 #endif
2717                         /* dw8 - dw20 */
2718                         uint32_t dw8_20rsvd1[13];
2719                 } v0;
2720                 struct {
2721 #ifdef _BIG_ENDIAN
2722                         /* dw4 */
2723                         uint32_t dw4rsvd2:8;
2724                         uint32_t nic_wq_type:8;
2725                         uint32_t dw4rsvd1:8;
2726                         uint32_t num_pages:8;
2727                         /* dw5 */
2728                         uint32_t dw5rsvd2:12;
2729                         uint32_t wq_size:4;
2730                         uint32_t iface_id:16;
2731                         /* dw6 */
2732                         uint32_t valid:1;
2733                         uint32_t dw6rsvd1:31;
2734                         /* dw7 */
2735                         uint32_t dw7rsvd1:16;
2736                         uint32_t cq_id:16;
2737 #else
2738                         /* dw4 */
2739                         uint32_t num_pages:8;
2740                         uint32_t dw4rsvd1:8;
2741                         uint32_t nic_wq_type:8;
2742                         uint32_t dw4rsvd2:8;
2743                         /* dw5 */
2744                         uint32_t iface_id:16;
2745                         uint32_t wq_size:4;
2746                         uint32_t dw5rsvd2:12;
2747                         /* dw6 */
2748                         uint32_t dw6rsvd1:31;
2749                         uint32_t valid:1;
2750                         /* dw7 */
2751                         uint32_t cq_id:16;
2752                         uint32_t dw7rsvd1:16;
2753 #endif
2754                         /* dw8 - dw20 */
2755                         uint32_t dw8_20rsvd1[13];
2756                 } v1;
2757 } oce_wq_ctx_t;
2758
2759 /**
2760  * @brief [07] NIC_CREATE_WQ
2761  * @note
2762  * Lancer requires an InterfaceID to be specified with every WQ. This
2763  * is the basis for NIC IOV where the Interface maps to a vPort and maps
2764  * to both Tx and Rx sides.
2765  */
2766 #define OCE_WQ_TYPE_FORWARDING  0x1     /* wq forwards pkts to TOE */
2767 #define OCE_WQ_TYPE_STANDARD    0x2     /* wq sends network pkts */
2768 struct mbx_create_nic_wq {
2769         struct mbx_hdr hdr;
2770         union {
2771                 struct {
2772                         uint8_t num_pages;
2773                         uint8_t ulp_num;
2774                         uint16_t nic_wq_type;
2775                         uint16_t if_id;
2776                         uint8_t wq_size;
2777                         uint8_t rsvd1;
2778                         uint32_t rsvd2;
2779                         uint16_t cq_id;
2780                         uint16_t rsvd3;
2781                         uint32_t rsvd4[13];
2782                         struct phys_addr pages[8];
2783
2784                 } req;
2785
2786                 struct {
2787                         uint16_t wq_id;
2788                         uint16_t rid;
2789                         uint32_t db_offset;
2790                         uint8_t tc_id;
2791                         uint8_t rsvd0[3];
2792                 } rsp;
2793         } params;
2794 };
2795
2796 /* [09] NIC_DELETE_WQ */
2797 struct mbx_delete_nic_wq {
2798         /* dw0 - dw3 */
2799         struct mbx_hdr hdr;
2800         union {
2801                 struct {
2802 #ifdef _BIG_ENDIAN
2803                         /* dw4 */
2804                         uint16_t rsvd0;
2805                         uint16_t wq_id;
2806 #else
2807                         /* dw4 */
2808                         uint16_t wq_id;
2809                         uint16_t rsvd0;
2810 #endif
2811                 } req;
2812                 struct {
2813                         uint32_t rsvd0;
2814                 } rsp;
2815         } params;
2816 };
2817
2818
2819
2820 struct mbx_create_nic_rq {
2821         struct mbx_hdr hdr;
2822         union {
2823                 struct {
2824                         uint16_t cq_id;
2825                         uint8_t frag_size;
2826                         uint8_t num_pages;
2827                         struct phys_addr pages[2];
2828                         uint32_t if_id;
2829                         uint16_t max_frame_size;
2830                         uint16_t page_size;
2831                         uint32_t is_rss_queue;
2832                 } req;
2833
2834                 struct {
2835                         uint16_t rq_id;
2836                         uint8_t rss_cpuid;
2837                         uint8_t rsvd0;
2838                 } rsp;
2839
2840         } params;
2841 };
2842
2843
2844
2845 /* [10] NIC_DELETE_RQ */
2846 struct mbx_delete_nic_rq {
2847         /* dw0 - dw3 */
2848         struct mbx_hdr hdr;
2849         union {
2850                 struct {
2851 #ifdef _BIG_ENDIAN
2852                         /* dw4 */
2853                         uint16_t bypass_flush;
2854                         uint16_t rq_id;
2855 #else
2856                         /* dw4 */
2857                         uint16_t rq_id;
2858                         uint16_t bypass_flush;
2859 #endif
2860                 } req;
2861
2862                 struct {
2863                         /* dw4 */
2864                         uint32_t rsvd0;
2865                 } rsp;
2866         } params;
2867 };
2868
2869
2870
2871
2872 struct oce_port_rxf_stats_v0 {
2873         uint32_t rx_bytes_lsd;                  /* dword 0*/
2874         uint32_t rx_bytes_msd;                  /* dword 1*/
2875         uint32_t rx_total_frames;               /* dword 2*/
2876         uint32_t rx_unicast_frames;             /* dword 3*/
2877         uint32_t rx_multicast_frames;           /* dword 4*/
2878         uint32_t rx_broadcast_frames;           /* dword 5*/
2879         uint32_t rx_crc_errors;                 /* dword 6*/
2880         uint32_t rx_alignment_symbol_errors;    /* dword 7*/
2881         uint32_t rx_pause_frames;               /* dword 8*/
2882         uint32_t rx_control_frames;             /* dword 9*/
2883         uint32_t rx_in_range_errors;            /* dword 10*/
2884         uint32_t rx_out_range_errors;           /* dword 11*/
2885         uint32_t rx_frame_too_long;             /* dword 12*/
2886         uint32_t rx_address_match_errors;       /* dword 13*/
2887         uint32_t rx_vlan_mismatch;              /* dword 14*/
2888         uint32_t rx_dropped_too_small;          /* dword 15*/
2889         uint32_t rx_dropped_too_short;          /* dword 16*/
2890         uint32_t rx_dropped_header_too_small;   /* dword 17*/
2891         uint32_t rx_dropped_tcp_length;         /* dword 18*/
2892         uint32_t rx_dropped_runt;               /* dword 19*/
2893         uint32_t rx_64_byte_packets;            /* dword 20*/
2894         uint32_t rx_65_127_byte_packets;        /* dword 21*/
2895         uint32_t rx_128_256_byte_packets;       /* dword 22*/
2896         uint32_t rx_256_511_byte_packets;       /* dword 23*/
2897         uint32_t rx_512_1023_byte_packets;      /* dword 24*/
2898         uint32_t rx_1024_1518_byte_packets;     /* dword 25*/
2899         uint32_t rx_1519_2047_byte_packets;     /* dword 26*/
2900         uint32_t rx_2048_4095_byte_packets;     /* dword 27*/
2901         uint32_t rx_4096_8191_byte_packets;     /* dword 28*/
2902         uint32_t rx_8192_9216_byte_packets;     /* dword 29*/
2903         uint32_t rx_ip_checksum_errs;           /* dword 30*/
2904         uint32_t rx_tcp_checksum_errs;          /* dword 31*/
2905         uint32_t rx_udp_checksum_errs;          /* dword 32*/
2906         uint32_t rx_non_rss_packets;            /* dword 33*/
2907         uint32_t rx_ipv4_packets;               /* dword 34*/
2908         uint32_t rx_ipv6_packets;               /* dword 35*/
2909         uint32_t rx_ipv4_bytes_lsd;             /* dword 36*/
2910         uint32_t rx_ipv4_bytes_msd;             /* dword 37*/
2911         uint32_t rx_ipv6_bytes_lsd;             /* dword 38*/
2912         uint32_t rx_ipv6_bytes_msd;             /* dword 39*/
2913         uint32_t rx_chute1_packets;             /* dword 40*/
2914         uint32_t rx_chute2_packets;             /* dword 41*/
2915         uint32_t rx_chute3_packets;             /* dword 42*/
2916         uint32_t rx_management_packets;         /* dword 43*/
2917         uint32_t rx_switched_unicast_packets;   /* dword 44*/
2918         uint32_t rx_switched_multicast_packets; /* dword 45*/
2919         uint32_t rx_switched_broadcast_packets; /* dword 46*/
2920         uint32_t tx_bytes_lsd;                  /* dword 47*/
2921         uint32_t tx_bytes_msd;                  /* dword 48*/
2922         uint32_t tx_unicastframes;              /* dword 49*/
2923         uint32_t tx_multicastframes;            /* dword 50*/
2924         uint32_t tx_broadcastframes;            /* dword 51*/
2925         uint32_t tx_pauseframes;                /* dword 52*/
2926         uint32_t tx_controlframes;              /* dword 53*/
2927         uint32_t tx_64_byte_packets;            /* dword 54*/
2928         uint32_t tx_65_127_byte_packets;        /* dword 55*/
2929         uint32_t tx_128_256_byte_packets;       /* dword 56*/
2930         uint32_t tx_256_511_byte_packets;       /* dword 57*/
2931         uint32_t tx_512_1023_byte_packets;      /* dword 58*/
2932         uint32_t tx_1024_1518_byte_packets;     /* dword 59*/
2933         uint32_t tx_1519_2047_byte_packets;     /* dword 60*/
2934         uint32_t tx_2048_4095_byte_packets;     /* dword 61*/
2935         uint32_t tx_4096_8191_byte_packets;     /* dword 62*/
2936         uint32_t tx_8192_9216_byte_packets;     /* dword 63*/
2937         uint32_t rxpp_fifo_overflow_drop;       /* dword 64*/
2938         uint32_t rx_input_fifo_overflow_drop;   /* dword 65*/
2939 };
2940
2941
2942 struct oce_rxf_stats_v0 {
2943         struct oce_port_rxf_stats_v0 port[2];
2944         uint32_t rx_drops_no_pbuf;              /* dword 132*/
2945         uint32_t rx_drops_no_txpb;              /* dword 133*/
2946         uint32_t rx_drops_no_erx_descr;         /* dword 134*/
2947         uint32_t rx_drops_no_tpre_descr;        /* dword 135*/
2948         uint32_t management_rx_port_packets;    /* dword 136*/
2949         uint32_t management_rx_port_bytes;      /* dword 137*/
2950         uint32_t management_rx_port_pause_frames;/* dword 138*/
2951         uint32_t management_rx_port_errors;     /* dword 139*/
2952         uint32_t management_tx_port_packets;    /* dword 140*/
2953         uint32_t management_tx_port_bytes;      /* dword 141*/
2954         uint32_t management_tx_port_pause;      /* dword 142*/
2955         uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
2956         uint32_t rx_drops_too_many_frags;       /* dword 144*/
2957         uint32_t rx_drops_invalid_ring;         /* dword 145*/
2958         uint32_t forwarded_packets;             /* dword 146*/
2959         uint32_t rx_drops_mtu;                  /* dword 147*/
2960         uint32_t rsvd0[7];
2961         uint32_t port0_jabber_events;
2962         uint32_t port1_jabber_events;
2963         uint32_t rsvd1[6];
2964 };
2965
2966 struct oce_port_rxf_stats_v1 {
2967         uint32_t rsvd0[12];
2968         uint32_t rx_crc_errors;
2969         uint32_t rx_alignment_symbol_errors;
2970         uint32_t rx_pause_frames;
2971         uint32_t rx_priority_pause_frames;
2972         uint32_t rx_control_frames;
2973         uint32_t rx_in_range_errors;
2974         uint32_t rx_out_range_errors;
2975         uint32_t rx_frame_too_long;
2976         uint32_t rx_address_match_errors;
2977         uint32_t rx_dropped_too_small;
2978         uint32_t rx_dropped_too_short;
2979         uint32_t rx_dropped_header_too_small;
2980         uint32_t rx_dropped_tcp_length;
2981         uint32_t rx_dropped_runt;
2982         uint32_t rsvd1[10];
2983         uint32_t rx_ip_checksum_errs;
2984         uint32_t rx_tcp_checksum_errs;
2985         uint32_t rx_udp_checksum_errs;
2986         uint32_t rsvd2[7];
2987         uint32_t rx_switched_unicast_packets;
2988         uint32_t rx_switched_multicast_packets;
2989         uint32_t rx_switched_broadcast_packets;
2990         uint32_t rsvd3[3];
2991         uint32_t tx_pauseframes;
2992         uint32_t tx_priority_pauseframes;
2993         uint32_t tx_controlframes;
2994         uint32_t rsvd4[10];
2995         uint32_t rxpp_fifo_overflow_drop;
2996         uint32_t rx_input_fifo_overflow_drop;
2997         uint32_t pmem_fifo_overflow_drop;
2998         uint32_t jabber_events;
2999         uint32_t rsvd5[3];
3000 };
3001
3002
3003 struct oce_rxf_stats_v1 {
3004         struct oce_port_rxf_stats_v1 port[4];
3005         uint32_t rsvd0[2];
3006         uint32_t rx_drops_no_pbuf;
3007         uint32_t rx_drops_no_txpb;
3008         uint32_t rx_drops_no_erx_descr;
3009         uint32_t rx_drops_no_tpre_descr;
3010         uint32_t rsvd1[6];
3011         uint32_t rx_drops_too_many_frags;
3012         uint32_t rx_drops_invalid_ring;
3013         uint32_t forwarded_packets;
3014         uint32_t rx_drops_mtu;
3015         uint32_t rsvd2[14];
3016 };
3017
3018 struct oce_erx_stats_v1 {
3019         uint32_t rx_drops_no_fragments[68];
3020         uint32_t rsvd[4];
3021 };
3022
3023
3024 struct oce_erx_stats_v0 {
3025         uint32_t rx_drops_no_fragments[44];
3026         uint32_t rsvd[4];
3027 };
3028
3029 struct oce_pmem_stats {
3030         uint32_t eth_red_drops;
3031         uint32_t rsvd[5];
3032 };
3033
3034 struct oce_hw_stats_v1 {
3035         struct oce_rxf_stats_v1 rxf;
3036         uint32_t rsvd0[OCE_TXP_SW_SZ];
3037         struct oce_erx_stats_v1 erx;
3038         struct oce_pmem_stats pmem;
3039         uint32_t rsvd1[18];
3040 };
3041
3042 struct oce_hw_stats_v0 {
3043         struct oce_rxf_stats_v0 rxf;
3044         uint32_t rsvd[48];
3045         struct oce_erx_stats_v0 erx;
3046         struct oce_pmem_stats pmem;
3047 };
3048
3049 struct mbx_get_nic_stats_v0 {
3050         struct mbx_hdr hdr;
3051         union {
3052                 struct {
3053                         uint32_t rsvd0;
3054                 } req;
3055
3056                 union {
3057                         struct oce_hw_stats_v0 stats;
3058                 } rsp;
3059         } params;
3060 };
3061
3062 struct mbx_get_nic_stats {
3063         struct mbx_hdr hdr;
3064         union {
3065                 struct {
3066                         uint32_t rsvd0;
3067                 } req;
3068
3069                 struct {
3070                         struct oce_hw_stats_v1 stats;
3071                 } rsp;
3072         } params;
3073 };
3074
3075
3076 /* [18(0x12)] NIC_GET_PPORT_STATS */
3077 struct pport_stats {
3078         uint64_t tx_pkts;
3079         uint64_t tx_unicast_pkts;
3080         uint64_t tx_multicast_pkts;
3081         uint64_t tx_broadcast_pkts;
3082         uint64_t tx_bytes;
3083         uint64_t tx_unicast_bytes;
3084         uint64_t tx_multicast_bytes;
3085         uint64_t tx_broadcast_bytes;
3086         uint64_t tx_discards;
3087         uint64_t tx_errors;
3088         uint64_t tx_pause_frames;
3089         uint64_t tx_pause_on_frames;
3090         uint64_t tx_pause_off_frames;
3091         uint64_t tx_internal_mac_errors;
3092         uint64_t tx_control_frames;
3093         uint64_t tx_pkts_64_bytes;
3094         uint64_t tx_pkts_65_to_127_bytes;
3095         uint64_t tx_pkts_128_to_255_bytes;
3096         uint64_t tx_pkts_256_to_511_bytes;
3097         uint64_t tx_pkts_512_to_1023_bytes;
3098         uint64_t tx_pkts_1024_to_1518_bytes;
3099         uint64_t tx_pkts_1519_to_2047_bytes;
3100         uint64_t tx_pkts_2048_to_4095_bytes;
3101         uint64_t tx_pkts_4096_to_8191_bytes;
3102         uint64_t tx_pkts_8192_to_9216_bytes;
3103         uint64_t tx_lso_pkts;
3104         uint64_t rx_pkts;
3105         uint64_t rx_unicast_pkts;
3106         uint64_t rx_multicast_pkts;
3107         uint64_t rx_broadcast_pkts;
3108         uint64_t rx_bytes;
3109         uint64_t rx_unicast_bytes;
3110         uint64_t rx_multicast_bytes;
3111         uint64_t rx_broadcast_bytes;
3112         uint32_t rx_unknown_protos;
3113         uint32_t reserved_word69;
3114         uint64_t rx_discards;
3115         uint64_t rx_errors;
3116         uint64_t rx_crc_errors;
3117         uint64_t rx_alignment_errors;
3118         uint64_t rx_symbol_errors;
3119         uint64_t rx_pause_frames;
3120         uint64_t rx_pause_on_frames;
3121         uint64_t rx_pause_off_frames;
3122         uint64_t rx_frames_too_long;
3123         uint64_t rx_internal_mac_errors;
3124         uint32_t rx_undersize_pkts;
3125         uint32_t rx_oversize_pkts;
3126         uint32_t rx_fragment_pkts;
3127         uint32_t rx_jabbers;
3128         uint64_t rx_control_frames;
3129         uint64_t rx_control_frames_unknown_opcode;
3130         uint32_t rx_in_range_errors;
3131         uint32_t rx_out_of_range_errors;
3132         uint32_t rx_address_match_errors;
3133         uint32_t rx_vlan_mismatch_errors;
3134         uint32_t rx_dropped_too_small;
3135         uint32_t rx_dropped_too_short;
3136         uint32_t rx_dropped_header_too_small;
3137         uint32_t rx_dropped_invalid_tcp_length;
3138         uint32_t rx_dropped_runt;
3139         uint32_t rx_ip_checksum_errors;
3140         uint32_t rx_tcp_checksum_errors;
3141         uint32_t rx_udp_checksum_errors;
3142         uint32_t rx_non_rss_pkts;
3143         uint64_t reserved_word111;
3144         uint64_t rx_ipv4_pkts;
3145         uint64_t rx_ipv6_pkts;
3146         uint64_t rx_ipv4_bytes;
3147         uint64_t rx_ipv6_bytes;
3148         uint64_t rx_nic_pkts;
3149         uint64_t rx_tcp_pkts;
3150         uint64_t rx_iscsi_pkts;
3151         uint64_t rx_management_pkts;
3152         uint64_t rx_switched_unicast_pkts;
3153         uint64_t rx_switched_multicast_pkts;
3154         uint64_t rx_switched_broadcast_pkts;
3155         uint64_t num_forwards;
3156         uint32_t rx_fifo_overflow;
3157         uint32_t rx_input_fifo_overflow;
3158         uint64_t rx_drops_too_many_frags;
3159         uint32_t rx_drops_invalid_queue;
3160         uint32_t reserved_word141;
3161         uint64_t rx_drops_mtu;
3162         uint64_t rx_pkts_64_bytes;
3163         uint64_t rx_pkts_65_to_127_bytes;
3164         uint64_t rx_pkts_128_to_255_bytes;
3165         uint64_t rx_pkts_256_to_511_bytes;
3166         uint64_t rx_pkts_512_to_1023_bytes;
3167         uint64_t rx_pkts_1024_to_1518_bytes;
3168         uint64_t rx_pkts_1519_to_2047_bytes;
3169         uint64_t rx_pkts_2048_to_4095_bytes;
3170         uint64_t rx_pkts_4096_to_8191_bytes;
3171         uint64_t rx_pkts_8192_to_9216_bytes;
3172 };
3173
3174 struct mbx_get_pport_stats {
3175         /* dw0 - dw3 */
3176         struct mbx_hdr hdr;
3177         union {
3178                 struct {
3179                         /* dw4 */
3180 #ifdef _BIG_ENDIAN
3181                         uint32_t reset_stats:8;
3182                         uint32_t rsvd0:8;
3183                         uint32_t port_number:16;
3184 #else
3185                         uint32_t port_number:16;
3186                         uint32_t rsvd0:8;
3187                         uint32_t reset_stats:8;
3188 #endif
3189                 } req;
3190
3191                 union {
3192                         struct pport_stats pps;
3193                         uint32_t pport_stats[164 - 4 + 1];
3194                 } rsp;
3195         } params;
3196 };
3197
3198 /* [19(0x13)] NIC_GET_VPORT_STATS */
3199 struct vport_stats {
3200         uint64_t tx_pkts;
3201         uint64_t tx_unicast_pkts;
3202         uint64_t tx_multicast_pkts;
3203         uint64_t tx_broadcast_pkts;
3204         uint64_t tx_bytes;
3205         uint64_t tx_unicast_bytes;
3206         uint64_t tx_multicast_bytes;
3207         uint64_t tx_broadcast_bytes;
3208         uint64_t tx_discards;
3209         uint64_t tx_errors;
3210         uint64_t tx_pkts_64_bytes;
3211         uint64_t tx_pkts_65_to_127_bytes;
3212         uint64_t tx_pkts_128_to_255_bytes;
3213         uint64_t tx_pkts_256_to_511_bytes;
3214         uint64_t tx_pkts_512_to_1023_bytes;
3215         uint64_t tx_pkts_1024_to_1518_bytes;
3216         uint64_t tx_pkts_1519_to_9699_bytes;
3217         uint64_t tx_pkts_over_9699_bytes;
3218         uint64_t rx_pkts;
3219         uint64_t rx_unicast_pkts;
3220         uint64_t rx_multicast_pkts;
3221         uint64_t rx_broadcast_pkts;
3222         uint64_t rx_bytes;
3223         uint64_t rx_unicast_bytes;
3224         uint64_t rx_multicast_bytes;
3225         uint64_t rx_broadcast_bytes;
3226         uint64_t rx_discards;
3227         uint64_t rx_errors;
3228         uint64_t rx_pkts_64_bytes;
3229         uint64_t rx_pkts_65_to_127_bytes;
3230         uint64_t rx_pkts_128_to_255_bytes;
3231         uint64_t rx_pkts_256_to_511_bytes;
3232         uint64_t rx_pkts_512_to_1023_bytes;
3233         uint64_t rx_pkts_1024_to_1518_bytes;
3234         uint64_t rx_pkts_1519_to_9699_bytes;
3235         uint64_t rx_pkts_gt_9699_bytes;
3236 };
3237 struct mbx_get_vport_stats {
3238         /* dw0 - dw3 */
3239         struct mbx_hdr hdr;
3240         union {
3241                 struct {
3242                         /* dw4 */
3243 #ifdef _BIG_ENDIAN
3244                         uint32_t reset_stats:8;
3245                         uint32_t rsvd0:8;
3246                         uint32_t vport_number:16;
3247 #else
3248                         uint32_t vport_number:16;
3249                         uint32_t rsvd0:8;
3250                         uint32_t reset_stats:8;
3251 #endif
3252                 } req;
3253
3254                 union {
3255                         struct vport_stats vps;
3256                         uint32_t vport_stats[75 - 4 + 1];
3257                 } rsp;
3258         } params;
3259 };
3260
3261 /**
3262  * @brief       [20(0x14)] NIC_GET_QUEUE_STATS
3263  * The significant difference between vPort and Queue statistics is
3264  * the packet byte counters.
3265  */
3266 struct queue_stats {
3267         uint64_t packets;
3268         uint64_t bytes;
3269         uint64_t errors;
3270         uint64_t drops;
3271         uint64_t buffer_errors;         /* rsvd when tx */
3272 };
3273
3274 #define QUEUE_TYPE_WQ           0
3275 #define QUEUE_TYPE_RQ           1
3276 #define QUEUE_TYPE_HDS_RQ       1       /* same as RQ */
3277
3278 struct mbx_get_queue_stats {
3279         /* dw0 - dw3 */
3280         struct mbx_hdr hdr;
3281         union {
3282                 struct {
3283                         /* dw4 */
3284 #ifdef _BIG_ENDIAN
3285                         uint32_t reset_stats:8;
3286                         uint32_t queue_type:8;
3287                         uint32_t queue_id:16;
3288 #else
3289                         uint32_t queue_id:16;
3290                         uint32_t queue_type:8;
3291                         uint32_t reset_stats:8;
3292 #endif
3293                 } req;
3294
3295                 union {
3296                         struct queue_stats qs;
3297                         uint32_t queue_stats[13 - 4 + 1];
3298                 } rsp;
3299         } params;
3300 };
3301
3302
3303 /* [01] NIC_CONFIG_RSS */
3304 #define OCE_HASH_TBL_SZ 10
3305 #define OCE_CPU_TBL_SZ  128
3306 #define OCE_FLUSH       1       /* RSS flush completion per CQ port */
3307 struct mbx_config_nic_rss {
3308         struct mbx_hdr hdr;
3309         union {
3310                 struct {
3311 #ifdef _BIG_ENDIAN
3312                         uint32_t if_id;
3313                         uint16_t cpu_tbl_sz_log2;
3314                         uint16_t enable_rss;
3315                         uint32_t hash[OCE_HASH_TBL_SZ];
3316                         uint8_t cputable[OCE_CPU_TBL_SZ];
3317                         uint8_t rsvd[3];
3318                         uint8_t flush;
3319 #else
3320                         uint32_t if_id;
3321                         uint16_t enable_rss;
3322                         uint16_t cpu_tbl_sz_log2;
3323                         uint32_t hash[OCE_HASH_TBL_SZ];
3324                         uint8_t cputable[OCE_CPU_TBL_SZ];
3325                         uint8_t flush;
3326                         uint8_t rsvd[3];
3327 #endif
3328                 } req;
3329                 struct {
3330                         uint8_t rsvd[3];
3331                         uint8_t rss_bank;
3332                 } rsp;
3333         } params;
3334 };
3335
3336
3337 #pragma pack()
3338
3339
3340 typedef uint32_t oce_stat_t;            /* statistic counter */
3341
3342 enum OCE_RXF_PORT_STATS {
3343         RXF_RX_BYTES_LSD,
3344         RXF_RX_BYTES_MSD,
3345         RXF_RX_TOTAL_FRAMES,
3346         RXF_RX_UNICAST_FRAMES,
3347         RXF_RX_MULTICAST_FRAMES,
3348         RXF_RX_BROADCAST_FRAMES,
3349         RXF_RX_CRC_ERRORS,
3350         RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
3351         RXF_RX_PAUSE_FRAMES,
3352         RXF_RX_CONTROL_FRAMES,
3353         RXF_RX_IN_RANGE_ERRORS,
3354         RXF_RX_OUT_RANGE_ERRORS,
3355         RXF_RX_FRAME_TOO_LONG,
3356         RXF_RX_ADDRESS_MATCH_ERRORS,
3357         RXF_RX_VLAN_MISMATCH,
3358         RXF_RX_DROPPED_TOO_SMALL,
3359         RXF_RX_DROPPED_TOO_SHORT,
3360         RXF_RX_DROPPED_HEADER_TOO_SMALL,
3361         RXF_RX_DROPPED_TCP_LENGTH,
3362         RXF_RX_DROPPED_RUNT,
3363         RXF_RX_64_BYTE_PACKETS,
3364         RXF_RX_65_127_BYTE_PACKETS,
3365         RXF_RX_128_256_BYTE_PACKETS,
3366         RXF_RX_256_511_BYTE_PACKETS,
3367         RXF_RX_512_1023_BYTE_PACKETS,
3368         RXF_RX_1024_1518_BYTE_PACKETS,
3369         RXF_RX_1519_2047_BYTE_PACKETS,
3370         RXF_RX_2048_4095_BYTE_PACKETS,
3371         RXF_RX_4096_8191_BYTE_PACKETS,
3372         RXF_RX_8192_9216_BYTE_PACKETS,
3373         RXF_RX_IP_CHECKSUM_ERRS,
3374         RXF_RX_TCP_CHECKSUM_ERRS,
3375         RXF_RX_UDP_CHECKSUM_ERRS,
3376         RXF_RX_NON_RSS_PACKETS,
3377         RXF_RX_IPV4_PACKETS,
3378         RXF_RX_IPV6_PACKETS,
3379         RXF_RX_IPV4_BYTES_LSD,
3380         RXF_RX_IPV4_BYTES_MSD,
3381         RXF_RX_IPV6_BYTES_LSD,
3382         RXF_RX_IPV6_BYTES_MSD,
3383         RXF_RX_CHUTE1_PACKETS,
3384         RXF_RX_CHUTE2_PACKETS,
3385         RXF_RX_CHUTE3_PACKETS,
3386         RXF_RX_MANAGEMENT_PACKETS,
3387         RXF_RX_SWITCHED_UNICAST_PACKETS,
3388         RXF_RX_SWITCHED_MULTICAST_PACKETS,
3389         RXF_RX_SWITCHED_BROADCAST_PACKETS,
3390         RXF_TX_BYTES_LSD,
3391         RXF_TX_BYTES_MSD,
3392         RXF_TX_UNICAST_FRAMES,
3393         RXF_TX_MULTICAST_FRAMES,
3394         RXF_TX_BROADCAST_FRAMES,
3395         RXF_TX_PAUSE_FRAMES,
3396         RXF_TX_CONTROL_FRAMES,
3397         RXF_TX_64_BYTE_PACKETS,
3398         RXF_TX_65_127_BYTE_PACKETS,
3399         RXF_TX_128_256_BYTE_PACKETS,
3400         RXF_TX_256_511_BYTE_PACKETS,
3401         RXF_TX_512_1023_BYTE_PACKETS,
3402         RXF_TX_1024_1518_BYTE_PACKETS,
3403         RXF_TX_1519_2047_BYTE_PACKETS,
3404         RXF_TX_2048_4095_BYTE_PACKETS,
3405         RXF_TX_4096_8191_BYTE_PACKETS,
3406         RXF_TX_8192_9216_BYTE_PACKETS,
3407         RXF_RX_FIFO_OVERFLOW,
3408         RXF_RX_INPUT_FIFO_OVERFLOW,
3409         RXF_PORT_STATS_N_WORDS
3410 };
3411
3412 enum OCE_RXF_ADDL_STATS {
3413         RXF_RX_DROPS_NO_PBUF,
3414         RXF_RX_DROPS_NO_TXPB,
3415         RXF_RX_DROPS_NO_ERX_DESCR,
3416         RXF_RX_DROPS_NO_TPRE_DESCR,
3417         RXF_MANAGEMENT_RX_PORT_PACKETS,
3418         RXF_MANAGEMENT_RX_PORT_BYTES,
3419         RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
3420         RXF_MANAGEMENT_RX_PORT_ERRORS,
3421         RXF_MANAGEMENT_TX_PORT_PACKETS,
3422         RXF_MANAGEMENT_TX_PORT_BYTES,
3423         RXF_MANAGEMENT_TX_PORT_PAUSE,
3424         RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
3425         RXF_RX_DROPS_TOO_MANY_FRAGS,
3426         RXF_RX_DROPS_INVALID_RING,
3427         RXF_FORWARDED_PACKETS,
3428         RXF_RX_DROPS_MTU,
3429         RXF_ADDL_STATS_N_WORDS
3430 };
3431
3432 enum OCE_TX_CHUTE_PORT_STATS {
3433         CTPT_XMT_IPV4_PKTS,
3434         CTPT_XMT_IPV4_LSD,
3435         CTPT_XMT_IPV4_MSD,
3436         CTPT_XMT_IPV6_PKTS,
3437         CTPT_XMT_IPV6_LSD,
3438         CTPT_XMT_IPV6_MSD,
3439         CTPT_REXMT_IPV4_PKTs,
3440         CTPT_REXMT_IPV4_LSD,
3441         CTPT_REXMT_IPV4_MSD,
3442         CTPT_REXMT_IPV6_PKTs,
3443         CTPT_REXMT_IPV6_LSD,
3444         CTPT_REXMT_IPV6_MSD,
3445         CTPT_N_WORDS,
3446 };
3447
3448 enum OCE_RX_ERR_STATS {
3449         RX_DROPS_NO_FRAGMENTS_0,
3450         RX_DROPS_NO_FRAGMENTS_1,
3451         RX_DROPS_NO_FRAGMENTS_2,
3452         RX_DROPS_NO_FRAGMENTS_3,
3453         RX_DROPS_NO_FRAGMENTS_4,
3454         RX_DROPS_NO_FRAGMENTS_5,
3455         RX_DROPS_NO_FRAGMENTS_6,
3456         RX_DROPS_NO_FRAGMENTS_7,
3457         RX_DROPS_NO_FRAGMENTS_8,
3458         RX_DROPS_NO_FRAGMENTS_9,
3459         RX_DROPS_NO_FRAGMENTS_10,
3460         RX_DROPS_NO_FRAGMENTS_11,
3461         RX_DROPS_NO_FRAGMENTS_12,
3462         RX_DROPS_NO_FRAGMENTS_13,
3463         RX_DROPS_NO_FRAGMENTS_14,
3464         RX_DROPS_NO_FRAGMENTS_15,
3465         RX_DROPS_NO_FRAGMENTS_16,
3466         RX_DROPS_NO_FRAGMENTS_17,
3467         RX_DROPS_NO_FRAGMENTS_18,
3468         RX_DROPS_NO_FRAGMENTS_19,
3469         RX_DROPS_NO_FRAGMENTS_20,
3470         RX_DROPS_NO_FRAGMENTS_21,
3471         RX_DROPS_NO_FRAGMENTS_22,
3472         RX_DROPS_NO_FRAGMENTS_23,
3473         RX_DROPS_NO_FRAGMENTS_24,
3474         RX_DROPS_NO_FRAGMENTS_25,
3475         RX_DROPS_NO_FRAGMENTS_26,
3476         RX_DROPS_NO_FRAGMENTS_27,
3477         RX_DROPS_NO_FRAGMENTS_28,
3478         RX_DROPS_NO_FRAGMENTS_29,
3479         RX_DROPS_NO_FRAGMENTS_30,
3480         RX_DROPS_NO_FRAGMENTS_31,
3481         RX_DROPS_NO_FRAGMENTS_32,
3482         RX_DROPS_NO_FRAGMENTS_33,
3483         RX_DROPS_NO_FRAGMENTS_34,
3484         RX_DROPS_NO_FRAGMENTS_35,
3485         RX_DROPS_NO_FRAGMENTS_36,
3486         RX_DROPS_NO_FRAGMENTS_37,
3487         RX_DROPS_NO_FRAGMENTS_38,
3488         RX_DROPS_NO_FRAGMENTS_39,
3489         RX_DROPS_NO_FRAGMENTS_40,
3490         RX_DROPS_NO_FRAGMENTS_41,
3491         RX_DROPS_NO_FRAGMENTS_42,
3492         RX_DROPS_NO_FRAGMENTS_43,
3493         RX_DEBUG_WDMA_SENT_HOLD,
3494         RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
3495         RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
3496         RX_DEBUG_PMEM_PBUF_DEALLOC,
3497         RX_ERRORS_N_WORDS
3498 };
3499
3500 enum OCE_PMEM_ERR_STATS {
3501         PMEM_ETH_RED_DROPS,
3502         PMEM_LRO_RED_DROPS,
3503         PMEM_ULP0_RED_DROPS,
3504         PMEM_ULP1_RED_DROPS,
3505         PMEM_GLOBAL_RED_DROPS,
3506         PMEM_ERRORS_N_WORDS
3507 };
3508
3509 /**
3510  * @brief Statistics for a given Physical Port
3511  * These satisfy all the required BE2 statistics and also the
3512  * following MIB objects:
3513  *
3514  * RFC 2863 - The Interfaces Group MIB
3515  * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
3516  * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
3517  * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
3518  *
3519  */
3520 enum OCE_PPORT_STATS {
3521         PPORT_TX_PKTS = 0,
3522         PPORT_TX_UNICAST_PKTS = 2,
3523         PPORT_TX_MULTICAST_PKTS = 4,
3524         PPORT_TX_BROADCAST_PKTS = 6,
3525         PPORT_TX_BYTES = 8,
3526         PPORT_TX_UNICAST_BYTES = 10,
3527         PPORT_TX_MULTICAST_BYTES = 12,
3528         PPORT_TX_BROADCAST_BYTES = 14,
3529         PPORT_TX_DISCARDS = 16,
3530         PPORT_TX_ERRORS = 18,
3531         PPORT_TX_PAUSE_FRAMES = 20,
3532         PPORT_TX_PAUSE_ON_FRAMES = 22,
3533         PPORT_TX_PAUSE_OFF_FRAMES = 24,
3534         PPORT_TX_INTERNAL_MAC_ERRORS = 26,
3535         PPORT_TX_CONTROL_FRAMES = 28,
3536         PPORT_TX_PKTS_64_BYTES = 30,
3537         PPORT_TX_PKTS_65_TO_127_BYTES = 32,
3538         PPORT_TX_PKTS_128_TO_255_BYTES = 34,
3539         PPORT_TX_PKTS_256_TO_511_BYTES = 36,
3540         PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
3541         PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
3542         PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
3543         PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
3544         PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
3545         PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
3546         PPORT_TX_LSO_PKTS = 50,
3547         PPORT_RX_PKTS = 52,
3548         PPORT_RX_UNICAST_PKTS = 54,
3549         PPORT_RX_MULTICAST_PKTS = 56,
3550         PPORT_RX_BROADCAST_PKTS = 58,
3551         PPORT_RX_BYTES = 60,
3552         PPORT_RX_UNICAST_BYTES = 62,
3553         PPORT_RX_MULTICAST_BYTES = 64,
3554         PPORT_RX_BROADCAST_BYTES = 66,
3555         PPORT_RX_UNKNOWN_PROTOS = 68,
3556         PPORT_RESERVED_WORD69 = 69,
3557         PPORT_RX_DISCARDS = 70,
3558         PPORT_RX_ERRORS = 72,
3559         PPORT_RX_CRC_ERRORS = 74,
3560         PPORT_RX_ALIGNMENT_ERRORS = 76,
3561         PPORT_RX_SYMBOL_ERRORS = 78,
3562         PPORT_RX_PAUSE_FRAMES = 80,
3563         PPORT_RX_PAUSE_ON_FRAMES = 82,
3564         PPORT_RX_PAUSE_OFF_FRAMES = 84,
3565         PPORT_RX_FRAMES_TOO_LONG = 86,
3566         PPORT_RX_INTERNAL_MAC_ERRORS = 88,
3567         PPORT_RX_UNDERSIZE_PKTS = 90,
3568         PPORT_RX_OVERSIZE_PKTS = 91,
3569         PPORT_RX_FRAGMENT_PKTS = 92,
3570         PPORT_RX_JABBERS = 93,
3571         PPORT_RX_CONTROL_FRAMES = 94,
3572         PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
3573         PPORT_RX_IN_RANGE_ERRORS = 98,
3574         PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
3575         PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
3576         PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
3577         PPORT_RX_DROPPED_TOO_SMALL = 102,
3578         PPORT_RX_DROPPED_TOO_SHORT = 103,
3579         PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
3580         PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
3581         PPORT_RX_DROPPED_RUNT = 106,
3582         PPORT_RX_IP_CHECKSUM_ERRORS = 107,
3583         PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
3584         PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
3585         PPORT_RX_NON_RSS_PKTS = 110,
3586         PPORT_RESERVED_WORD111 = 111,
3587         PPORT_RX_IPV4_PKTS = 112,
3588         PPORT_RX_IPV6_PKTS = 114,
3589         PPORT_RX_IPV4_BYTES = 116,
3590         PPORT_RX_IPV6_BYTES = 118,
3591         PPORT_RX_NIC_PKTS = 120,
3592         PPORT_RX_TCP_PKTS = 122,
3593         PPORT_RX_ISCSI_PKTS = 124,
3594         PPORT_RX_MANAGEMENT_PKTS = 126,
3595         PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
3596         PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
3597         PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
3598         PPORT_NUM_FORWARDS = 134,
3599         PPORT_RX_FIFO_OVERFLOW = 136,
3600         PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
3601         PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
3602         PPORT_RX_DROPS_INVALID_QUEUE = 140,
3603         PPORT_RESERVED_WORD141 = 141,
3604         PPORT_RX_DROPS_MTU = 142,
3605         PPORT_RX_PKTS_64_BYTES = 144,
3606         PPORT_RX_PKTS_65_TO_127_BYTES = 146,
3607         PPORT_RX_PKTS_128_TO_255_BYTES = 148,
3608         PPORT_RX_PKTS_256_TO_511_BYTES = 150,
3609         PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
3610         PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
3611         PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
3612         PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
3613         PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
3614         PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
3615         PPORT_N_WORDS = 164
3616 };
3617
3618 /**
3619  * @brief Statistics for a given Virtual Port (vPort)
3620  * The following describes the vPort statistics satisfying
3621  * requirements of Linux/VMWare netdev statistics and
3622  * Microsoft Windows Statistics along with other Operating Systems.
3623  */
3624 enum OCE_VPORT_STATS {
3625         VPORT_TX_PKTS = 0,
3626         VPORT_TX_UNICAST_PKTS = 2,
3627         VPORT_TX_MULTICAST_PKTS = 4,
3628         VPORT_TX_BROADCAST_PKTS = 6,
3629         VPORT_TX_BYTES = 8,
3630         VPORT_TX_UNICAST_BYTES = 10,
3631         VPORT_TX_MULTICAST_BYTES = 12,
3632         VPORT_TX_BROADCAST_BYTES = 14,
3633         VPORT_TX_DISCARDS = 16,
3634         VPORT_TX_ERRORS = 18,
3635         VPORT_TX_PKTS_64_BYTES = 20,
3636         VPORT_TX_PKTS_65_TO_127_BYTES = 22,
3637         VPORT_TX_PKTS_128_TO_255_BYTES = 24,
3638         VPORT_TX_PKTS_256_TO_511_BYTES = 26,
3639         VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
3640         VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
3641         VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
3642         VPORT_TX_PKTS_OVER_9699_BYTES = 34,
3643         VPORT_RX_PKTS = 36,
3644         VPORT_RX_UNICAST_PKTS = 38,
3645         VPORT_RX_MULTICAST_PKTS = 40,
3646         VPORT_RX_BROADCAST_PKTS = 42,
3647         VPORT_RX_BYTES = 44,
3648         VPORT_RX_UNICAST_BYTES = 46,
3649         VPORT_RX_MULTICAST_BYTES = 48,
3650         VPORT_RX_BROADCAST_BYTES = 50,
3651         VPORT_RX_DISCARDS = 52,
3652         VPORT_RX_ERRORS = 54,
3653         VPORT_RX_PKTS_64_BYTES = 56,
3654         VPORT_RX_PKTS_65_TO_127_BYTES = 58,
3655         VPORT_RX_PKTS_128_TO_255_BYTES = 60,
3656         VPORT_RX_PKTS_256_TO_511_BYTES = 62,
3657         VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
3658         VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
3659         VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
3660         VPORT_RX_PKTS_OVER_9699_BYTES = 70,
3661         VPORT_N_WORDS = 72
3662 };
3663
3664 /**
3665  * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
3666  * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
3667  */
3668 enum OCE_QUEUE_TX_STATS {
3669         QUEUE_TX_PKTS = 0,
3670         QUEUE_TX_BYTES = 2,
3671         QUEUE_TX_ERRORS = 4,
3672         QUEUE_TX_DROPS = 6,
3673         QUEUE_TX_N_WORDS = 8
3674 };
3675
3676 enum OCE_QUEUE_RX_STATS {
3677         QUEUE_RX_PKTS = 0,
3678         QUEUE_RX_BYTES = 2,
3679         QUEUE_RX_ERRORS = 4,
3680         QUEUE_RX_DROPS = 6,
3681         QUEUE_RX_BUFFER_ERRORS = 8,
3682         QUEUE_RX_N_WORDS = 10
3683 };
3684