sys/dev/oce/oce_if.c

   1 /*-
   2  * Copyright (C) 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the Emulex Corporation nor the names of its
  16  *    contributors may be used to endorse or promote products derived from
  17  *    this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Contact Information:
  32  * freebsd-drivers@emulex.com
  33  *
  34  * Emulex
  35  * 3333 Susan Street
  36  * Costa Mesa, CA 92626
  37  */
  38
  39
  40 /* $FreeBSD$ */
  41
  42 #include "opt_inet6.h"
  43 #include "opt_inet.h"
  44
  45 #include "oce_if.h"
  46
  47
  48 /* Driver entry points prototypes */
  49 static int  oce_probe(device_t dev);
  50 static int  oce_attach(device_t dev);
  51 static int  oce_detach(device_t dev);
  52 static int  oce_shutdown(device_t dev);
  53 static int  oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
  54 static void oce_init(void *xsc);
  55 static int  oce_multiq_start(struct ifnet *ifp, struct mbuf *m);
  56 static void oce_multiq_flush(struct ifnet *ifp);
  57
  58 /* Driver interrupt routines protypes */
  59 static void oce_intr(void *arg, int pending);
  60 static int  oce_setup_intr(POCE_SOFTC sc);
  61 static int  oce_fast_isr(void *arg);
  62 static int  oce_alloc_intr(POCE_SOFTC sc, int vector,
  63                           void (*isr) (void *arg, int pending));
  64
  65 /* Media callbacks prototypes */
  66 static void oce_media_status(struct ifnet *ifp, struct ifmediareq *req);
  67 static int  oce_media_change(struct ifnet *ifp);
  68
  69 /* Transmit routines prototypes */
  70 static int  oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index);
  71 static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq);
  72 static void oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx,
  73                                         uint32_t status);
  74 static int  oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m,
  75                                  struct oce_wq *wq);
  76
  77 /* Receive routines prototypes */
  78 static void oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe);
  79 static int  oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
  80 static int  oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
  81 static void oce_rx(struct oce_rq *rq, uint32_t rqe_idx,
  82                                                 struct oce_nic_rx_cqe *cqe);
  83
  84 /* Helper function prototypes in this file */
  85 static int  oce_attach_ifp(POCE_SOFTC sc);
  86 static void oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag);
  87 static void oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag);
  88 static int  oce_vid_config(POCE_SOFTC sc);
  89 static void oce_mac_addr_set(POCE_SOFTC sc);
  90 static int  oce_handle_passthrough(struct ifnet *ifp, caddr_t data);
  91 static void oce_local_timer(void *arg);
  92 static void oce_if_deactivate(POCE_SOFTC sc);
  93 static void oce_if_activate(POCE_SOFTC sc);
  94 static void setup_max_queues_want(POCE_SOFTC sc);
  95 static void update_queues_got(POCE_SOFTC sc);
  96 static void process_link_state(POCE_SOFTC sc,
  97                  struct oce_async_cqe_link_state *acqe);
  98 static int oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m);
  99 static void oce_get_config(POCE_SOFTC sc);
 100 static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete);
 101
 102 /* IP specific */
 103 #if defined(INET6) || defined(INET)
 104 static int  oce_init_lro(POCE_SOFTC sc);
 105 static void oce_rx_flush_lro(struct oce_rq *rq);
 106 static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp);
 107 #endif
 108
 109 static device_method_t oce_dispatch[] = {
 110         DEVMETHOD(device_probe, oce_probe),
 111         DEVMETHOD(device_attach, oce_attach),
 112         DEVMETHOD(device_detach, oce_detach),
 113         DEVMETHOD(device_shutdown, oce_shutdown),
 114         {0, 0}
 115 };
 116
 117 static driver_t oce_driver = {
 118         "oce",
 119         oce_dispatch,
 120         sizeof(OCE_SOFTC)
 121 };
 122 static devclass_t oce_devclass;
 123
 124
 125 DRIVER_MODULE(oce, pci, oce_driver, oce_devclass, 0, 0);
 126 MODULE_DEPEND(oce, pci, 1, 1, 1);
 127 MODULE_DEPEND(oce, ether, 1, 1, 1);
 128 MODULE_VERSION(oce, 1);
 129
 130
 131 /* global vars */
 132 const char component_revision[32] = {"///" COMPONENT_REVISION "///"};
 133
 134 /* Module capabilites and parameters */
 135 uint32_t oce_max_rsp_handled = OCE_MAX_RSP_HANDLED;
 136 uint32_t oce_enable_rss = OCE_MODCAP_RSS;
 137
 138
 139 TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled);
 140 TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss);
 141
 142
 143 /* Supported devices table */
 144 static uint32_t supportedDevices[] =  {
 145         (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE2,
 146         (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE3,
 147         (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_BE3,
 148         (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201,
 149         (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201_VF,
 150         (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_SH
 151 };
 152
 153
 154
 155
 156 /*****************************************************************************
 157  *                      Driver entry points functions                        *
 158  *****************************************************************************/
 159
 160 static int
 161 oce_probe(device_t dev)
 162 {
 163         uint16_t vendor = 0;
 164         uint16_t device = 0;
 165         int i = 0;
 166         char str[256] = {0};
 167         POCE_SOFTC sc;
 168
 169         sc = device_get_softc(dev);
 170         bzero(sc, sizeof(OCE_SOFTC));
 171         sc->dev = dev;
 172
 173         vendor = pci_get_vendor(dev);
 174         device = pci_get_device(dev);
 175
 176         for (i = 0; i < (sizeof(supportedDevices) / sizeof(uint32_t)); i++) {
 177                 if (vendor == ((supportedDevices[i] >> 16) & 0xffff)) {
 178                         if (device == (supportedDevices[i] & 0xffff)) {
 179                                 sprintf(str, "%s:%s", "Emulex CNA NIC function",
 180                                         component_revision);
 181                                 device_set_desc_copy(dev, str);
 182
 183                                 switch (device) {
 184                                 case PCI_PRODUCT_BE2:
 185                                         sc->flags |= OCE_FLAGS_BE2;
 186                                         break;
 187                                 case PCI_PRODUCT_BE3:
 188                                         sc->flags |= OCE_FLAGS_BE3;
 189                                         break;
 190                                 case PCI_PRODUCT_XE201:
 191                                 case PCI_PRODUCT_XE201_VF:
 192                                         sc->flags |= OCE_FLAGS_XE201;
 193                                         break;
 194                                 case PCI_PRODUCT_SH:
 195                                         sc->flags |= OCE_FLAGS_SH;
 196                                         break;
 197                                 default:
 198                                         return ENXIO;
 199                                 }
 200                                 return BUS_PROBE_DEFAULT;
 201                         }
 202                 }
 203         }
 204
 205         return ENXIO;
 206 }
 207
 208
 209 static int
 210 oce_attach(device_t dev)
 211 {
 212         POCE_SOFTC sc;
 213         int rc = 0;
 214
 215         sc = device_get_softc(dev);
 216
 217         rc = oce_hw_pci_alloc(sc);
 218         if (rc)
 219                 return rc;
 220
 221         sc->tx_ring_size = OCE_TX_RING_SIZE;
 222         sc->rx_ring_size = OCE_RX_RING_SIZE;
 223         sc->rq_frag_size = OCE_RQ_BUF_SIZE;
 224         sc->flow_control = OCE_DEFAULT_FLOW_CONTROL;
 225         sc->promisc      = OCE_DEFAULT_PROMISCUOUS;
 226
 227         LOCK_CREATE(&sc->bmbx_lock, "Mailbox_lock");
 228         LOCK_CREATE(&sc->dev_lock,  "Device_lock");
 229
 230         /* initialise the hardware */
 231         rc = oce_hw_init(sc);
 232         if (rc)
 233                 goto pci_res_free;
 234
 235         oce_get_config(sc);
 236
 237         setup_max_queues_want(sc);
 238
 239         rc = oce_setup_intr(sc);
 240         if (rc)
 241                 goto mbox_free;
 242
 243         rc = oce_queue_init_all(sc);
 244         if (rc)
 245                 goto intr_free;
 246
 247         rc = oce_attach_ifp(sc);
 248         if (rc)
 249                 goto queues_free;
 250
 251 #if defined(INET6) || defined(INET)
 252         rc = oce_init_lro(sc);
 253         if (rc)
 254                 goto ifp_free;
 255 #endif
 256
 257         rc = oce_hw_start(sc);
 258         if (rc)
 259                 goto lro_free;
 260
 261         sc->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 262                                 oce_add_vlan, sc, EVENTHANDLER_PRI_FIRST);
 263         sc->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 264                                 oce_del_vlan, sc, EVENTHANDLER_PRI_FIRST);
 265
 266         rc = oce_stats_init(sc);
 267         if (rc)
 268                 goto vlan_free;
 269
 270         oce_add_sysctls(sc);
 271
 272         callout_init(&sc->timer, CALLOUT_MPSAFE);
 273         rc = callout_reset(&sc->timer, 2 * hz, oce_local_timer, sc);
 274         if (rc)
 275                 goto stats_free;
 276
 277         return 0;
 278
 279 stats_free:
 280         callout_drain(&sc->timer);
 281         oce_stats_free(sc);
 282 vlan_free:
 283         if (sc->vlan_attach)
 284                 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
 285         if (sc->vlan_detach)
 286                 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
 287         oce_hw_intr_disable(sc);
 288 lro_free:
 289 #if defined(INET6) || defined(INET)
 290         oce_free_lro(sc);
 291 ifp_free:
 292 #endif
 293         ether_ifdetach(sc->ifp);
 294         if_free(sc->ifp);
 295 queues_free:
 296         oce_queue_release_all(sc);
 297 intr_free:
 298         oce_intr_free(sc);
 299 mbox_free:
 300         oce_dma_free(sc, &sc->bsmbx);
 301 pci_res_free:
 302         oce_hw_pci_free(sc);
 303         LOCK_DESTROY(&sc->dev_lock);
 304         LOCK_DESTROY(&sc->bmbx_lock);
 305         return rc;
 306
 307 }
 308
 309
 310 static int
 311 oce_detach(device_t dev)
 312 {
 313         POCE_SOFTC sc = device_get_softc(dev);
 314
 315         LOCK(&sc->dev_lock);
 316         oce_if_deactivate(sc);
 317         UNLOCK(&sc->dev_lock);
 318
 319         callout_drain(&sc->timer);
 320
 321         if (sc->vlan_attach != NULL)
 322                 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
 323         if (sc->vlan_detach != NULL)
 324                 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
 325
 326         ether_ifdetach(sc->ifp);
 327
 328         if_free(sc->ifp);
 329
 330         oce_hw_shutdown(sc);
 331
 332         bus_generic_detach(dev);
 333
 334         return 0;
 335 }
 336
 337
 338 static int
 339 oce_shutdown(device_t dev)
 340 {
 341         int rc;
 342
 343         rc = oce_detach(dev);
 344
 345         return rc;
 346 }
 347
 348
 349 static int
 350 oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 351 {
 352         struct ifreq *ifr = (struct ifreq *)data;
 353         POCE_SOFTC sc = ifp->if_softc;
 354         int rc = 0;
 355         uint32_t u;
 356
 357         switch (command) {
 358
 359         case SIOCGIFMEDIA:
 360                 rc = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 361                 break;
 362
 363         case SIOCSIFMTU:
 364                 if (ifr->ifr_mtu > OCE_MAX_MTU)
 365                         rc = EINVAL;
 366                 else
 367                         ifp->if_mtu = ifr->ifr_mtu;
 368                 break;
 369
 370         case SIOCSIFFLAGS:
 371                 if (ifp->if_flags & IFF_UP) {
 372                         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 373                                 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
 374                                 oce_init(sc);
 375                         }
 376                         device_printf(sc->dev, "Interface Up\n");
 377                 } else {
 378                         LOCK(&sc->dev_lock);
 379
 380                         sc->ifp->if_drv_flags &=
 381                             ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 382                         oce_if_deactivate(sc);
 383
 384                         UNLOCK(&sc->dev_lock);
 385
 386                         device_printf(sc->dev, "Interface Down\n");
 387                 }
 388
 389                 if ((ifp->if_flags & IFF_PROMISC) && !sc->promisc) {
 390                         sc->promisc = TRUE;
 391                         oce_rxf_set_promiscuous(sc, sc->promisc);
 392                 } else if (!(ifp->if_flags & IFF_PROMISC) && sc->promisc) {
 393                         sc->promisc = FALSE;
 394                         oce_rxf_set_promiscuous(sc, sc->promisc);
 395                 }
 396
 397                 break;
 398
 399         case SIOCADDMULTI:
 400         case SIOCDELMULTI:
 401                 rc = oce_hw_update_multicast(sc);
 402                 if (rc)
 403                         device_printf(sc->dev,
 404                                 "Update multicast address failed\n");
 405                 break;
 406
 407         case SIOCSIFCAP:
 408                 u = ifr->ifr_reqcap ^ ifp->if_capenable;
 409
 410                 if (u & IFCAP_TXCSUM) {
 411                         ifp->if_capenable ^= IFCAP_TXCSUM;
 412                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
 413
 414                         if (IFCAP_TSO & ifp->if_capenable &&
 415                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
 416                                 ifp->if_capenable &= ~IFCAP_TSO;
 417                                 ifp->if_hwassist &= ~CSUM_TSO;
 418                                 if_printf(ifp,
 419                                          "TSO disabled due to -txcsum.\n");
 420                         }
 421                 }
 422
 423                 if (u & IFCAP_RXCSUM)
 424                         ifp->if_capenable ^= IFCAP_RXCSUM;
 425
 426                 if (u & IFCAP_TSO4) {
 427                         ifp->if_capenable ^= IFCAP_TSO4;
 428
 429                         if (IFCAP_TSO & ifp->if_capenable) {
 430                                 if (IFCAP_TXCSUM & ifp->if_capenable)
 431                                         ifp->if_hwassist |= CSUM_TSO;
 432                                 else {
 433                                         ifp->if_capenable &= ~IFCAP_TSO;
 434                                         ifp->if_hwassist &= ~CSUM_TSO;
 435                                         if_printf(ifp,
 436                                             "Enable txcsum first.\n");
 437                                         rc = EAGAIN;
 438                                 }
 439                         } else
 440                                 ifp->if_hwassist &= ~CSUM_TSO;
 441                 }
 442
 443                 if (u & IFCAP_VLAN_HWTAGGING)
 444                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 445
 446                 if (u & IFCAP_VLAN_HWFILTER) {
 447                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
 448                         oce_vid_config(sc);
 449                 }
 450 #if defined(INET6) || defined(INET)
 451                 if (u & IFCAP_LRO)
 452                         ifp->if_capenable ^= IFCAP_LRO;
 453 #endif
 454
 455                 break;
 456
 457         case SIOCGPRIVATE_0:
 458                 rc = oce_handle_passthrough(ifp, data);
 459                 break;
 460         default:
 461                 rc = ether_ioctl(ifp, command, data);
 462                 break;
 463         }
 464
 465         return rc;
 466 }
 467
 468
 469 static void
 470 oce_init(void *arg)
 471 {
 472         POCE_SOFTC sc = arg;
 473
 474         LOCK(&sc->dev_lock);
 475
 476         if (sc->ifp->if_flags & IFF_UP) {
 477                 oce_if_deactivate(sc);
 478                 oce_if_activate(sc);
 479         }
 480
 481         UNLOCK(&sc->dev_lock);
 482
 483 }
 484
 485
 486 static int
 487 oce_multiq_start(struct ifnet *ifp, struct mbuf *m)
 488 {
 489         POCE_SOFTC sc = ifp->if_softc;
 490         struct oce_wq *wq = NULL;
 491         int queue_index = 0;
 492         int status = 0;
 493
 494         if (!sc->link_status)
 495                 return ENXIO;
 496
 497         if ((m->m_flags & M_FLOWID) != 0)
 498                 queue_index = m->m_pkthdr.flowid % sc->nwqs;
 499
 500         wq = sc->wq[queue_index];
 501
 502         LOCK(&wq->tx_lock);
 503         status = oce_multiq_transmit(ifp, m, wq);
 504         UNLOCK(&wq->tx_lock);
 505
 506         return status;
 507
 508 }
 509
 510
 511 static void
 512 oce_multiq_flush(struct ifnet *ifp)
 513 {
 514         POCE_SOFTC sc = ifp->if_softc;
 515         struct mbuf     *m;
 516         int i = 0;
 517
 518         for (i = 0; i < sc->nwqs; i++) {
 519                 while ((m = buf_ring_dequeue_sc(sc->wq[i]->br)) != NULL)
 520                         m_freem(m);
 521         }
 522         if_qflush(ifp);
 523 }
 524
 525
 526
 527 /*****************************************************************************
 528  *                   Driver interrupt routines functions                     *
 529  *****************************************************************************/
 530
 531 static void
 532 oce_intr(void *arg, int pending)
 533 {
 534
 535         POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
 536         POCE_SOFTC sc = ii->sc;
 537         struct oce_eq *eq = ii->eq;
 538         struct oce_eqe *eqe;
 539         struct oce_cq *cq = NULL;
 540         int i, num_eqes = 0;
 541
 542
 543         bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
 544                                  BUS_DMASYNC_POSTWRITE);
 545         do {
 546                 eqe = RING_GET_CONSUMER_ITEM_VA(eq->ring, struct oce_eqe);
 547                 if (eqe->evnt == 0)
 548                         break;
 549                 eqe->evnt = 0;
 550                 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
 551                                         BUS_DMASYNC_POSTWRITE);
 552                 RING_GET(eq->ring, 1);
 553                 num_eqes++;
 554
 555         } while (TRUE);
 556
 557         if (!num_eqes)
 558                 goto eq_arm; /* Spurious */
 559
 560         /* Clear EQ entries, but dont arm */
 561         oce_arm_eq(sc, eq->eq_id, num_eqes, FALSE, FALSE);
 562
 563         /* Process TX, RX and MCC. But dont arm CQ*/
 564         for (i = 0; i < eq->cq_valid; i++) {
 565                 cq = eq->cq[i];
 566                 (*cq->cq_handler)(cq->cb_arg);
 567         }
 568
 569         /* Arm all cqs connected to this EQ */
 570         for (i = 0; i < eq->cq_valid; i++) {
 571                 cq = eq->cq[i];
 572                 oce_arm_cq(sc, cq->cq_id, 0, TRUE);
 573         }
 574
 575 eq_arm:
 576         oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
 577
 578         return;
 579 }
 580
 581
 582 static int
 583 oce_setup_intr(POCE_SOFTC sc)
 584 {
 585         int rc = 0, use_intx = 0;
 586         int vector = 0, req_vectors = 0;
 587
 588         if (is_rss_enabled(sc))
 589                 req_vectors = MAX((sc->nrqs - 1), sc->nwqs);
 590         else
 591                 req_vectors = 1;
 592
 593         if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) {
 594                 sc->intr_count = req_vectors;
 595                 rc = pci_alloc_msix(sc->dev, &sc->intr_count);
 596                 if (rc != 0) {
 597                         use_intx = 1;
 598                         pci_release_msi(sc->dev);
 599                 } else
 600                         sc->flags |= OCE_FLAGS_USING_MSIX;
 601         } else
 602                 use_intx = 1;
 603
 604         if (use_intx)
 605                 sc->intr_count = 1;
 606
 607         /* Scale number of queues based on intr we got */
 608         update_queues_got(sc);
 609
 610         if (use_intx) {
 611                 device_printf(sc->dev, "Using legacy interrupt\n");
 612                 rc = oce_alloc_intr(sc, vector, oce_intr);
 613                 if (rc)
 614                         goto error;
 615         } else {
 616                 for (; vector < sc->intr_count; vector++) {
 617                         rc = oce_alloc_intr(sc, vector, oce_intr);
 618                         if (rc)
 619                                 goto error;
 620                 }
 621         }
 622
 623         return 0;
 624 error:
 625         oce_intr_free(sc);
 626         return rc;
 627 }
 628
 629
 630 static int
 631 oce_fast_isr(void *arg)
 632 {
 633         POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
 634         POCE_SOFTC sc = ii->sc;
 635
 636         if (ii->eq == NULL)
 637                 return FILTER_STRAY;
 638
 639         oce_arm_eq(sc, ii->eq->eq_id, 0, FALSE, TRUE);
 640
 641         taskqueue_enqueue_fast(ii->tq, &ii->task);
 642
 643         ii->eq->intr++;
 644
 645         return FILTER_HANDLED;
 646 }
 647
 648
 649 static int
 650 oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending))
 651 {
 652         POCE_INTR_INFO ii = &sc->intrs[vector];
 653         int rc = 0, rr;
 654
 655         if (vector >= OCE_MAX_EQ)
 656                 return (EINVAL);
 657
 658         /* Set the resource id for the interrupt.
 659          * MSIx is vector + 1 for the resource id,
 660          * INTx is 0 for the resource id.
 661          */
 662         if (sc->flags & OCE_FLAGS_USING_MSIX)
 663                 rr = vector + 1;
 664         else
 665                 rr = 0;
 666         ii->intr_res = bus_alloc_resource_any(sc->dev,
 667                                               SYS_RES_IRQ,
 668                                               &rr, RF_ACTIVE|RF_SHAREABLE);
 669         ii->irq_rr = rr;
 670         if (ii->intr_res == NULL) {
 671                 device_printf(sc->dev,
 672                           "Could not allocate interrupt\n");
 673                 rc = ENXIO;
 674                 return rc;
 675         }
 676
 677         TASK_INIT(&ii->task, 0, isr, ii);
 678         ii->vector = vector;
 679         sprintf(ii->task_name, "oce_task[%d]", ii->vector);
 680         ii->tq = taskqueue_create_fast(ii->task_name,
 681                         M_NOWAIT,
 682                         taskqueue_thread_enqueue,
 683                         &ii->tq);
 684         taskqueue_start_threads(&ii->tq, 1, PI_NET, "%s taskq",
 685                         device_get_nameunit(sc->dev));
 686
 687         ii->sc = sc;
 688         rc = bus_setup_intr(sc->dev,
 689                         ii->intr_res,
 690                         INTR_TYPE_NET,
 691                         oce_fast_isr, NULL, ii, &ii->tag);
 692         return rc;
 693
 694 }
 695
 696
 697 void
 698 oce_intr_free(POCE_SOFTC sc)
 699 {
 700         int i = 0;
 701
 702         for (i = 0; i < sc->intr_count; i++) {
 703
 704                 if (sc->intrs[i].tag != NULL)
 705                         bus_teardown_intr(sc->dev, sc->intrs[i].intr_res,
 706                                                 sc->intrs[i].tag);
 707                 if (sc->intrs[i].tq != NULL)
 708                         taskqueue_free(sc->intrs[i].tq);
 709
 710                 if (sc->intrs[i].intr_res != NULL)
 711                         bus_release_resource(sc->dev, SYS_RES_IRQ,
 712                                                 sc->intrs[i].irq_rr,
 713                                                 sc->intrs[i].intr_res);
 714                 sc->intrs[i].tag = NULL;
 715                 sc->intrs[i].intr_res = NULL;
 716         }
 717
 718         if (sc->flags & OCE_FLAGS_USING_MSIX)
 719                 pci_release_msi(sc->dev);
 720
 721 }
 722
 723
 724
 725 /******************************************************************************
 726 *                         Media callbacks functions                           *
 727 ******************************************************************************/
 728
 729 static void
 730 oce_media_status(struct ifnet *ifp, struct ifmediareq *req)
 731 {
 732         POCE_SOFTC sc = (POCE_SOFTC) ifp->if_softc;
 733
 734
 735         req->ifm_status = IFM_AVALID;
 736         req->ifm_active = IFM_ETHER;
 737
 738         if (sc->link_status == 1)
 739                 req->ifm_status |= IFM_ACTIVE;
 740         else
 741                 return;
 742
 743         switch (sc->link_speed) {
 744         case 1: /* 10 Mbps */
 745                 req->ifm_active |= IFM_10_T | IFM_FDX;
 746                 sc->speed = 10;
 747                 break;
 748         case 2: /* 100 Mbps */
 749                 req->ifm_active |= IFM_100_TX | IFM_FDX;
 750                 sc->speed = 100;
 751                 break;
 752         case 3: /* 1 Gbps */
 753                 req->ifm_active |= IFM_1000_T | IFM_FDX;
 754                 sc->speed = 1000;
 755                 break;
 756         case 4: /* 10 Gbps */
 757                 req->ifm_active |= IFM_10G_SR | IFM_FDX;
 758                 sc->speed = 10000;
 759                 break;
 760         }
 761
 762         return;
 763 }
 764
 765
 766 int
 767 oce_media_change(struct ifnet *ifp)
 768 {
 769         return 0;
 770 }
 771
 772
 773
 774
 775 /*****************************************************************************
 776  *                        Transmit routines functions                        *
 777  *****************************************************************************/
 778
 779 static int
 780 oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
 781 {
 782         int rc = 0, i, retry_cnt = 0;
 783         bus_dma_segment_t segs[OCE_MAX_TX_ELEMENTS];
 784         struct mbuf *m, *m_temp;
 785         struct oce_wq *wq = sc->wq[wq_index];
 786         struct oce_packet_desc *pd;
 787         struct oce_nic_hdr_wqe *nichdr;
 788         struct oce_nic_frag_wqe *nicfrag;
 789         int num_wqes;
 790         uint32_t reg_value;
 791         boolean_t complete = TRUE;
 792
 793         m = *mpp;
 794         if (!m)
 795                 return EINVAL;
 796
 797         if (!(m->m_flags & M_PKTHDR)) {
 798                 rc = ENXIO;
 799                 goto free_ret;
 800         }
 801
 802         if(oce_tx_asic_stall_verify(sc, m)) {
 803                 m = oce_insert_vlan_tag(sc, m, &complete);
 804                 if(!m) {
 805                         device_printf(sc->dev, "Insertion unsuccessful\n");
 806                         return 0;
 807                 }
 808
 809         }
 810
 811         if (m->m_pkthdr.csum_flags & CSUM_TSO) {
 812                 /* consolidate packet buffers for TSO/LSO segment offload */
 813 #if defined(INET6) || defined(INET)
 814                 m = oce_tso_setup(sc, mpp);
 815 #else
 816                 m = NULL;
 817 #endif
 818                 if (m == NULL) {
 819                         rc = ENXIO;
 820                         goto free_ret;
 821                 }
 822         }
 823
 824         pd = &wq->pckts[wq->pkt_desc_head];
 825 retry:
 826         rc = bus_dmamap_load_mbuf_sg(wq->tag,
 827                                      pd->map,
 828                                      m, segs, &pd->nsegs, BUS_DMA_NOWAIT);
 829         if (rc == 0) {
 830                 num_wqes = pd->nsegs + 1;
 831                 if (IS_BE(sc) || IS_SH(sc)) {
 832                         /*Dummy required only for BE3.*/
 833                         if (num_wqes & 1)
 834                                 num_wqes++;
 835                 }
 836                 if (num_wqes >= RING_NUM_FREE(wq->ring)) {
 837                         bus_dmamap_unload(wq->tag, pd->map);
 838                         return EBUSY;
 839                 }
 840                 atomic_store_rel_int(&wq->pkt_desc_head,
 841                                      (wq->pkt_desc_head + 1) % \
 842                                       OCE_WQ_PACKET_ARRAY_SIZE);
 843                 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_PREWRITE);
 844                 pd->mbuf = m;
 845
 846                 nichdr =
 847                     RING_GET_PRODUCER_ITEM_VA(wq->ring, struct oce_nic_hdr_wqe);
 848                 nichdr->u0.dw[0] = 0;
 849                 nichdr->u0.dw[1] = 0;
 850                 nichdr->u0.dw[2] = 0;
 851                 nichdr->u0.dw[3] = 0;
 852
 853                 nichdr->u0.s.complete = complete;
 854                 nichdr->u0.s.event = 1;
 855                 nichdr->u0.s.crc = 1;
 856                 nichdr->u0.s.forward = 0;
 857                 nichdr->u0.s.ipcs = (m->m_pkthdr.csum_flags & CSUM_IP) ? 1 : 0;
 858                 nichdr->u0.s.udpcs =
 859                         (m->m_pkthdr.csum_flags & CSUM_UDP) ? 1 : 0;
 860                 nichdr->u0.s.tcpcs =
 861                         (m->m_pkthdr.csum_flags & CSUM_TCP) ? 1 : 0;
 862                 nichdr->u0.s.num_wqe = num_wqes;
 863                 nichdr->u0.s.total_length = m->m_pkthdr.len;
 864                 if (m->m_flags & M_VLANTAG) {
 865                         nichdr->u0.s.vlan = 1; /*Vlan present*/
 866                         nichdr->u0.s.vlan_tag = m->m_pkthdr.ether_vtag;
 867                 }
 868                 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
 869                         if (m->m_pkthdr.tso_segsz) {
 870                                 nichdr->u0.s.lso = 1;
 871                                 nichdr->u0.s.lso_mss  = m->m_pkthdr.tso_segsz;
 872                         }
 873                         if (!IS_BE(sc) || !IS_SH(sc))
 874                                 nichdr->u0.s.ipcs = 1;
 875                 }
 876
 877                 RING_PUT(wq->ring, 1);
 878                 atomic_add_int(&wq->ring->num_used, 1);
 879
 880                 for (i = 0; i < pd->nsegs; i++) {
 881                         nicfrag =
 882                             RING_GET_PRODUCER_ITEM_VA(wq->ring,
 883                                                       struct oce_nic_frag_wqe);
 884                         nicfrag->u0.s.rsvd0 = 0;
 885                         nicfrag->u0.s.frag_pa_hi = ADDR_HI(segs[i].ds_addr);
 886                         nicfrag->u0.s.frag_pa_lo = ADDR_LO(segs[i].ds_addr);
 887                         nicfrag->u0.s.frag_len = segs[i].ds_len;
 888                         pd->wqe_idx = wq->ring->pidx;
 889                         RING_PUT(wq->ring, 1);
 890                         atomic_add_int(&wq->ring->num_used, 1);
 891                 }
 892                 if (num_wqes > (pd->nsegs + 1)) {
 893                         nicfrag =
 894                             RING_GET_PRODUCER_ITEM_VA(wq->ring,
 895                                                       struct oce_nic_frag_wqe);
 896                         nicfrag->u0.dw[0] = 0;
 897                         nicfrag->u0.dw[1] = 0;
 898                         nicfrag->u0.dw[2] = 0;
 899                         nicfrag->u0.dw[3] = 0;
 900                         pd->wqe_idx = wq->ring->pidx;
 901                         RING_PUT(wq->ring, 1);
 902                         atomic_add_int(&wq->ring->num_used, 1);
 903                         pd->nsegs++;
 904                 }
 905
 906                 sc->ifp->if_opackets++;
 907                 wq->tx_stats.tx_reqs++;
 908                 wq->tx_stats.tx_wrbs += num_wqes;
 909                 wq->tx_stats.tx_bytes += m->m_pkthdr.len;
 910                 wq->tx_stats.tx_pkts++;
 911
 912                 bus_dmamap_sync(wq->ring->dma.tag, wq->ring->dma.map,
 913                                 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 914                 reg_value = (num_wqes << 16) | wq->wq_id;
 915                 OCE_WRITE_REG32(sc, db, wq->db_offset, reg_value);
 916
 917         } else if (rc == EFBIG) {
 918                 if (retry_cnt == 0) {
 919                         m_temp = m_defrag(m, M_NOWAIT);
 920                         if (m_temp == NULL)
 921                                 goto free_ret;
 922                         m = m_temp;
 923                         *mpp = m_temp;
 924                         retry_cnt = retry_cnt + 1;
 925                         goto retry;
 926                 } else
 927                         goto free_ret;
 928         } else if (rc == ENOMEM)
 929                 return rc;
 930         else
 931                 goto free_ret;
 932
 933         return 0;
 934
 935 free_ret:
 936         m_freem(*mpp);
 937         *mpp = NULL;
 938         return rc;
 939 }
 940
 941
 942 static void
 943 oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx, uint32_t status)
 944 {
 945         struct oce_packet_desc *pd;
 946         POCE_SOFTC sc = (POCE_SOFTC) wq->parent;
 947         struct mbuf *m;
 948
 949         pd = &wq->pckts[wq->pkt_desc_tail];
 950         atomic_store_rel_int(&wq->pkt_desc_tail,
 951                              (wq->pkt_desc_tail + 1) % OCE_WQ_PACKET_ARRAY_SIZE);
 952         atomic_subtract_int(&wq->ring->num_used, pd->nsegs + 1);
 953         bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
 954         bus_dmamap_unload(wq->tag, pd->map);
 955
 956         m = pd->mbuf;
 957         m_freem(m);
 958         pd->mbuf = NULL;
 959
 960
 961         if (sc->ifp->if_drv_flags & IFF_DRV_OACTIVE) {
 962                 if (wq->ring->num_used < (wq->ring->num_items / 2)) {
 963                         sc->ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE);
 964                         oce_tx_restart(sc, wq);
 965                 }
 966         }
 967 }
 968
 969
 970 static void
 971 oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq)
 972 {
 973
 974         if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != IFF_DRV_RUNNING)
 975                 return;
 976
 977 #if __FreeBSD_version >= 800000
 978         if (!drbr_empty(sc->ifp, wq->br))
 979 #else
 980         if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd))
 981 #endif
 982                 taskqueue_enqueue_fast(taskqueue_swi, &wq->txtask);
 983
 984 }
 985
 986
 987 #if defined(INET6) || defined(INET)
 988 static struct mbuf *
 989 oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp)
 990 {
 991         struct mbuf *m;
 992 #ifdef INET
 993         struct ip *ip;
 994 #endif
 995 #ifdef INET6
 996         struct ip6_hdr *ip6;
 997 #endif
 998         struct ether_vlan_header *eh;
 999         struct tcphdr *th;
1000         uint16_t etype;
1001         int total_len = 0, ehdrlen = 0;
1002
1003         m = *mpp;
1004
1005         if (M_WRITABLE(m) == 0) {
1006                 m = m_dup(*mpp, M_NOWAIT);
1007                 if (!m)
1008                         return NULL;
1009                 m_freem(*mpp);
1010                 *mpp = m;
1011         }
1012
1013         eh = mtod(m, struct ether_vlan_header *);
1014         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1015                 etype = ntohs(eh->evl_proto);
1016                 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1017         } else {
1018                 etype = ntohs(eh->evl_encap_proto);
1019                 ehdrlen = ETHER_HDR_LEN;
1020         }
1021
1022         switch (etype) {
1023 #ifdef INET
1024         case ETHERTYPE_IP:
1025                 ip = (struct ip *)(m->m_data + ehdrlen);
1026                 if (ip->ip_p != IPPROTO_TCP)
1027                         return NULL;
1028                 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
1029
1030                 total_len = ehdrlen + (ip->ip_hl << 2) + (th->th_off << 2);
1031                 break;
1032 #endif
1033 #ifdef INET6
1034         case ETHERTYPE_IPV6:
1035                 ip6 = (struct ip6_hdr *)(m->m_data + ehdrlen);
1036                 if (ip6->ip6_nxt != IPPROTO_TCP)
1037                         return NULL;
1038                 th = (struct tcphdr *)((caddr_t)ip6 + sizeof(struct ip6_hdr));
1039
1040                 total_len = ehdrlen + sizeof(struct ip6_hdr) + (th->th_off << 2);
1041                 break;
1042 #endif
1043         default:
1044                 return NULL;
1045         }
1046
1047         m = m_pullup(m, total_len);
1048         if (!m)
1049                 return NULL;
1050         *mpp = m;
1051         return m;
1052
1053 }
1054 #endif /* INET6 || INET */
1055
1056 void
1057 oce_tx_task(void *arg, int npending)
1058 {
1059         struct oce_wq *wq = arg;
1060         POCE_SOFTC sc = wq->parent;
1061         struct ifnet *ifp = sc->ifp;
1062         int rc = 0;
1063
1064 #if __FreeBSD_version >= 800000
1065         LOCK(&wq->tx_lock);
1066         rc = oce_multiq_transmit(ifp, NULL, wq);
1067         if (rc) {
1068                 device_printf(sc->dev,
1069                                 "TX[%d] restart failed\n", wq->queue_index);
1070         }
1071         UNLOCK(&wq->tx_lock);
1072 #else
1073         oce_start(ifp);
1074 #endif
1075
1076 }
1077
1078
1079 void
1080 oce_start(struct ifnet *ifp)
1081 {
1082         POCE_SOFTC sc = ifp->if_softc;
1083         struct mbuf *m;
1084         int rc = 0;
1085         int def_q = 0; /* Defualt tx queue is 0*/
1086
1087         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1088                         IFF_DRV_RUNNING)
1089                 return;
1090
1091         if (!sc->link_status)
1092                 return;
1093
1094         do {
1095                 IF_DEQUEUE(&sc->ifp->if_snd, m);
1096                 if (m == NULL)
1097                         break;
1098
1099                 LOCK(&sc->wq[def_q]->tx_lock);
1100                 rc = oce_tx(sc, &m, def_q);
1101                 UNLOCK(&sc->wq[def_q]->tx_lock);
1102                 if (rc) {
1103                         if (m != NULL) {
1104                                 sc->wq[def_q]->tx_stats.tx_stops ++;
1105                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1106                                 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1107                                 m = NULL;
1108                         }
1109                         break;
1110                 }
1111                 if (m != NULL)
1112                         ETHER_BPF_MTAP(ifp, m);
1113
1114         } while (TRUE);
1115
1116         return;
1117 }
1118
1119
1120 /* Handle the Completion Queue for transmit */
1121 uint16_t
1122 oce_wq_handler(void *arg)
1123 {
1124         struct oce_wq *wq = (struct oce_wq *)arg;
1125         POCE_SOFTC sc = wq->parent;
1126         struct oce_cq *cq = wq->cq;
1127         struct oce_nic_tx_cqe *cqe;
1128         int num_cqes = 0;
1129
1130         bus_dmamap_sync(cq->ring->dma.tag,
1131                         cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1132         cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1133         while (cqe->u0.dw[3]) {
1134                 DW_SWAP((uint32_t *) cqe, sizeof(oce_wq_cqe));
1135
1136                 wq->ring->cidx = cqe->u0.s.wqe_index + 1;
1137                 if (wq->ring->cidx >= wq->ring->num_items)
1138                         wq->ring->cidx -= wq->ring->num_items;
1139
1140                 oce_tx_complete(wq, cqe->u0.s.wqe_index, cqe->u0.s.status);
1141                 wq->tx_stats.tx_compl++;
1142                 cqe->u0.dw[3] = 0;
1143                 RING_GET(cq->ring, 1);
1144                 bus_dmamap_sync(cq->ring->dma.tag,
1145                                 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1146                 cqe =
1147                     RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1148                 num_cqes++;
1149         }
1150
1151         if (num_cqes)
1152                 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
1153
1154         return 0;
1155 }
1156
1157
1158 static int
1159 oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq)
1160 {
1161         POCE_SOFTC sc = ifp->if_softc;
1162         int status = 0, queue_index = 0;
1163         struct mbuf *next = NULL;
1164         struct buf_ring *br = NULL;
1165
1166         br  = wq->br;
1167         queue_index = wq->queue_index;
1168
1169         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1170                 IFF_DRV_RUNNING) {
1171                 if (m != NULL)
1172                         status = drbr_enqueue(ifp, br, m);
1173                 return status;
1174         }
1175
1176         if (m == NULL)
1177                 next = drbr_dequeue(ifp, br);
1178         else if (drbr_needs_enqueue(ifp, br)) {
1179                 if ((status = drbr_enqueue(ifp, br, m)) != 0)
1180                         return status;
1181                 next = drbr_dequeue(ifp, br);
1182         } else
1183                 next = m;
1184
1185         while (next != NULL) {
1186                 if (oce_tx(sc, &next, queue_index)) {
1187                         if (next != NULL) {
1188                                 wq->tx_stats.tx_stops ++;
1189                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1190                                 status = drbr_enqueue(ifp, br, next);
1191                         }
1192                         break;
1193                 }
1194                 ifp->if_obytes += next->m_pkthdr.len;
1195                 if (next->m_flags & M_MCAST)
1196                         ifp->if_omcasts++;
1197                 ETHER_BPF_MTAP(ifp, next);
1198                 next = drbr_dequeue(ifp, br);
1199         }
1200
1201         return status;
1202 }
1203
1204
1205
1206
1207 /*****************************************************************************
1208  *                          Receive  routines functions                      *
1209  *****************************************************************************/
1210
1211 static void
1212 oce_rx(struct oce_rq *rq, uint32_t rqe_idx, struct oce_nic_rx_cqe *cqe)
1213 {
1214         uint32_t out;
1215         struct oce_packet_desc *pd;
1216         POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1217         int i, len, frag_len;
1218         struct mbuf *m = NULL, *tail = NULL;
1219         uint16_t vtag;
1220
1221         len = cqe->u0.s.pkt_size;
1222         if (!len) {
1223                 /*partial DMA workaround for Lancer*/
1224                 oce_discard_rx_comp(rq, cqe);
1225                 goto exit;
1226         }
1227
1228          /* Get vlan_tag value */
1229         if(IS_BE(sc) || IS_SH(sc))
1230                 vtag = BSWAP_16(cqe->u0.s.vlan_tag);
1231         else
1232                 vtag = cqe->u0.s.vlan_tag;
1233
1234
1235         for (i = 0; i < cqe->u0.s.num_fragments; i++) {
1236
1237                 if (rq->packets_out == rq->packets_in) {
1238                         device_printf(sc->dev,
1239                                   "RQ transmit descriptor missing\n");
1240                 }
1241                 out = rq->packets_out + 1;
1242                 if (out == OCE_RQ_PACKET_ARRAY_SIZE)
1243                         out = 0;
1244                 pd = &rq->pckts[rq->packets_out];
1245                 rq->packets_out = out;
1246
1247                 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1248                 bus_dmamap_unload(rq->tag, pd->map);
1249                 rq->pending--;
1250
1251                 frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len;
1252                 pd->mbuf->m_len = frag_len;
1253
1254                 if (tail != NULL) {
1255                         /* additional fragments */
1256                         pd->mbuf->m_flags &= ~M_PKTHDR;
1257                         tail->m_next = pd->mbuf;
1258                         tail = pd->mbuf;
1259                 } else {
1260                         /* first fragment, fill out much of the packet header */
1261                         pd->mbuf->m_pkthdr.len = len;
1262                         pd->mbuf->m_pkthdr.csum_flags = 0;
1263                         if (IF_CSUM_ENABLED(sc)) {
1264                                 if (cqe->u0.s.l4_cksum_pass) {
1265                                         pd->mbuf->m_pkthdr.csum_flags |=
1266                                             (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1267                                         pd->mbuf->m_pkthdr.csum_data = 0xffff;
1268                                 }
1269                                 if (cqe->u0.s.ip_cksum_pass) {
1270                                         if (!cqe->u0.s.ip_ver) { /* IPV4 */
1271                                                 pd->mbuf->m_pkthdr.csum_flags |=
1272                                                 (CSUM_IP_CHECKED|CSUM_IP_VALID);
1273                                         }
1274                                 }
1275                         }
1276                         m = tail = pd->mbuf;
1277                 }
1278                 pd->mbuf = NULL;
1279                 len -= frag_len;
1280         }
1281
1282         if (m) {
1283                 if (!oce_cqe_portid_valid(sc, cqe)) {
1284                          m_freem(m);
1285                          goto exit;
1286                 }
1287
1288                 m->m_pkthdr.rcvif = sc->ifp;
1289 #if __FreeBSD_version >= 800000
1290                 if (rq->queue_index)
1291                         m->m_pkthdr.flowid = (rq->queue_index - 1);
1292                 else
1293                         m->m_pkthdr.flowid = rq->queue_index;
1294                 m->m_flags |= M_FLOWID;
1295 #endif
1296                 /* This deternies if vlan tag is Valid */
1297                 if (oce_cqe_vtp_valid(sc, cqe)) {
1298                         if (sc->function_mode & FNM_FLEX10_MODE) {
1299                                 /* FLEX10. If QnQ is not set, neglect VLAN */
1300                                 if (cqe->u0.s.qnq) {
1301                                         m->m_pkthdr.ether_vtag = vtag;
1302                                         m->m_flags |= M_VLANTAG;
1303                                 }
1304                         } else if (sc->pvid != (vtag & VLAN_VID_MASK))  {
1305                                 /* In UMC mode generally pvid will be striped by
1306                                    hw. But in some cases we have seen it comes
1307                                    with pvid. So if pvid == vlan, neglect vlan.
1308                                 */
1309                                 m->m_pkthdr.ether_vtag = vtag;
1310                                 m->m_flags |= M_VLANTAG;
1311                         }
1312                 }
1313
1314                 sc->ifp->if_ipackets++;
1315 #if defined(INET6) || defined(INET)
1316                 /* Try to queue to LRO */
1317                 if (IF_LRO_ENABLED(sc) &&
1318                     (cqe->u0.s.ip_cksum_pass) &&
1319                     (cqe->u0.s.l4_cksum_pass) &&
1320                     (!cqe->u0.s.ip_ver)       &&
1321                     (rq->lro.lro_cnt != 0)) {
1322
1323                         if (tcp_lro_rx(&rq->lro, m, 0) == 0) {
1324                                 rq->lro_pkts_queued ++;
1325                                 goto post_done;
1326                         }
1327                         /* If LRO posting fails then try to post to STACK */
1328                 }
1329 #endif
1330
1331                 (*sc->ifp->if_input) (sc->ifp, m);
1332 #if defined(INET6) || defined(INET)
1333 post_done:
1334 #endif
1335                 /* Update rx stats per queue */
1336                 rq->rx_stats.rx_pkts++;
1337                 rq->rx_stats.rx_bytes += cqe->u0.s.pkt_size;
1338                 rq->rx_stats.rx_frags += cqe->u0.s.num_fragments;
1339                 if (cqe->u0.s.pkt_type == OCE_MULTICAST_PACKET)
1340                         rq->rx_stats.rx_mcast_pkts++;
1341                 if (cqe->u0.s.pkt_type == OCE_UNICAST_PACKET)
1342                         rq->rx_stats.rx_ucast_pkts++;
1343         }
1344 exit:
1345         return;
1346 }
1347
1348
1349 static void
1350 oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe)
1351 {
1352         uint32_t out, i = 0;
1353         struct oce_packet_desc *pd;
1354         POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1355         int num_frags = cqe->u0.s.num_fragments;
1356
1357         for (i = 0; i < num_frags; i++) {
1358                 if (rq->packets_out == rq->packets_in) {
1359                         device_printf(sc->dev,
1360                                 "RQ transmit descriptor missing\n");
1361                 }
1362                 out = rq->packets_out + 1;
1363                 if (out == OCE_RQ_PACKET_ARRAY_SIZE)
1364                         out = 0;
1365                 pd = &rq->pckts[rq->packets_out];
1366                 rq->packets_out = out;
1367
1368                 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1369                 bus_dmamap_unload(rq->tag, pd->map);
1370                 rq->pending--;
1371                 m_freem(pd->mbuf);
1372         }
1373
1374 }
1375
1376
1377 static int
1378 oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1379 {
1380         struct oce_nic_rx_cqe_v1 *cqe_v1;
1381         int vtp = 0;
1382
1383         if (sc->be3_native) {
1384                 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1385                 vtp =  cqe_v1->u0.s.vlan_tag_present;
1386         } else
1387                 vtp = cqe->u0.s.vlan_tag_present;
1388
1389         return vtp;
1390
1391 }
1392
1393
1394 static int
1395 oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1396 {
1397         struct oce_nic_rx_cqe_v1 *cqe_v1;
1398         int port_id = 0;
1399
1400         if (sc->be3_native && (IS_BE(sc) || IS_SH(sc))) {
1401                 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1402                 port_id =  cqe_v1->u0.s.port;
1403                 if (sc->port_id != port_id)
1404                         return 0;
1405         } else
1406                 ;/* For BE3 legacy and Lancer this is dummy */
1407
1408         return 1;
1409
1410 }
1411
1412 #if defined(INET6) || defined(INET)
1413 static void
1414 oce_rx_flush_lro(struct oce_rq *rq)
1415 {
1416         struct lro_ctrl *lro = &rq->lro;
1417         struct lro_entry *queued;
1418         POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1419
1420         if (!IF_LRO_ENABLED(sc))
1421                 return;
1422
1423         while ((queued = SLIST_FIRST(&lro->lro_active)) != NULL) {
1424                 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1425                 tcp_lro_flush(lro, queued);
1426         }
1427         rq->lro_pkts_queued = 0;
1428
1429         return;
1430 }
1431
1432
1433 static int
1434 oce_init_lro(POCE_SOFTC sc)
1435 {
1436         struct lro_ctrl *lro = NULL;
1437         int i = 0, rc = 0;
1438
1439         for (i = 0; i < sc->nrqs; i++) {
1440                 lro = &sc->rq[i]->lro;
1441                 rc = tcp_lro_init(lro);
1442                 if (rc != 0) {
1443                         device_printf(sc->dev, "LRO init failed\n");
1444                         return rc;
1445                 }
1446                 lro->ifp = sc->ifp;
1447         }
1448
1449         return rc;
1450 }
1451
1452
1453 void
1454 oce_free_lro(POCE_SOFTC sc)
1455 {
1456         struct lro_ctrl *lro = NULL;
1457         int i = 0;
1458
1459         for (i = 0; i < sc->nrqs; i++) {
1460                 lro = &sc->rq[i]->lro;
1461                 if (lro)
1462                         tcp_lro_free(lro);
1463         }
1464 }
1465 #endif
1466
1467 int
1468 oce_alloc_rx_bufs(struct oce_rq *rq, int count)
1469 {
1470         POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1471         int i, in, rc;
1472         struct oce_packet_desc *pd;
1473         bus_dma_segment_t segs[6];
1474         int nsegs, added = 0;
1475         struct oce_nic_rqe *rqe;
1476         pd_rxulp_db_t rxdb_reg;
1477
1478         bzero(&rxdb_reg, sizeof(pd_rxulp_db_t));
1479         for (i = 0; i < count; i++) {
1480                 in = rq->packets_in + 1;
1481                 if (in == OCE_RQ_PACKET_ARRAY_SIZE)
1482                         in = 0;
1483                 if (in == rq->packets_out)
1484                         break;  /* no more room */
1485
1486                 pd = &rq->pckts[rq->packets_in];
1487                 pd->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1488                 if (pd->mbuf == NULL)
1489                         break;
1490
1491                 pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = MCLBYTES;
1492                 rc = bus_dmamap_load_mbuf_sg(rq->tag,
1493                                              pd->map,
1494                                              pd->mbuf,
1495                                              segs, &nsegs, BUS_DMA_NOWAIT);
1496                 if (rc) {
1497                         m_free(pd->mbuf);
1498                         break;
1499                 }
1500
1501                 if (nsegs != 1) {
1502                         i--;
1503                         continue;
1504                 }
1505
1506                 rq->packets_in = in;
1507                 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_PREREAD);
1508
1509                 rqe = RING_GET_PRODUCER_ITEM_VA(rq->ring, struct oce_nic_rqe);
1510                 rqe->u0.s.frag_pa_hi = ADDR_HI(segs[0].ds_addr);
1511                 rqe->u0.s.frag_pa_lo = ADDR_LO(segs[0].ds_addr);
1512                 DW_SWAP(u32ptr(rqe), sizeof(struct oce_nic_rqe));
1513                 RING_PUT(rq->ring, 1);
1514                 added++;
1515                 rq->pending++;
1516         }
1517         if (added != 0) {
1518                 for (i = added / OCE_MAX_RQ_POSTS; i > 0; i--) {
1519                         rxdb_reg.bits.num_posted = OCE_MAX_RQ_POSTS;
1520                         rxdb_reg.bits.qid = rq->rq_id;
1521                         OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1522                         added -= OCE_MAX_RQ_POSTS;
1523                 }
1524                 if (added > 0) {
1525                         rxdb_reg.bits.qid = rq->rq_id;
1526                         rxdb_reg.bits.num_posted = added;
1527                         OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1528                 }
1529         }
1530
1531         return 0;
1532 }
1533
1534
1535 /* Handle the Completion Queue for receive */
1536 uint16_t
1537 oce_rq_handler(void *arg)
1538 {
1539         struct oce_rq *rq = (struct oce_rq *)arg;
1540         struct oce_cq *cq = rq->cq;
1541         POCE_SOFTC sc = rq->parent;
1542         struct oce_nic_rx_cqe *cqe;
1543         int num_cqes = 0, rq_buffers_used = 0;
1544
1545
1546         bus_dmamap_sync(cq->ring->dma.tag,
1547                         cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1548         cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
1549         while (cqe->u0.dw[2]) {
1550                 DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe));
1551
1552                 RING_GET(rq->ring, 1);
1553                 if (cqe->u0.s.error == 0) {
1554                         oce_rx(rq, cqe->u0.s.frag_index, cqe);
1555                 } else {
1556                         rq->rx_stats.rxcp_err++;
1557                         sc->ifp->if_ierrors++;
1558                         /* Post L3/L4 errors to stack.*/
1559                         oce_rx(rq, cqe->u0.s.frag_index, cqe);
1560                 }
1561                 rq->rx_stats.rx_compl++;
1562                 cqe->u0.dw[2] = 0;
1563
1564 #if defined(INET6) || defined(INET)
1565                 if (IF_LRO_ENABLED(sc) && rq->lro_pkts_queued >= 16) {
1566                         oce_rx_flush_lro(rq);
1567                 }
1568 #endif
1569
1570                 RING_GET(cq->ring, 1);
1571                 bus_dmamap_sync(cq->ring->dma.tag,
1572                                 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1573                 cqe =
1574                     RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
1575                 num_cqes++;
1576                 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
1577                         break;
1578         }
1579
1580 #if defined(INET6) || defined(INET)
1581         if (IF_LRO_ENABLED(sc))
1582                 oce_rx_flush_lro(rq);
1583 #endif
1584
1585         if (num_cqes) {
1586                 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
1587                 rq_buffers_used = OCE_RQ_PACKET_ARRAY_SIZE - rq->pending;
1588                 if (rq_buffers_used > 1)
1589                         oce_alloc_rx_bufs(rq, (rq_buffers_used - 1));
1590         }
1591
1592         return 0;
1593
1594 }
1595
1596
1597
1598
1599 /*****************************************************************************
1600  *                 Helper function prototypes in this file                   *
1601  *****************************************************************************/
1602
1603 static int
1604 oce_attach_ifp(POCE_SOFTC sc)
1605 {
1606
1607         sc->ifp = if_alloc(IFT_ETHER);
1608         if (!sc->ifp)
1609                 return ENOMEM;
1610
1611         ifmedia_init(&sc->media, IFM_IMASK, oce_media_change, oce_media_status);
1612         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1613         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1614
1615         sc->ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST;
1616         sc->ifp->if_ioctl = oce_ioctl;
1617         sc->ifp->if_start = oce_start;
1618         sc->ifp->if_init = oce_init;
1619         sc->ifp->if_mtu = ETHERMTU;
1620         sc->ifp->if_softc = sc;
1621 #if __FreeBSD_version >= 800000
1622         sc->ifp->if_transmit = oce_multiq_start;
1623         sc->ifp->if_qflush = oce_multiq_flush;
1624 #endif
1625
1626         if_initname(sc->ifp,
1627                     device_get_name(sc->dev), device_get_unit(sc->dev));
1628
1629         sc->ifp->if_snd.ifq_drv_maxlen = OCE_MAX_TX_DESC - 1;
1630         IFQ_SET_MAXLEN(&sc->ifp->if_snd, sc->ifp->if_snd.ifq_drv_maxlen);
1631         IFQ_SET_READY(&sc->ifp->if_snd);
1632
1633         sc->ifp->if_hwassist = OCE_IF_HWASSIST;
1634         sc->ifp->if_hwassist |= CSUM_TSO;
1635         sc->ifp->if_hwassist |= (CSUM_IP | CSUM_TCP | CSUM_UDP);
1636
1637         sc->ifp->if_capabilities = OCE_IF_CAPABILITIES;
1638         sc->ifp->if_capabilities |= IFCAP_HWCSUM;
1639         sc->ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
1640
1641 #if defined(INET6) || defined(INET)
1642         sc->ifp->if_capabilities |= IFCAP_TSO;
1643         sc->ifp->if_capabilities |= IFCAP_LRO;
1644         sc->ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
1645 #endif
1646
1647         sc->ifp->if_capenable = sc->ifp->if_capabilities;
1648         sc->ifp->if_baudrate = IF_Gbps(10UL);
1649
1650         ether_ifattach(sc->ifp, sc->macaddr.mac_addr);
1651
1652         return 0;
1653 }
1654
1655
1656 static void
1657 oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag)
1658 {
1659         POCE_SOFTC sc = ifp->if_softc;
1660
1661         if (ifp->if_softc !=  arg)
1662                 return;
1663         if ((vtag == 0) || (vtag > 4095))
1664                 return;
1665
1666         sc->vlan_tag[vtag] = 1;
1667         sc->vlans_added++;
1668         oce_vid_config(sc);
1669 }
1670
1671
1672 static void
1673 oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag)
1674 {
1675         POCE_SOFTC sc = ifp->if_softc;
1676
1677         if (ifp->if_softc !=  arg)
1678                 return;
1679         if ((vtag == 0) || (vtag > 4095))
1680                 return;
1681
1682         sc->vlan_tag[vtag] = 0;
1683         sc->vlans_added--;
1684         oce_vid_config(sc);
1685 }
1686
1687
1688 /*
1689  * A max of 64 vlans can be configured in BE. If the user configures
1690  * more, place the card in vlan promiscuous mode.
1691  */
1692 static int
1693 oce_vid_config(POCE_SOFTC sc)
1694 {
1695         struct normal_vlan vtags[MAX_VLANFILTER_SIZE];
1696         uint16_t ntags = 0, i;
1697         int status = 0;
1698
1699         if ((sc->vlans_added <= MAX_VLANFILTER_SIZE) &&
1700                         (sc->ifp->if_capenable & IFCAP_VLAN_HWFILTER)) {
1701                 for (i = 0; i < MAX_VLANS; i++) {
1702                         if (sc->vlan_tag[i]) {
1703                                 vtags[ntags].vtag = i;
1704                                 ntags++;
1705                         }
1706                 }
1707                 if (ntags)
1708                         status = oce_config_vlan(sc, (uint8_t) sc->if_id,
1709                                                 vtags, ntags, 1, 0);
1710         } else
1711                 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
1712                                                 NULL, 0, 1, 1);
1713         return status;
1714 }
1715
1716
1717 static void
1718 oce_mac_addr_set(POCE_SOFTC sc)
1719 {
1720         uint32_t old_pmac_id = sc->pmac_id;
1721         int status = 0;
1722
1723
1724         status = bcmp((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr,
1725                          sc->macaddr.size_of_struct);
1726         if (!status)
1727                 return;
1728
1729         status = oce_mbox_macaddr_add(sc, (uint8_t *)(IF_LLADDR(sc->ifp)),
1730                                         sc->if_id, &sc->pmac_id);
1731         if (!status) {
1732                 status = oce_mbox_macaddr_del(sc, sc->if_id, old_pmac_id);
1733                 bcopy((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr,
1734                                  sc->macaddr.size_of_struct);
1735         }
1736         if (status)
1737                 device_printf(sc->dev, "Failed update macaddress\n");
1738
1739 }
1740
1741
1742 static int
1743 oce_handle_passthrough(struct ifnet *ifp, caddr_t data)
1744 {
1745         POCE_SOFTC sc = ifp->if_softc;
1746         struct ifreq *ifr = (struct ifreq *)data;
1747         int rc = ENXIO;
1748         char cookie[32] = {0};
1749         void *priv_data = (void *)ifr->ifr_data;
1750         void *ioctl_ptr;
1751         uint32_t req_size;
1752         struct mbx_hdr req;
1753         OCE_DMA_MEM dma_mem;
1754         struct mbx_common_get_cntl_attr *fw_cmd;
1755
1756         if (copyin(priv_data, cookie, strlen(IOCTL_COOKIE)))
1757                 return EFAULT;
1758
1759         if (memcmp(cookie, IOCTL_COOKIE, strlen(IOCTL_COOKIE)))
1760                 return EINVAL;
1761
1762         ioctl_ptr = (char *)priv_data + strlen(IOCTL_COOKIE);
1763         if (copyin(ioctl_ptr, &req, sizeof(struct mbx_hdr)))
1764                 return EFAULT;
1765
1766         req_size = le32toh(req.u0.req.request_length);
1767         if (req_size > 65536)
1768                 return EINVAL;
1769
1770         req_size += sizeof(struct mbx_hdr);
1771         rc = oce_dma_alloc(sc, req_size, &dma_mem, 0);
1772         if (rc)
1773                 return ENOMEM;
1774
1775         if (copyin(ioctl_ptr, OCE_DMAPTR(&dma_mem,char), req_size)) {
1776                 rc = EFAULT;
1777                 goto dma_free;
1778         }
1779
1780         rc = oce_pass_through_mbox(sc, &dma_mem, req_size);
1781         if (rc) {
1782                 rc = EIO;
1783                 goto dma_free;
1784         }
1785
1786         if (copyout(OCE_DMAPTR(&dma_mem,char), ioctl_ptr, req_size))
1787                 rc =  EFAULT;
1788
1789         /*
1790            firmware is filling all the attributes for this ioctl except
1791            the driver version..so fill it
1792          */
1793         if(req.u0.rsp.opcode == OPCODE_COMMON_GET_CNTL_ATTRIBUTES) {
1794                 fw_cmd = (struct mbx_common_get_cntl_attr *) ioctl_ptr;
1795                 strncpy(fw_cmd->params.rsp.cntl_attr_info.hba_attr.drv_ver_str,
1796                         COMPONENT_REVISION, strlen(COMPONENT_REVISION));
1797         }
1798
1799 dma_free:
1800         oce_dma_free(sc, &dma_mem);
1801         return rc;
1802
1803 }
1804
1805 static void
1806 oce_eqd_set_periodic(POCE_SOFTC sc)
1807 {
1808         struct oce_set_eqd set_eqd[OCE_MAX_EQ];
1809         struct oce_aic_obj *aic;
1810         struct oce_eq *eqo;
1811         uint64_t now = 0, delta;
1812         int eqd, i, num = 0;
1813         uint32_t ips = 0;
1814         int tps;
1815
1816         for (i = 0 ; i < sc->neqs; i++) {
1817                 eqo = sc->eq[i];
1818                 aic = &sc->aic_obj[i];
1819                 /* When setting the static eq delay from the user space */
1820                 if (!aic->enable) {
1821                         eqd = aic->et_eqd;
1822                         goto modify_eqd;
1823                 }
1824
1825                 now = ticks;
1826
1827                 /* Over flow check */
1828                 if ((now < aic->ticks) || (eqo->intr < aic->intr_prev))
1829                         goto done;
1830
1831                 delta = now - aic->ticks;
1832                 tps = delta/hz;
1833
1834                 /* Interrupt rate based on elapsed ticks */
1835                 if(tps)
1836                         ips = (uint32_t)(eqo->intr - aic->intr_prev) / tps;
1837
1838                 if (ips > INTR_RATE_HWM)
1839                         eqd = aic->cur_eqd + 20;
1840                 else if (ips < INTR_RATE_LWM)
1841                         eqd = aic->cur_eqd / 2;
1842                 else
1843                         goto done;
1844
1845                 if (eqd < 10)
1846                         eqd = 0;
1847
1848                 /* Make sure that the eq delay is in the known range */
1849                 eqd = min(eqd, aic->max_eqd);
1850                 eqd = max(eqd, aic->min_eqd);
1851
1852 modify_eqd:
1853                 if (eqd != aic->cur_eqd) {
1854                         set_eqd[num].delay_multiplier = (eqd * 65)/100;
1855                         set_eqd[num].eq_id = eqo->eq_id;
1856                         aic->cur_eqd = eqd;
1857                         num++;
1858                 }
1859 done:
1860                 aic->intr_prev = eqo->intr;
1861                 aic->ticks = now;
1862         }
1863
1864         /* Is there atleast one eq that needs to be modified? */
1865         if(num)
1866                 oce_mbox_eqd_modify_periodic(sc, set_eqd, num);
1867
1868 }
1869
1870 static void
1871 oce_local_timer(void *arg)
1872 {
1873         POCE_SOFTC sc = arg;
1874         int i = 0;
1875
1876         oce_refresh_nic_stats(sc);
1877         oce_refresh_queue_stats(sc);
1878         oce_mac_addr_set(sc);
1879
1880         /* TX Watch Dog*/
1881         for (i = 0; i < sc->nwqs; i++)
1882                 oce_tx_restart(sc, sc->wq[i]);
1883
1884         /* calculate and set the eq delay for optimal interrupt rate */
1885         if (IS_BE(sc) || IS_SH(sc))
1886                 oce_eqd_set_periodic(sc);
1887
1888         callout_reset(&sc->timer, hz, oce_local_timer, sc);
1889 }
1890
1891
1892 /* NOTE : This should only be called holding
1893  *        DEVICE_LOCK.
1894 */
1895 static void
1896 oce_if_deactivate(POCE_SOFTC sc)
1897 {
1898         int i, mtime = 0;
1899         int wait_req = 0;
1900         struct oce_rq *rq;
1901         struct oce_wq *wq;
1902         struct oce_eq *eq;
1903
1904         sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1905
1906         /*Wait for max of 400ms for TX completions to be done */
1907         while (mtime < 400) {
1908                 wait_req = 0;
1909                 for_all_wq_queues(sc, wq, i) {
1910                         if (wq->ring->num_used) {
1911                                 wait_req = 1;
1912                                 DELAY(1);
1913                                 break;
1914                         }
1915                 }
1916                 mtime += 1;
1917                 if (!wait_req)
1918                         break;
1919         }
1920
1921         /* Stop intrs and finish any bottom halves pending */
1922         oce_hw_intr_disable(sc);
1923
1924         /* Since taskqueue_drain takes a Gaint Lock, We should not acquire
1925            any other lock. So unlock device lock and require after
1926            completing taskqueue_drain.
1927         */
1928         UNLOCK(&sc->dev_lock);
1929         for (i = 0; i < sc->intr_count; i++) {
1930                 if (sc->intrs[i].tq != NULL) {
1931                         taskqueue_drain(sc->intrs[i].tq, &sc->intrs[i].task);
1932                 }
1933         }
1934         LOCK(&sc->dev_lock);
1935
1936         /* Delete RX queue in card with flush param */
1937         oce_stop_rx(sc);
1938
1939         /* Invalidate any pending cq and eq entries*/
1940         for_all_evnt_queues(sc, eq, i)
1941                 oce_drain_eq(eq);
1942         for_all_rq_queues(sc, rq, i)
1943                 oce_drain_rq_cq(rq);
1944         for_all_wq_queues(sc, wq, i)
1945                 oce_drain_wq_cq(wq);
1946
1947         /* But still we need to get MCC aync events.
1948            So enable intrs and also arm first EQ
1949         */
1950         oce_hw_intr_enable(sc);
1951         oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
1952
1953         DELAY(10);
1954 }
1955
1956
1957 static void
1958 oce_if_activate(POCE_SOFTC sc)
1959 {
1960         struct oce_eq *eq;
1961         struct oce_rq *rq;
1962         struct oce_wq *wq;
1963         int i, rc = 0;
1964
1965         sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
1966
1967         oce_hw_intr_disable(sc);
1968
1969         oce_start_rx(sc);
1970
1971         for_all_rq_queues(sc, rq, i) {
1972                 rc = oce_start_rq(rq);
1973                 if (rc)
1974                         device_printf(sc->dev, "Unable to start RX\n");
1975         }
1976
1977         for_all_wq_queues(sc, wq, i) {
1978                 rc = oce_start_wq(wq);
1979                 if (rc)
1980                         device_printf(sc->dev, "Unable to start TX\n");
1981         }
1982
1983
1984         for_all_evnt_queues(sc, eq, i)
1985                 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
1986
1987         oce_hw_intr_enable(sc);
1988
1989 }
1990
1991 static void
1992 process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe)
1993 {
1994         /* Update Link status */
1995         if ((acqe->u0.s.link_status & ~ASYNC_EVENT_LOGICAL) ==
1996              ASYNC_EVENT_LINK_UP) {
1997                 sc->link_status = ASYNC_EVENT_LINK_UP;
1998                 if_link_state_change(sc->ifp, LINK_STATE_UP);
1999         } else {
2000                 sc->link_status = ASYNC_EVENT_LINK_DOWN;
2001                 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
2002         }
2003
2004         /* Update speed */
2005         sc->link_speed = acqe->u0.s.speed;
2006         sc->qos_link_speed = (uint32_t) acqe->u0.s.qos_link_speed * 10;
2007
2008 }
2009
2010
2011 /* Handle the Completion Queue for the Mailbox/Async notifications */
2012 uint16_t
2013 oce_mq_handler(void *arg)
2014 {
2015         struct oce_mq *mq = (struct oce_mq *)arg;
2016         POCE_SOFTC sc = mq->parent;
2017         struct oce_cq *cq = mq->cq;
2018         int num_cqes = 0, evt_type = 0, optype = 0;
2019         struct oce_mq_cqe *cqe;
2020         struct oce_async_cqe_link_state *acqe;
2021         struct oce_async_event_grp5_pvid_state *gcqe;
2022         struct oce_async_event_qnq *dbgcqe;
2023
2024
2025         bus_dmamap_sync(cq->ring->dma.tag,
2026                         cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2027         cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2028
2029         while (cqe->u0.dw[3]) {
2030                 DW_SWAP((uint32_t *) cqe, sizeof(oce_mq_cqe));
2031                 if (cqe->u0.s.async_event) {
2032                         evt_type = cqe->u0.s.event_type;
2033                         optype = cqe->u0.s.async_type;
2034                         if (evt_type  == ASYNC_EVENT_CODE_LINK_STATE) {
2035                                 /* Link status evt */
2036                                 acqe = (struct oce_async_cqe_link_state *)cqe;
2037                                 process_link_state(sc, acqe);
2038                         } else if ((evt_type == ASYNC_EVENT_GRP5) &&
2039                                    (optype == ASYNC_EVENT_PVID_STATE)) {
2040                                 /* GRP5 PVID */
2041                                 gcqe =
2042                                 (struct oce_async_event_grp5_pvid_state *)cqe;
2043                                 if (gcqe->enabled)
2044                                         sc->pvid = gcqe->tag & VLAN_VID_MASK;
2045                                 else
2046                                         sc->pvid = 0;
2047
2048                         }
2049                         else if(evt_type == ASYNC_EVENT_CODE_DEBUG &&
2050                                 optype == ASYNC_EVENT_DEBUG_QNQ) {
2051                                 dbgcqe =
2052                                 (struct oce_async_event_qnq *)cqe;
2053                                 if(dbgcqe->valid)
2054                                         sc->qnqid = dbgcqe->vlan_tag;
2055                                 sc->qnq_debug_event = TRUE;
2056                         }
2057                 }
2058                 cqe->u0.dw[3] = 0;
2059                 RING_GET(cq->ring, 1);
2060                 bus_dmamap_sync(cq->ring->dma.tag,
2061                                 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2062                 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2063                 num_cqes++;
2064         }
2065
2066         if (num_cqes)
2067                 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
2068
2069         return 0;
2070 }
2071
2072
2073 static void
2074 setup_max_queues_want(POCE_SOFTC sc)
2075 {
2076         /* Check if it is FLEX machine. Is so dont use RSS */
2077         if ((sc->function_mode & FNM_FLEX10_MODE) ||
2078             (sc->function_mode & FNM_UMC_MODE)    ||
2079             (sc->function_mode & FNM_VNIC_MODE)   ||
2080             (!is_rss_enabled(sc))                 ||
2081             (sc->flags & OCE_FLAGS_BE2)) {
2082                 sc->nrqs = 1;
2083                 sc->nwqs = 1;
2084         }
2085 }
2086
2087
2088 static void
2089 update_queues_got(POCE_SOFTC sc)
2090 {
2091         if (is_rss_enabled(sc)) {
2092                 sc->nrqs = sc->intr_count + 1;
2093                 sc->nwqs = sc->intr_count;
2094         } else {
2095                 sc->nrqs = 1;
2096                 sc->nwqs = 1;
2097         }
2098 }
2099
2100 static int
2101 oce_check_ipv6_ext_hdr(struct mbuf *m)
2102 {
2103         struct ether_header *eh = mtod(m, struct ether_header *);
2104         caddr_t m_datatemp = m->m_data;
2105
2106         if (eh->ether_type == htons(ETHERTYPE_IPV6)) {
2107                 m->m_data += sizeof(struct ether_header);
2108                 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
2109
2110                 if((ip6->ip6_nxt != IPPROTO_TCP) && \
2111                                 (ip6->ip6_nxt != IPPROTO_UDP)){
2112                         struct ip6_ext *ip6e = NULL;
2113                         m->m_data += sizeof(struct ip6_hdr);
2114
2115                         ip6e = (struct ip6_ext *) mtod(m, struct ip6_ext *);
2116                         if(ip6e->ip6e_len == 0xff) {
2117                                 m->m_data = m_datatemp;
2118                                 return TRUE;
2119                         }
2120                 }
2121                 m->m_data = m_datatemp;
2122         }
2123         return FALSE;
2124 }
2125
2126 static int
2127 is_be3_a1(POCE_SOFTC sc)
2128 {
2129         if((sc->flags & OCE_FLAGS_BE3)  && ((sc->asic_revision & 0xFF) < 2)) {
2130                 return TRUE;
2131         }
2132         return FALSE;
2133 }
2134
2135 static struct mbuf *
2136 oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete)
2137 {
2138         uint16_t vlan_tag = 0;
2139
2140         if(!M_WRITABLE(m))
2141                 return NULL;
2142
2143         /* Embed vlan tag in the packet if it is not part of it */
2144         if(m->m_flags & M_VLANTAG) {
2145                 vlan_tag = EVL_VLANOFTAG(m->m_pkthdr.ether_vtag);
2146                 m->m_flags &= ~M_VLANTAG;
2147         }
2148
2149         /* if UMC, ignore vlan tag insertion and instead insert pvid */
2150         if(sc->pvid) {
2151                 if(!vlan_tag)
2152                         vlan_tag = sc->pvid;
2153                 *complete = FALSE;
2154         }
2155
2156         if(vlan_tag) {
2157                 m = ether_vlanencap(m, vlan_tag);
2158         }
2159
2160         if(sc->qnqid) {
2161                 m = ether_vlanencap(m, sc->qnqid);
2162                 *complete = FALSE;
2163         }
2164         return m;
2165 }
2166
2167 static int
2168 oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m)
2169 {
2170         if(is_be3_a1(sc) && IS_QNQ_OR_UMC(sc) && \
2171                         oce_check_ipv6_ext_hdr(m)) {
2172                 return TRUE;
2173         }
2174         return FALSE;
2175 }
2176
2177 static void
2178 oce_get_config(POCE_SOFTC sc)
2179 {
2180         int rc = 0;
2181         uint32_t max_rss = 0;
2182
2183         if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2184                 max_rss = OCE_LEGACY_MODE_RSS;
2185         else
2186                 max_rss = OCE_MAX_RSS;
2187
2188         if (!IS_BE(sc)) {
2189                 rc = oce_get_func_config(sc);
2190                 if (rc) {
2191                         sc->nwqs = OCE_MAX_WQ;
2192                         sc->nrssqs = max_rss;
2193                         sc->nrqs = sc->nrssqs + 1;
2194                 }
2195         }
2196         else {
2197                 rc = oce_get_profile_config(sc);
2198                 sc->nrssqs = max_rss;
2199                 sc->nrqs = sc->nrssqs + 1;
2200                 if (rc)
2201                         sc->nwqs = OCE_MAX_WQ;
2202         }
2203 }