2 * Copyright (C) 2013 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
45 extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
48 * @brief Reset (firmware) common function
49 * @param sc software handle to the device
50 * @returns 0 on success, ETIMEDOUT on failure
53 oce_reset_fun(POCE_SOFTC sc)
57 struct ioctl_common_function_reset *fwcmd;
60 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) {
61 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
63 bzero(mbx, sizeof(struct oce_mbx));
65 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
66 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
68 OPCODE_COMMON_FUNCTION_RESET,
69 10, /* MBX_TIMEOUT_SEC */
71 ioctl_common_function_reset),
74 mbx->u0.s.embedded = 1;
76 sizeof(struct ioctl_common_function_reset);
78 rc = oce_mbox_dispatch(sc, 2);
86 * @brief This funtions tells firmware we are
88 * @param sc software handle to the device
89 * @returns 0 on success, ETIMEDOUT on failure
92 oce_fw_clean(POCE_SOFTC sc)
98 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
99 ptr = (uint8_t *) &mbx->mbx;
101 /* Endian Signature */
111 ret = oce_mbox_dispatch(sc, 2);
118 * @brief Mailbox wait
119 * @param sc software handle to the device
120 * @param tmo_sec timeout in seconds
123 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
126 pd_mpu_mbox_db_t mbox_db;
134 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
136 if (mbox_db.bits.ready)
142 device_printf(sc->dev, "Mailbox timed out\n");
149 * @brief Mailbox dispatch
150 * @param sc software handle to the device
151 * @param tmo_sec timeout in seconds
154 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
156 pd_mpu_mbox_db_t mbox_db;
160 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
161 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
162 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
163 mbox_db.bits.ready = 0;
165 mbox_db.bits.address = pa;
167 rc = oce_mbox_wait(sc, tmo_sec);
169 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
171 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
172 mbox_db.bits.ready = 0;
174 mbox_db.bits.address = pa;
176 rc = oce_mbox_wait(sc, tmo_sec);
179 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
181 rc = oce_mbox_wait(sc, tmo_sec);
183 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
193 * @brief Mailbox common request header initialization
194 * @param hdr mailbox header
197 * @param subsys subsystem
198 * @param opcode opcode
199 * @param timeout timeout
200 * @param pyld_len payload length
203 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
204 uint8_t dom, uint8_t port,
205 uint8_t subsys, uint8_t opcode,
206 uint32_t timeout, uint32_t pyld_len,
209 hdr->u0.req.opcode = opcode;
210 hdr->u0.req.subsystem = subsys;
211 hdr->u0.req.port_number = port;
212 hdr->u0.req.domain = dom;
214 hdr->u0.req.timeout = timeout;
215 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
216 hdr->u0.req.version = version;
222 * @brief Function to initialize the hw with host endian information
223 * @param sc software handle to the device
224 * @returns 0 on success, ETIMEDOUT on failure
227 oce_mbox_init(POCE_SOFTC sc)
229 struct oce_bmbx *mbx;
233 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
234 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
235 ptr = (uint8_t *) &mbx->mbx;
237 /* Endian Signature */
247 ret = oce_mbox_dispatch(sc, 0);
255 * @brief Function to get the firmware version
256 * @param sc software handle to the device
257 * @returns 0 on success, EIO on failure
260 oce_get_fw_version(POCE_SOFTC sc)
263 struct mbx_get_common_fw_version *fwcmd;
266 bzero(&mbx, sizeof(struct oce_mbx));
268 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
269 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
270 MBX_SUBSYSTEM_COMMON,
271 OPCODE_COMMON_GET_FW_VERSION,
273 sizeof(struct mbx_get_common_fw_version),
276 mbx.u0.s.embedded = 1;
277 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
278 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
280 ret = oce_mbox_post(sc, &mbx, NULL);
282 ret = fwcmd->hdr.u0.rsp.status;
284 device_printf(sc->dev,"%s failed - cmd status: %d\n",
289 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
296 * @brief Firmware will send gracious notifications during
297 * attach only after sending first mcc commnad. We
298 * use MCC queue only for getting async and mailbox
299 * for sending cmds. So to get gracious notifications
300 * atleast send one dummy command on mcc.
303 oce_first_mcc_cmd(POCE_SOFTC sc)
306 struct oce_mq *mq = sc->mq;
307 struct mbx_get_common_fw_version *fwcmd;
310 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
311 bzero(mbx, sizeof(struct oce_mbx));
313 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
314 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
315 MBX_SUBSYSTEM_COMMON,
316 OPCODE_COMMON_GET_FW_VERSION,
318 sizeof(struct mbx_get_common_fw_version),
320 mbx->u0.s.embedded = 1;
321 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
322 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
324 RING_PUT(mq->ring, 1);
325 reg_value = (1 << 16) | mq->mq_id;
326 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
332 * @brief Function to post a MBX to the mbox
333 * @param sc software handle to the device
334 * @param mbx pointer to the MBX to send
335 * @param mbxctx pointer to the mbx context structure
336 * @returns 0 on success, error on failure
339 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
341 struct oce_mbx *mb_mbx = NULL;
342 struct oce_mq_cqe *mb_cqe = NULL;
343 struct oce_bmbx *mb = NULL;
346 uint32_t cstatus = 0;
347 uint32_t xstatus = 0;
349 LOCK(&sc->bmbx_lock);
351 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
358 /* copy mbx into mbox */
359 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
362 rc = oce_mbox_dispatch(sc, tmo);
365 * the command completed successfully. Now get the
366 * completion queue entry
369 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
371 /* copy mbox mbx back */
372 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
374 /* pick up the mailbox status */
375 cstatus = mb_cqe->u0.s.completion_status;
376 xstatus = mb_cqe->u0.s.extended_status;
379 * store the mbx context in the cqe tag section so that
380 * the upper layer handling the cqe can associate the mbx
383 if (cstatus == 0 && mbxctx) {
385 mbxctx->mbx = mb_mbx;
386 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
387 sizeof(struct oce_mbx_ctx *));
391 UNLOCK(&sc->bmbx_lock);
397 * @brief Function to read the mac address associated with an interface
398 * @param sc software handle to the device
399 * @param if_id interface id to read the address from
400 * @param perm set to 1 if reading the factory mac address.
401 * In this case if_id is ignored
402 * @param type type of the mac address, whether network or storage
403 * @param[out] mac [OUTPUT] pointer to a buffer containing the
404 * mac address when the command succeeds.
405 * @returns 0 on success, EIO on failure
408 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
409 uint8_t perm, uint8_t type, struct mac_address_format *mac)
412 struct mbx_query_common_iface_mac *fwcmd;
415 bzero(&mbx, sizeof(struct oce_mbx));
417 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
418 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
419 MBX_SUBSYSTEM_COMMON,
420 OPCODE_COMMON_QUERY_IFACE_MAC,
422 sizeof(struct mbx_query_common_iface_mac),
425 fwcmd->params.req.permanent = perm;
427 fwcmd->params.req.if_id = (uint16_t) if_id;
429 fwcmd->params.req.if_id = 0;
431 fwcmd->params.req.type = type;
433 mbx.u0.s.embedded = 1;
434 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
435 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
437 ret = oce_mbox_post(sc, &mbx, NULL);
439 ret = fwcmd->hdr.u0.rsp.status;
441 device_printf(sc->dev,"%s failed - cmd status: %d\n",
446 /* copy the mac addres in the output parameter */
447 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
448 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
449 mac->size_of_struct);
455 * @brief Function to query the fw attributes from the hw
456 * @param sc software handle to the device
457 * @returns 0 on success, EIO on failure
460 oce_get_fw_config(POCE_SOFTC sc)
463 struct mbx_common_query_fw_config *fwcmd;
466 bzero(&mbx, sizeof(struct oce_mbx));
468 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
469 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
470 MBX_SUBSYSTEM_COMMON,
471 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
473 sizeof(struct mbx_common_query_fw_config),
476 mbx.u0.s.embedded = 1;
477 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
478 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
480 ret = oce_mbox_post(sc, &mbx, NULL);
482 ret = fwcmd->hdr.u0.rsp.status;
484 device_printf(sc->dev,"%s failed - cmd status: %d\n",
489 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
491 sc->config_number = fwcmd->params.rsp.config_number;
492 sc->asic_revision = fwcmd->params.rsp.asic_revision;
493 sc->port_id = fwcmd->params.rsp.port_id;
494 sc->function_mode = fwcmd->params.rsp.function_mode;
495 sc->function_caps = fwcmd->params.rsp.function_caps;
497 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
498 sc->max_tx_rings = fwcmd->params.rsp.ulp[0].nic_wq_tot;
499 sc->max_rx_rings = fwcmd->params.rsp.ulp[0].lro_rqid_tot;
501 sc->max_tx_rings = fwcmd->params.rsp.ulp[1].nic_wq_tot;
502 sc->max_rx_rings = fwcmd->params.rsp.ulp[1].lro_rqid_tot;
512 * @brief function to create a device interface
513 * @param sc software handle to the device
514 * @param cap_flags capability flags
515 * @param en_flags enable capability flags
516 * @param vlan_tag optional vlan tag to associate with the if
517 * @param mac_addr pointer to a buffer containing the mac address
518 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
520 * @returns 0 on success, EIO on failure
523 oce_if_create(POCE_SOFTC sc,
531 struct mbx_create_common_iface *fwcmd;
534 bzero(&mbx, sizeof(struct oce_mbx));
536 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
537 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
538 MBX_SUBSYSTEM_COMMON,
539 OPCODE_COMMON_CREATE_IFACE,
541 sizeof(struct mbx_create_common_iface),
543 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
545 fwcmd->params.req.version = 0;
546 fwcmd->params.req.cap_flags = LE_32(cap_flags);
547 fwcmd->params.req.enable_flags = LE_32(en_flags);
548 if (mac_addr != NULL) {
549 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
550 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
551 fwcmd->params.req.mac_invalid = 0;
553 fwcmd->params.req.mac_invalid = 1;
556 mbx.u0.s.embedded = 1;
557 mbx.payload_length = sizeof(struct mbx_create_common_iface);
558 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
560 rc = oce_mbox_post(sc, &mbx, NULL);
562 rc = fwcmd->hdr.u0.rsp.status;
564 device_printf(sc->dev,"%s failed - cmd status: %d\n",
569 *if_id = LE_32(fwcmd->params.rsp.if_id);
571 if (mac_addr != NULL)
572 sc->pmac_id = LE_32(fwcmd->params.rsp.pmac_id);
578 * @brief Function to delete an interface
579 * @param sc software handle to the device
580 * @param if_id ID of the interface to delete
581 * @returns 0 on success, EIO on failure
584 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
587 struct mbx_destroy_common_iface *fwcmd;
590 bzero(&mbx, sizeof(struct oce_mbx));
592 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
593 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
594 MBX_SUBSYSTEM_COMMON,
595 OPCODE_COMMON_DESTROY_IFACE,
597 sizeof(struct mbx_destroy_common_iface),
600 fwcmd->params.req.if_id = if_id;
602 mbx.u0.s.embedded = 1;
603 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
604 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
606 rc = oce_mbox_post(sc, &mbx, NULL);
608 rc = fwcmd->hdr.u0.rsp.status;
610 device_printf(sc->dev,"%s failed - cmd status: %d\n",
616 * @brief Function to send the mbx command to configure vlan
617 * @param sc software handle to the device
618 * @param if_id interface identifier index
619 * @param vtag_arr array of vlan tags
620 * @param vtag_cnt number of elements in array
621 * @param untagged boolean TRUE/FLASE
622 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
623 * @returns 0 on success, EIO on failure
626 oce_config_vlan(POCE_SOFTC sc,
628 struct normal_vlan *vtag_arr,
629 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
632 struct mbx_common_config_vlan *fwcmd;
635 bzero(&mbx, sizeof(struct oce_mbx));
636 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
638 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
639 MBX_SUBSYSTEM_COMMON,
640 OPCODE_COMMON_CONFIG_IFACE_VLAN,
642 sizeof(struct mbx_common_config_vlan),
645 fwcmd->params.req.if_id = (uint8_t) if_id;
646 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
647 fwcmd->params.req.untagged = (uint8_t) untagged;
648 fwcmd->params.req.num_vlans = vtag_cnt;
650 if (!enable_promisc) {
651 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
652 vtag_cnt * sizeof(struct normal_vlan));
654 mbx.u0.s.embedded = 1;
655 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
656 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
658 rc = oce_mbox_post(sc, &mbx, NULL);
660 rc = fwcmd->hdr.u0.rsp.status;
662 device_printf(sc->dev,"%s failed - cmd status: %d\n",
669 * @brief Function to set flow control capability in the hardware
670 * @param sc software handle to the device
671 * @param flow_control flow control flags to set
672 * @returns 0 on success, EIO on failure
675 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
678 struct mbx_common_get_set_flow_control *fwcmd =
679 (struct mbx_common_get_set_flow_control *)&mbx.payload;
682 bzero(&mbx, sizeof(struct oce_mbx));
684 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
685 MBX_SUBSYSTEM_COMMON,
686 OPCODE_COMMON_SET_FLOW_CONTROL,
688 sizeof(struct mbx_common_get_set_flow_control),
691 if (flow_control & OCE_FC_TX)
692 fwcmd->tx_flow_control = 1;
694 if (flow_control & OCE_FC_RX)
695 fwcmd->rx_flow_control = 1;
697 mbx.u0.s.embedded = 1;
698 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
699 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
701 rc = oce_mbox_post(sc, &mbx, NULL);
703 rc = fwcmd->hdr.u0.rsp.status;
705 device_printf(sc->dev,"%s failed - cmd status: %d\n",
711 * @brief Initialize the RSS CPU indirection table
713 * The table is used to choose the queue to place the incomming packets.
714 * Incomming packets are hashed. The lowest bits in the hash result
715 * are used as the index into the CPU indirection table.
716 * Each entry in the table contains the RSS CPU-ID returned by the NIC
717 * create. Based on the CPU ID, the receive completion is routed to
718 * the corresponding RSS CQs. (Non-RSS packets are always completed
719 * on the default (0) CQ).
721 * @param sc software handle to the device
722 * @param *fwcmd pointer to the rss mbox command
726 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
728 int i = 0, j = 0, rc = 0;
729 uint8_t *tbl = fwcmd->params.req.cputable;
730 struct oce_rq *rq = NULL;
733 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
734 for_all_rss_queues(sc, rq, i) {
735 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
737 tbl[j + i] = rq->rss_cpuid;
741 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
746 /* fill log2 value indicating the size of the CPU table */
748 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
754 * @brief Function to set flow control capability in the hardware
755 * @param sc software handle to the device
756 * @param if_id interface id to read the address from
757 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
758 * @returns 0 on success, EIO on failure
761 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
765 struct mbx_config_nic_rss *fwcmd =
766 (struct mbx_config_nic_rss *)&mbx.payload;
769 bzero(&mbx, sizeof(struct oce_mbx));
771 if (IS_XE201(sc) || IS_SH(sc)) {
772 version = OCE_MBX_VER_V1;
773 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
776 version = OCE_MBX_VER_V0;
778 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
782 sizeof(struct mbx_config_nic_rss),
785 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
786 RSS_ENABLE_TCP_IPV4 |
788 RSS_ENABLE_TCP_IPV6);
789 fwcmd->params.req.flush = OCE_FLUSH;
790 fwcmd->params.req.if_id = LE_32(if_id);
792 srandom(arc4random()); /* random entropy seed */
793 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
795 rc = oce_rss_itbl_init(sc, fwcmd);
797 mbx.u0.s.embedded = 1;
798 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
799 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
801 rc = oce_mbox_post(sc, &mbx, NULL);
803 rc = fwcmd->hdr.u0.rsp.status;
805 device_printf(sc->dev,"%s failed - cmd status: %d\n",
812 * @brief RXF function to enable/disable device promiscuous mode
813 * @param sc software handle to the device
814 * @param enable enable/disable flag
815 * @returns 0 on success, EIO on failure
817 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
818 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
821 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable)
823 struct mbx_set_common_iface_rx_filter *fwcmd;
824 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
825 iface_rx_filter_ctx_t *req;
829 /* allocate mbx payload's dma scatter/gather memory */
830 rc = oce_dma_alloc(sc, sz, &sgl, 0);
834 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
836 req = &fwcmd->params.req;
837 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
838 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
840 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
841 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
843 req->if_id = sc->if_id;
845 rc = oce_set_common_iface_rx_filter(sc, &sgl);
846 oce_dma_free(sc, &sgl);
853 * @brief Function modify and select rx filter options
854 * @param sc software handle to the device
855 * @param sgl scatter/gather request/response
856 * @returns 0 on success, error code on failure
859 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
862 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
863 struct mbx_set_common_iface_rx_filter *fwcmd;
866 bzero(&mbx, sizeof(struct oce_mbx));
867 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
869 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
870 MBX_SUBSYSTEM_COMMON,
871 OPCODE_COMMON_SET_IFACE_RX_FILTER,
876 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
877 mbx.u0.s.embedded = 0;
878 mbx.u0.s.sge_count = 1;
879 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
880 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
881 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
882 mbx.payload_length = mbx_sz;
883 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
885 rc = oce_mbox_post(sc, &mbx, NULL);
887 rc = fwcmd->hdr.u0.rsp.status;
889 device_printf(sc->dev,"%s failed - cmd status: %d\n",
895 * @brief Function to query the link status from the hardware
896 * @param sc software handle to the device
897 * @param[out] link pointer to the structure returning link attributes
898 * @returns 0 on success, EIO on failure
901 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
904 struct mbx_query_common_link_config *fwcmd;
907 bzero(&mbx, sizeof(struct oce_mbx));
909 IS_XE201(sc) ? (version = OCE_MBX_VER_V1) : (version = OCE_MBX_VER_V0);
911 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
912 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
913 MBX_SUBSYSTEM_COMMON,
914 OPCODE_COMMON_QUERY_LINK_CONFIG,
916 sizeof(struct mbx_query_common_link_config),
919 mbx.u0.s.embedded = 1;
920 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
921 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
923 rc = oce_mbox_post(sc, &mbx, NULL);
926 rc = fwcmd->hdr.u0.rsp.status;
928 device_printf(sc->dev,"%s failed - cmd status: %d\n",
932 /* interpret response */
933 bcopy(&fwcmd->params.rsp, link, sizeof(struct link_status));
934 link->logical_link_status = LE_32(link->logical_link_status);
935 link->qos_link_speed = LE_16(link->qos_link_speed);
943 oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
946 struct mbx_get_nic_stats_v0 *fwcmd;
949 bzero(&mbx, sizeof(struct oce_mbx));
951 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
952 bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
954 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
958 sizeof(struct mbx_get_nic_stats_v0),
961 mbx.u0.s.embedded = 0;
962 mbx.u0.s.sge_count = 1;
964 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
966 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
967 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
968 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
970 mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
972 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
974 rc = oce_mbox_post(sc, &mbx, NULL);
976 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
979 rc = fwcmd->hdr.u0.rsp.status;
981 device_printf(sc->dev,"%s failed - cmd status: %d\n",
989 * @brief Function to get NIC statistics
990 * @param sc software handle to the device
991 * @param *stats pointer to where to store statistics
992 * @param reset_stats resets statistics of set
993 * @returns 0 on success, EIO on failure
994 * @note command depricated in Lancer
997 oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
1000 struct mbx_get_nic_stats *fwcmd;
1003 bzero(&mbx, sizeof(struct oce_mbx));
1004 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
1005 bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
1007 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1011 sizeof(struct mbx_get_nic_stats),
1015 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1016 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1018 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1019 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1020 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1021 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
1023 mbx.payload_length = sizeof(struct mbx_get_nic_stats);
1024 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1026 rc = oce_mbox_post(sc, &mbx, NULL);
1027 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1029 rc = fwcmd->hdr.u0.rsp.status;
1031 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1038 * @brief Function to get pport (physical port) statistics
1039 * @param sc software handle to the device
1040 * @param *stats pointer to where to store statistics
1041 * @param reset_stats resets statistics of set
1042 * @returns 0 on success, EIO on failure
1045 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1046 uint32_t reset_stats)
1049 struct mbx_get_pport_stats *fwcmd;
1052 bzero(&mbx, sizeof(struct oce_mbx));
1053 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1054 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1056 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1058 NIC_GET_PPORT_STATS,
1060 sizeof(struct mbx_get_pport_stats),
1063 fwcmd->params.req.reset_stats = reset_stats;
1064 fwcmd->params.req.port_number = sc->port_id;
1066 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1067 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1069 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1070 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1071 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1072 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1074 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1075 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1077 rc = oce_mbox_post(sc, &mbx, NULL);
1078 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1081 rc = fwcmd->hdr.u0.rsp.status;
1083 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1090 * @brief Function to get vport (virtual port) statistics
1091 * @param sc software handle to the device
1092 * @param *stats pointer to where to store statistics
1093 * @param reset_stats resets statistics of set
1094 * @returns 0 on success, EIO on failure
1097 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1098 uint32_t req_size, uint32_t reset_stats)
1101 struct mbx_get_vport_stats *fwcmd;
1104 bzero(&mbx, sizeof(struct oce_mbx));
1106 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1107 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1109 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1111 NIC_GET_VPORT_STATS,
1113 sizeof(struct mbx_get_vport_stats),
1116 fwcmd->params.req.reset_stats = reset_stats;
1117 fwcmd->params.req.vport_number = sc->if_id;
1119 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1120 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1122 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1123 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1124 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1125 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1127 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1128 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1130 rc = oce_mbox_post(sc, &mbx, NULL);
1131 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1134 rc = fwcmd->hdr.u0.rsp.status;
1136 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1143 * @brief Function to update the muticast filter with
1145 * @param sc software handle to the device
1146 * @param dma_mem pointer to dma memory region
1147 * @returns 0 on success, EIO on failure
1150 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1153 struct oce_mq_sge *sgl;
1154 struct mbx_set_common_iface_multicast *req = NULL;
1157 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1158 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1159 MBX_SUBSYSTEM_COMMON,
1160 OPCODE_COMMON_SET_IFACE_MULTICAST,
1162 sizeof(struct mbx_set_common_iface_multicast),
1165 bzero(&mbx, sizeof(struct oce_mbx));
1167 mbx.u0.s.embedded = 0; /*Non embeded*/
1168 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1169 mbx.u0.s.sge_count = 1;
1170 sgl = &mbx.payload.u0.u1.sgl[0];
1171 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1172 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1173 sgl->length = htole32(mbx.payload_length);
1175 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1177 rc = oce_mbox_post(sc, &mbx, NULL);
1179 rc = req->hdr.u0.rsp.status;
1181 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1188 * @brief Function to send passthrough Ioctls
1189 * @param sc software handle to the device
1190 * @param dma_mem pointer to dma memory region
1191 * @param req_size size of dma_mem
1192 * @returns 0 on success, EIO on failure
1195 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1198 struct oce_mq_sge *sgl;
1201 bzero(&mbx, sizeof(struct oce_mbx));
1203 mbx.u0.s.embedded = 0; /*Non embeded*/
1204 mbx.payload_length = req_size;
1205 mbx.u0.s.sge_count = 1;
1206 sgl = &mbx.payload.u0.u1.sgl[0];
1207 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1208 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1209 sgl->length = htole32(req_size);
1211 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1213 rc = oce_mbox_post(sc, &mbx, NULL);
1219 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1220 uint32_t if_id, uint32_t *pmac_id)
1223 struct mbx_add_common_iface_mac *fwcmd;
1226 bzero(&mbx, sizeof(struct oce_mbx));
1228 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1229 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1230 MBX_SUBSYSTEM_COMMON,
1231 OPCODE_COMMON_ADD_IFACE_MAC,
1233 sizeof(struct mbx_add_common_iface_mac),
1236 fwcmd->params.req.if_id = (uint16_t) if_id;
1237 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1239 mbx.u0.s.embedded = 1;
1240 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1241 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1242 rc = oce_mbox_post(sc, &mbx, NULL);
1244 rc = fwcmd->hdr.u0.rsp.status;
1246 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1250 *pmac_id = fwcmd->params.rsp.pmac_id;
1257 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1260 struct mbx_del_common_iface_mac *fwcmd;
1263 bzero(&mbx, sizeof(struct oce_mbx));
1265 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1266 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1267 MBX_SUBSYSTEM_COMMON,
1268 OPCODE_COMMON_DEL_IFACE_MAC,
1270 sizeof(struct mbx_del_common_iface_mac),
1273 fwcmd->params.req.if_id = (uint16_t)if_id;
1274 fwcmd->params.req.pmac_id = pmac_id;
1276 mbx.u0.s.embedded = 1;
1277 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1278 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1280 rc = oce_mbox_post(sc, &mbx, NULL);
1282 rc = fwcmd->hdr.u0.rsp.status;
1284 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1292 oce_mbox_check_native_mode(POCE_SOFTC sc)
1295 struct mbx_common_set_function_cap *fwcmd;
1298 bzero(&mbx, sizeof(struct oce_mbx));
1300 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1301 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1302 MBX_SUBSYSTEM_COMMON,
1303 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1305 sizeof(struct mbx_common_set_function_cap),
1308 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1309 CAP_BE3_NATIVE_ERX_API;
1311 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1313 mbx.u0.s.embedded = 1;
1314 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1315 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1317 rc = oce_mbox_post(sc, &mbx, NULL);
1319 rc = fwcmd->hdr.u0.rsp.status;
1321 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1325 sc->be3_native = fwcmd->params.rsp.capability_flags
1326 & CAP_BE3_NATIVE_ERX_API;
1335 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1336 uint8_t loopback_type, uint8_t enable)
1339 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1343 bzero(&mbx, sizeof(struct oce_mbx));
1345 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1346 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1347 MBX_SUBSYSTEM_LOWLEVEL,
1348 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1350 sizeof(struct mbx_lowlevel_set_loopback_mode),
1353 fwcmd->params.req.src_port = port_num;
1354 fwcmd->params.req.dest_port = port_num;
1355 fwcmd->params.req.loopback_type = loopback_type;
1356 fwcmd->params.req.loopback_state = enable;
1358 mbx.u0.s.embedded = 1;
1359 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1360 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1362 rc = oce_mbox_post(sc, &mbx, NULL);
1364 rc = fwcmd->hdr.u0.rsp.status;
1366 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1374 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1375 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1380 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1384 bzero(&mbx, sizeof(struct oce_mbx));
1386 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1387 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1388 MBX_SUBSYSTEM_LOWLEVEL,
1389 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1391 sizeof(struct mbx_lowlevel_test_loopback_mode),
1394 fwcmd->params.req.pattern = pattern;
1395 fwcmd->params.req.src_port = port_num;
1396 fwcmd->params.req.dest_port = port_num;
1397 fwcmd->params.req.pkt_size = pkt_size;
1398 fwcmd->params.req.num_pkts = num_pkts;
1399 fwcmd->params.req.loopback_type = loopback_type;
1401 mbx.u0.s.embedded = 1;
1402 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1403 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1405 rc = oce_mbox_post(sc, &mbx, NULL);
1407 rc = fwcmd->hdr.u0.rsp.status;
1409 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1416 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1417 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1421 struct oce_mq_sge *sgl = NULL;
1422 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1423 int rc = 0, payload_len = 0;
1425 bzero(&mbx, sizeof(struct oce_mbx));
1426 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1427 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1429 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1430 MBX_SUBSYSTEM_COMMON,
1431 OPCODE_COMMON_WRITE_FLASHROM,
1436 fwcmd->flash_op_type = optype;
1437 fwcmd->flash_op_code = opcode;
1438 fwcmd->data_buffer_size = num_bytes;
1440 mbx.u0.s.embedded = 0; /*Non embeded*/
1441 mbx.payload_length = payload_len;
1442 mbx.u0.s.sge_count = 1;
1444 sgl = &mbx.payload.u0.u1.sgl[0];
1445 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1446 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1447 sgl->length = payload_len;
1449 /* post the command */
1450 rc = oce_mbox_post(sc, &mbx, NULL);
1452 rc = fwcmd->hdr.u0.rsp.status;
1454 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1462 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1463 uint32_t offset, uint32_t optype)
1466 int rc = 0, payload_len = 0;
1468 struct mbx_common_read_write_flashrom *fwcmd;
1470 bzero(&mbx, sizeof(struct oce_mbx));
1472 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1474 /* Firmware requires extra 4 bytes with this ioctl. Since there
1475 is enough room in the mbx payload it should be good enough
1476 Reference: Bug 14853
1478 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1480 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1481 MBX_SUBSYSTEM_COMMON,
1482 OPCODE_COMMON_READ_FLASHROM,
1487 fwcmd->flash_op_type = optype;
1488 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1489 fwcmd->data_offset = offset;
1490 fwcmd->data_buffer_size = 0x4;
1492 mbx.u0.s.embedded = 1;
1493 mbx.payload_length = payload_len;
1495 /* post the command */
1496 rc = oce_mbox_post(sc, &mbx, NULL);
1498 rc = fwcmd->hdr.u0.rsp.status;
1500 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1504 bcopy(fwcmd->data_buffer, flash_crc, 4);
1510 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1514 struct mbx_common_phy_info *fwcmd;
1517 bzero(&mbx, sizeof(struct oce_mbx));
1519 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1520 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1521 MBX_SUBSYSTEM_COMMON,
1522 OPCODE_COMMON_GET_PHY_CONFIG,
1524 sizeof(struct mbx_common_phy_info),
1527 mbx.u0.s.embedded = 1;
1528 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1530 /* now post the command */
1531 rc = oce_mbox_post(sc, &mbx, NULL);
1533 rc = fwcmd->hdr.u0.rsp.status;
1535 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1539 phy_info->phy_type = fwcmd->params.rsp.phy_info.phy_type;
1540 phy_info->interface_type =
1541 fwcmd->params.rsp.phy_info.interface_type;
1542 phy_info->auto_speeds_supported =
1543 fwcmd->params.rsp.phy_info.auto_speeds_supported;
1544 phy_info->fixed_speeds_supported =
1545 fwcmd->params.rsp.phy_info.fixed_speeds_supported;
1546 phy_info->misc_params =fwcmd->params.rsp.phy_info.misc_params;
1554 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1555 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1556 uint32_t *written_data, uint32_t *additional_status)
1560 struct mbx_lancer_common_write_object *fwcmd = NULL;
1561 int rc = 0, payload_len = 0;
1563 bzero(&mbx, sizeof(struct oce_mbx));
1564 payload_len = sizeof(struct mbx_lancer_common_write_object);
1566 mbx.u0.s.embedded = 1;/* Embedded */
1567 mbx.payload_length = payload_len;
1568 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1570 /* initialize the ioctl header */
1571 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1572 MBX_SUBSYSTEM_COMMON,
1573 OPCODE_COMMON_WRITE_OBJECT,
1578 fwcmd->params.req.write_length = data_size;
1580 fwcmd->params.req.eof = 1;
1582 fwcmd->params.req.eof = 0;
1584 strcpy(fwcmd->params.req.object_name, "/prg");
1585 fwcmd->params.req.descriptor_count = 1;
1586 fwcmd->params.req.write_offset = data_offset;
1587 fwcmd->params.req.buffer_length = data_size;
1588 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1589 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1591 /* post the command */
1592 rc = oce_mbox_post(sc, &mbx, NULL);
1594 rc = fwcmd->params.rsp.status;
1596 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1600 *written_data = fwcmd->params.rsp.actual_write_length;
1601 *additional_status = fwcmd->params.rsp.additional_status;
1610 oce_mbox_create_rq(struct oce_rq *rq)
1614 struct mbx_create_nic_rq *fwcmd;
1615 POCE_SOFTC sc = rq->parent;
1616 int rc, num_pages = 0;
1618 if (rq->qstate == QCREATED)
1621 bzero(&mbx, sizeof(struct oce_mbx));
1623 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1624 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1626 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1627 sizeof(struct mbx_create_nic_rq),
1630 /* oce_page_list will also prepare pages */
1631 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1634 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1635 fwcmd->params.req.page_size = 1;
1636 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1638 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1639 fwcmd->params.req.num_pages = num_pages;
1640 fwcmd->params.req.cq_id = rq->cq->cq_id;
1641 fwcmd->params.req.if_id = sc->if_id;
1642 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1643 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1645 mbx.u0.s.embedded = 1;
1646 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1648 rc = oce_mbox_post(sc, &mbx, NULL);
1650 rc = fwcmd->hdr.u0.rsp.status;
1652 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1656 rq->rq_id = fwcmd->params.rsp.rq_id;
1657 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1666 oce_mbox_create_wq(struct oce_wq *wq)
1669 struct mbx_create_nic_wq *fwcmd;
1670 POCE_SOFTC sc = wq->parent;
1671 int rc = 0, version, num_pages;
1673 bzero(&mbx, sizeof(struct oce_mbx));
1675 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1677 version = OCE_MBX_VER_V1;
1678 fwcmd->params.req.if_id = sc->if_id;
1679 } else if(IS_BE(sc))
1680 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1681 : (version = OCE_MBX_VER_V0);
1683 version = OCE_MBX_VER_V2;
1685 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1687 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1688 sizeof(struct mbx_create_nic_wq),
1691 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1693 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1694 fwcmd->params.req.num_pages = num_pages;
1695 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1696 fwcmd->params.req.cq_id = wq->cq->cq_id;
1697 fwcmd->params.req.ulp_num = 1;
1699 mbx.u0.s.embedded = 1;
1700 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1702 rc = oce_mbox_post(sc, &mbx, NULL);
1704 rc = fwcmd->hdr.u0.rsp.status;
1706 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1710 wq->wq_id = LE_16(fwcmd->params.rsp.wq_id);
1711 if (version == OCE_MBX_VER_V2)
1712 wq->db_offset = LE_32(fwcmd->params.rsp.db_offset);
1714 wq->db_offset = PD_TXULP_DB;
1723 oce_mbox_create_eq(struct oce_eq *eq)
1726 struct mbx_create_common_eq *fwcmd;
1727 POCE_SOFTC sc = eq->parent;
1731 bzero(&mbx, sizeof(struct oce_mbx));
1733 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1735 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1736 MBX_SUBSYSTEM_COMMON,
1737 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1738 sizeof(struct mbx_create_common_eq),
1741 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1742 fwcmd->params.req.ctx.num_pages = num_pages;
1743 fwcmd->params.req.ctx.valid = 1;
1744 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1745 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1746 fwcmd->params.req.ctx.armed = 0;
1747 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1750 mbx.u0.s.embedded = 1;
1751 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1753 rc = oce_mbox_post(sc, &mbx, NULL);
1755 rc = fwcmd->hdr.u0.rsp.status;
1757 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1761 eq->eq_id = LE_16(fwcmd->params.rsp.eq_id);
1769 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1772 struct mbx_create_common_cq *fwcmd;
1773 POCE_SOFTC sc = cq->parent;
1776 uint32_t num_pages, page_size;
1780 bzero(&mbx, sizeof(struct oce_mbx));
1782 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1785 version = OCE_MBX_VER_V2;
1787 version = OCE_MBX_VER_V0;
1789 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1790 MBX_SUBSYSTEM_COMMON,
1791 OPCODE_COMMON_CREATE_CQ,
1793 sizeof(struct mbx_create_common_cq),
1796 ctx = &fwcmd->params.req.cq_ctx;
1798 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1799 page_size = 1; /* 1 for 4K */
1801 if (version == OCE_MBX_VER_V2) {
1802 ctx->v2.num_pages = LE_16(num_pages);
1803 ctx->v2.page_size = page_size;
1804 ctx->v2.eventable = is_eventable;
1806 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1807 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1808 ctx->v2.coalesce_wm = ncoalesce;
1810 ctx->v2.eq_id = cq->eq->eq_id;
1811 if (ctx->v2.count == 3) {
1812 if (cq->cq_cfg.q_len > (4*1024)-1)
1813 ctx->v2.cqe_count = (4*1024)-1;
1815 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1818 ctx->v0.num_pages = LE_16(num_pages);
1819 ctx->v0.eventable = is_eventable;
1821 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1822 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1823 ctx->v0.coalesce_wm = ncoalesce;
1825 ctx->v0.eq_id = cq->eq->eq_id;
1828 mbx.u0.s.embedded = 1;
1829 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1831 rc = oce_mbox_post(sc, &mbx, NULL);
1833 rc = fwcmd->hdr.u0.rsp.status;
1835 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1839 cq->cq_id = LE_16(fwcmd->params.rsp.cq_id);
1846 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1850 struct mbx_read_common_transrecv_data *fwcmd;
1851 struct oce_mq_sge *sgl;
1854 /* Allocate DMA mem*/
1855 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1859 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1860 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1862 bzero(&mbx, sizeof(struct oce_mbx));
1863 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1864 MBX_SUBSYSTEM_COMMON,
1865 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1867 sizeof(struct mbx_read_common_transrecv_data),
1870 /* fill rest of mbx */
1871 mbx.u0.s.embedded = 0;
1872 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1873 mbx.u0.s.sge_count = 1;
1874 sgl = &mbx.payload.u0.u1.sgl[0];
1875 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1876 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1877 sgl->length = htole32(mbx.payload_length);
1878 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1880 fwcmd->params.req.port = LE_32(sc->port_id);
1881 fwcmd->params.req.page_num = LE_32(page_num);
1884 rc = oce_mbox_post(sc, &mbx, NULL);
1886 rc = fwcmd->hdr.u0.rsp.status;
1888 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1892 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1894 bcopy((char *)fwcmd->params.rsp.page_data,
1895 (char *)&sfp_vpd_dump_buffer[0],
1896 TRANSCEIVER_A0_SIZE);
1899 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1901 bcopy((char *)fwcmd->params.rsp.page_data,
1902 (char *)&sfp_vpd_dump_buffer[32],
1903 TRANSCEIVER_A2_SIZE);
1906 oce_dma_free(sc, &dma);
1911 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1915 struct mbx_modify_common_eq_delay *fwcmd;
1919 bzero(&mbx, sizeof(struct oce_mbx));
1921 /* Initialize MODIFY_EQ_DELAY ioctl header */
1922 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1923 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1924 MBX_SUBSYSTEM_COMMON,
1925 OPCODE_COMMON_MODIFY_EQ_DELAY,
1927 sizeof(struct mbx_modify_common_eq_delay),
1929 /* fill rest of mbx */
1930 mbx.u0.s.embedded = 1;
1931 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
1932 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1934 fwcmd->params.req.num_eq = num;
1935 for (i = 0; i < num; i++) {
1936 fwcmd->params.req.delay[i].eq_id =
1937 htole32(set_eqd[i].eq_id);
1938 fwcmd->params.req.delay[i].phase = 0;
1939 fwcmd->params.req.delay[i].dm =
1940 htole32(set_eqd[i].delay_multiplier);
1945 rc = oce_mbox_post(sc, &mbx, NULL);
1948 rc = fwcmd->hdr.u0.rsp.status;
1950 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1955 oce_get_profile_config(POCE_SOFTC sc)
1958 struct mbx_common_get_profile_config *fwcmd;
1961 struct oce_mq_sge *sgl;
1963 uint32_t desc_count = 0;
1964 struct oce_nic_resc_desc *nic_desc = NULL;
1966 boolean_t nic_desc_valid = FALSE;
1971 /* Allocate DMA mem*/
1972 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
1976 /* Initialize MODIFY_EQ_DELAY ioctl header */
1977 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
1978 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
1981 version = OCE_MBX_VER_V1;
1983 version = OCE_MBX_VER_V0;
1985 bzero(&mbx, sizeof(struct oce_mbx));
1986 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1987 MBX_SUBSYSTEM_COMMON,
1988 OPCODE_COMMON_GET_PROFILE_CONFIG,
1990 sizeof(struct mbx_common_get_profile_config),
1992 /* fill rest of mbx */
1993 mbx.u0.s.embedded = 0;
1994 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
1995 mbx.u0.s.sge_count = 1;
1996 sgl = &mbx.payload.u0.u1.sgl[0];
1997 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1998 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1999 sgl->length = htole32(mbx.payload_length);
2000 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2002 fwcmd->params.req.type = ACTIVE_PROFILE;
2005 rc = oce_mbox_post(sc, &mbx, NULL);
2007 rc = fwcmd->hdr.u0.rsp.status;
2009 device_printf(sc->dev,"%s failed - cmd status: %d\n",
2014 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2015 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2016 for (i = 0; i < desc_count; i++) {
2017 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2018 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2019 nic_desc_valid = TRUE;
2022 nic_desc = (struct oce_nic_resc_desc *) \
2023 ((char *)nic_desc + nic_desc->desc_len);
2025 if (!nic_desc_valid) {
2030 sc->nwqs = HOST_32(nic_desc->txq_count);
2032 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2034 sc->nwqs = OCE_MAX_WQ;
2038 oce_dma_free(sc, &dma);
2044 oce_get_func_config(POCE_SOFTC sc)
2047 struct mbx_common_get_func_config *fwcmd;
2050 struct oce_mq_sge *sgl;
2052 uint32_t desc_count = 0;
2053 struct oce_nic_resc_desc *nic_desc = NULL;
2055 boolean_t nic_desc_valid = FALSE;
2056 uint32_t max_rss = 0;
2058 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2059 max_rss = OCE_LEGACY_MODE_RSS;
2061 max_rss = OCE_MAX_RSS;
2063 /* Allocate DMA mem*/
2064 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2068 /* Initialize MODIFY_EQ_DELAY ioctl header */
2069 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2070 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2073 version = OCE_MBX_VER_V1;
2075 version = OCE_MBX_VER_V0;
2077 bzero(&mbx, sizeof(struct oce_mbx));
2078 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2079 MBX_SUBSYSTEM_COMMON,
2080 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2082 sizeof(struct mbx_common_get_func_config),
2084 /* fill rest of mbx */
2085 mbx.u0.s.embedded = 0;
2086 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2087 mbx.u0.s.sge_count = 1;
2088 sgl = &mbx.payload.u0.u1.sgl[0];
2089 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2090 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2091 sgl->length = htole32(mbx.payload_length);
2092 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2095 rc = oce_mbox_post(sc, &mbx, NULL);
2097 rc = fwcmd->hdr.u0.rsp.status;
2099 device_printf(sc->dev,"%s failed - cmd status: %d\n",
2104 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2105 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2106 for (i = 0; i < desc_count; i++) {
2107 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2108 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2109 nic_desc_valid = TRUE;
2112 nic_desc = (struct oce_nic_resc_desc *) \
2113 ((char *)nic_desc + nic_desc->desc_len);
2115 if (!nic_desc_valid) {
2120 sc->nwqs = HOST_32(nic_desc->txq_count);
2122 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2124 sc->nwqs = OCE_MAX_WQ;
2126 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2128 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2130 sc->nrssqs = max_rss;
2131 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */;
2134 oce_dma_free(sc, &dma);