sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /*-
  35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  36  *
  37  * Permission to use, copy, modify, and distribute this software for any
  38  * purpose with or without fee is hereby granted, provided that the above
  39  * copyright notice and this permission notice appear in all copies.
  40  *
  41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  48  */
  49
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/mbuf.h>
  93 #include <sys/malloc.h>
  94 #include <sys/kernel.h>
  95 #include <sys/module.h>
  96 #include <sys/socket.h>
  97 #include <sys/sockio.h>
  98 #include <sys/queue.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/bpf.h>
 102 #include <net/ethernet.h>
 103 #include <net/if.h>
 104 #include <net/if_arp.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107 #include <net/if_types.h>
 108 #include <net/if_vlan_var.h>
 109
 110 #include <netinet/in.h>
 111 #include <netinet/in_systm.h>
 112 #include <netinet/ip.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/in_cksum.h>
 116 #include <machine/resource.h>
 117 #include <sys/rman.h>
 118
 119 #include <dev/mii/mii.h>
 120 #include <dev/mii/miivar.h>
 121 #include <dev/mii/brgphyreg.h>
 122
 123 #include <dev/pci/pcireg.h>
 124 #include <dev/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include <dev/sk/if_skreg.h>
 131 #include <dev/sk/xmaciireg.h>
 132 #include <dev/sk/yukonreg.h>
 133
 134 MODULE_DEPEND(sk, pci, 1, 1, 1);
 135 MODULE_DEPEND(sk, ether, 1, 1, 1);
 136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 137
 138 /* "device miibus" required.  See GENERIC if you get errors here. */
 139 #include "miibus_if.h"
 140
 141 #ifndef lint
 142 static const char rcsid[] =
 143   "$FreeBSD$";
 144 #endif
 145
 146 static const struct sk_type sk_devs[] = {
 147         {
 148                 VENDORID_SK,
 149                 DEVICEID_SK_V1,
 150                 "SysKonnect Gigabit Ethernet (V1.0)"
 151         },
 152         {
 153                 VENDORID_SK,
 154                 DEVICEID_SK_V2,
 155                 "SysKonnect Gigabit Ethernet (V2.0)"
 156         },
 157         {
 158                 VENDORID_MARVELL,
 159                 DEVICEID_SK_V2,
 160                 "Marvell Gigabit Ethernet"
 161         },
 162         {
 163                 VENDORID_MARVELL,
 164                 DEVICEID_BELKIN_5005,
 165                 "Belkin F5D5005 Gigabit Ethernet"
 166         },
 167         {
 168                 VENDORID_3COM,
 169                 DEVICEID_3COM_3C940,
 170                 "3Com 3C940 Gigabit Ethernet"
 171         },
 172         {
 173                 VENDORID_LINKSYS,
 174                 DEVICEID_LINKSYS_EG1032,
 175                 "Linksys EG1032 Gigabit Ethernet"
 176         },
 177         {
 178                 VENDORID_DLINK,
 179                 DEVICEID_DLINK_DGE530T_A1,
 180                 "D-Link DGE-530T Gigabit Ethernet"
 181         },
 182         {
 183                 VENDORID_DLINK,
 184                 DEVICEID_DLINK_DGE530T_B1,
 185                 "D-Link DGE-530T Gigabit Ethernet"
 186         },
 187         { 0, 0, NULL }
 188 };
 189
 190 static int skc_probe(device_t);
 191 static int skc_attach(device_t);
 192 static int skc_detach(device_t);
 193 static int skc_shutdown(device_t);
 194 static int skc_suspend(device_t);
 195 static int skc_resume(device_t);
 196 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
 197 static int sk_detach(device_t);
 198 static int sk_probe(device_t);
 199 static int sk_attach(device_t);
 200 static void sk_tick(void *);
 201 static void sk_yukon_tick(void *);
 202 static void sk_intr(void *);
 203 static void sk_intr_xmac(struct sk_if_softc *);
 204 static void sk_intr_bcom(struct sk_if_softc *);
 205 static void sk_intr_yukon(struct sk_if_softc *);
 206 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 207 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 208 static void sk_rxeof(struct sk_if_softc *);
 209 static void sk_jumbo_rxeof(struct sk_if_softc *);
 210 static void sk_txeof(struct sk_if_softc *);
 211 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 212 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 213 static void sk_start(struct ifnet *);
 214 static void sk_start_locked(struct ifnet *);
 215 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 216 static void sk_init(void *);
 217 static void sk_init_locked(struct sk_if_softc *);
 218 static void sk_init_xmac(struct sk_if_softc *);
 219 static void sk_init_yukon(struct sk_if_softc *);
 220 static void sk_stop(struct sk_if_softc *);
 221 static void sk_watchdog(void *);
 222 static int sk_ifmedia_upd(struct ifnet *);
 223 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 224 static void sk_reset(struct sk_softc *);
 225 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 226 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 227 static int sk_newbuf(struct sk_if_softc *, int);
 228 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 229 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 230 static int sk_dma_alloc(struct sk_if_softc *);
 231 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
 232 static void sk_dma_free(struct sk_if_softc *);
 233 static void sk_dma_jumbo_free(struct sk_if_softc *);
 234 static int sk_init_rx_ring(struct sk_if_softc *);
 235 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 236 static void sk_init_tx_ring(struct sk_if_softc *);
 237 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 238 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 239 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 240 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 241 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 242 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 243
 244 static int sk_miibus_readreg(device_t, int, int);
 245 static int sk_miibus_writereg(device_t, int, int, int);
 246 static void sk_miibus_statchg(device_t);
 247
 248 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 249 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 250                                                 int);
 251 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 252
 253 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 254 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 255                                                 int);
 256 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 257
 258 static uint32_t sk_xmchash(const uint8_t *);
 259 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 260 static void sk_rxfilter(struct sk_if_softc *);
 261 static void sk_rxfilter_genesis(struct sk_if_softc *);
 262 static void sk_rxfilter_yukon(struct sk_if_softc *);
 263
 264 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 265 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 266
 267 /* Tunables. */
 268 static int jumbo_disable = 0;
 269 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
 270
 271 /*
 272  * It seems that SK-NET GENESIS supports very simple checksum offload
 273  * capability for Tx and I believe it can generate 0 checksum value for
 274  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 275  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 276  * means sender didn't perforam checksum computation. For the safety I
 277  * disabled UDP checksum offload capability at the moment. Alternatively
 278  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 279  * offload routine.
 280  */
 281 #define SK_CSUM_FEATURES        (CSUM_TCP)
 282
 283 /*
 284  * Note that we have newbus methods for both the GEnesis controller
 285  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 286  * the miibus code is a child of the XMACs. We need to do it this way
 287  * so that the miibus drivers can access the PHY registers on the
 288  * right PHY. It's not quite what I had in mind, but it's the only
 289  * design that achieves the desired effect.
 290  */
 291 static device_method_t skc_methods[] = {
 292         /* Device interface */
 293         DEVMETHOD(device_probe,         skc_probe),
 294         DEVMETHOD(device_attach,        skc_attach),
 295         DEVMETHOD(device_detach,        skc_detach),
 296         DEVMETHOD(device_suspend,       skc_suspend),
 297         DEVMETHOD(device_resume,        skc_resume),
 298         DEVMETHOD(device_shutdown,      skc_shutdown),
 299
 300         DEVMETHOD(bus_get_dma_tag,      skc_get_dma_tag),
 301
 302         DEVMETHOD_END
 303 };
 304
 305 static driver_t skc_driver = {
 306         "skc",
 307         skc_methods,
 308         sizeof(struct sk_softc)
 309 };
 310
 311 static devclass_t skc_devclass;
 312
 313 static device_method_t sk_methods[] = {
 314         /* Device interface */
 315         DEVMETHOD(device_probe,         sk_probe),
 316         DEVMETHOD(device_attach,        sk_attach),
 317         DEVMETHOD(device_detach,        sk_detach),
 318         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 319
 320         /* MII interface */
 321         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 322         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 323         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 324
 325         DEVMETHOD_END
 326 };
 327
 328 static driver_t sk_driver = {
 329         "sk",
 330         sk_methods,
 331         sizeof(struct sk_if_softc)
 332 };
 333
 334 static devclass_t sk_devclass;
 335
 336 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
 337 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
 338 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
 339
 340 static struct resource_spec sk_res_spec_io[] = {
 341         { SYS_RES_IOPORT,       PCIR_BAR(1),    RF_ACTIVE },
 342         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 343         { -1,                   0,              0 }
 344 };
 345
 346 static struct resource_spec sk_res_spec_mem[] = {
 347         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 348         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 349         { -1,                   0,              0 }
 350 };
 351
 352 #define SK_SETBIT(sc, reg, x)           \
 353         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 354
 355 #define SK_CLRBIT(sc, reg, x)           \
 356         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 357
 358 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 359         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 360
 361 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 362         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 363
 364 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 365         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 366
 367 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 368         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 369
 370 static u_int32_t
 371 sk_win_read_4(sc, reg)
 372         struct sk_softc         *sc;
 373         int                     reg;
 374 {
 375 #ifdef SK_USEIOSPACE
 376         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 377         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 378 #else
 379         return(CSR_READ_4(sc, reg));
 380 #endif
 381 }
 382
 383 static u_int16_t
 384 sk_win_read_2(sc, reg)
 385         struct sk_softc         *sc;
 386         int                     reg;
 387 {
 388 #ifdef SK_USEIOSPACE
 389         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 390         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 391 #else
 392         return(CSR_READ_2(sc, reg));
 393 #endif
 394 }
 395
 396 static u_int8_t
 397 sk_win_read_1(sc, reg)
 398         struct sk_softc         *sc;
 399         int                     reg;
 400 {
 401 #ifdef SK_USEIOSPACE
 402         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 403         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 404 #else
 405         return(CSR_READ_1(sc, reg));
 406 #endif
 407 }
 408
 409 static void
 410 sk_win_write_4(sc, reg, val)
 411         struct sk_softc         *sc;
 412         int                     reg;
 413         u_int32_t               val;
 414 {
 415 #ifdef SK_USEIOSPACE
 416         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 417         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 418 #else
 419         CSR_WRITE_4(sc, reg, val);
 420 #endif
 421         return;
 422 }
 423
 424 static void
 425 sk_win_write_2(sc, reg, val)
 426         struct sk_softc         *sc;
 427         int                     reg;
 428         u_int32_t               val;
 429 {
 430 #ifdef SK_USEIOSPACE
 431         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 432         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 433 #else
 434         CSR_WRITE_2(sc, reg, val);
 435 #endif
 436         return;
 437 }
 438
 439 static void
 440 sk_win_write_1(sc, reg, val)
 441         struct sk_softc         *sc;
 442         int                     reg;
 443         u_int32_t               val;
 444 {
 445 #ifdef SK_USEIOSPACE
 446         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 447         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 448 #else
 449         CSR_WRITE_1(sc, reg, val);
 450 #endif
 451         return;
 452 }
 453
 454 static int
 455 sk_miibus_readreg(dev, phy, reg)
 456         device_t                dev;
 457         int                     phy, reg;
 458 {
 459         struct sk_if_softc      *sc_if;
 460         int                     v;
 461
 462         sc_if = device_get_softc(dev);
 463
 464         SK_IF_MII_LOCK(sc_if);
 465         switch(sc_if->sk_softc->sk_type) {
 466         case SK_GENESIS:
 467                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 468                 break;
 469         case SK_YUKON:
 470         case SK_YUKON_LITE:
 471         case SK_YUKON_LP:
 472                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 473                 break;
 474         default:
 475                 v = 0;
 476                 break;
 477         }
 478         SK_IF_MII_UNLOCK(sc_if);
 479
 480         return (v);
 481 }
 482
 483 static int
 484 sk_miibus_writereg(dev, phy, reg, val)
 485         device_t                dev;
 486         int                     phy, reg, val;
 487 {
 488         struct sk_if_softc      *sc_if;
 489         int                     v;
 490
 491         sc_if = device_get_softc(dev);
 492
 493         SK_IF_MII_LOCK(sc_if);
 494         switch(sc_if->sk_softc->sk_type) {
 495         case SK_GENESIS:
 496                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 497                 break;
 498         case SK_YUKON:
 499         case SK_YUKON_LITE:
 500         case SK_YUKON_LP:
 501                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 502                 break;
 503         default:
 504                 v = 0;
 505                 break;
 506         }
 507         SK_IF_MII_UNLOCK(sc_if);
 508
 509         return (v);
 510 }
 511
 512 static void
 513 sk_miibus_statchg(dev)
 514         device_t                dev;
 515 {
 516         struct sk_if_softc      *sc_if;
 517
 518         sc_if = device_get_softc(dev);
 519
 520         SK_IF_MII_LOCK(sc_if);
 521         switch(sc_if->sk_softc->sk_type) {
 522         case SK_GENESIS:
 523                 sk_xmac_miibus_statchg(sc_if);
 524                 break;
 525         case SK_YUKON:
 526         case SK_YUKON_LITE:
 527         case SK_YUKON_LP:
 528                 sk_marv_miibus_statchg(sc_if);
 529                 break;
 530         }
 531         SK_IF_MII_UNLOCK(sc_if);
 532
 533         return;
 534 }
 535
 536 static int
 537 sk_xmac_miibus_readreg(sc_if, phy, reg)
 538         struct sk_if_softc      *sc_if;
 539         int                     phy, reg;
 540 {
 541         int                     i;
 542
 543         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 544         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 545         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 546                 for (i = 0; i < SK_TIMEOUT; i++) {
 547                         DELAY(1);
 548                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 549                             XM_MMUCMD_PHYDATARDY)
 550                                 break;
 551                 }
 552
 553                 if (i == SK_TIMEOUT) {
 554                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 555                         return(0);
 556                 }
 557         }
 558         DELAY(1);
 559         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 560
 561         return(i);
 562 }
 563
 564 static int
 565 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 566         struct sk_if_softc      *sc_if;
 567         int                     phy, reg, val;
 568 {
 569         int                     i;
 570
 571         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 572         for (i = 0; i < SK_TIMEOUT; i++) {
 573                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 574                         break;
 575         }
 576
 577         if (i == SK_TIMEOUT) {
 578                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 579                 return (ETIMEDOUT);
 580         }
 581
 582         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 583         for (i = 0; i < SK_TIMEOUT; i++) {
 584                 DELAY(1);
 585                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 586                         break;
 587         }
 588         if (i == SK_TIMEOUT)
 589                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 590
 591         return(0);
 592 }
 593
 594 static void
 595 sk_xmac_miibus_statchg(sc_if)
 596         struct sk_if_softc      *sc_if;
 597 {
 598         struct mii_data         *mii;
 599
 600         mii = device_get_softc(sc_if->sk_miibus);
 601
 602         /*
 603          * If this is a GMII PHY, manually set the XMAC's
 604          * duplex mode accordingly.
 605          */
 606         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 607                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 608                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 609                 } else {
 610                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 611                 }
 612         }
 613 }
 614
 615 static int
 616 sk_marv_miibus_readreg(sc_if, phy, reg)
 617         struct sk_if_softc      *sc_if;
 618         int                     phy, reg;
 619 {
 620         u_int16_t               val;
 621         int                     i;
 622
 623         if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 624             sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
 625                 return(0);
 626         }
 627
 628         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 629                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 630
 631         for (i = 0; i < SK_TIMEOUT; i++) {
 632                 DELAY(1);
 633                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 634                 if (val & YU_SMICR_READ_VALID)
 635                         break;
 636         }
 637
 638         if (i == SK_TIMEOUT) {
 639                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 640                 return(0);
 641         }
 642
 643         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 644
 645         return(val);
 646 }
 647
 648 static int
 649 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 650         struct sk_if_softc      *sc_if;
 651         int                     phy, reg, val;
 652 {
 653         int                     i;
 654
 655         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 656         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 657                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 658
 659         for (i = 0; i < SK_TIMEOUT; i++) {
 660                 DELAY(1);
 661                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 662                         break;
 663         }
 664         if (i == SK_TIMEOUT)
 665                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 666
 667         return(0);
 668 }
 669
 670 static void
 671 sk_marv_miibus_statchg(sc_if)
 672         struct sk_if_softc      *sc_if;
 673 {
 674         return;
 675 }
 676
 677 #define HASH_BITS               6
 678
 679 static u_int32_t
 680 sk_xmchash(addr)
 681         const uint8_t *addr;
 682 {
 683         uint32_t crc;
 684
 685         /* Compute CRC for the address value. */
 686         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 687
 688         return (~crc & ((1 << HASH_BITS) - 1));
 689 }
 690
 691 static void
 692 sk_setfilt(sc_if, addr, slot)
 693         struct sk_if_softc      *sc_if;
 694         u_int16_t               *addr;
 695         int                     slot;
 696 {
 697         int                     base;
 698
 699         base = XM_RXFILT_ENTRY(slot);
 700
 701         SK_XM_WRITE_2(sc_if, base, addr[0]);
 702         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 703         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 704
 705         return;
 706 }
 707
 708 static void
 709 sk_rxfilter(sc_if)
 710         struct sk_if_softc      *sc_if;
 711 {
 712         struct sk_softc         *sc;
 713
 714         SK_IF_LOCK_ASSERT(sc_if);
 715
 716         sc = sc_if->sk_softc;
 717         if (sc->sk_type == SK_GENESIS)
 718                 sk_rxfilter_genesis(sc_if);
 719         else
 720                 sk_rxfilter_yukon(sc_if);
 721 }
 722
 723 static void
 724 sk_rxfilter_genesis(sc_if)
 725         struct sk_if_softc      *sc_if;
 726 {
 727         struct ifnet            *ifp = sc_if->sk_ifp;
 728         u_int32_t               hashes[2] = { 0, 0 }, mode;
 729         int                     h = 0, i;
 730         struct ifmultiaddr      *ifma;
 731         u_int16_t               dummy[] = { 0, 0, 0 };
 732         u_int16_t               maddr[(ETHER_ADDR_LEN+1)/2];
 733
 734         SK_IF_LOCK_ASSERT(sc_if);
 735
 736         mode = SK_XM_READ_4(sc_if, XM_MODE);
 737         mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
 738             XM_MODE_RX_USE_PERFECT);
 739         /* First, zot all the existing perfect filters. */
 740         for (i = 1; i < XM_RXFILT_MAX; i++)
 741                 sk_setfilt(sc_if, dummy, i);
 742
 743         /* Now program new ones. */
 744         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 745                 if (ifp->if_flags & IFF_ALLMULTI)
 746                         mode |= XM_MODE_RX_USE_HASH;
 747                 if (ifp->if_flags & IFF_PROMISC)
 748                         mode |= XM_MODE_RX_PROMISC;
 749                 hashes[0] = 0xFFFFFFFF;
 750                 hashes[1] = 0xFFFFFFFF;
 751         } else {
 752                 i = 1;
 753                 if_maddr_rlock(ifp);
 754                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 755                     ifma_link) {
 756                         if (ifma->ifma_addr->sa_family != AF_LINK)
 757                                 continue;
 758                         /*
 759                          * Program the first XM_RXFILT_MAX multicast groups
 760                          * into the perfect filter.
 761                          */
 762                         bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 763                             maddr, ETHER_ADDR_LEN);
 764                         if (i < XM_RXFILT_MAX) {
 765                                 sk_setfilt(sc_if, maddr, i);
 766                                 mode |= XM_MODE_RX_USE_PERFECT;
 767                                 i++;
 768                                 continue;
 769                         }
 770                         h = sk_xmchash((const uint8_t *)maddr);
 771                         if (h < 32)
 772                                 hashes[0] |= (1 << h);
 773                         else
 774                                 hashes[1] |= (1 << (h - 32));
 775                         mode |= XM_MODE_RX_USE_HASH;
 776                 }
 777                 if_maddr_runlock(ifp);
 778         }
 779
 780         SK_XM_WRITE_4(sc_if, XM_MODE, mode);
 781         SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 782         SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 783 }
 784
 785 static void
 786 sk_rxfilter_yukon(sc_if)
 787         struct sk_if_softc      *sc_if;
 788 {
 789         struct ifnet            *ifp;
 790         u_int32_t               crc, hashes[2] = { 0, 0 }, mode;
 791         struct ifmultiaddr      *ifma;
 792
 793         SK_IF_LOCK_ASSERT(sc_if);
 794
 795         ifp = sc_if->sk_ifp;
 796         mode = SK_YU_READ_2(sc_if, YUKON_RCR);
 797         if (ifp->if_flags & IFF_PROMISC)
 798                 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
 799         else if (ifp->if_flags & IFF_ALLMULTI) {
 800                 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
 801                 hashes[0] = 0xFFFFFFFF;
 802                 hashes[1] = 0xFFFFFFFF;
 803         } else {
 804                 mode |= YU_RCR_UFLEN;
 805                 if_maddr_rlock(ifp);
 806                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 807                         if (ifma->ifma_addr->sa_family != AF_LINK)
 808                                 continue;
 809                         crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 810                             ifma->ifma_addr), ETHER_ADDR_LEN);
 811                         /* Just want the 6 least significant bits. */
 812                         crc &= 0x3f;
 813                         /* Set the corresponding bit in the hash table. */
 814                         hashes[crc >> 5] |= 1 << (crc & 0x1f);
 815                 }
 816                 if_maddr_runlock(ifp);
 817                 if (hashes[0] != 0 || hashes[1] != 0)
 818                         mode |= YU_RCR_MUFLEN;
 819         }
 820
 821         SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 822         SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 823         SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 824         SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 825         SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
 826 }
 827
 828 static int
 829 sk_init_rx_ring(sc_if)
 830         struct sk_if_softc      *sc_if;
 831 {
 832         struct sk_ring_data     *rd;
 833         bus_addr_t              addr;
 834         u_int32_t               csum_start;
 835         int                     i;
 836
 837         sc_if->sk_cdata.sk_rx_cons = 0;
 838
 839         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 840             ETHER_HDR_LEN;
 841         rd = &sc_if->sk_rdata;
 842         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 843         for (i = 0; i < SK_RX_RING_CNT; i++) {
 844                 if (sk_newbuf(sc_if, i) != 0)
 845                         return (ENOBUFS);
 846                 if (i == (SK_RX_RING_CNT - 1))
 847                         addr = SK_RX_RING_ADDR(sc_if, 0);
 848                 else
 849                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 850                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 851                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 852         }
 853
 854         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 855             sc_if->sk_cdata.sk_rx_ring_map,
 856             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 857
 858         return(0);
 859 }
 860
 861 static int
 862 sk_init_jumbo_rx_ring(sc_if)
 863         struct sk_if_softc      *sc_if;
 864 {
 865         struct sk_ring_data     *rd;
 866         bus_addr_t              addr;
 867         u_int32_t               csum_start;
 868         int                     i;
 869
 870         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
 871
 872         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
 873             ETHER_HDR_LEN;
 874         rd = &sc_if->sk_rdata;
 875         bzero(rd->sk_jumbo_rx_ring,
 876             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
 877         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
 878                 if (sk_jumbo_newbuf(sc_if, i) != 0)
 879                         return (ENOBUFS);
 880                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
 881                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
 882                 else
 883                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
 884                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 885                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
 886         }
 887
 888         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
 889             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
 890             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 891
 892         return (0);
 893 }
 894
 895 static void
 896 sk_init_tx_ring(sc_if)
 897         struct sk_if_softc      *sc_if;
 898 {
 899         struct sk_ring_data     *rd;
 900         struct sk_txdesc        *txd;
 901         bus_addr_t              addr;
 902         int                     i;
 903
 904         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
 905         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
 906
 907         sc_if->sk_cdata.sk_tx_prod = 0;
 908         sc_if->sk_cdata.sk_tx_cons = 0;
 909         sc_if->sk_cdata.sk_tx_cnt = 0;
 910
 911         rd = &sc_if->sk_rdata;
 912         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 913         for (i = 0; i < SK_TX_RING_CNT; i++) {
 914                 if (i == (SK_TX_RING_CNT - 1))
 915                         addr = SK_TX_RING_ADDR(sc_if, 0);
 916                 else
 917                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
 918                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 919                 txd = &sc_if->sk_cdata.sk_txdesc[i];
 920                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
 921         }
 922
 923         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
 924             sc_if->sk_cdata.sk_tx_ring_map,
 925             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 926 }
 927
 928 static __inline void
 929 sk_discard_rxbuf(sc_if, idx)
 930         struct sk_if_softc      *sc_if;
 931         int                     idx;
 932 {
 933         struct sk_rx_desc       *r;
 934         struct sk_rxdesc        *rxd;
 935         struct mbuf             *m;
 936
 937
 938         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 939         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 940         m = rxd->rx_m;
 941         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 942 }
 943
 944 static __inline void
 945 sk_discard_jumbo_rxbuf(sc_if, idx)
 946         struct sk_if_softc      *sc_if;
 947         int                     idx;
 948 {
 949         struct sk_rx_desc       *r;
 950         struct sk_rxdesc        *rxd;
 951         struct mbuf             *m;
 952
 953         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
 954         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
 955         m = rxd->rx_m;
 956         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 957 }
 958
 959 static int
 960 sk_newbuf(sc_if, idx)
 961         struct sk_if_softc      *sc_if;
 962         int                     idx;
 963 {
 964         struct sk_rx_desc       *r;
 965         struct sk_rxdesc        *rxd;
 966         struct mbuf             *m;
 967         bus_dma_segment_t       segs[1];
 968         bus_dmamap_t            map;
 969         int                     nsegs;
 970
 971         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 972         if (m == NULL)
 973                 return (ENOBUFS);
 974         m->m_len = m->m_pkthdr.len = MCLBYTES;
 975         m_adj(m, ETHER_ALIGN);
 976
 977         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
 978             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 979                 m_freem(m);
 980                 return (ENOBUFS);
 981         }
 982         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 983
 984         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 985         if (rxd->rx_m != NULL) {
 986                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 987                     BUS_DMASYNC_POSTREAD);
 988                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
 989         }
 990         map = rxd->rx_dmamap;
 991         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
 992         sc_if->sk_cdata.sk_rx_sparemap = map;
 993         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 994             BUS_DMASYNC_PREREAD);
 995         rxd->rx_m = m;
 996         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 997         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
 998         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
 999         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1000
1001         return (0);
1002 }
1003
1004 static int
1005 sk_jumbo_newbuf(sc_if, idx)
1006         struct sk_if_softc      *sc_if;
1007         int                     idx;
1008 {
1009         struct sk_rx_desc       *r;
1010         struct sk_rxdesc        *rxd;
1011         struct mbuf             *m;
1012         bus_dma_segment_t       segs[1];
1013         bus_dmamap_t            map;
1014         int                     nsegs;
1015
1016         m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1017         if (m == NULL)
1018                 return (ENOBUFS);
1019         if ((m->m_flags & M_EXT) == 0) {
1020                 m_freem(m);
1021                 return (ENOBUFS);
1022         }
1023         m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1024         /*
1025          * Adjust alignment so packet payload begins on a
1026          * longword boundary. Mandatory for Alpha, useful on
1027          * x86 too.
1028          */
1029         m_adj(m, ETHER_ALIGN);
1030
1031         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1032             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1033                 m_freem(m);
1034                 return (ENOBUFS);
1035         }
1036         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1037
1038         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1039         if (rxd->rx_m != NULL) {
1040                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1041                     BUS_DMASYNC_POSTREAD);
1042                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1043                     rxd->rx_dmamap);
1044         }
1045         map = rxd->rx_dmamap;
1046         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1047         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1048         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1049             BUS_DMASYNC_PREREAD);
1050         rxd->rx_m = m;
1051         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1052         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1053         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1054         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1055
1056         return (0);
1057 }
1058
1059 /*
1060  * Set media options.
1061  */
1062 static int
1063 sk_ifmedia_upd(ifp)
1064         struct ifnet            *ifp;
1065 {
1066         struct sk_if_softc      *sc_if = ifp->if_softc;
1067         struct mii_data         *mii;
1068
1069         mii = device_get_softc(sc_if->sk_miibus);
1070         sk_init(sc_if);
1071         mii_mediachg(mii);
1072
1073         return(0);
1074 }
1075
1076 /*
1077  * Report current media status.
1078  */
1079 static void
1080 sk_ifmedia_sts(ifp, ifmr)
1081         struct ifnet            *ifp;
1082         struct ifmediareq       *ifmr;
1083 {
1084         struct sk_if_softc      *sc_if;
1085         struct mii_data         *mii;
1086
1087         sc_if = ifp->if_softc;
1088         mii = device_get_softc(sc_if->sk_miibus);
1089
1090         mii_pollstat(mii);
1091         ifmr->ifm_active = mii->mii_media_active;
1092         ifmr->ifm_status = mii->mii_media_status;
1093
1094         return;
1095 }
1096
1097 static int
1098 sk_ioctl(ifp, command, data)
1099         struct ifnet            *ifp;
1100         u_long                  command;
1101         caddr_t                 data;
1102 {
1103         struct sk_if_softc      *sc_if = ifp->if_softc;
1104         struct ifreq            *ifr = (struct ifreq *) data;
1105         int                     error, mask;
1106         struct mii_data         *mii;
1107
1108         error = 0;
1109         switch(command) {
1110         case SIOCSIFMTU:
1111                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1112                         error = EINVAL;
1113                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1114                         if (sc_if->sk_jumbo_disable != 0 &&
1115                             ifr->ifr_mtu > SK_MAX_FRAMELEN)
1116                                 error = EINVAL;
1117                         else {
1118                                 SK_IF_LOCK(sc_if);
1119                                 ifp->if_mtu = ifr->ifr_mtu;
1120                                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1121                                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1122                                         sk_init_locked(sc_if);
1123                                 }
1124                                 SK_IF_UNLOCK(sc_if);
1125                         }
1126                 }
1127                 break;
1128         case SIOCSIFFLAGS:
1129                 SK_IF_LOCK(sc_if);
1130                 if (ifp->if_flags & IFF_UP) {
1131                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1132                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1133                                     & (IFF_PROMISC | IFF_ALLMULTI))
1134                                         sk_rxfilter(sc_if);
1135                         } else
1136                                 sk_init_locked(sc_if);
1137                 } else {
1138                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1139                                 sk_stop(sc_if);
1140                 }
1141                 sc_if->sk_if_flags = ifp->if_flags;
1142                 SK_IF_UNLOCK(sc_if);
1143                 break;
1144         case SIOCADDMULTI:
1145         case SIOCDELMULTI:
1146                 SK_IF_LOCK(sc_if);
1147                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1148                         sk_rxfilter(sc_if);
1149                 SK_IF_UNLOCK(sc_if);
1150                 break;
1151         case SIOCGIFMEDIA:
1152         case SIOCSIFMEDIA:
1153                 mii = device_get_softc(sc_if->sk_miibus);
1154                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1155                 break;
1156         case SIOCSIFCAP:
1157                 SK_IF_LOCK(sc_if);
1158                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1159                         SK_IF_UNLOCK(sc_if);
1160                         break;
1161                 }
1162                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1163                 if ((mask & IFCAP_TXCSUM) != 0 &&
1164                     (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1165                         ifp->if_capenable ^= IFCAP_TXCSUM;
1166                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1167                                 ifp->if_hwassist |= SK_CSUM_FEATURES;
1168                         else
1169                                 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1170                 }
1171                 if ((mask & IFCAP_RXCSUM) != 0 &&
1172                     (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1173                         ifp->if_capenable ^= IFCAP_RXCSUM;
1174                 SK_IF_UNLOCK(sc_if);
1175                 break;
1176         default:
1177                 error = ether_ioctl(ifp, command, data);
1178                 break;
1179         }
1180
1181         return (error);
1182 }
1183
1184 /*
1185  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1186  * IDs against our list and return a device name if we find a match.
1187  */
1188 static int
1189 skc_probe(dev)
1190         device_t                dev;
1191 {
1192         const struct sk_type    *t = sk_devs;
1193
1194         while(t->sk_name != NULL) {
1195                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1196                     (pci_get_device(dev) == t->sk_did)) {
1197                         /*
1198                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1199                          * Rev. 3 is supported by re(4).
1200                          */
1201                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1202                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1203                                 (pci_get_subdevice(dev) !=
1204                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1205                                 t++;
1206                                 continue;
1207                         }
1208                         device_set_desc(dev, t->sk_name);
1209                         return (BUS_PROBE_DEFAULT);
1210                 }
1211                 t++;
1212         }
1213
1214         return(ENXIO);
1215 }
1216
1217 /*
1218  * Force the GEnesis into reset, then bring it out of reset.
1219  */
1220 static void
1221 sk_reset(sc)
1222         struct sk_softc         *sc;
1223 {
1224
1225         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1226         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1227         if (SK_YUKON_FAMILY(sc->sk_type))
1228                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1229
1230         DELAY(1000);
1231         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1232         DELAY(2);
1233         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1234         if (SK_YUKON_FAMILY(sc->sk_type))
1235                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1236
1237         if (sc->sk_type == SK_GENESIS) {
1238                 /* Configure packet arbiter */
1239                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1240                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1241                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1242                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1243                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1244         }
1245
1246         /* Enable RAM interface */
1247         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1248
1249         /*
1250          * Configure interrupt moderation. The moderation timer
1251          * defers interrupts specified in the interrupt moderation
1252          * timer mask based on the timeout specified in the interrupt
1253          * moderation timer init register. Each bit in the timer
1254          * register represents one tick, so to specify a timeout in
1255          * microseconds, we have to multiply by the correct number of
1256          * ticks-per-microsecond.
1257          */
1258         switch (sc->sk_type) {
1259         case SK_GENESIS:
1260                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1261                 break;
1262         default:
1263                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1264                 break;
1265         }
1266         if (bootverbose)
1267                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1268                     sc->sk_int_mod);
1269         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1270             sc->sk_int_ticks));
1271         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1272             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1273         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1274
1275         return;
1276 }
1277
1278 static int
1279 sk_probe(dev)
1280         device_t                dev;
1281 {
1282         struct sk_softc         *sc;
1283
1284         sc = device_get_softc(device_get_parent(dev));
1285
1286         /*
1287          * Not much to do here. We always know there will be
1288          * at least one XMAC present, and if there are two,
1289          * skc_attach() will create a second device instance
1290          * for us.
1291          */
1292         switch (sc->sk_type) {
1293         case SK_GENESIS:
1294                 device_set_desc(dev, "XaQti Corp. XMAC II");
1295                 break;
1296         case SK_YUKON:
1297         case SK_YUKON_LITE:
1298         case SK_YUKON_LP:
1299                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1300                 break;
1301         }
1302
1303         return (BUS_PROBE_DEFAULT);
1304 }
1305
1306 /*
1307  * Each XMAC chip is attached as a separate logical IP interface.
1308  * Single port cards will have only one logical interface of course.
1309  */
1310 static int
1311 sk_attach(dev)
1312         device_t                dev;
1313 {
1314         struct sk_softc         *sc;
1315         struct sk_if_softc      *sc_if;
1316         struct ifnet            *ifp;
1317         u_int32_t               r;
1318         int                     error, i, phy, port;
1319         u_char                  eaddr[6];
1320         u_char                  inv_mac[] = {0, 0, 0, 0, 0, 0};
1321
1322         if (dev == NULL)
1323                 return(EINVAL);
1324
1325         error = 0;
1326         sc_if = device_get_softc(dev);
1327         sc = device_get_softc(device_get_parent(dev));
1328         port = *(int *)device_get_ivars(dev);
1329
1330         sc_if->sk_if_dev = dev;
1331         sc_if->sk_port = port;
1332         sc_if->sk_softc = sc;
1333         sc->sk_if[port] = sc_if;
1334         if (port == SK_PORT_A)
1335                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1336         if (port == SK_PORT_B)
1337                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1338
1339         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1340         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1341
1342         if (sk_dma_alloc(sc_if) != 0) {
1343                 error = ENOMEM;
1344                 goto fail;
1345         }
1346         sk_dma_jumbo_alloc(sc_if);
1347
1348         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1349         if (ifp == NULL) {
1350                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1351                 error = ENOSPC;
1352                 goto fail;
1353         }
1354         ifp->if_softc = sc_if;
1355         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1356         ifp->if_mtu = ETHERMTU;
1357         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1358         /*
1359          * SK_GENESIS has a bug in checksum offload - From linux.
1360          */
1361         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1362                 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1363                 ifp->if_hwassist = 0;
1364         } else {
1365                 ifp->if_capabilities = 0;
1366                 ifp->if_hwassist = 0;
1367         }
1368         ifp->if_capenable = ifp->if_capabilities;
1369         /*
1370          * Some revision of Yukon controller generates corrupted
1371          * frame when TX checksum offloading is enabled.  The
1372          * frame has a valid checksum value so payload might be
1373          * modified during TX checksum calculation. Disable TX
1374          * checksum offloading but give users chance to enable it
1375          * when they know their controller works without problems
1376          * with TX checksum offloading.
1377          */
1378         ifp->if_capenable &= ~IFCAP_TXCSUM;
1379         ifp->if_ioctl = sk_ioctl;
1380         ifp->if_start = sk_start;
1381         ifp->if_init = sk_init;
1382         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1383         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1384         IFQ_SET_READY(&ifp->if_snd);
1385
1386         /*
1387          * Get station address for this interface. Note that
1388          * dual port cards actually come with three station
1389          * addresses: one for each port, plus an extra. The
1390          * extra one is used by the SysKonnect driver software
1391          * as a 'virtual' station address for when both ports
1392          * are operating in failover mode. Currently we don't
1393          * use this extra address.
1394          */
1395         SK_IF_LOCK(sc_if);
1396         for (i = 0; i < ETHER_ADDR_LEN; i++)
1397                 eaddr[i] =
1398                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1399
1400         /* Verify whether the station address is invalid or not. */
1401         if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1402                 device_printf(sc_if->sk_if_dev,
1403                     "Generating random ethernet address\n");
1404                 r = arc4random();
1405                 /*
1406                  * Set OUI to convenient locally assigned address.  'b'
1407                  * is 0x62, which has the locally assigned bit set, and
1408                  * the broadcast/multicast bit clear.
1409                  */
1410                 eaddr[0] = 'b';
1411                 eaddr[1] = 's';
1412                 eaddr[2] = 'd';
1413                 eaddr[3] = (r >> 16) & 0xff;
1414                 eaddr[4] = (r >>  8) & 0xff;
1415                 eaddr[5] = (r >>  0) & 0xff;
1416         }
1417         /*
1418          * Set up RAM buffer addresses. The NIC will have a certain
1419          * amount of SRAM on it, somewhere between 512K and 2MB. We
1420          * need to divide this up a) between the transmitter and
1421          * receiver and b) between the two XMACs, if this is a
1422          * dual port NIC. Our algotithm is to divide up the memory
1423          * evenly so that everyone gets a fair share.
1424          *
1425          * Just to be contrary, Yukon2 appears to have separate memory
1426          * for each MAC.
1427          */
1428         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1429                 u_int32_t               chunk, val;
1430
1431                 chunk = sc->sk_ramsize / 2;
1432                 val = sc->sk_rboff / sizeof(u_int64_t);
1433                 sc_if->sk_rx_ramstart = val;
1434                 val += (chunk / sizeof(u_int64_t));
1435                 sc_if->sk_rx_ramend = val - 1;
1436                 sc_if->sk_tx_ramstart = val;
1437                 val += (chunk / sizeof(u_int64_t));
1438                 sc_if->sk_tx_ramend = val - 1;
1439         } else {
1440                 u_int32_t               chunk, val;
1441
1442                 chunk = sc->sk_ramsize / 4;
1443                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1444                     sizeof(u_int64_t);
1445                 sc_if->sk_rx_ramstart = val;
1446                 val += (chunk / sizeof(u_int64_t));
1447                 sc_if->sk_rx_ramend = val - 1;
1448                 sc_if->sk_tx_ramstart = val;
1449                 val += (chunk / sizeof(u_int64_t));
1450                 sc_if->sk_tx_ramend = val - 1;
1451         }
1452
1453         /* Read and save PHY type and set PHY address */
1454         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1455         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1456                 switch(sc_if->sk_phytype) {
1457                 case SK_PHYTYPE_XMAC:
1458                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1459                         break;
1460                 case SK_PHYTYPE_BCOM:
1461                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1462                         break;
1463                 default:
1464                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1465                             sc_if->sk_phytype);
1466                         error = ENODEV;
1467                         SK_IF_UNLOCK(sc_if);
1468                         goto fail;
1469                 }
1470         } else {
1471                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1472                     sc->sk_pmd != 'S') {
1473                         /* not initialized, punt */
1474                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1475                         sc->sk_coppertype = 1;
1476                 }
1477
1478                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1479
1480                 if (!(sc->sk_coppertype))
1481                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1482         }
1483
1484         /*
1485          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1486          */
1487         SK_IF_UNLOCK(sc_if);
1488         ether_ifattach(ifp, eaddr);
1489         SK_IF_LOCK(sc_if);
1490
1491         /*
1492          * The hardware should be ready for VLAN_MTU by default:
1493          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1494          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1495          *
1496          */
1497         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1498         ifp->if_capenable |= IFCAP_VLAN_MTU;
1499         /*
1500          * Tell the upper layer(s) we support long frames.
1501          * Must appear after the call to ether_ifattach() because
1502          * ether_ifattach() sets ifi_hdrlen to the default value.
1503          */
1504         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1505
1506         /*
1507          * Do miibus setup.
1508          */
1509         phy = MII_PHY_ANY;
1510         switch (sc->sk_type) {
1511         case SK_GENESIS:
1512                 sk_init_xmac(sc_if);
1513                 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1514                         phy = 0;
1515                 break;
1516         case SK_YUKON:
1517         case SK_YUKON_LITE:
1518         case SK_YUKON_LP:
1519                 sk_init_yukon(sc_if);
1520                 phy = 0;
1521                 break;
1522         }
1523
1524         SK_IF_UNLOCK(sc_if);
1525         error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1526             sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1527         if (error != 0) {
1528                 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1529                 ether_ifdetach(ifp);
1530                 goto fail;
1531         }
1532
1533 fail:
1534         if (error) {
1535                 /* Access should be ok even though lock has been dropped */
1536                 sc->sk_if[port] = NULL;
1537                 sk_detach(dev);
1538         }
1539
1540         return(error);
1541 }
1542
1543 /*
1544  * Attach the interface. Allocate softc structures, do ifmedia
1545  * setup and ethernet/BPF attach.
1546  */
1547 static int
1548 skc_attach(dev)
1549         device_t                dev;
1550 {
1551         struct sk_softc         *sc;
1552         int                     error = 0, *port;
1553         uint8_t                 skrs;
1554         const char              *pname = NULL;
1555         char                    *revstr;
1556
1557         sc = device_get_softc(dev);
1558         sc->sk_dev = dev;
1559
1560         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1561             MTX_DEF);
1562         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1563         /*
1564          * Map control/status registers.
1565          */
1566         pci_enable_busmaster(dev);
1567
1568         /* Allocate resources */
1569 #ifdef SK_USEIOSPACE
1570         sc->sk_res_spec = sk_res_spec_io;
1571 #else
1572         sc->sk_res_spec = sk_res_spec_mem;
1573 #endif
1574         error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1575         if (error) {
1576                 if (sc->sk_res_spec == sk_res_spec_mem)
1577                         sc->sk_res_spec = sk_res_spec_io;
1578                 else
1579                         sc->sk_res_spec = sk_res_spec_mem;
1580                 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1581                 if (error) {
1582                         device_printf(dev, "couldn't allocate %s resources\n",
1583                             sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1584                             "I/O");
1585                         goto fail;
1586                 }
1587         }
1588
1589         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1590         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1591
1592         /* Bail out if chip is not recognized. */
1593         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1594                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1595                     sc->sk_type, sc->sk_rev);
1596                 error = ENXIO;
1597                 goto fail;
1598         }
1599
1600         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1601                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1602                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1603                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1604                 "SK interrupt moderation");
1605
1606         /* Pull in device tunables. */
1607         sc->sk_int_mod = SK_IM_DEFAULT;
1608         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1609                 "int_mod", &sc->sk_int_mod);
1610         if (error == 0) {
1611                 if (sc->sk_int_mod < SK_IM_MIN ||
1612                     sc->sk_int_mod > SK_IM_MAX) {
1613                         device_printf(dev, "int_mod value out of range; "
1614                             "using default: %d\n", SK_IM_DEFAULT);
1615                         sc->sk_int_mod = SK_IM_DEFAULT;
1616                 }
1617         }
1618
1619         /* Reset the adapter. */
1620         sk_reset(sc);
1621
1622         skrs = sk_win_read_1(sc, SK_EPROM0);
1623         if (sc->sk_type == SK_GENESIS) {
1624                 /* Read and save RAM size and RAMbuffer offset */
1625                 switch(skrs) {
1626                 case SK_RAMSIZE_512K_64:
1627                         sc->sk_ramsize = 0x80000;
1628                         sc->sk_rboff = SK_RBOFF_0;
1629                         break;
1630                 case SK_RAMSIZE_1024K_64:
1631                         sc->sk_ramsize = 0x100000;
1632                         sc->sk_rboff = SK_RBOFF_80000;
1633                         break;
1634                 case SK_RAMSIZE_1024K_128:
1635                         sc->sk_ramsize = 0x100000;
1636                         sc->sk_rboff = SK_RBOFF_0;
1637                         break;
1638                 case SK_RAMSIZE_2048K_128:
1639                         sc->sk_ramsize = 0x200000;
1640                         sc->sk_rboff = SK_RBOFF_0;
1641                         break;
1642                 default:
1643                         device_printf(dev, "unknown ram size: %d\n", skrs);
1644                         error = ENXIO;
1645                         goto fail;
1646                 }
1647         } else { /* SK_YUKON_FAMILY */
1648                 if (skrs == 0x00)
1649                         sc->sk_ramsize = 0x20000;
1650                 else
1651                         sc->sk_ramsize = skrs * (1<<12);
1652                 sc->sk_rboff = SK_RBOFF_0;
1653         }
1654
1655         /* Read and save physical media type */
1656          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1657
1658          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1659                  sc->sk_coppertype = 1;
1660          else
1661                  sc->sk_coppertype = 0;
1662
1663         /* Determine whether to name it with VPD PN or just make it up.
1664          * Marvell Yukon VPD PN seems to freqently be bogus. */
1665         switch (pci_get_device(dev)) {
1666         case DEVICEID_SK_V1:
1667         case DEVICEID_BELKIN_5005:
1668         case DEVICEID_3COM_3C940:
1669         case DEVICEID_LINKSYS_EG1032:
1670         case DEVICEID_DLINK_DGE530T_A1:
1671         case DEVICEID_DLINK_DGE530T_B1:
1672                 /* Stay with VPD PN. */
1673                 (void) pci_get_vpd_ident(dev, &pname);
1674                 break;
1675         case DEVICEID_SK_V2:
1676                 /* YUKON VPD PN might bear no resemblance to reality. */
1677                 switch (sc->sk_type) {
1678                 case SK_GENESIS:
1679                         /* Stay with VPD PN. */
1680                         (void) pci_get_vpd_ident(dev, &pname);
1681                         break;
1682                 case SK_YUKON:
1683                         pname = "Marvell Yukon Gigabit Ethernet";
1684                         break;
1685                 case SK_YUKON_LITE:
1686                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1687                         break;
1688                 case SK_YUKON_LP:
1689                         pname = "Marvell Yukon LP Gigabit Ethernet";
1690                         break;
1691                 default:
1692                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1693                         break;
1694                 }
1695
1696                 /* Yukon Lite Rev. A0 needs special test. */
1697                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1698                         u_int32_t far;
1699                         u_int8_t testbyte;
1700
1701                         /* Save flash address register before testing. */
1702                         far = sk_win_read_4(sc, SK_EP_ADDR);
1703
1704                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1705                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1706
1707                         if (testbyte != 0x00) {
1708                                 /* Yukon Lite Rev. A0 detected. */
1709                                 sc->sk_type = SK_YUKON_LITE;
1710                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1711                                 /* Restore flash address register. */
1712                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1713                         }
1714                 }
1715                 break;
1716         default:
1717                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1718                         "chipver=%02x, rev=%x\n",
1719                         pci_get_vendor(dev), pci_get_device(dev),
1720                         sc->sk_type, sc->sk_rev);
1721                 error = ENXIO;
1722                 goto fail;
1723         }
1724
1725         if (sc->sk_type == SK_YUKON_LITE) {
1726                 switch (sc->sk_rev) {
1727                 case SK_YUKON_LITE_REV_A0:
1728                         revstr = "A0";
1729                         break;
1730                 case SK_YUKON_LITE_REV_A1:
1731                         revstr = "A1";
1732                         break;
1733                 case SK_YUKON_LITE_REV_A3:
1734                         revstr = "A3";
1735                         break;
1736                 default:
1737                         revstr = "";
1738                         break;
1739                 }
1740         } else {
1741                 revstr = "";
1742         }
1743
1744         /* Announce the product name and more VPD data if there. */
1745         if (pname != NULL)
1746                 device_printf(dev, "%s rev. %s(0x%x)\n",
1747                         pname, revstr, sc->sk_rev);
1748
1749         if (bootverbose) {
1750                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1751                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1752                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1753                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1754         }
1755
1756         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1757         if (sc->sk_devs[SK_PORT_A] == NULL) {
1758                 device_printf(dev, "failed to add child for PORT_A\n");
1759                 error = ENXIO;
1760                 goto fail;
1761         }
1762         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1763         if (port == NULL) {
1764                 device_printf(dev, "failed to allocate memory for "
1765                     "ivars of PORT_A\n");
1766                 error = ENXIO;
1767                 goto fail;
1768         }
1769         *port = SK_PORT_A;
1770         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1771
1772         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1773                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1774                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1775                         device_printf(dev, "failed to add child for PORT_B\n");
1776                         error = ENXIO;
1777                         goto fail;
1778                 }
1779                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1780                 if (port == NULL) {
1781                         device_printf(dev, "failed to allocate memory for "
1782                             "ivars of PORT_B\n");
1783                         error = ENXIO;
1784                         goto fail;
1785                 }
1786                 *port = SK_PORT_B;
1787                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1788         }
1789
1790         /* Turn on the 'driver is loaded' LED. */
1791         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1792
1793         error = bus_generic_attach(dev);
1794         if (error) {
1795                 device_printf(dev, "failed to attach port(s)\n");
1796                 goto fail;
1797         }
1798
1799         /* Hook interrupt last to avoid having to lock softc */
1800         error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1801             NULL, sk_intr, sc, &sc->sk_intrhand);
1802
1803         if (error) {
1804                 device_printf(dev, "couldn't set up irq\n");
1805                 goto fail;
1806         }
1807
1808 fail:
1809         if (error)
1810                 skc_detach(dev);
1811
1812         return(error);
1813 }
1814
1815 /*
1816  * Shutdown hardware and free up resources. This can be called any
1817  * time after the mutex has been initialized. It is called in both
1818  * the error case in attach and the normal detach case so it needs
1819  * to be careful about only freeing resources that have actually been
1820  * allocated.
1821  */
1822 static int
1823 sk_detach(dev)
1824         device_t                dev;
1825 {
1826         struct sk_if_softc      *sc_if;
1827         struct ifnet            *ifp;
1828
1829         sc_if = device_get_softc(dev);
1830         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1831             ("sk mutex not initialized in sk_detach"));
1832         SK_IF_LOCK(sc_if);
1833
1834         ifp = sc_if->sk_ifp;
1835         /* These should only be active if attach_xmac succeeded */
1836         if (device_is_attached(dev)) {
1837                 sk_stop(sc_if);
1838                 /* Can't hold locks while calling detach */
1839                 SK_IF_UNLOCK(sc_if);
1840                 callout_drain(&sc_if->sk_tick_ch);
1841                 callout_drain(&sc_if->sk_watchdog_ch);
1842                 ether_ifdetach(ifp);
1843                 SK_IF_LOCK(sc_if);
1844         }
1845         if (ifp)
1846                 if_free(ifp);
1847         /*
1848          * We're generally called from skc_detach() which is using
1849          * device_delete_child() to get to here. It's already trashed
1850          * miibus for us, so don't do it here or we'll panic.
1851          */
1852         /*
1853         if (sc_if->sk_miibus != NULL)
1854                 device_delete_child(dev, sc_if->sk_miibus);
1855         */
1856         bus_generic_detach(dev);
1857         sk_dma_jumbo_free(sc_if);
1858         sk_dma_free(sc_if);
1859         SK_IF_UNLOCK(sc_if);
1860
1861         return(0);
1862 }
1863
1864 static int
1865 skc_detach(dev)
1866         device_t                dev;
1867 {
1868         struct sk_softc         *sc;
1869
1870         sc = device_get_softc(dev);
1871         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1872
1873         if (device_is_alive(dev)) {
1874                 if (sc->sk_devs[SK_PORT_A] != NULL) {
1875                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1876                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1877                 }
1878                 if (sc->sk_devs[SK_PORT_B] != NULL) {
1879                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1880                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1881                 }
1882                 bus_generic_detach(dev);
1883         }
1884
1885         if (sc->sk_intrhand)
1886                 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1887         bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1888
1889         mtx_destroy(&sc->sk_mii_mtx);
1890         mtx_destroy(&sc->sk_mtx);
1891
1892         return(0);
1893 }
1894
1895 static bus_dma_tag_t
1896 skc_get_dma_tag(device_t bus, device_t child __unused)
1897 {
1898
1899         return (bus_get_dma_tag(bus));
1900 }
1901
1902 struct sk_dmamap_arg {
1903         bus_addr_t      sk_busaddr;
1904 };
1905
1906 static void
1907 sk_dmamap_cb(arg, segs, nseg, error)
1908         void                    *arg;
1909         bus_dma_segment_t       *segs;
1910         int                     nseg;
1911         int                     error;
1912 {
1913         struct sk_dmamap_arg    *ctx;
1914
1915         if (error != 0)
1916                 return;
1917
1918         ctx = arg;
1919         ctx->sk_busaddr = segs[0].ds_addr;
1920 }
1921
1922 /*
1923  * Allocate jumbo buffer storage. The SysKonnect adapters support
1924  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1925  * use them in their drivers. In order for us to use them, we need
1926  * large 9K receive buffers, however standard mbuf clusters are only
1927  * 2048 bytes in size. Consequently, we need to allocate and manage
1928  * our own jumbo buffer pool. Fortunately, this does not require an
1929  * excessive amount of additional code.
1930  */
1931 static int
1932 sk_dma_alloc(sc_if)
1933         struct sk_if_softc      *sc_if;
1934 {
1935         struct sk_dmamap_arg    ctx;
1936         struct sk_txdesc        *txd;
1937         struct sk_rxdesc        *rxd;
1938         int                     error, i;
1939
1940         /* create parent tag */
1941         /*
1942          * XXX
1943          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1944          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1945          * However bz@ reported that it does not work on amd64 with > 4GB
1946          * RAM. Until we have more clues of the breakage, disable DAC mode
1947          * by limiting DMA address to be in 32bit address space.
1948          */
1949         error = bus_dma_tag_create(
1950                     bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1951                     1, 0,                       /* algnmnt, boundary */
1952                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1953                     BUS_SPACE_MAXADDR,          /* highaddr */
1954                     NULL, NULL,                 /* filter, filterarg */
1955                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1956                     0,                          /* nsegments */
1957                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1958                     0,                          /* flags */
1959                     NULL, NULL,                 /* lockfunc, lockarg */
1960                     &sc_if->sk_cdata.sk_parent_tag);
1961         if (error != 0) {
1962                 device_printf(sc_if->sk_if_dev,
1963                     "failed to create parent DMA tag\n");
1964                 goto fail;
1965         }
1966
1967         /* create tag for Tx ring */
1968         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1969                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1970                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1971                     BUS_SPACE_MAXADDR,          /* highaddr */
1972                     NULL, NULL,                 /* filter, filterarg */
1973                     SK_TX_RING_SZ,              /* maxsize */
1974                     1,                          /* nsegments */
1975                     SK_TX_RING_SZ,              /* maxsegsize */
1976                     0,                          /* flags */
1977                     NULL, NULL,                 /* lockfunc, lockarg */
1978                     &sc_if->sk_cdata.sk_tx_ring_tag);
1979         if (error != 0) {
1980                 device_printf(sc_if->sk_if_dev,
1981                     "failed to allocate Tx ring DMA tag\n");
1982                 goto fail;
1983         }
1984
1985         /* create tag for Rx ring */
1986         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1987                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1988                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1989                     BUS_SPACE_MAXADDR,          /* highaddr */
1990                     NULL, NULL,                 /* filter, filterarg */
1991                     SK_RX_RING_SZ,              /* maxsize */
1992                     1,                          /* nsegments */
1993                     SK_RX_RING_SZ,              /* maxsegsize */
1994                     0,                          /* flags */
1995                     NULL, NULL,                 /* lockfunc, lockarg */
1996                     &sc_if->sk_cdata.sk_rx_ring_tag);
1997         if (error != 0) {
1998                 device_printf(sc_if->sk_if_dev,
1999                     "failed to allocate Rx ring DMA tag\n");
2000                 goto fail;
2001         }
2002
2003         /* create tag for Tx buffers */
2004         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2005                     1, 0,                       /* algnmnt, boundary */
2006                     BUS_SPACE_MAXADDR,          /* lowaddr */
2007                     BUS_SPACE_MAXADDR,          /* highaddr */
2008                     NULL, NULL,                 /* filter, filterarg */
2009                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
2010                     SK_MAXTXSEGS,               /* nsegments */
2011                     MCLBYTES,                   /* maxsegsize */
2012                     0,                          /* flags */
2013                     NULL, NULL,                 /* lockfunc, lockarg */
2014                     &sc_if->sk_cdata.sk_tx_tag);
2015         if (error != 0) {
2016                 device_printf(sc_if->sk_if_dev,
2017                     "failed to allocate Tx DMA tag\n");
2018                 goto fail;
2019         }
2020
2021         /* create tag for Rx buffers */
2022         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2023                     1, 0,                       /* algnmnt, boundary */
2024                     BUS_SPACE_MAXADDR,          /* lowaddr */
2025                     BUS_SPACE_MAXADDR,          /* highaddr */
2026                     NULL, NULL,                 /* filter, filterarg */
2027                     MCLBYTES,                   /* maxsize */
2028                     1,                          /* nsegments */
2029                     MCLBYTES,                   /* maxsegsize */
2030                     0,                          /* flags */
2031                     NULL, NULL,                 /* lockfunc, lockarg */
2032                     &sc_if->sk_cdata.sk_rx_tag);
2033         if (error != 0) {
2034                 device_printf(sc_if->sk_if_dev,
2035                     "failed to allocate Rx DMA tag\n");
2036                 goto fail;
2037         }
2038
2039         /* allocate DMA'able memory and load the DMA map for Tx ring */
2040         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2041             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2042             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2043         if (error != 0) {
2044                 device_printf(sc_if->sk_if_dev,
2045                     "failed to allocate DMA'able memory for Tx ring\n");
2046                 goto fail;
2047         }
2048
2049         ctx.sk_busaddr = 0;
2050         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2051             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2052             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2053         if (error != 0) {
2054                 device_printf(sc_if->sk_if_dev,
2055                     "failed to load DMA'able memory for Tx ring\n");
2056                 goto fail;
2057         }
2058         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2059
2060         /* allocate DMA'able memory and load the DMA map for Rx ring */
2061         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2062             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2063             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2064         if (error != 0) {
2065                 device_printf(sc_if->sk_if_dev,
2066                     "failed to allocate DMA'able memory for Rx ring\n");
2067                 goto fail;
2068         }
2069
2070         ctx.sk_busaddr = 0;
2071         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2072             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2073             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2074         if (error != 0) {
2075                 device_printf(sc_if->sk_if_dev,
2076                     "failed to load DMA'able memory for Rx ring\n");
2077                 goto fail;
2078         }
2079         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2080
2081         /* create DMA maps for Tx buffers */
2082         for (i = 0; i < SK_TX_RING_CNT; i++) {
2083                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2084                 txd->tx_m = NULL;
2085                 txd->tx_dmamap = NULL;
2086                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2087                     &txd->tx_dmamap);
2088                 if (error != 0) {
2089                         device_printf(sc_if->sk_if_dev,
2090                             "failed to create Tx dmamap\n");
2091                         goto fail;
2092                 }
2093         }
2094
2095         /* create DMA maps for Rx buffers */
2096         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2097             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2098                 device_printf(sc_if->sk_if_dev,
2099                     "failed to create spare Rx dmamap\n");
2100                 goto fail;
2101         }
2102         for (i = 0; i < SK_RX_RING_CNT; i++) {
2103                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2104                 rxd->rx_m = NULL;
2105                 rxd->rx_dmamap = NULL;
2106                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2107                     &rxd->rx_dmamap);
2108                 if (error != 0) {
2109                         device_printf(sc_if->sk_if_dev,
2110                             "failed to create Rx dmamap\n");
2111                         goto fail;
2112                 }
2113         }
2114
2115 fail:
2116         return (error);
2117 }
2118
2119 static int
2120 sk_dma_jumbo_alloc(sc_if)
2121         struct sk_if_softc      *sc_if;
2122 {
2123         struct sk_dmamap_arg    ctx;
2124         struct sk_rxdesc        *jrxd;
2125         int                     error, i;
2126
2127         if (jumbo_disable != 0) {
2128                 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2129                 sc_if->sk_jumbo_disable = 1;
2130                 return (0);
2131         }
2132         /* create tag for jumbo Rx ring */
2133         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2134                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2135                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2136                     BUS_SPACE_MAXADDR,          /* highaddr */
2137                     NULL, NULL,                 /* filter, filterarg */
2138                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2139                     1,                          /* nsegments */
2140                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2141                     0,                          /* flags */
2142                     NULL, NULL,                 /* lockfunc, lockarg */
2143                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2144         if (error != 0) {
2145                 device_printf(sc_if->sk_if_dev,
2146                     "failed to allocate jumbo Rx ring DMA tag\n");
2147                 goto jumbo_fail;
2148         }
2149
2150         /* create tag for jumbo Rx buffers */
2151         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2152                     1, 0,                       /* algnmnt, boundary */
2153                     BUS_SPACE_MAXADDR,          /* lowaddr */
2154                     BUS_SPACE_MAXADDR,          /* highaddr */
2155                     NULL, NULL,                 /* filter, filterarg */
2156                     MJUM9BYTES,                 /* maxsize */
2157                     1,                          /* nsegments */
2158                     MJUM9BYTES,                 /* maxsegsize */
2159                     0,                          /* flags */
2160                     NULL, NULL,                 /* lockfunc, lockarg */
2161                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2162         if (error != 0) {
2163                 device_printf(sc_if->sk_if_dev,
2164                     "failed to allocate jumbo Rx DMA tag\n");
2165                 goto jumbo_fail;
2166         }
2167
2168         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2169         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2170             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2171             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2172             &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2173         if (error != 0) {
2174                 device_printf(sc_if->sk_if_dev,
2175                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2176                 goto jumbo_fail;
2177         }
2178
2179         ctx.sk_busaddr = 0;
2180         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2181             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2182             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2183             &ctx, BUS_DMA_NOWAIT);
2184         if (error != 0) {
2185                 device_printf(sc_if->sk_if_dev,
2186                     "failed to load DMA'able memory for jumbo Rx ring\n");
2187                 goto jumbo_fail;
2188         }
2189         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2190
2191         /* create DMA maps for jumbo Rx buffers */
2192         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2193             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2194                 device_printf(sc_if->sk_if_dev,
2195                     "failed to create spare jumbo Rx dmamap\n");
2196                 goto jumbo_fail;
2197         }
2198         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2199                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2200                 jrxd->rx_m = NULL;
2201                 jrxd->rx_dmamap = NULL;
2202                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2203                     &jrxd->rx_dmamap);
2204                 if (error != 0) {
2205                         device_printf(sc_if->sk_if_dev,
2206                             "failed to create jumbo Rx dmamap\n");
2207                         goto jumbo_fail;
2208                 }
2209         }
2210
2211         return (0);
2212
2213 jumbo_fail:
2214         sk_dma_jumbo_free(sc_if);
2215         device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2216             "resource shortage\n");
2217         sc_if->sk_jumbo_disable = 1;
2218         return (0);
2219 }
2220
2221 static void
2222 sk_dma_free(sc_if)
2223         struct sk_if_softc      *sc_if;
2224 {
2225         struct sk_txdesc        *txd;
2226         struct sk_rxdesc        *rxd;
2227         int                     i;
2228
2229         /* Tx ring */
2230         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2231                 if (sc_if->sk_cdata.sk_tx_ring_map)
2232                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2233                             sc_if->sk_cdata.sk_tx_ring_map);
2234                 if (sc_if->sk_cdata.sk_tx_ring_map &&
2235                     sc_if->sk_rdata.sk_tx_ring)
2236                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2237                             sc_if->sk_rdata.sk_tx_ring,
2238                             sc_if->sk_cdata.sk_tx_ring_map);
2239                 sc_if->sk_rdata.sk_tx_ring = NULL;
2240                 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2241                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2242                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2243         }
2244         /* Rx ring */
2245         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2246                 if (sc_if->sk_cdata.sk_rx_ring_map)
2247                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2248                             sc_if->sk_cdata.sk_rx_ring_map);
2249                 if (sc_if->sk_cdata.sk_rx_ring_map &&
2250                     sc_if->sk_rdata.sk_rx_ring)
2251                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2252                             sc_if->sk_rdata.sk_rx_ring,
2253                             sc_if->sk_cdata.sk_rx_ring_map);
2254                 sc_if->sk_rdata.sk_rx_ring = NULL;
2255                 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2256                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2257                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2258         }
2259         /* Tx buffers */
2260         if (sc_if->sk_cdata.sk_tx_tag) {
2261                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2262                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2263                         if (txd->tx_dmamap) {
2264                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2265                                     txd->tx_dmamap);
2266                                 txd->tx_dmamap = NULL;
2267                         }
2268                 }
2269                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2270                 sc_if->sk_cdata.sk_tx_tag = NULL;
2271         }
2272         /* Rx buffers */
2273         if (sc_if->sk_cdata.sk_rx_tag) {
2274                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2275                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2276                         if (rxd->rx_dmamap) {
2277                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2278                                     rxd->rx_dmamap);
2279                                 rxd->rx_dmamap = NULL;
2280                         }
2281                 }
2282                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2283                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2284                             sc_if->sk_cdata.sk_rx_sparemap);
2285                         sc_if->sk_cdata.sk_rx_sparemap = NULL;
2286                 }
2287                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2288                 sc_if->sk_cdata.sk_rx_tag = NULL;
2289         }
2290
2291         if (sc_if->sk_cdata.sk_parent_tag) {
2292                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2293                 sc_if->sk_cdata.sk_parent_tag = NULL;
2294         }
2295 }
2296
2297 static void
2298 sk_dma_jumbo_free(sc_if)
2299         struct sk_if_softc      *sc_if;
2300 {
2301         struct sk_rxdesc        *jrxd;
2302         int                     i;
2303
2304         /* jumbo Rx ring */
2305         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2306                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2307                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2308                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2309                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2310                     sc_if->sk_rdata.sk_jumbo_rx_ring)
2311                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2312                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2313                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2314                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2315                 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2316                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2317                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2318         }
2319
2320         /* jumbo Rx buffers */
2321         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2322                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2323                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2324                         if (jrxd->rx_dmamap) {
2325                                 bus_dmamap_destroy(
2326                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2327                                     jrxd->rx_dmamap);
2328                                 jrxd->rx_dmamap = NULL;
2329                         }
2330                 }
2331                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2332                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2333                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2334                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2335                 }
2336                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2337                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2338         }
2339 }
2340
2341 static void
2342 sk_txcksum(ifp, m, f)
2343         struct ifnet            *ifp;
2344         struct mbuf             *m;
2345         struct sk_tx_desc       *f;
2346 {
2347         struct ip               *ip;
2348         u_int16_t               offset;
2349         u_int8_t                *p;
2350
2351         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2352         for(; m && m->m_len == 0; m = m->m_next)
2353                 ;
2354         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2355                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2356                 /* checksum may be corrupted */
2357                 goto sendit;
2358         }
2359         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2360                 if (m->m_len != ETHER_HDR_LEN) {
2361                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2362                             __func__);
2363                         /* checksum may be corrupted */
2364                         goto sendit;
2365                 }
2366                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2367                         ;
2368                 if (m == NULL) {
2369                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2370                         /* checksum may be corrupted */
2371                         goto sendit;
2372                 }
2373                 ip = mtod(m, struct ip *);
2374         } else {
2375                 p = mtod(m, u_int8_t *);
2376                 p += ETHER_HDR_LEN;
2377                 ip = (struct ip *)p;
2378         }
2379         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2380
2381 sendit:
2382         f->sk_csum_startval = 0;
2383         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2384             (offset << 16));
2385 }
2386
2387 static int
2388 sk_encap(sc_if, m_head)
2389         struct sk_if_softc      *sc_if;
2390         struct mbuf             **m_head;
2391 {
2392         struct sk_txdesc        *txd;
2393         struct sk_tx_desc       *f = NULL;
2394         struct mbuf             *m;
2395         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2396         u_int32_t               cflags, frag, si, sk_ctl;
2397         int                     error, i, nseg;
2398
2399         SK_IF_LOCK_ASSERT(sc_if);
2400
2401         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2402                 return (ENOBUFS);
2403
2404         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2405             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2406         if (error == EFBIG) {
2407                 m = m_defrag(*m_head, M_NOWAIT);
2408                 if (m == NULL) {
2409                         m_freem(*m_head);
2410                         *m_head = NULL;
2411                         return (ENOMEM);
2412                 }
2413                 *m_head = m;
2414                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2415                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2416                 if (error != 0) {
2417                         m_freem(*m_head);
2418                         *m_head = NULL;
2419                         return (error);
2420                 }
2421         } else if (error != 0)
2422                 return (error);
2423         if (nseg == 0) {
2424                 m_freem(*m_head);
2425                 *m_head = NULL;
2426                 return (EIO);
2427         }
2428         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2429                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2430                 return (ENOBUFS);
2431         }
2432
2433         m = *m_head;
2434         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2435                 cflags = SK_OPCODE_CSUM;
2436         else
2437                 cflags = SK_OPCODE_DEFAULT;
2438         si = frag = sc_if->sk_cdata.sk_tx_prod;
2439         for (i = 0; i < nseg; i++) {
2440                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2441                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2442                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2443                 sk_ctl = txsegs[i].ds_len | cflags;
2444                 if (i == 0) {
2445                         if (cflags == SK_OPCODE_CSUM)
2446                                 sk_txcksum(sc_if->sk_ifp, m, f);
2447                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2448                 } else
2449                         sk_ctl |= SK_TXCTL_OWN;
2450                 f->sk_ctl = htole32(sk_ctl);
2451                 sc_if->sk_cdata.sk_tx_cnt++;
2452                 SK_INC(frag, SK_TX_RING_CNT);
2453         }
2454         sc_if->sk_cdata.sk_tx_prod = frag;
2455
2456         /* set EOF on the last desciptor */
2457         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2458         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2459         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2460
2461         /* turn the first descriptor ownership to NIC */
2462         f = &sc_if->sk_rdata.sk_tx_ring[si];
2463         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2464
2465         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2466         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2467         txd->tx_m = m;
2468
2469         /* sync descriptors */
2470         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2471             BUS_DMASYNC_PREWRITE);
2472         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2473             sc_if->sk_cdata.sk_tx_ring_map,
2474             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2475
2476         return (0);
2477 }
2478
2479 static void
2480 sk_start(ifp)
2481         struct ifnet            *ifp;
2482 {
2483         struct sk_if_softc *sc_if;
2484
2485         sc_if = ifp->if_softc;
2486
2487         SK_IF_LOCK(sc_if);
2488         sk_start_locked(ifp);
2489         SK_IF_UNLOCK(sc_if);
2490
2491         return;
2492 }
2493
2494 static void
2495 sk_start_locked(ifp)
2496         struct ifnet            *ifp;
2497 {
2498         struct sk_softc         *sc;
2499         struct sk_if_softc      *sc_if;
2500         struct mbuf             *m_head;
2501         int                     enq;
2502
2503         sc_if = ifp->if_softc;
2504         sc = sc_if->sk_softc;
2505
2506         SK_IF_LOCK_ASSERT(sc_if);
2507
2508         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2509             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2510                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2511                 if (m_head == NULL)
2512                         break;
2513
2514                 /*
2515                  * Pack the data into the transmit ring. If we
2516                  * don't have room, set the OACTIVE flag and wait
2517                  * for the NIC to drain the ring.
2518                  */
2519                 if (sk_encap(sc_if, &m_head)) {
2520                         if (m_head == NULL)
2521                                 break;
2522                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2523                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2524                         break;
2525                 }
2526
2527                 enq++;
2528                 /*
2529                  * If there's a BPF listener, bounce a copy of this frame
2530                  * to him.
2531                  */
2532                 BPF_MTAP(ifp, m_head);
2533         }
2534
2535         if (enq > 0) {
2536                 /* Transmit */
2537                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2538
2539                 /* Set a timeout in case the chip goes out to lunch. */
2540                 sc_if->sk_watchdog_timer = 5;
2541         }
2542 }
2543
2544
2545 static void
2546 sk_watchdog(arg)
2547         void                    *arg;
2548 {
2549         struct sk_if_softc      *sc_if;
2550         struct ifnet            *ifp;
2551
2552         ifp = arg;
2553         sc_if = ifp->if_softc;
2554
2555         SK_IF_LOCK_ASSERT(sc_if);
2556
2557         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2558                 goto done;
2559
2560         /*
2561          * Reclaim first as there is a possibility of losing Tx completion
2562          * interrupts.
2563          */
2564         sk_txeof(sc_if);
2565         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2566                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2567                 ifp->if_oerrors++;
2568                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2569                 sk_init_locked(sc_if);
2570         }
2571
2572 done:
2573         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2574
2575         return;
2576 }
2577
2578 static int
2579 skc_shutdown(dev)
2580         device_t                dev;
2581 {
2582         struct sk_softc         *sc;
2583
2584         sc = device_get_softc(dev);
2585         SK_LOCK(sc);
2586
2587         /* Turn off the 'driver is loaded' LED. */
2588         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2589
2590         /*
2591          * Reset the GEnesis controller. Doing this should also
2592          * assert the resets on the attached XMAC(s).
2593          */
2594         sk_reset(sc);
2595         SK_UNLOCK(sc);
2596
2597         return (0);
2598 }
2599
2600 static int
2601 skc_suspend(dev)
2602         device_t                dev;
2603 {
2604         struct sk_softc         *sc;
2605         struct sk_if_softc      *sc_if0, *sc_if1;
2606         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2607
2608         sc = device_get_softc(dev);
2609
2610         SK_LOCK(sc);
2611
2612         sc_if0 = sc->sk_if[SK_PORT_A];
2613         sc_if1 = sc->sk_if[SK_PORT_B];
2614         if (sc_if0 != NULL)
2615                 ifp0 = sc_if0->sk_ifp;
2616         if (sc_if1 != NULL)
2617                 ifp1 = sc_if1->sk_ifp;
2618         if (ifp0 != NULL)
2619                 sk_stop(sc_if0);
2620         if (ifp1 != NULL)
2621                 sk_stop(sc_if1);
2622         sc->sk_suspended = 1;
2623
2624         SK_UNLOCK(sc);
2625
2626         return (0);
2627 }
2628
2629 static int
2630 skc_resume(dev)
2631         device_t                dev;
2632 {
2633         struct sk_softc         *sc;
2634         struct sk_if_softc      *sc_if0, *sc_if1;
2635         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2636
2637         sc = device_get_softc(dev);
2638
2639         SK_LOCK(sc);
2640
2641         sc_if0 = sc->sk_if[SK_PORT_A];
2642         sc_if1 = sc->sk_if[SK_PORT_B];
2643         if (sc_if0 != NULL)
2644                 ifp0 = sc_if0->sk_ifp;
2645         if (sc_if1 != NULL)
2646                 ifp1 = sc_if1->sk_ifp;
2647         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2648                 sk_init_locked(sc_if0);
2649         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2650                 sk_init_locked(sc_if1);
2651         sc->sk_suspended = 0;
2652
2653         SK_UNLOCK(sc);
2654
2655         return (0);
2656 }
2657
2658 /*
2659  * According to the data sheet from SK-NET GENESIS the hardware can compute
2660  * two Rx checksums at the same time(Each checksum start position is
2661  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2662  * does not work at least on my Yukon hardware. I tried every possible ways
2663  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2664  * checksum offload was disabled at the moment and only IP checksum offload
2665  * was enabled.
2666  * As nomral IP header size is 20 bytes I can't expect it would give an
2667  * increase in throughput. However it seems it doesn't hurt performance in
2668  * my testing. If there is a more detailed information for checksum secret
2669  * of the hardware in question please contact yongari@FreeBSD.org to add
2670  * TCP/UDP checksum offload support.
2671  */
2672 static __inline void
2673 sk_rxcksum(ifp, m, csum)
2674         struct ifnet            *ifp;
2675         struct mbuf             *m;
2676         u_int32_t               csum;
2677 {
2678         struct ether_header     *eh;
2679         struct ip               *ip;
2680         int32_t                 hlen, len, pktlen;
2681         u_int16_t               csum1, csum2, ipcsum;
2682
2683         pktlen = m->m_pkthdr.len;
2684         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2685                 return;
2686         eh = mtod(m, struct ether_header *);
2687         if (eh->ether_type != htons(ETHERTYPE_IP))
2688                 return;
2689         ip = (struct ip *)(eh + 1);
2690         if (ip->ip_v != IPVERSION)
2691                 return;
2692         hlen = ip->ip_hl << 2;
2693         pktlen -= sizeof(struct ether_header);
2694         if (hlen < sizeof(struct ip))
2695                 return;
2696         if (ntohs(ip->ip_len) < hlen)
2697                 return;
2698         if (ntohs(ip->ip_len) != pktlen)
2699                 return;
2700
2701         csum1 = htons(csum & 0xffff);
2702         csum2 = htons((csum >> 16) & 0xffff);
2703         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2704         /* checksum fixup for IP options */
2705         len = hlen - sizeof(struct ip);
2706         if (len > 0) {
2707                 /*
2708                  * If the second checksum value is correct we can compute IP
2709                  * checksum with simple math. Unfortunately the second checksum
2710                  * value is wrong so we can't verify the checksum from the
2711                  * value(It seems there is some magic here to get correct
2712                  * value). If the second checksum value is correct it also
2713                  * means we can get TCP/UDP checksum) here. However, it still
2714                  * needs pseudo header checksum calculation due to hardware
2715                  * limitations.
2716                  */
2717                 return;
2718         }
2719         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2720         if (ipcsum == 0xffff)
2721                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2722 }
2723
2724 static __inline int
2725 sk_rxvalid(sc, stat, len)
2726         struct sk_softc         *sc;
2727         u_int32_t               stat, len;
2728 {
2729
2730         if (sc->sk_type == SK_GENESIS) {
2731                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2732                     XM_RXSTAT_BYTES(stat) != len)
2733                         return (0);
2734         } else {
2735                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2736                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2737                     YU_RXSTAT_JABBER)) != 0 ||
2738                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2739                     YU_RXSTAT_BYTES(stat) != len)
2740                         return (0);
2741         }
2742
2743         return (1);
2744 }
2745
2746 static void
2747 sk_rxeof(sc_if)
2748         struct sk_if_softc      *sc_if;
2749 {
2750         struct sk_softc         *sc;
2751         struct mbuf             *m;
2752         struct ifnet            *ifp;
2753         struct sk_rx_desc       *cur_rx;
2754         struct sk_rxdesc        *rxd;
2755         int                     cons, prog;
2756         u_int32_t               csum, rxstat, sk_ctl;
2757
2758         sc = sc_if->sk_softc;
2759         ifp = sc_if->sk_ifp;
2760
2761         SK_IF_LOCK_ASSERT(sc_if);
2762
2763         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2764             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2765
2766         prog = 0;
2767         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2768             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2769                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2770                 sk_ctl = le32toh(cur_rx->sk_ctl);
2771                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2772                         break;
2773                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2774                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2775
2776                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2777                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2778                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2779                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2780                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2781                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2782                         ifp->if_ierrors++;
2783                         sk_discard_rxbuf(sc_if, cons);
2784                         continue;
2785                 }
2786
2787                 m = rxd->rx_m;
2788                 csum = le32toh(cur_rx->sk_csum);
2789                 if (sk_newbuf(sc_if, cons) != 0) {
2790                         ifp->if_iqdrops++;
2791                         /* reuse old buffer */
2792                         sk_discard_rxbuf(sc_if, cons);
2793                         continue;
2794                 }
2795                 m->m_pkthdr.rcvif = ifp;
2796                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2797                 ifp->if_ipackets++;
2798                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2799                         sk_rxcksum(ifp, m, csum);
2800                 SK_IF_UNLOCK(sc_if);
2801                 (*ifp->if_input)(ifp, m);
2802                 SK_IF_LOCK(sc_if);
2803         }
2804
2805         if (prog > 0) {
2806                 sc_if->sk_cdata.sk_rx_cons = cons;
2807                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2808                     sc_if->sk_cdata.sk_rx_ring_map,
2809                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2810         }
2811 }
2812
2813 static void
2814 sk_jumbo_rxeof(sc_if)
2815         struct sk_if_softc      *sc_if;
2816 {
2817         struct sk_softc         *sc;
2818         struct mbuf             *m;
2819         struct ifnet            *ifp;
2820         struct sk_rx_desc       *cur_rx;
2821         struct sk_rxdesc        *jrxd;
2822         int                     cons, prog;
2823         u_int32_t               csum, rxstat, sk_ctl;
2824
2825         sc = sc_if->sk_softc;
2826         ifp = sc_if->sk_ifp;
2827
2828         SK_IF_LOCK_ASSERT(sc_if);
2829
2830         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2831             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2832
2833         prog = 0;
2834         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2835             prog < SK_JUMBO_RX_RING_CNT;
2836             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2837                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2838                 sk_ctl = le32toh(cur_rx->sk_ctl);
2839                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2840                         break;
2841                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2842                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2843
2844                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2845                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2846                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2847                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2848                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2849                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2850                         ifp->if_ierrors++;
2851                         sk_discard_jumbo_rxbuf(sc_if, cons);
2852                         continue;
2853                 }
2854
2855                 m = jrxd->rx_m;
2856                 csum = le32toh(cur_rx->sk_csum);
2857                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2858                         ifp->if_iqdrops++;
2859                         /* reuse old buffer */
2860                         sk_discard_jumbo_rxbuf(sc_if, cons);
2861                         continue;
2862                 }
2863                 m->m_pkthdr.rcvif = ifp;
2864                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2865                 ifp->if_ipackets++;
2866                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2867                         sk_rxcksum(ifp, m, csum);
2868                 SK_IF_UNLOCK(sc_if);
2869                 (*ifp->if_input)(ifp, m);
2870                 SK_IF_LOCK(sc_if);
2871         }
2872
2873         if (prog > 0) {
2874                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2875                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2876                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2877                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2878         }
2879 }
2880
2881 static void
2882 sk_txeof(sc_if)
2883         struct sk_if_softc      *sc_if;
2884 {
2885         struct sk_softc         *sc;
2886         struct sk_txdesc        *txd;
2887         struct sk_tx_desc       *cur_tx;
2888         struct ifnet            *ifp;
2889         u_int32_t               idx, sk_ctl;
2890
2891         sc = sc_if->sk_softc;
2892         ifp = sc_if->sk_ifp;
2893
2894         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2895         if (txd == NULL)
2896                 return;
2897         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2898             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2899         /*
2900          * Go through our tx ring and free mbufs for those
2901          * frames that have been sent.
2902          */
2903         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2904                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2905                         break;
2906                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2907                 sk_ctl = le32toh(cur_tx->sk_ctl);
2908                 if (sk_ctl & SK_TXCTL_OWN)
2909                         break;
2910                 sc_if->sk_cdata.sk_tx_cnt--;
2911                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2912                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2913                         continue;
2914                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2915                     BUS_DMASYNC_POSTWRITE);
2916                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2917
2918                 ifp->if_opackets++;
2919                 m_freem(txd->tx_m);
2920                 txd->tx_m = NULL;
2921                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2922                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2923                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2924         }
2925         sc_if->sk_cdata.sk_tx_cons = idx;
2926         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2927
2928         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2929             sc_if->sk_cdata.sk_tx_ring_map,
2930             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2931 }
2932
2933 static void
2934 sk_tick(xsc_if)
2935         void                    *xsc_if;
2936 {
2937         struct sk_if_softc      *sc_if;
2938         struct mii_data         *mii;
2939         struct ifnet            *ifp;
2940         int                     i;
2941
2942         sc_if = xsc_if;
2943         ifp = sc_if->sk_ifp;
2944         mii = device_get_softc(sc_if->sk_miibus);
2945
2946         if (!(ifp->if_flags & IFF_UP))
2947                 return;
2948
2949         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2950                 sk_intr_bcom(sc_if);
2951                 return;
2952         }
2953
2954         /*
2955          * According to SysKonnect, the correct way to verify that
2956          * the link has come back up is to poll bit 0 of the GPIO
2957          * register three times. This pin has the signal from the
2958          * link_sync pin connected to it; if we read the same link
2959          * state 3 times in a row, we know the link is up.
2960          */
2961         for (i = 0; i < 3; i++) {
2962                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2963                         break;
2964         }
2965
2966         if (i != 3) {
2967                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2968                 return;
2969         }
2970
2971         /* Turn the GP0 interrupt back on. */
2972         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2973         SK_XM_READ_2(sc_if, XM_ISR);
2974         mii_tick(mii);
2975         callout_stop(&sc_if->sk_tick_ch);
2976 }
2977
2978 static void
2979 sk_yukon_tick(xsc_if)
2980         void                    *xsc_if;
2981 {
2982         struct sk_if_softc      *sc_if;
2983         struct mii_data         *mii;
2984
2985         sc_if = xsc_if;
2986         mii = device_get_softc(sc_if->sk_miibus);
2987
2988         mii_tick(mii);
2989         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2990 }
2991
2992 static void
2993 sk_intr_bcom(sc_if)
2994         struct sk_if_softc      *sc_if;
2995 {
2996         struct mii_data         *mii;
2997         struct ifnet            *ifp;
2998         int                     status;
2999         mii = device_get_softc(sc_if->sk_miibus);
3000         ifp = sc_if->sk_ifp;
3001
3002         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3003
3004         /*
3005          * Read the PHY interrupt register to make sure
3006          * we clear any pending interrupts.
3007          */
3008         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3009
3010         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3011                 sk_init_xmac(sc_if);
3012                 return;
3013         }
3014
3015         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3016                 int                     lstat;
3017                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3018                     BRGPHY_MII_AUXSTS);
3019
3020                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3021                         mii_mediachg(mii);
3022                         /* Turn off the link LED. */
3023                         SK_IF_WRITE_1(sc_if, 0,
3024                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3025                         sc_if->sk_link = 0;
3026                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3027                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3028                             BRGPHY_MII_IMR, 0xFF00);
3029                         mii_tick(mii);
3030                         sc_if->sk_link = 1;
3031                         /* Turn on the link LED. */
3032                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3033                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3034                             SK_LINKLED_BLINK_OFF);
3035                 } else {
3036                         mii_tick(mii);
3037                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3038                 }
3039         }
3040
3041         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3042
3043         return;
3044 }
3045
3046 static void
3047 sk_intr_xmac(sc_if)
3048         struct sk_if_softc      *sc_if;
3049 {
3050         struct sk_softc         *sc;
3051         u_int16_t               status;
3052
3053         sc = sc_if->sk_softc;
3054         status = SK_XM_READ_2(sc_if, XM_ISR);
3055
3056         /*
3057          * Link has gone down. Start MII tick timeout to
3058          * watch for link resync.
3059          */
3060         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3061                 if (status & XM_ISR_GP0_SET) {
3062                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3063                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3064                 }
3065
3066                 if (status & XM_ISR_AUTONEG_DONE) {
3067                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3068                 }
3069         }
3070
3071         if (status & XM_IMR_TX_UNDERRUN)
3072                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3073
3074         if (status & XM_IMR_RX_OVERRUN)
3075                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3076
3077         status = SK_XM_READ_2(sc_if, XM_ISR);
3078
3079         return;
3080 }
3081
3082 static void
3083 sk_intr_yukon(sc_if)
3084         struct sk_if_softc      *sc_if;
3085 {
3086         u_int8_t status;
3087
3088         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3089         /* RX overrun */
3090         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3091                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3092                     SK_RFCTL_RX_FIFO_OVER);
3093         }
3094         /* TX underrun */
3095         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3096                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3097                     SK_TFCTL_TX_FIFO_UNDER);
3098         }
3099 }
3100
3101 static void
3102 sk_intr(xsc)
3103         void                    *xsc;
3104 {
3105         struct sk_softc         *sc = xsc;
3106         struct sk_if_softc      *sc_if0, *sc_if1;
3107         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3108         u_int32_t               status;
3109
3110         SK_LOCK(sc);
3111
3112         status = CSR_READ_4(sc, SK_ISSR);
3113         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3114                 goto done_locked;
3115
3116         sc_if0 = sc->sk_if[SK_PORT_A];
3117         sc_if1 = sc->sk_if[SK_PORT_B];
3118
3119         if (sc_if0 != NULL)
3120                 ifp0 = sc_if0->sk_ifp;
3121         if (sc_if1 != NULL)
3122                 ifp1 = sc_if1->sk_ifp;
3123
3124         for (; (status &= sc->sk_intrmask) != 0;) {
3125                 /* Handle receive interrupts first. */
3126                 if (status & SK_ISR_RX1_EOF) {
3127                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3128                                 sk_jumbo_rxeof(sc_if0);
3129                         else
3130                                 sk_rxeof(sc_if0);
3131                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3132                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3133                 }
3134                 if (status & SK_ISR_RX2_EOF) {
3135                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3136                                 sk_jumbo_rxeof(sc_if1);
3137                         else
3138                                 sk_rxeof(sc_if1);
3139                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3140                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3141                 }
3142
3143                 /* Then transmit interrupts. */
3144                 if (status & SK_ISR_TX1_S_EOF) {
3145                         sk_txeof(sc_if0);
3146                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3147                 }
3148                 if (status & SK_ISR_TX2_S_EOF) {
3149                         sk_txeof(sc_if1);
3150                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3151                 }
3152
3153                 /* Then MAC interrupts. */
3154                 if (status & SK_ISR_MAC1 &&
3155                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3156                         if (sc->sk_type == SK_GENESIS)
3157                                 sk_intr_xmac(sc_if0);
3158                         else
3159                                 sk_intr_yukon(sc_if0);
3160                 }
3161
3162                 if (status & SK_ISR_MAC2 &&
3163                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3164                         if (sc->sk_type == SK_GENESIS)
3165                                 sk_intr_xmac(sc_if1);
3166                         else
3167                                 sk_intr_yukon(sc_if1);
3168                 }
3169
3170                 if (status & SK_ISR_EXTERNAL_REG) {
3171                         if (ifp0 != NULL &&
3172                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3173                                 sk_intr_bcom(sc_if0);
3174                         if (ifp1 != NULL &&
3175                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3176                                 sk_intr_bcom(sc_if1);
3177                 }
3178                 status = CSR_READ_4(sc, SK_ISSR);
3179         }
3180
3181         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3182
3183         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3184                 sk_start_locked(ifp0);
3185         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3186                 sk_start_locked(ifp1);
3187
3188 done_locked:
3189         SK_UNLOCK(sc);
3190 }
3191
3192 static void
3193 sk_init_xmac(sc_if)
3194         struct sk_if_softc      *sc_if;
3195 {
3196         struct sk_softc         *sc;
3197         struct ifnet            *ifp;
3198         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3199         static const struct sk_bcom_hack bhack[] = {
3200         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3201         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3202         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3203         { 0, 0 } };
3204
3205         SK_IF_LOCK_ASSERT(sc_if);
3206
3207         sc = sc_if->sk_softc;
3208         ifp = sc_if->sk_ifp;
3209
3210         /* Unreset the XMAC. */
3211         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3212         DELAY(1000);
3213
3214         /* Reset the XMAC's internal state. */
3215         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3216
3217         /* Save the XMAC II revision */
3218         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3219
3220         /*
3221          * Perform additional initialization for external PHYs,
3222          * namely for the 1000baseTX cards that use the XMAC's
3223          * GMII mode.
3224          */
3225         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3226                 int                     i = 0;
3227                 u_int32_t               val;
3228
3229                 /* Take PHY out of reset. */
3230                 val = sk_win_read_4(sc, SK_GPIO);
3231                 if (sc_if->sk_port == SK_PORT_A)
3232                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3233                 else
3234                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3235                 sk_win_write_4(sc, SK_GPIO, val);
3236
3237                 /* Enable GMII mode on the XMAC. */
3238                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3239
3240                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3241                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3242                 DELAY(10000);
3243                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3244                     BRGPHY_MII_IMR, 0xFFF0);
3245
3246                 /*
3247                  * Early versions of the BCM5400 apparently have
3248                  * a bug that requires them to have their reserved
3249                  * registers initialized to some magic values. I don't
3250                  * know what the numbers do, I'm just the messenger.
3251                  */
3252                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3253                     == 0x6041) {
3254                         while(bhack[i].reg) {
3255                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3256                                     bhack[i].reg, bhack[i].val);
3257                                 i++;
3258                         }
3259                 }
3260         }
3261
3262         /* Set station address */
3263         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3264         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3265         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3266         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3267         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3268
3269         if (ifp->if_flags & IFF_BROADCAST) {
3270                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3271         } else {
3272                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3273         }
3274
3275         /* We don't need the FCS appended to the packet. */
3276         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3277
3278         /* We want short frames padded to 60 bytes. */
3279         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3280
3281         /*
3282          * Enable the reception of all error frames. This is is
3283          * a necessary evil due to the design of the XMAC. The
3284          * XMAC's receive FIFO is only 8K in size, however jumbo
3285          * frames can be up to 9000 bytes in length. When bad
3286          * frame filtering is enabled, the XMAC's RX FIFO operates
3287          * in 'store and forward' mode. For this to work, the
3288          * entire frame has to fit into the FIFO, but that means
3289          * that jumbo frames larger than 8192 bytes will be
3290          * truncated. Disabling all bad frame filtering causes
3291          * the RX FIFO to operate in streaming mode, in which
3292          * case the XMAC will start transfering frames out of the
3293          * RX FIFO as soon as the FIFO threshold is reached.
3294          */
3295         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3296                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3297                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3298                     XM_MODE_RX_INRANGELEN);
3299                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3300         } else
3301                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3302
3303         /*
3304          * Bump up the transmit threshold. This helps hold off transmit
3305          * underruns when we're blasting traffic from both ports at once.
3306          */
3307         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3308
3309         /* Set Rx filter */
3310         sk_rxfilter_genesis(sc_if);
3311
3312         /* Clear and enable interrupts */
3313         SK_XM_READ_2(sc_if, XM_ISR);
3314         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3315                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3316         else
3317                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3318
3319         /* Configure MAC arbiter */
3320         switch(sc_if->sk_xmac_rev) {
3321         case XM_XMAC_REV_B2:
3322                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3323                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3324                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3325                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3326                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3327                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3328                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3329                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3330                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3331                 break;
3332         case XM_XMAC_REV_C1:
3333                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3334                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3335                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3336                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3337                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3338                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3339                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3340                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3341                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3342                 break;
3343         default:
3344                 break;
3345         }
3346         sk_win_write_2(sc, SK_MACARB_CTL,
3347             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3348
3349         sc_if->sk_link = 1;
3350
3351         return;
3352 }
3353
3354 static void
3355 sk_init_yukon(sc_if)
3356         struct sk_if_softc      *sc_if;
3357 {
3358         u_int32_t               phy, v;
3359         u_int16_t               reg;
3360         struct sk_softc         *sc;
3361         struct ifnet            *ifp;
3362         u_int8_t                *eaddr;
3363         int                     i;
3364
3365         SK_IF_LOCK_ASSERT(sc_if);
3366
3367         sc = sc_if->sk_softc;
3368         ifp = sc_if->sk_ifp;
3369
3370         if (sc->sk_type == SK_YUKON_LITE &&
3371             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3372                 /*
3373                  * Workaround code for COMA mode, set PHY reset.
3374                  * Otherwise it will not correctly take chip out of
3375                  * powerdown (coma)
3376                  */
3377                 v = sk_win_read_4(sc, SK_GPIO);
3378                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3379                 sk_win_write_4(sc, SK_GPIO, v);
3380         }
3381
3382         /* GMAC and GPHY Reset */
3383         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3384         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3385         DELAY(1000);
3386
3387         if (sc->sk_type == SK_YUKON_LITE &&
3388             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3389                 /*
3390                  * Workaround code for COMA mode, clear PHY reset
3391                  */
3392                 v = sk_win_read_4(sc, SK_GPIO);
3393                 v |= SK_GPIO_DIR9;
3394                 v &= ~SK_GPIO_DAT9;
3395                 sk_win_write_4(sc, SK_GPIO, v);
3396         }
3397
3398         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3399                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3400
3401         if (sc->sk_coppertype)
3402                 phy |= SK_GPHY_COPPER;
3403         else
3404                 phy |= SK_GPHY_FIBER;
3405
3406         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3407         DELAY(1000);
3408         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3409         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3410                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3411
3412         /* unused read of the interrupt source register */
3413         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3414
3415         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3416
3417         /* MIB Counter Clear Mode set */
3418         reg |= YU_PAR_MIB_CLR;
3419         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3420
3421         /* MIB Counter Clear Mode clear */
3422         reg &= ~YU_PAR_MIB_CLR;
3423         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3424
3425         /* receive control reg */
3426         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3427
3428         /* transmit parameter register */
3429         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3430                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3431
3432         /* serial mode register */
3433         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3434         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3435                 reg |= YU_SMR_MFL_JUMBO;
3436         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3437
3438         /* Setup Yukon's station address */
3439         eaddr = IF_LLADDR(sc_if->sk_ifp);
3440         for (i = 0; i < 3; i++)
3441                 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3442                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3443         /* Set GMAC source address of flow control. */
3444         for (i = 0; i < 3; i++)
3445                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3446                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3447         /* Set GMAC virtual address. */
3448         for (i = 0; i < 3; i++)
3449                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3450                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3451
3452         /* Set Rx filter */
3453         sk_rxfilter_yukon(sc_if);
3454
3455         /* enable interrupt mask for counter overflows */
3456         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3457         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3458         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3459
3460         /* Configure RX MAC FIFO Flush Mask */
3461         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3462             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3463             YU_RXSTAT_JABBER;
3464         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3465
3466         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3467         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3468                 v = SK_TFCTL_OPERATION_ON;
3469         else
3470                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3471         /* Configure RX MAC FIFO */
3472         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3473         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3474
3475         /* Increase flush threshould to 64 bytes */
3476         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3477             SK_RFCTL_FIFO_THRESHOLD + 1);
3478
3479         /* Configure TX MAC FIFO */
3480         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3481         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3482 }
3483
3484 /*
3485  * Note that to properly initialize any part of the GEnesis chip,
3486  * you first have to take it out of reset mode.
3487  */
3488 static void
3489 sk_init(xsc)
3490         void                    *xsc;
3491 {
3492         struct sk_if_softc      *sc_if = xsc;
3493
3494         SK_IF_LOCK(sc_if);
3495         sk_init_locked(sc_if);
3496         SK_IF_UNLOCK(sc_if);
3497
3498         return;
3499 }
3500
3501 static void
3502 sk_init_locked(sc_if)
3503         struct sk_if_softc      *sc_if;
3504 {
3505         struct sk_softc         *sc;
3506         struct ifnet            *ifp;
3507         struct mii_data         *mii;
3508         u_int16_t               reg;
3509         u_int32_t               imr;
3510         int                     error;
3511
3512         SK_IF_LOCK_ASSERT(sc_if);
3513
3514         ifp = sc_if->sk_ifp;
3515         sc = sc_if->sk_softc;
3516         mii = device_get_softc(sc_if->sk_miibus);
3517
3518         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3519                 return;
3520
3521         /* Cancel pending I/O and free all RX/TX buffers. */
3522         sk_stop(sc_if);
3523
3524         if (sc->sk_type == SK_GENESIS) {
3525                 /* Configure LINK_SYNC LED */
3526                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3527                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3528                         SK_LINKLED_LINKSYNC_ON);
3529
3530                 /* Configure RX LED */
3531                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3532                         SK_RXLEDCTL_COUNTER_START);
3533
3534                 /* Configure TX LED */
3535                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3536                         SK_TXLEDCTL_COUNTER_START);
3537         }
3538
3539         /*
3540          * Configure descriptor poll timer
3541          *
3542          * SK-NET GENESIS data sheet says that possibility of losing Start
3543          * transmit command due to CPU/cache related interim storage problems
3544          * under certain conditions. The document recommends a polling
3545          * mechanism to send a Start transmit command to initiate transfer
3546          * of ready descriptors regulary. To cope with this issue sk(4) now
3547          * enables descriptor poll timer to initiate descriptor processing
3548          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3549          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3550          * command instead of waiting for next descriptor polling time.
3551          * The same rule may apply to Rx side too but it seems that is not
3552          * needed at the moment.
3553          * Since sk(4) uses descriptor polling as a last resort there is no
3554          * need to set smaller polling time than maximum allowable one.
3555          */
3556         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3557
3558         /* Configure I2C registers */
3559
3560         /* Configure XMAC(s) */
3561         switch (sc->sk_type) {
3562         case SK_GENESIS:
3563                 sk_init_xmac(sc_if);
3564                 break;
3565         case SK_YUKON:
3566         case SK_YUKON_LITE:
3567         case SK_YUKON_LP:
3568                 sk_init_yukon(sc_if);
3569                 break;
3570         }
3571         mii_mediachg(mii);
3572
3573         if (sc->sk_type == SK_GENESIS) {
3574                 /* Configure MAC FIFOs */
3575                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3576                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3577                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3578
3579                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3580                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3581                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3582         }
3583
3584         /* Configure transmit arbiter(s) */
3585         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3586             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3587
3588         /* Configure RAMbuffers */
3589         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3590         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3591         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3592         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3593         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3594         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3595
3596         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3597         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3598         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3599         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3600         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3601         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3602         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3603
3604         /* Configure BMUs */
3605         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3606         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3607                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3608                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3609                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3610                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3611         } else {
3612                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3613                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3614                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3615                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3616         }
3617
3618         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3619         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3620             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3621         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3622             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3623
3624         /* Init descriptors */
3625         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3626                 error = sk_init_jumbo_rx_ring(sc_if);
3627         else
3628                 error = sk_init_rx_ring(sc_if);
3629         if (error != 0) {
3630                 device_printf(sc_if->sk_if_dev,
3631                     "initialization failed: no memory for rx buffers\n");
3632                 sk_stop(sc_if);
3633                 return;
3634         }
3635         sk_init_tx_ring(sc_if);
3636
3637         /* Set interrupt moderation if changed via sysctl. */
3638         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3639         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3640                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3641                     sc->sk_int_ticks));
3642                 if (bootverbose)
3643                         device_printf(sc_if->sk_if_dev,
3644                             "interrupt moderation is %d us.\n",
3645                             sc->sk_int_mod);
3646         }
3647
3648         /* Configure interrupt handling */
3649         CSR_READ_4(sc, SK_ISSR);
3650         if (sc_if->sk_port == SK_PORT_A)
3651                 sc->sk_intrmask |= SK_INTRS1;
3652         else
3653                 sc->sk_intrmask |= SK_INTRS2;
3654
3655         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3656
3657         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3658
3659         /* Start BMUs. */
3660         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3661
3662         switch(sc->sk_type) {
3663         case SK_GENESIS:
3664                 /* Enable XMACs TX and RX state machines */
3665                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3666                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3667                 break;
3668         case SK_YUKON:
3669         case SK_YUKON_LITE:
3670         case SK_YUKON_LP:
3671                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3672                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3673 #if 0
3674                 /* XXX disable 100Mbps and full duplex mode? */
3675                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3676 #endif
3677                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3678         }
3679
3680         /* Activate descriptor polling timer */
3681         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3682         /* start transfer of Tx descriptors */
3683         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3684
3685         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3686         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3687
3688         switch (sc->sk_type) {
3689         case SK_YUKON:
3690         case SK_YUKON_LITE:
3691         case SK_YUKON_LP:
3692                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3693                 break;
3694         }
3695
3696         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3697
3698         return;
3699 }
3700
3701 static void
3702 sk_stop(sc_if)
3703         struct sk_if_softc      *sc_if;
3704 {
3705         int                     i;
3706         struct sk_softc         *sc;
3707         struct sk_txdesc        *txd;
3708         struct sk_rxdesc        *rxd;
3709         struct sk_rxdesc        *jrxd;
3710         struct ifnet            *ifp;
3711         u_int32_t               val;
3712
3713         SK_IF_LOCK_ASSERT(sc_if);
3714         sc = sc_if->sk_softc;
3715         ifp = sc_if->sk_ifp;
3716
3717         callout_stop(&sc_if->sk_tick_ch);
3718         callout_stop(&sc_if->sk_watchdog_ch);
3719
3720         /* stop Tx descriptor polling timer */
3721         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3722         /* stop transfer of Tx descriptors */
3723         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3724         for (i = 0; i < SK_TIMEOUT; i++) {
3725                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3726                 if ((val & SK_TXBMU_TX_STOP) == 0)
3727                         break;
3728                 DELAY(1);
3729         }
3730         if (i == SK_TIMEOUT)
3731                 device_printf(sc_if->sk_if_dev,
3732                     "can not stop transfer of Tx descriptor\n");
3733         /* stop transfer of Rx descriptors */
3734         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3735         for (i = 0; i < SK_TIMEOUT; i++) {
3736                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3737                 if ((val & SK_RXBMU_RX_STOP) == 0)
3738                         break;
3739                 DELAY(1);
3740         }
3741         if (i == SK_TIMEOUT)
3742                 device_printf(sc_if->sk_if_dev,
3743                     "can not stop transfer of Rx descriptor\n");
3744
3745         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3746                 /* Put PHY back into reset. */
3747                 val = sk_win_read_4(sc, SK_GPIO);
3748                 if (sc_if->sk_port == SK_PORT_A) {
3749                         val |= SK_GPIO_DIR0;
3750                         val &= ~SK_GPIO_DAT0;
3751                 } else {
3752                         val |= SK_GPIO_DIR2;
3753                         val &= ~SK_GPIO_DAT2;
3754                 }
3755                 sk_win_write_4(sc, SK_GPIO, val);
3756         }
3757
3758         /* Turn off various components of this interface. */
3759         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3760         switch (sc->sk_type) {
3761         case SK_GENESIS:
3762                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3763                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3764                 break;
3765         case SK_YUKON:
3766         case SK_YUKON_LITE:
3767         case SK_YUKON_LP:
3768                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3769                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3770                 break;
3771         }
3772         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3773         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3774         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3775         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3776         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3777         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3778         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3779         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3780         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3781
3782         /* Disable interrupts */
3783         if (sc_if->sk_port == SK_PORT_A)
3784                 sc->sk_intrmask &= ~SK_INTRS1;
3785         else
3786                 sc->sk_intrmask &= ~SK_INTRS2;
3787         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3788
3789         SK_XM_READ_2(sc_if, XM_ISR);
3790         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3791
3792         /* Free RX and TX mbufs still in the queues. */
3793         for (i = 0; i < SK_RX_RING_CNT; i++) {
3794                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3795                 if (rxd->rx_m != NULL) {
3796                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3797                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3798                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3799                             rxd->rx_dmamap);
3800                         m_freem(rxd->rx_m);
3801                         rxd->rx_m = NULL;
3802                 }
3803         }
3804         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3805                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3806                 if (jrxd->rx_m != NULL) {
3807                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3808                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3809                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3810                             jrxd->rx_dmamap);
3811                         m_freem(jrxd->rx_m);
3812                         jrxd->rx_m = NULL;
3813                 }
3814         }
3815         for (i = 0; i < SK_TX_RING_CNT; i++) {
3816                 txd = &sc_if->sk_cdata.sk_txdesc[i];
3817                 if (txd->tx_m != NULL) {
3818                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3819                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3820                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3821                             txd->tx_dmamap);
3822                         m_freem(txd->tx_m);
3823                         txd->tx_m = NULL;
3824                 }
3825         }
3826
3827         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3828
3829         return;
3830 }
3831
3832 static int
3833 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3834 {
3835         int error, value;
3836
3837         if (!arg1)
3838                 return (EINVAL);
3839         value = *(int *)arg1;
3840         error = sysctl_handle_int(oidp, &value, 0, req);
3841         if (error || !req->newptr)
3842                 return (error);
3843         if (value < low || value > high)
3844                 return (EINVAL);
3845         *(int *)arg1 = value;
3846         return (0);
3847 }
3848
3849 static int
3850 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3851 {
3852         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3853 }