5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This file contains the driver for the ATMEGA series USB OTG Controller. This
31 * driver currently only supports the DCI mode of the USB hardware.
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
39 #include <sys/stdint.h>
40 #include <sys/stddef.h>
41 #include <sys/param.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/condvar.h>
51 #include <sys/sysctl.h>
53 #include <sys/unistd.h>
54 #include <sys/callout.h>
55 #include <sys/malloc.h>
58 #include <dev/usb/usb.h>
59 #include <dev/usb/usbdi.h>
61 #define USB_DEBUG_VAR atmegadci_debug
63 #include <dev/usb/usb_core.h>
64 #include <dev/usb/usb_debug.h>
65 #include <dev/usb/usb_busdma.h>
66 #include <dev/usb/usb_process.h>
67 #include <dev/usb/usb_transfer.h>
68 #include <dev/usb/usb_device.h>
69 #include <dev/usb/usb_hub.h>
70 #include <dev/usb/usb_util.h>
72 #include <dev/usb/usb_controller.h>
73 #include <dev/usb/usb_bus.h>
74 #include <dev/usb/controller/atmegadci.h>
76 #define ATMEGA_BUS2SC(bus) \
77 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
78 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
80 #define ATMEGA_PC2SC(pc) \
81 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
84 static int atmegadci_debug = 0;
86 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0,
88 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW,
89 &atmegadci_debug, 0, "ATMEGA DCI debug level");
92 #define ATMEGA_INTR_ENDPT 1
96 struct usb_bus_methods atmegadci_bus_methods;
97 struct usb_pipe_methods atmegadci_device_non_isoc_methods;
98 struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
100 static atmegadci_cmd_t atmegadci_setup_rx;
101 static atmegadci_cmd_t atmegadci_data_rx;
102 static atmegadci_cmd_t atmegadci_data_tx;
103 static atmegadci_cmd_t atmegadci_data_tx_sync;
104 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
105 static void atmegadci_do_poll(struct usb_bus *);
106 static void atmegadci_standard_done(struct usb_xfer *);
107 static void atmegadci_root_intr(struct atmegadci_softc *sc);
110 * Here is a list of what the chip supports:
112 static const struct usb_hw_ep_profile
113 atmegadci_ep_profile[2] = {
116 .max_in_frame_size = 64,
117 .max_out_frame_size = 64,
119 .support_control = 1,
122 .max_in_frame_size = 64,
123 .max_out_frame_size = 64,
126 .support_interrupt = 1,
127 .support_isochronous = 1,
134 atmegadci_get_hw_ep_profile(struct usb_device *udev,
135 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
138 *ppf = atmegadci_ep_profile;
139 else if (ep_addr < ATMEGA_EP_MAX)
140 *ppf = atmegadci_ep_profile + 1;
146 atmegadci_clocks_on(struct atmegadci_softc *sc)
148 if (sc->sc_flags.clocks_off &&
149 sc->sc_flags.port_powered) {
154 (sc->sc_clocks_on) (&sc->sc_bus);
156 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
158 ATMEGA_USBCON_OTGPADE |
159 ATMEGA_USBCON_VBUSTE);
161 sc->sc_flags.clocks_off = 0;
163 /* enable transceiver ? */
168 atmegadci_clocks_off(struct atmegadci_softc *sc)
170 if (!sc->sc_flags.clocks_off) {
174 /* disable Transceiver ? */
176 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
178 ATMEGA_USBCON_OTGPADE |
179 ATMEGA_USBCON_FRZCLK |
180 ATMEGA_USBCON_VBUSTE);
182 /* turn clocks off */
183 (sc->sc_clocks_off) (&sc->sc_bus);
185 sc->sc_flags.clocks_off = 1;
190 atmegadci_pull_up(struct atmegadci_softc *sc)
192 /* pullup D+, if possible */
194 if (!sc->sc_flags.d_pulled_up &&
195 sc->sc_flags.port_powered) {
196 sc->sc_flags.d_pulled_up = 1;
197 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
202 atmegadci_pull_down(struct atmegadci_softc *sc)
204 /* pulldown D+, if possible */
206 if (sc->sc_flags.d_pulled_up) {
207 sc->sc_flags.d_pulled_up = 0;
208 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
213 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
217 if (!sc->sc_flags.status_suspend) {
221 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
222 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
224 /* wait 8 milliseconds */
225 /* Wait for reset to complete. */
226 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
228 /* hardware should have cleared RMWKUP bit */
232 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
234 DPRINTFN(5, "addr=%d\n", addr);
236 addr |= ATMEGA_UDADDR_ADDEN;
238 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
242 atmegadci_setup_rx(struct atmegadci_td *td)
244 struct atmegadci_softc *sc;
245 struct usb_device_request req;
249 /* get pointer to softc */
250 sc = ATMEGA_PC2SC(td->pc);
252 /* select endpoint number */
253 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
255 /* check endpoint status */
256 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
258 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
260 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
263 /* clear did stall */
265 /* get the packet byte count */
267 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
268 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
270 /* mask away undefined bits */
273 /* verify data length */
274 if (count != td->remainder) {
275 DPRINTFN(0, "Invalid SETUP packet "
276 "length, %d bytes\n", count);
279 if (count != sizeof(req)) {
280 DPRINTFN(0, "Unsupported SETUP packet "
281 "length, %d bytes\n", count);
285 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
286 (void *)&req, sizeof(req));
288 /* copy data into real buffer */
289 usbd_copy_in(td->pc, 0, &req, sizeof(req));
291 td->offset = sizeof(req);
294 /* sneak peek the set address */
295 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
296 (req.bRequest == UR_SET_ADDRESS)) {
297 sc->sc_dv_addr = req.wValue[0] & 0x7F;
298 /* must write address before ZLP */
299 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
301 sc->sc_dv_addr = 0xFF;
304 /* Clear SETUP packet interrupt and all other previous interrupts */
305 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
306 return (0); /* complete */
309 /* abort any ongoing transfer */
310 if (!td->did_stall) {
311 DPRINTFN(5, "stalling\n");
312 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
314 ATMEGA_UECONX_STALLRQ);
317 if (temp & ATMEGA_UEINTX_RXSTPI) {
318 /* clear SETUP packet interrupt */
319 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
321 /* we only want to know if there is a SETUP packet */
322 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
323 return (1); /* not complete */
327 atmegadci_data_rx(struct atmegadci_td *td)
329 struct atmegadci_softc *sc;
330 struct usb_page_search buf_res;
336 to = 3; /* don't loop forever! */
339 /* get pointer to softc */
340 sc = ATMEGA_PC2SC(td->pc);
342 /* select endpoint number */
343 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
346 /* check if any of the FIFO banks have data */
347 /* check endpoint status */
348 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
350 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
352 if (temp & ATMEGA_UEINTX_RXSTPI) {
353 if (td->remainder == 0) {
355 * We are actually complete and have
356 * received the next SETUP
358 DPRINTFN(5, "faking complete\n");
359 return (0); /* complete */
362 * USB Host Aborted the transfer.
365 return (0); /* complete */
368 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
369 ATMEGA_UEINTX_RXOUTI))) {
373 /* get the packet byte count */
375 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
376 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
378 /* mask away undefined bits */
381 /* verify the packet byte count */
382 if (count != td->max_packet_size) {
383 if (count < td->max_packet_size) {
384 /* we have a short packet */
388 /* invalid USB packet */
390 return (0); /* we are complete */
393 /* verify the packet byte count */
394 if (count > td->remainder) {
395 /* invalid USB packet */
397 return (0); /* we are complete */
400 usbd_get_page(td->pc, td->offset, &buf_res);
402 /* get correct length */
403 if (buf_res.length > count) {
404 buf_res.length = count;
407 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
408 buf_res.buffer, buf_res.length);
410 /* update counters */
411 count -= buf_res.length;
412 td->offset += buf_res.length;
413 td->remainder -= buf_res.length;
416 /* clear OUT packet interrupt */
417 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
419 /* release FIFO bank */
420 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
422 /* check if we are complete */
423 if ((td->remainder == 0) || got_short) {
425 /* we are complete */
428 /* else need to receive a zero length packet */
434 /* we only want to know if there is a SETUP packet or OUT packet */
435 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
436 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
437 return (1); /* not complete */
441 atmegadci_data_tx(struct atmegadci_td *td)
443 struct atmegadci_softc *sc;
444 struct usb_page_search buf_res;
449 to = 3; /* don't loop forever! */
451 /* get pointer to softc */
452 sc = ATMEGA_PC2SC(td->pc);
454 /* select endpoint number */
455 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
459 /* check endpoint status */
460 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
462 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
464 if (temp & ATMEGA_UEINTX_RXSTPI) {
466 * The current transfer was aborted
470 return (0); /* complete */
473 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
475 /* cannot write any data - a bank is busy */
479 count = td->max_packet_size;
480 if (td->remainder < count) {
481 /* we have a short packet */
483 count = td->remainder;
487 usbd_get_page(td->pc, td->offset, &buf_res);
489 /* get correct length */
490 if (buf_res.length > count) {
491 buf_res.length = count;
494 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
495 buf_res.buffer, buf_res.length);
497 /* update counters */
498 count -= buf_res.length;
499 td->offset += buf_res.length;
500 td->remainder -= buf_res.length;
503 /* clear IN packet interrupt */
504 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
506 /* allocate FIFO bank */
507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
509 /* check remainder */
510 if (td->remainder == 0) {
512 return (0); /* complete */
514 /* else we need to transmit a short packet */
520 /* we only want to know if there is a SETUP packet or free IN packet */
521 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
522 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
523 return (1); /* not complete */
527 atmegadci_data_tx_sync(struct atmegadci_td *td)
529 struct atmegadci_softc *sc;
532 /* get pointer to softc */
533 sc = ATMEGA_PC2SC(td->pc);
535 /* select endpoint number */
536 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
538 /* check endpoint status */
539 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
541 DPRINTFN(5, "temp=0x%02x\n", temp);
543 if (temp & ATMEGA_UEINTX_RXSTPI) {
544 DPRINTFN(5, "faking complete\n");
546 return (0); /* complete */
549 * The control endpoint has only got one bank, so if that bank
550 * is free the packet has been transferred!
552 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
554 /* cannot write any data - a bank is busy */
557 if (sc->sc_dv_addr != 0xFF) {
558 /* set new address */
559 atmegadci_set_address(sc, sc->sc_dv_addr);
561 return (0); /* complete */
564 /* we only want to know if there is a SETUP packet or free IN packet */
565 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
566 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
567 return (1); /* not complete */
571 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
573 struct atmegadci_td *td;
577 td = xfer->td_transfer_cache;
579 if ((td->func) (td)) {
580 /* operation in progress */
583 if (((void *)td) == xfer->td_transfer_last) {
588 } else if (td->remainder > 0) {
590 * We had a short transfer. If there is no alternate
591 * next, stop processing !
598 * Fetch the next transfer descriptor and transfer
599 * some flags to the next transfer descriptor
602 xfer->td_transfer_cache = td;
604 return (1); /* not complete */
607 /* compute all actual lengths */
609 atmegadci_standard_done(xfer);
610 return (0); /* complete */
614 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
616 struct usb_xfer *xfer;
619 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
620 if (!atmegadci_xfer_do_fifo(xfer)) {
621 /* queue has been modified */
628 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
630 DPRINTFN(5, "vbus = %u\n", is_on);
633 if (!sc->sc_flags.status_vbus) {
634 sc->sc_flags.status_vbus = 1;
636 /* complete root HUB interrupt endpoint */
638 atmegadci_root_intr(sc);
641 if (sc->sc_flags.status_vbus) {
642 sc->sc_flags.status_vbus = 0;
643 sc->sc_flags.status_bus_reset = 0;
644 sc->sc_flags.status_suspend = 0;
645 sc->sc_flags.change_suspend = 0;
646 sc->sc_flags.change_connect = 1;
648 /* complete root HUB interrupt endpoint */
650 atmegadci_root_intr(sc);
656 atmegadci_interrupt(struct atmegadci_softc *sc)
660 USB_BUS_LOCK(&sc->sc_bus);
662 /* read interrupt status */
663 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
665 /* clear all set interrupts */
666 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
668 DPRINTFN(14, "UDINT=0x%02x\n", status);
670 /* check for any bus state change interrupts */
671 if (status & ATMEGA_UDINT_EORSTI) {
673 DPRINTFN(5, "end of reset\n");
675 /* set correct state */
676 sc->sc_flags.status_bus_reset = 1;
677 sc->sc_flags.status_suspend = 0;
678 sc->sc_flags.change_suspend = 0;
679 sc->sc_flags.change_connect = 1;
681 /* disable resume interrupt */
682 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
684 ATMEGA_UDINT_EORSTE);
686 /* complete root HUB interrupt endpoint */
687 atmegadci_root_intr(sc);
690 * If resume and suspend is set at the same time we interpret
691 * that like RESUME. Resume is set when there is at least 3
692 * milliseconds of inactivity on the USB BUS.
694 if (status & ATMEGA_UDINT_WAKEUPI) {
696 DPRINTFN(5, "resume interrupt\n");
698 if (sc->sc_flags.status_suspend) {
699 /* update status bits */
700 sc->sc_flags.status_suspend = 0;
701 sc->sc_flags.change_suspend = 1;
703 /* disable resume interrupt */
704 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
706 ATMEGA_UDINT_EORSTE);
708 /* complete root HUB interrupt endpoint */
709 atmegadci_root_intr(sc);
711 } else if (status & ATMEGA_UDINT_SUSPI) {
713 DPRINTFN(5, "suspend interrupt\n");
715 if (!sc->sc_flags.status_suspend) {
716 /* update status bits */
717 sc->sc_flags.status_suspend = 1;
718 sc->sc_flags.change_suspend = 1;
720 /* disable suspend interrupt */
721 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
722 ATMEGA_UDINT_WAKEUPE |
723 ATMEGA_UDINT_EORSTE);
725 /* complete root HUB interrupt endpoint */
726 atmegadci_root_intr(sc);
730 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
732 /* clear all set interrupts */
733 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
735 if (status & ATMEGA_USBINT_VBUSTI) {
738 DPRINTFN(5, "USBINT=0x%02x\n", status);
740 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
741 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
743 /* check for any endpoint interrupts */
744 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
745 /* the hardware will clear the UEINT bits automatically */
748 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
750 atmegadci_interrupt_poll(sc);
752 USB_BUS_UNLOCK(&sc->sc_bus);
756 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
758 struct atmegadci_td *td;
760 /* get current Transfer Descriptor */
764 /* prepare for next TD */
765 temp->td_next = td->obj_next;
767 /* fill out the Transfer Descriptor */
768 td->func = temp->func;
770 td->offset = temp->offset;
771 td->remainder = temp->len;
773 td->did_stall = temp->did_stall;
774 td->short_pkt = temp->short_pkt;
775 td->alt_next = temp->setup_alt_next;
779 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
781 struct atmegadci_std_temp temp;
782 struct atmegadci_softc *sc;
783 struct atmegadci_td *td;
788 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
789 xfer->address, UE_GET_ADDR(xfer->endpointno),
790 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
792 temp.max_frame_size = xfer->max_frame_size;
794 td = xfer->td_start[0];
795 xfer->td_transfer_first = td;
796 xfer->td_transfer_cache = td;
802 temp.td_next = xfer->td_start[0];
804 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
805 temp.did_stall = !xfer->flags_int.control_stall;
807 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
808 ep_no = (xfer->endpointno & UE_ADDR);
810 /* check if we should prepend a setup message */
812 if (xfer->flags_int.control_xfr) {
813 if (xfer->flags_int.control_hdr) {
815 temp.func = &atmegadci_setup_rx;
816 temp.len = xfer->frlengths[0];
817 temp.pc = xfer->frbuffers + 0;
818 temp.short_pkt = temp.len ? 1 : 0;
819 /* check for last frame */
820 if (xfer->nframes == 1) {
821 /* no STATUS stage yet, SETUP is last */
822 if (xfer->flags_int.control_act)
823 temp.setup_alt_next = 0;
826 atmegadci_setup_standard_chain_sub(&temp);
833 if (x != xfer->nframes) {
834 if (xfer->endpointno & UE_DIR_IN) {
835 temp.func = &atmegadci_data_tx;
838 temp.func = &atmegadci_data_rx;
842 /* setup "pc" pointer */
843 temp.pc = xfer->frbuffers + x;
847 while (x != xfer->nframes) {
849 /* DATA0 / DATA1 message */
851 temp.len = xfer->frlengths[x];
855 if (x == xfer->nframes) {
856 if (xfer->flags_int.control_xfr) {
857 if (xfer->flags_int.control_act) {
858 temp.setup_alt_next = 0;
861 temp.setup_alt_next = 0;
866 /* make sure that we send an USB packet */
872 /* regular data transfer */
874 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
877 atmegadci_setup_standard_chain_sub(&temp);
879 if (xfer->flags_int.isochronous_xfr) {
880 temp.offset += temp.len;
882 /* get next Page Cache pointer */
883 temp.pc = xfer->frbuffers + x;
887 if (xfer->flags_int.control_xfr) {
889 /* always setup a valid "pc" pointer for status and sync */
890 temp.pc = xfer->frbuffers + 0;
893 temp.setup_alt_next = 0;
895 /* check if we need to sync */
897 /* we need a SYNC point after TX */
898 temp.func = &atmegadci_data_tx_sync;
899 atmegadci_setup_standard_chain_sub(&temp);
902 /* check if we should append a status stage */
903 if (!xfer->flags_int.control_act) {
906 * Send a DATA1 message and invert the current
907 * endpoint direction.
909 if (xfer->endpointno & UE_DIR_IN) {
910 temp.func = &atmegadci_data_rx;
913 temp.func = &atmegadci_data_tx;
917 atmegadci_setup_standard_chain_sub(&temp);
919 /* we need a SYNC point after TX */
920 temp.func = &atmegadci_data_tx_sync;
921 atmegadci_setup_standard_chain_sub(&temp);
925 /* must have at least one frame! */
927 xfer->td_transfer_last = td;
931 atmegadci_timeout(void *arg)
933 struct usb_xfer *xfer = arg;
935 DPRINTF("xfer=%p\n", xfer);
937 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
939 /* transfer is transferred */
940 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
944 atmegadci_start_standard_chain(struct usb_xfer *xfer)
948 /* poll one time - will turn on interrupts */
949 if (atmegadci_xfer_do_fifo(xfer)) {
951 /* put transfer on interrupt queue */
952 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
954 /* start timeout, if any */
955 if (xfer->timeout != 0) {
956 usbd_transfer_timeout_ms(xfer,
957 &atmegadci_timeout, xfer->timeout);
963 atmegadci_root_intr(struct atmegadci_softc *sc)
967 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
970 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
972 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
973 sizeof(sc->sc_hub_idata));
977 atmegadci_standard_done_sub(struct usb_xfer *xfer)
979 struct atmegadci_td *td;
985 td = xfer->td_transfer_cache;
990 if (xfer->aframes != xfer->nframes) {
992 * Verify the length and subtract
993 * the remainder from "frlengths[]":
995 if (len > xfer->frlengths[xfer->aframes]) {
998 xfer->frlengths[xfer->aframes] -= len;
1001 /* Check for transfer error */
1003 /* the transfer is finished */
1008 /* Check for short transfer */
1010 if (xfer->flags_int.short_frames_ok) {
1011 /* follow alt next */
1018 /* the transfer is finished */
1026 /* this USB frame is complete */
1032 /* update transfer cache */
1034 xfer->td_transfer_cache = td;
1037 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1041 atmegadci_standard_done(struct usb_xfer *xfer)
1043 usb_error_t err = 0;
1045 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1046 xfer, xfer->endpoint);
1050 xfer->td_transfer_cache = xfer->td_transfer_first;
1052 if (xfer->flags_int.control_xfr) {
1054 if (xfer->flags_int.control_hdr) {
1056 err = atmegadci_standard_done_sub(xfer);
1060 if (xfer->td_transfer_cache == NULL) {
1064 while (xfer->aframes != xfer->nframes) {
1066 err = atmegadci_standard_done_sub(xfer);
1069 if (xfer->td_transfer_cache == NULL) {
1074 if (xfer->flags_int.control_xfr &&
1075 !xfer->flags_int.control_act) {
1077 err = atmegadci_standard_done_sub(xfer);
1080 atmegadci_device_done(xfer, err);
1083 /*------------------------------------------------------------------------*
1084 * atmegadci_device_done
1086 * NOTE: this function can be called more than one time on the
1087 * same USB transfer!
1088 *------------------------------------------------------------------------*/
1090 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1092 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1095 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1097 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1098 xfer, xfer->endpoint, error);
1100 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1101 ep_no = (xfer->endpointno & UE_ADDR);
1103 /* select endpoint number */
1104 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1106 /* disable endpoint interrupt */
1107 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1109 DPRINTFN(15, "disabled interrupts!\n");
1111 /* dequeue transfer and start next transfer */
1112 usbd_transfer_done(xfer, error);
1116 atmegadci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1117 struct usb_endpoint *ep, uint8_t *did_stall)
1119 struct atmegadci_softc *sc;
1122 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1124 DPRINTFN(5, "endpoint=%p\n", ep);
1127 /* cancel any ongoing transfers */
1128 atmegadci_device_done(xfer, USB_ERR_STALLED);
1130 sc = ATMEGA_BUS2SC(udev->bus);
1131 /* get endpoint number */
1132 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1133 /* select endpoint number */
1134 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1136 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1137 ATMEGA_UECONX_EPEN |
1138 ATMEGA_UECONX_STALLRQ);
1142 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1143 uint8_t ep_type, uint8_t ep_dir)
1147 if (ep_type == UE_CONTROL) {
1148 /* clearing stall is not needed */
1151 /* select endpoint number */
1152 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1154 /* set endpoint reset */
1155 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1157 /* clear endpoint reset */
1158 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1161 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1162 ATMEGA_UECONX_EPEN |
1163 ATMEGA_UECONX_STALLRQ);
1165 /* reset data toggle */
1166 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1167 ATMEGA_UECONX_EPEN |
1168 ATMEGA_UECONX_RSTDT);
1171 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1172 ATMEGA_UECONX_EPEN |
1173 ATMEGA_UECONX_STALLRQC);
1176 if (ep_type == UE_BULK) {
1177 temp = ATMEGA_UECFG0X_EPTYPE2;
1178 } else if (ep_type == UE_INTERRUPT) {
1179 temp = ATMEGA_UECFG0X_EPTYPE3;
1181 temp = ATMEGA_UECFG0X_EPTYPE1;
1183 if (ep_dir & UE_DIR_IN) {
1184 temp |= ATMEGA_UECFG0X_EPDIR;
1186 /* two banks, 64-bytes wMaxPacket */
1187 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1188 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1189 ATMEGA_UECFG1X_ALLOC |
1190 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1191 ATMEGA_UECFG1X_EPSIZE(3));
1193 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1194 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1195 device_printf(sc->sc_bus.bdev,
1196 "Chip rejected configuration\n");
1202 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1204 struct atmegadci_softc *sc;
1205 struct usb_endpoint_descriptor *ed;
1207 DPRINTFN(5, "endpoint=%p\n", ep);
1209 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1212 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1217 sc = ATMEGA_BUS2SC(udev->bus);
1219 /* get endpoint descriptor */
1222 /* reset endpoint */
1223 atmegadci_clear_stall_sub(sc,
1224 (ed->bEndpointAddress & UE_ADDR),
1225 (ed->bmAttributes & UE_XFERTYPE),
1226 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1230 atmegadci_init(struct atmegadci_softc *sc)
1236 /* set up the bus structure */
1237 sc->sc_bus.usbrev = USB_REV_1_1;
1238 sc->sc_bus.methods = &atmegadci_bus_methods;
1240 USB_BUS_LOCK(&sc->sc_bus);
1242 /* make sure USB is enabled */
1243 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1244 ATMEGA_USBCON_USBE |
1245 ATMEGA_USBCON_FRZCLK);
1247 /* enable USB PAD regulator */
1248 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1249 ATMEGA_UHWCON_UVREGE |
1250 ATMEGA_UHWCON_UIMOD);
1252 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1253 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1255 /* wait for PLL to lock */
1256 for (n = 0; n != 20; n++) {
1257 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1259 /* wait a little bit for PLL to start */
1260 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1263 /* make sure USB is enabled */
1264 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1265 ATMEGA_USBCON_USBE |
1266 ATMEGA_USBCON_OTGPADE |
1267 ATMEGA_USBCON_VBUSTE);
1269 /* turn on clocks */
1270 (sc->sc_clocks_on) (&sc->sc_bus);
1272 /* make sure device is re-enumerated */
1273 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1275 /* wait a little for things to stabilise */
1276 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1278 /* enable interrupts */
1279 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1280 ATMEGA_UDINT_SUSPE |
1281 ATMEGA_UDINT_EORSTE);
1283 /* reset all endpoints */
1284 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1285 (1 << ATMEGA_EP_MAX) - 1);
1288 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1290 /* disable all endpoints */
1291 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1293 /* select endpoint */
1294 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1296 /* disable endpoint interrupt */
1297 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1299 /* disable endpoint */
1300 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1303 /* turn off clocks */
1305 atmegadci_clocks_off(sc);
1307 /* read initial VBUS state */
1309 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1310 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1312 USB_BUS_UNLOCK(&sc->sc_bus);
1314 /* catch any lost interrupts */
1316 atmegadci_do_poll(&sc->sc_bus);
1318 return (0); /* success */
1322 atmegadci_uninit(struct atmegadci_softc *sc)
1324 USB_BUS_LOCK(&sc->sc_bus);
1326 /* turn on clocks */
1327 (sc->sc_clocks_on) (&sc->sc_bus);
1329 /* disable interrupts */
1330 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1332 /* reset all endpoints */
1333 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1334 (1 << ATMEGA_EP_MAX) - 1);
1337 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1339 sc->sc_flags.port_powered = 0;
1340 sc->sc_flags.status_vbus = 0;
1341 sc->sc_flags.status_bus_reset = 0;
1342 sc->sc_flags.status_suspend = 0;
1343 sc->sc_flags.change_suspend = 0;
1344 sc->sc_flags.change_connect = 1;
1346 atmegadci_pull_down(sc);
1347 atmegadci_clocks_off(sc);
1349 /* disable USB PAD regulator */
1350 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1352 USB_BUS_UNLOCK(&sc->sc_bus);
1356 atmegadci_suspend(struct atmegadci_softc *sc)
1362 atmegadci_resume(struct atmegadci_softc *sc)
1368 atmegadci_do_poll(struct usb_bus *bus)
1370 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1372 USB_BUS_LOCK(&sc->sc_bus);
1373 atmegadci_interrupt_poll(sc);
1374 USB_BUS_UNLOCK(&sc->sc_bus);
1377 /*------------------------------------------------------------------------*
1378 * at91dci bulk support
1379 * at91dci control support
1380 * at91dci interrupt support
1381 *------------------------------------------------------------------------*/
1383 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1389 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1391 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1395 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1401 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1404 atmegadci_setup_standard_chain(xfer);
1405 atmegadci_start_standard_chain(xfer);
1408 struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1410 .open = atmegadci_device_non_isoc_open,
1411 .close = atmegadci_device_non_isoc_close,
1412 .enter = atmegadci_device_non_isoc_enter,
1413 .start = atmegadci_device_non_isoc_start,
1416 /*------------------------------------------------------------------------*
1417 * at91dci full speed isochronous support
1418 *------------------------------------------------------------------------*/
1420 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1426 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1428 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1432 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1434 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1438 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1439 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1441 /* get the current frame index */
1444 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1445 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1447 nframes &= ATMEGA_FRAME_MASK;
1450 * check if the frame index is within the window where the frames
1453 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1455 if ((xfer->endpoint->is_synced == 0) ||
1456 (temp < xfer->nframes)) {
1458 * If there is data underflow or the pipe queue is
1459 * empty we schedule the transfer a few frames ahead
1460 * of the current frame position. Else two isochronous
1461 * transfers might overlap.
1463 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1464 xfer->endpoint->is_synced = 1;
1465 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1468 * compute how many milliseconds the insertion is ahead of the
1469 * current frame position:
1471 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1474 * pre-compute when the isochronous transfer will be finished:
1476 xfer->isoc_time_complete =
1477 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1480 /* compute frame number for next insertion */
1481 xfer->endpoint->isoc_next += xfer->nframes;
1484 atmegadci_setup_standard_chain(xfer);
1488 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1490 /* start TD chain */
1491 atmegadci_start_standard_chain(xfer);
1494 struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1496 .open = atmegadci_device_isoc_fs_open,
1497 .close = atmegadci_device_isoc_fs_close,
1498 .enter = atmegadci_device_isoc_fs_enter,
1499 .start = atmegadci_device_isoc_fs_start,
1502 /*------------------------------------------------------------------------*
1503 * at91dci root control support
1504 *------------------------------------------------------------------------*
1505 * Simulate a hardware HUB by handling all the necessary requests.
1506 *------------------------------------------------------------------------*/
1508 static const struct usb_device_descriptor atmegadci_devd = {
1509 .bLength = sizeof(struct usb_device_descriptor),
1510 .bDescriptorType = UDESC_DEVICE,
1511 .bcdUSB = {0x00, 0x02},
1512 .bDeviceClass = UDCLASS_HUB,
1513 .bDeviceSubClass = UDSUBCLASS_HUB,
1514 .bDeviceProtocol = UDPROTO_FSHUB,
1515 .bMaxPacketSize = 64,
1516 .bcdDevice = {0x00, 0x01},
1519 .bNumConfigurations = 1,
1522 static const struct atmegadci_config_desc atmegadci_confd = {
1524 .bLength = sizeof(struct usb_config_descriptor),
1525 .bDescriptorType = UDESC_CONFIG,
1526 .wTotalLength[0] = sizeof(atmegadci_confd),
1528 .bConfigurationValue = 1,
1529 .iConfiguration = 0,
1530 .bmAttributes = UC_SELF_POWERED,
1534 .bLength = sizeof(struct usb_interface_descriptor),
1535 .bDescriptorType = UDESC_INTERFACE,
1537 .bInterfaceClass = UICLASS_HUB,
1538 .bInterfaceSubClass = UISUBCLASS_HUB,
1539 .bInterfaceProtocol = 0,
1542 .bLength = sizeof(struct usb_endpoint_descriptor),
1543 .bDescriptorType = UDESC_ENDPOINT,
1544 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1545 .bmAttributes = UE_INTERRUPT,
1546 .wMaxPacketSize[0] = 8,
1551 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1553 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1554 .bDescLength = sizeof(atmegadci_hubd),
1555 .bDescriptorType = UDESC_HUB,
1557 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1558 .bPwrOn2PwrGood = 50,
1559 .bHubContrCurrent = 0,
1560 .DeviceRemovable = {0}, /* port is removable */
1563 #define STRING_LANG \
1564 0x09, 0x04, /* American English */
1566 #define STRING_VENDOR \
1567 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0
1569 #define STRING_PRODUCT \
1570 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1571 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1574 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab);
1575 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1576 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1579 atmegadci_roothub_exec(struct usb_device *udev,
1580 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1582 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1590 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1593 ptr = (const void *)&sc->sc_hub_temp;
1597 value = UGETW(req->wValue);
1598 index = UGETW(req->wIndex);
1600 /* demultiplex the control request */
1602 switch (req->bmRequestType) {
1603 case UT_READ_DEVICE:
1604 switch (req->bRequest) {
1605 case UR_GET_DESCRIPTOR:
1606 goto tr_handle_get_descriptor;
1608 goto tr_handle_get_config;
1610 goto tr_handle_get_status;
1616 case UT_WRITE_DEVICE:
1617 switch (req->bRequest) {
1618 case UR_SET_ADDRESS:
1619 goto tr_handle_set_address;
1621 goto tr_handle_set_config;
1622 case UR_CLEAR_FEATURE:
1623 goto tr_valid; /* nop */
1624 case UR_SET_DESCRIPTOR:
1625 goto tr_valid; /* nop */
1626 case UR_SET_FEATURE:
1632 case UT_WRITE_ENDPOINT:
1633 switch (req->bRequest) {
1634 case UR_CLEAR_FEATURE:
1635 switch (UGETW(req->wValue)) {
1636 case UF_ENDPOINT_HALT:
1637 goto tr_handle_clear_halt;
1638 case UF_DEVICE_REMOTE_WAKEUP:
1639 goto tr_handle_clear_wakeup;
1644 case UR_SET_FEATURE:
1645 switch (UGETW(req->wValue)) {
1646 case UF_ENDPOINT_HALT:
1647 goto tr_handle_set_halt;
1648 case UF_DEVICE_REMOTE_WAKEUP:
1649 goto tr_handle_set_wakeup;
1654 case UR_SYNCH_FRAME:
1655 goto tr_valid; /* nop */
1661 case UT_READ_ENDPOINT:
1662 switch (req->bRequest) {
1664 goto tr_handle_get_ep_status;
1670 case UT_WRITE_INTERFACE:
1671 switch (req->bRequest) {
1672 case UR_SET_INTERFACE:
1673 goto tr_handle_set_interface;
1674 case UR_CLEAR_FEATURE:
1675 goto tr_valid; /* nop */
1676 case UR_SET_FEATURE:
1682 case UT_READ_INTERFACE:
1683 switch (req->bRequest) {
1684 case UR_GET_INTERFACE:
1685 goto tr_handle_get_interface;
1687 goto tr_handle_get_iface_status;
1693 case UT_WRITE_CLASS_INTERFACE:
1694 case UT_WRITE_VENDOR_INTERFACE:
1698 case UT_READ_CLASS_INTERFACE:
1699 case UT_READ_VENDOR_INTERFACE:
1703 case UT_WRITE_CLASS_DEVICE:
1704 switch (req->bRequest) {
1705 case UR_CLEAR_FEATURE:
1707 case UR_SET_DESCRIPTOR:
1708 case UR_SET_FEATURE:
1715 case UT_WRITE_CLASS_OTHER:
1716 switch (req->bRequest) {
1717 case UR_CLEAR_FEATURE:
1718 goto tr_handle_clear_port_feature;
1719 case UR_SET_FEATURE:
1720 goto tr_handle_set_port_feature;
1721 case UR_CLEAR_TT_BUFFER:
1731 case UT_READ_CLASS_OTHER:
1732 switch (req->bRequest) {
1733 case UR_GET_TT_STATE:
1734 goto tr_handle_get_tt_state;
1736 goto tr_handle_get_port_status;
1742 case UT_READ_CLASS_DEVICE:
1743 switch (req->bRequest) {
1744 case UR_GET_DESCRIPTOR:
1745 goto tr_handle_get_class_descriptor;
1747 goto tr_handle_get_class_status;
1758 tr_handle_get_descriptor:
1759 switch (value >> 8) {
1764 len = sizeof(atmegadci_devd);
1765 ptr = (const void *)&atmegadci_devd;
1771 len = sizeof(atmegadci_confd);
1772 ptr = (const void *)&atmegadci_confd;
1775 switch (value & 0xff) {
1776 case 0: /* Language table */
1777 len = sizeof(atmegadci_langtab);
1778 ptr = (const void *)&atmegadci_langtab;
1781 case 1: /* Vendor */
1782 len = sizeof(atmegadci_vendor);
1783 ptr = (const void *)&atmegadci_vendor;
1786 case 2: /* Product */
1787 len = sizeof(atmegadci_product);
1788 ptr = (const void *)&atmegadci_product;
1799 tr_handle_get_config:
1801 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1804 tr_handle_get_status:
1806 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1809 tr_handle_set_address:
1810 if (value & 0xFF00) {
1813 sc->sc_rt_addr = value;
1816 tr_handle_set_config:
1820 sc->sc_conf = value;
1823 tr_handle_get_interface:
1825 sc->sc_hub_temp.wValue[0] = 0;
1828 tr_handle_get_tt_state:
1829 tr_handle_get_class_status:
1830 tr_handle_get_iface_status:
1831 tr_handle_get_ep_status:
1833 USETW(sc->sc_hub_temp.wValue, 0);
1837 tr_handle_set_interface:
1838 tr_handle_set_wakeup:
1839 tr_handle_clear_wakeup:
1840 tr_handle_clear_halt:
1843 tr_handle_clear_port_feature:
1847 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1850 case UHF_PORT_SUSPEND:
1851 atmegadci_wakeup_peer(sc);
1854 case UHF_PORT_ENABLE:
1855 sc->sc_flags.port_enabled = 0;
1859 case UHF_PORT_INDICATOR:
1860 case UHF_C_PORT_ENABLE:
1861 case UHF_C_PORT_OVER_CURRENT:
1862 case UHF_C_PORT_RESET:
1865 case UHF_PORT_POWER:
1866 sc->sc_flags.port_powered = 0;
1867 atmegadci_pull_down(sc);
1868 atmegadci_clocks_off(sc);
1870 case UHF_C_PORT_CONNECTION:
1871 /* clear connect change flag */
1872 sc->sc_flags.change_connect = 0;
1874 if (!sc->sc_flags.status_bus_reset) {
1875 /* we are not connected */
1879 /* configure the control endpoint */
1881 /* select endpoint number */
1882 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1884 /* set endpoint reset */
1885 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1887 /* clear endpoint reset */
1888 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1890 /* enable and stall endpoint */
1891 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1892 ATMEGA_UECONX_EPEN |
1893 ATMEGA_UECONX_STALLRQ);
1895 /* one bank, 64-bytes wMaxPacket */
1896 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1897 ATMEGA_UECFG0X_EPTYPE0);
1898 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1899 ATMEGA_UECFG1X_ALLOC |
1900 ATMEGA_UECFG1X_EPBK0 |
1901 ATMEGA_UECFG1X_EPSIZE(3));
1903 /* check valid config */
1904 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1905 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1906 device_printf(sc->sc_bus.bdev,
1907 "Chip rejected EP0 configuration\n");
1910 case UHF_C_PORT_SUSPEND:
1911 sc->sc_flags.change_suspend = 0;
1914 err = USB_ERR_IOERROR;
1919 tr_handle_set_port_feature:
1923 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1926 case UHF_PORT_ENABLE:
1927 sc->sc_flags.port_enabled = 1;
1929 case UHF_PORT_SUSPEND:
1930 case UHF_PORT_RESET:
1932 case UHF_PORT_INDICATOR:
1935 case UHF_PORT_POWER:
1936 sc->sc_flags.port_powered = 1;
1939 err = USB_ERR_IOERROR;
1944 tr_handle_get_port_status:
1946 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1951 if (sc->sc_flags.status_vbus) {
1952 atmegadci_clocks_on(sc);
1953 atmegadci_pull_up(sc);
1955 atmegadci_pull_down(sc);
1956 atmegadci_clocks_off(sc);
1959 /* Select FULL-speed and Device Side Mode */
1961 value = UPS_PORT_MODE_DEVICE;
1963 if (sc->sc_flags.port_powered) {
1964 value |= UPS_PORT_POWER;
1966 if (sc->sc_flags.port_enabled) {
1967 value |= UPS_PORT_ENABLED;
1969 if (sc->sc_flags.status_vbus &&
1970 sc->sc_flags.status_bus_reset) {
1971 value |= UPS_CURRENT_CONNECT_STATUS;
1973 if (sc->sc_flags.status_suspend) {
1974 value |= UPS_SUSPEND;
1976 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1980 if (sc->sc_flags.change_connect) {
1981 value |= UPS_C_CONNECT_STATUS;
1983 if (sc->sc_flags.change_suspend) {
1984 value |= UPS_C_SUSPEND;
1986 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1987 len = sizeof(sc->sc_hub_temp.ps);
1990 tr_handle_get_class_descriptor:
1994 ptr = (const void *)&atmegadci_hubd;
1995 len = sizeof(atmegadci_hubd);
1999 err = USB_ERR_STALLED;
2008 atmegadci_xfer_setup(struct usb_setup_params *parm)
2010 const struct usb_hw_ep_profile *pf;
2011 struct atmegadci_softc *sc;
2012 struct usb_xfer *xfer;
2018 sc = ATMEGA_BUS2SC(parm->udev->bus);
2019 xfer = parm->curr_xfer;
2022 * NOTE: This driver does not use any of the parameters that
2023 * are computed from the following values. Just set some
2024 * reasonable dummies:
2026 parm->hc_max_packet_size = 0x500;
2027 parm->hc_max_packet_count = 1;
2028 parm->hc_max_frame_size = 0x500;
2030 usbd_transfer_setup_sub(parm);
2033 * compute maximum number of TDs
2035 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2037 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2041 ntd = xfer->nframes + 1 /* SYNC */ ;
2045 * check if "usbd_transfer_setup_sub" set an error
2051 * allocate transfer descriptors
2058 ep_no = xfer->endpointno & UE_ADDR;
2059 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2062 /* should not happen */
2063 parm->err = USB_ERR_INVAL;
2068 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2070 for (n = 0; n != ntd; n++) {
2072 struct atmegadci_td *td;
2076 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2079 td->max_packet_size = xfer->max_packet_size;
2081 if (pf->support_multi_buffer) {
2082 td->support_multi_buffer = 1;
2084 td->obj_next = last_obj;
2088 parm->size[0] += sizeof(*td);
2091 xfer->td_start[0] = last_obj;
2095 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2101 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2102 struct usb_endpoint *ep)
2104 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2106 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2108 edesc->bEndpointAddress, udev->flags.usb_mode,
2109 sc->sc_rt_addr, udev->device_index);
2111 if (udev->device_index != sc->sc_rt_addr) {
2113 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2117 if (udev->speed != USB_SPEED_FULL) {
2121 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2122 ep->methods = &atmegadci_device_isoc_fs_methods;
2124 ep->methods = &atmegadci_device_non_isoc_methods;
2129 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2131 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
2134 case USB_HW_POWER_SUSPEND:
2135 atmegadci_suspend(sc);
2137 case USB_HW_POWER_SHUTDOWN:
2138 atmegadci_uninit(sc);
2140 case USB_HW_POWER_RESUME:
2141 atmegadci_resume(sc);
2148 struct usb_bus_methods atmegadci_bus_methods =
2150 .endpoint_init = &atmegadci_ep_init,
2151 .xfer_setup = &atmegadci_xfer_setup,
2152 .xfer_unsetup = &atmegadci_xfer_unsetup,
2153 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2154 .set_stall = &atmegadci_set_stall,
2155 .clear_stall = &atmegadci_clear_stall,
2156 .roothub_exec = &atmegadci_roothub_exec,
2157 .xfer_poll = &atmegadci_do_poll,
2158 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep,