sys/dev/usb/controller/avr32dci.c

   1 #include <sys/cdefs.h>
   2 __FBSDID("$FreeBSD$");
   3
   4 /*-
   5  * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the AVR32 series USB Device
  31  * Controller
  32  */
  33
  34 /*
  35  * NOTE: When the chip detects BUS-reset it will also reset the
  36  * endpoints, Function-address and more.
  37  */
  38
  39 #include <sys/stdint.h>
  40 #include <sys/stddef.h>
  41 #include <sys/param.h>
  42 #include <sys/queue.h>
  43 #include <sys/types.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/bus.h>
  47 #include <sys/module.h>
  48 #include <sys/lock.h>
  49 #include <sys/mutex.h>
  50 #include <sys/condvar.h>
  51 #include <sys/sysctl.h>
  52 #include <sys/sx.h>
  53 #include <sys/unistd.h>
  54 #include <sys/callout.h>
  55 #include <sys/malloc.h>
  56 #include <sys/priv.h>
  57
  58 #include <dev/usb/usb.h>
  59 #include <dev/usb/usbdi.h>
  60
  61 #define USB_DEBUG_VAR avr32dci_debug
  62
  63 #include <dev/usb/usb_core.h>
  64 #include <dev/usb/usb_debug.h>
  65 #include <dev/usb/usb_busdma.h>
  66 #include <dev/usb/usb_process.h>
  67 #include <dev/usb/usb_transfer.h>
  68 #include <dev/usb/usb_device.h>
  69 #include <dev/usb/usb_hub.h>
  70 #include <dev/usb/usb_util.h>
  71
  72 #include <dev/usb/usb_controller.h>
  73 #include <dev/usb/usb_bus.h>
  74 #include <dev/usb/controller/avr32dci.h>
  75
  76 #define AVR32_BUS2SC(bus) \
  77    ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \
  78     ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus))))
  79
  80 #define AVR32_PC2SC(pc) \
  81    AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  82
  83 #ifdef USB_DEBUG
  84 static int avr32dci_debug = 0;
  85
  86 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI");
  87 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RW,
  88     &avr32dci_debug, 0, "AVR32 DCI debug level");
  89 #endif
  90
  91 #define AVR32_INTR_ENDPT 1
  92
  93 /* prototypes */
  94
  95 struct usb_bus_methods avr32dci_bus_methods;
  96 struct usb_pipe_methods avr32dci_device_non_isoc_methods;
  97 struct usb_pipe_methods avr32dci_device_isoc_fs_methods;
  98
  99 static avr32dci_cmd_t avr32dci_setup_rx;
 100 static avr32dci_cmd_t avr32dci_data_rx;
 101 static avr32dci_cmd_t avr32dci_data_tx;
 102 static avr32dci_cmd_t avr32dci_data_tx_sync;
 103 static void avr32dci_device_done(struct usb_xfer *, usb_error_t);
 104 static void avr32dci_do_poll(struct usb_bus *);
 105 static void avr32dci_standard_done(struct usb_xfer *);
 106 static void avr32dci_root_intr(struct avr32dci_softc *sc);
 107
 108 /*
 109  * Here is a list of what the chip supports:
 110  */
 111 static const struct usb_hw_ep_profile
 112         avr32dci_ep_profile[4] = {
 113
 114         [0] = {
 115                 .max_in_frame_size = 64,
 116                 .max_out_frame_size = 64,
 117                 .is_simplex = 1,
 118                 .support_control = 1,
 119         },
 120
 121         [1] = {
 122                 .max_in_frame_size = 512,
 123                 .max_out_frame_size = 512,
 124                 .is_simplex = 1,
 125                 .support_bulk = 1,
 126                 .support_interrupt = 1,
 127                 .support_isochronous = 1,
 128                 .support_in = 1,
 129                 .support_out = 1,
 130         },
 131
 132         [2] = {
 133                 .max_in_frame_size = 64,
 134                 .max_out_frame_size = 64,
 135                 .is_simplex = 1,
 136                 .support_bulk = 1,
 137                 .support_interrupt = 1,
 138                 .support_in = 1,
 139                 .support_out = 1,
 140         },
 141
 142         [3] = {
 143                 .max_in_frame_size = 1024,
 144                 .max_out_frame_size = 1024,
 145                 .is_simplex = 1,
 146                 .support_bulk = 1,
 147                 .support_interrupt = 1,
 148                 .support_isochronous = 1,
 149                 .support_in = 1,
 150                 .support_out = 1,
 151         },
 152 };
 153
 154 static void
 155 avr32dci_get_hw_ep_profile(struct usb_device *udev,
 156     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 157 {
 158         if (ep_addr == 0)
 159                 *ppf = avr32dci_ep_profile;
 160         else if (ep_addr < 3)
 161                 *ppf = avr32dci_ep_profile + 1;
 162         else if (ep_addr < 5)
 163                 *ppf = avr32dci_ep_profile + 2;
 164         else if (ep_addr < 7)
 165                 *ppf = avr32dci_ep_profile + 3;
 166         else
 167                 *ppf = NULL;
 168 }
 169
 170 static void
 171 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
 172 {
 173         uint32_t temp;
 174
 175         temp = AVR32_READ_4(sc, AVR32_CTRL);
 176         temp |= set;
 177         temp &= ~clear;
 178         AVR32_WRITE_4(sc, AVR32_CTRL, temp);
 179 }
 180
 181 static void
 182 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
 183 {
 184         uint32_t temp;
 185
 186         temp = AVR32_READ_4(sc, AVR32_IEN);
 187         temp |= set;
 188         temp &= ~clear;
 189         AVR32_WRITE_4(sc, AVR32_IEN, temp);
 190 }
 191
 192 static void
 193 avr32dci_clocks_on(struct avr32dci_softc *sc)
 194 {
 195         if (sc->sc_flags.clocks_off &&
 196             sc->sc_flags.port_powered) {
 197
 198                 DPRINTFN(5, "\n");
 199
 200                 /* turn on clocks */
 201                 (sc->sc_clocks_on) (&sc->sc_bus);
 202
 203                 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
 204
 205                 sc->sc_flags.clocks_off = 0;
 206         }
 207 }
 208
 209 static void
 210 avr32dci_clocks_off(struct avr32dci_softc *sc)
 211 {
 212         if (!sc->sc_flags.clocks_off) {
 213
 214                 DPRINTFN(5, "\n");
 215
 216                 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA);
 217
 218                 /* turn clocks off */
 219                 (sc->sc_clocks_off) (&sc->sc_bus);
 220
 221                 sc->sc_flags.clocks_off = 1;
 222         }
 223 }
 224
 225 static void
 226 avr32dci_pull_up(struct avr32dci_softc *sc)
 227 {
 228         /* pullup D+, if possible */
 229
 230         if (!sc->sc_flags.d_pulled_up &&
 231             sc->sc_flags.port_powered) {
 232                 sc->sc_flags.d_pulled_up = 1;
 233                 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH);
 234         }
 235 }
 236
 237 static void
 238 avr32dci_pull_down(struct avr32dci_softc *sc)
 239 {
 240         /* pulldown D+, if possible */
 241
 242         if (sc->sc_flags.d_pulled_up) {
 243                 sc->sc_flags.d_pulled_up = 0;
 244                 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
 245         }
 246 }
 247
 248 static void
 249 avr32dci_wakeup_peer(struct avr32dci_softc *sc)
 250 {
 251         if (!sc->sc_flags.status_suspend) {
 252                 return;
 253         }
 254         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0);
 255
 256         /* wait 8 milliseconds */
 257         /* Wait for reset to complete. */
 258         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 259
 260         /* hardware should have cleared RMWKUP bit */
 261 }
 262
 263 static void
 264 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr)
 265 {
 266         DPRINTFN(5, "addr=%d\n", addr);
 267
 268         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0);
 269 }
 270
 271 static uint8_t
 272 avr32dci_setup_rx(struct avr32dci_td *td)
 273 {
 274         struct avr32dci_softc *sc;
 275         struct usb_device_request req;
 276         uint16_t count;
 277         uint32_t temp;
 278
 279         /* get pointer to softc */
 280         sc = AVR32_PC2SC(td->pc);
 281
 282         /* check endpoint status */
 283         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 284
 285         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 286
 287         if (!(temp & AVR32_EPTSTA_RX_SETUP)) {
 288                 goto not_complete;
 289         }
 290         /* clear did stall */
 291         td->did_stall = 0;
 292         /* get the packet byte count */
 293         count = AVR32_EPTSTA_BYTE_COUNT(temp);
 294
 295         /* verify data length */
 296         if (count != td->remainder) {
 297                 DPRINTFN(0, "Invalid SETUP packet "
 298                     "length, %d bytes\n", count);
 299                 goto not_complete;
 300         }
 301         if (count != sizeof(req)) {
 302                 DPRINTFN(0, "Unsupported SETUP packet "
 303                     "length, %d bytes\n", count);
 304                 goto not_complete;
 305         }
 306         /* receive data */
 307         memcpy(&req, sc->physdata, sizeof(req));
 308
 309         /* copy data into real buffer */
 310         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 311
 312         td->offset = sizeof(req);
 313         td->remainder = 0;
 314
 315         /* sneak peek the set address */
 316         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 317             (req.bRequest == UR_SET_ADDRESS)) {
 318                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 319                 /* must write address before ZLP */
 320                 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN |
 321                     AVR32_CTRL_DEV_ADDR);
 322                 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0);
 323         } else {
 324                 sc->sc_dv_addr = 0xFF;
 325         }
 326
 327         /* clear SETUP packet interrupt */
 328         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
 329         return (0);                     /* complete */
 330
 331 not_complete:
 332         if (temp & AVR32_EPTSTA_RX_SETUP) {
 333                 /* clear SETUP packet interrupt */
 334                 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
 335         }
 336         /* abort any ongoing transfer */
 337         if (!td->did_stall) {
 338                 DPRINTFN(5, "stalling\n");
 339                 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no),
 340                     AVR32_EPTSTA_FRCESTALL);
 341                 td->did_stall = 1;
 342         }
 343         return (1);                     /* not complete */
 344 }
 345
 346 static uint8_t
 347 avr32dci_data_rx(struct avr32dci_td *td)
 348 {
 349         struct avr32dci_softc *sc;
 350         struct usb_page_search buf_res;
 351         uint16_t count;
 352         uint32_t temp;
 353         uint8_t to;
 354         uint8_t got_short;
 355
 356         to = 4;                         /* don't loop forever! */
 357         got_short = 0;
 358
 359         /* get pointer to softc */
 360         sc = AVR32_PC2SC(td->pc);
 361
 362 repeat:
 363         /* check if any of the FIFO banks have data */
 364         /* check endpoint status */
 365         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 366
 367         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 368
 369         if (temp & AVR32_EPTSTA_RX_SETUP) {
 370                 if (td->remainder == 0) {
 371                         /*
 372                          * We are actually complete and have
 373                          * received the next SETUP
 374                          */
 375                         DPRINTFN(5, "faking complete\n");
 376                         return (0);     /* complete */
 377                 }
 378                 /*
 379                  * USB Host Aborted the transfer.
 380                  */
 381                 td->error = 1;
 382                 return (0);             /* complete */
 383         }
 384         /* check status */
 385         if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) {
 386                 /* no data */
 387                 goto not_complete;
 388         }
 389         /* get the packet byte count */
 390         count = AVR32_EPTSTA_BYTE_COUNT(temp);
 391
 392         /* verify the packet byte count */
 393         if (count != td->max_packet_size) {
 394                 if (count < td->max_packet_size) {
 395                         /* we have a short packet */
 396                         td->short_pkt = 1;
 397                         got_short = 1;
 398                 } else {
 399                         /* invalid USB packet */
 400                         td->error = 1;
 401                         return (0);     /* we are complete */
 402                 }
 403         }
 404         /* verify the packet byte count */
 405         if (count > td->remainder) {
 406                 /* invalid USB packet */
 407                 td->error = 1;
 408                 return (0);             /* we are complete */
 409         }
 410         while (count > 0) {
 411                 usbd_get_page(td->pc, td->offset, &buf_res);
 412
 413                 /* get correct length */
 414                 if (buf_res.length > count) {
 415                         buf_res.length = count;
 416                 }
 417                 /* receive data */
 418                 memcpy(buf_res.buffer, sc->physdata +
 419                     (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
 420                     (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length);
 421                 /* update counters */
 422                 count -= buf_res.length;
 423                 td->offset += buf_res.length;
 424                 td->remainder -= buf_res.length;
 425         }
 426
 427         /* clear OUT packet interrupt */
 428         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY);
 429
 430         /* check if we are complete */
 431         if ((td->remainder == 0) || got_short) {
 432                 if (td->short_pkt) {
 433                         /* we are complete */
 434                         return (0);
 435                 }
 436                 /* else need to receive a zero length packet */
 437         }
 438         if (--to) {
 439                 goto repeat;
 440         }
 441 not_complete:
 442         return (1);                     /* not complete */
 443 }
 444
 445 static uint8_t
 446 avr32dci_data_tx(struct avr32dci_td *td)
 447 {
 448         struct avr32dci_softc *sc;
 449         struct usb_page_search buf_res;
 450         uint16_t count;
 451         uint8_t to;
 452         uint32_t temp;
 453
 454         to = 4;                         /* don't loop forever! */
 455
 456         /* get pointer to softc */
 457         sc = AVR32_PC2SC(td->pc);
 458
 459 repeat:
 460
 461         /* check endpoint status */
 462         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 463
 464         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 465
 466         if (temp & AVR32_EPTSTA_RX_SETUP) {
 467                 /*
 468                  * The current transfer was aborted
 469                  * by the USB Host
 470                  */
 471                 td->error = 1;
 472                 return (0);             /* complete */
 473         }
 474         if (temp & AVR32_EPTSTA_TX_PK_RDY) {
 475                 /* cannot write any data - all banks are busy */
 476                 goto not_complete;
 477         }
 478         count = td->max_packet_size;
 479         if (td->remainder < count) {
 480                 /* we have a short packet */
 481                 td->short_pkt = 1;
 482                 count = td->remainder;
 483         }
 484         while (count > 0) {
 485
 486                 usbd_get_page(td->pc, td->offset, &buf_res);
 487
 488                 /* get correct length */
 489                 if (buf_res.length > count) {
 490                         buf_res.length = count;
 491                 }
 492                 /* transmit data */
 493                 memcpy(sc->physdata +
 494                     (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
 495                     (td->ep_no << 16) + (td->offset % td->max_packet_size),
 496                     buf_res.buffer, buf_res.length);
 497                 /* update counters */
 498                 count -= buf_res.length;
 499                 td->offset += buf_res.length;
 500                 td->remainder -= buf_res.length;
 501         }
 502
 503         /* allocate FIFO bank */
 504         AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY);
 505
 506         /* check remainder */
 507         if (td->remainder == 0) {
 508                 if (td->short_pkt) {
 509                         return (0);     /* complete */
 510                 }
 511                 /* else we need to transmit a short packet */
 512         }
 513         if (--to) {
 514                 goto repeat;
 515         }
 516 not_complete:
 517         return (1);                     /* not complete */
 518 }
 519
 520 static uint8_t
 521 avr32dci_data_tx_sync(struct avr32dci_td *td)
 522 {
 523         struct avr32dci_softc *sc;
 524         uint32_t temp;
 525
 526         /* get pointer to softc */
 527         sc = AVR32_PC2SC(td->pc);
 528
 529         /* check endpoint status */
 530         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 531
 532         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 533
 534         if (temp & AVR32_EPTSTA_RX_SETUP) {
 535                 DPRINTFN(5, "faking complete\n");
 536                 /* Race condition */
 537                 return (0);             /* complete */
 538         }
 539         /*
 540          * The control endpoint has only got one bank, so if that bank
 541          * is free the packet has been transferred!
 542          */
 543         if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) {
 544                 /* cannot write any data - a bank is busy */
 545                 goto not_complete;
 546         }
 547         if (sc->sc_dv_addr != 0xFF) {
 548                 /* set new address */
 549                 avr32dci_set_address(sc, sc->sc_dv_addr);
 550         }
 551         return (0);                     /* complete */
 552
 553 not_complete:
 554         return (1);                     /* not complete */
 555 }
 556
 557 static uint8_t
 558 avr32dci_xfer_do_fifo(struct usb_xfer *xfer)
 559 {
 560         struct avr32dci_td *td;
 561
 562         DPRINTFN(9, "\n");
 563
 564         td = xfer->td_transfer_cache;
 565         while (1) {
 566                 if ((td->func) (td)) {
 567                         /* operation in progress */
 568                         break;
 569                 }
 570                 if (((void *)td) == xfer->td_transfer_last) {
 571                         goto done;
 572                 }
 573                 if (td->error) {
 574                         goto done;
 575                 } else if (td->remainder > 0) {
 576                         /*
 577                          * We had a short transfer. If there is no alternate
 578                          * next, stop processing !
 579                          */
 580                         if (!td->alt_next) {
 581                                 goto done;
 582                         }
 583                 }
 584                 /*
 585                  * Fetch the next transfer descriptor and transfer
 586                  * some flags to the next transfer descriptor
 587                  */
 588                 td = td->obj_next;
 589                 xfer->td_transfer_cache = td;
 590         }
 591         return (1);                     /* not complete */
 592
 593 done:
 594         /* compute all actual lengths */
 595
 596         avr32dci_standard_done(xfer);
 597         return (0);                     /* complete */
 598 }
 599
 600 static void
 601 avr32dci_interrupt_poll(struct avr32dci_softc *sc)
 602 {
 603         struct usb_xfer *xfer;
 604
 605 repeat:
 606         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 607                 if (!avr32dci_xfer_do_fifo(xfer)) {
 608                         /* queue has been modified */
 609                         goto repeat;
 610                 }
 611         }
 612 }
 613
 614 void
 615 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on)
 616 {
 617         DPRINTFN(5, "vbus = %u\n", is_on);
 618
 619         if (is_on) {
 620                 if (!sc->sc_flags.status_vbus) {
 621                         sc->sc_flags.status_vbus = 1;
 622
 623                         /* complete root HUB interrupt endpoint */
 624
 625                         avr32dci_root_intr(sc);
 626                 }
 627         } else {
 628                 if (sc->sc_flags.status_vbus) {
 629                         sc->sc_flags.status_vbus = 0;
 630                         sc->sc_flags.status_bus_reset = 0;
 631                         sc->sc_flags.status_suspend = 0;
 632                         sc->sc_flags.change_suspend = 0;
 633                         sc->sc_flags.change_connect = 1;
 634
 635                         /* complete root HUB interrupt endpoint */
 636
 637                         avr32dci_root_intr(sc);
 638                 }
 639         }
 640 }
 641
 642 void
 643 avr32dci_interrupt(struct avr32dci_softc *sc)
 644 {
 645         uint32_t status;
 646
 647         USB_BUS_LOCK(&sc->sc_bus);
 648
 649         /* read interrupt status */
 650         status = AVR32_READ_4(sc, AVR32_INTSTA);
 651
 652         /* clear all set interrupts */
 653         AVR32_WRITE_4(sc, AVR32_CLRINT, status);
 654
 655         DPRINTFN(14, "INTSTA=0x%08x\n", status);
 656
 657         /* check for any bus state change interrupts */
 658         if (status & AVR32_INT_ENDRESET) {
 659
 660                 DPRINTFN(5, "end of reset\n");
 661
 662                 /* set correct state */
 663                 sc->sc_flags.status_bus_reset = 1;
 664                 sc->sc_flags.status_suspend = 0;
 665                 sc->sc_flags.change_suspend = 0;
 666                 sc->sc_flags.change_connect = 1;
 667
 668                 /* disable resume interrupt */
 669                 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
 670                     AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
 671
 672                 /* complete root HUB interrupt endpoint */
 673                 avr32dci_root_intr(sc);
 674         }
 675         /*
 676          * If resume and suspend is set at the same time we interpret
 677          * that like RESUME. Resume is set when there is at least 3
 678          * milliseconds of inactivity on the USB BUS.
 679          */
 680         if (status & AVR32_INT_WAKE_UP) {
 681
 682                 DPRINTFN(5, "resume interrupt\n");
 683
 684                 if (sc->sc_flags.status_suspend) {
 685                         /* update status bits */
 686                         sc->sc_flags.status_suspend = 0;
 687                         sc->sc_flags.change_suspend = 1;
 688
 689                         /* disable resume interrupt */
 690                         avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
 691                             AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
 692
 693                         /* complete root HUB interrupt endpoint */
 694                         avr32dci_root_intr(sc);
 695                 }
 696         } else if (status & AVR32_INT_DET_SUSPD) {
 697
 698                 DPRINTFN(5, "suspend interrupt\n");
 699
 700                 if (!sc->sc_flags.status_suspend) {
 701                         /* update status bits */
 702                         sc->sc_flags.status_suspend = 1;
 703                         sc->sc_flags.change_suspend = 1;
 704
 705                         /* disable suspend interrupt */
 706                         avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP |
 707                             AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD);
 708
 709                         /* complete root HUB interrupt endpoint */
 710                         avr32dci_root_intr(sc);
 711                 }
 712         }
 713         /* check for any endpoint interrupts */
 714         if (status & -AVR32_INT_EPT_INT(0)) {
 715
 716                 DPRINTFN(5, "real endpoint interrupt\n");
 717
 718                 avr32dci_interrupt_poll(sc);
 719         }
 720         USB_BUS_UNLOCK(&sc->sc_bus);
 721 }
 722
 723 static void
 724 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp)
 725 {
 726         struct avr32dci_td *td;
 727
 728         /* get current Transfer Descriptor */
 729         td = temp->td_next;
 730         temp->td = td;
 731
 732         /* prepare for next TD */
 733         temp->td_next = td->obj_next;
 734
 735         /* fill out the Transfer Descriptor */
 736         td->func = temp->func;
 737         td->pc = temp->pc;
 738         td->offset = temp->offset;
 739         td->remainder = temp->len;
 740         td->error = 0;
 741         td->did_stall = temp->did_stall;
 742         td->short_pkt = temp->short_pkt;
 743         td->alt_next = temp->setup_alt_next;
 744 }
 745
 746 static void
 747 avr32dci_setup_standard_chain(struct usb_xfer *xfer)
 748 {
 749         struct avr32dci_std_temp temp;
 750         struct avr32dci_softc *sc;
 751         struct avr32dci_td *td;
 752         uint32_t x;
 753         uint8_t ep_no;
 754         uint8_t need_sync;
 755
 756         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 757             xfer->address, UE_GET_ADDR(xfer->endpointno),
 758             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 759
 760         temp.max_frame_size = xfer->max_frame_size;
 761
 762         td = xfer->td_start[0];
 763         xfer->td_transfer_first = td;
 764         xfer->td_transfer_cache = td;
 765
 766         /* setup temp */
 767
 768         temp.pc = NULL;
 769         temp.td = NULL;
 770         temp.td_next = xfer->td_start[0];
 771         temp.offset = 0;
 772         temp.setup_alt_next = xfer->flags_int.short_frames_ok;
 773         temp.did_stall = !xfer->flags_int.control_stall;
 774
 775         sc = AVR32_BUS2SC(xfer->xroot->bus);
 776         ep_no = (xfer->endpointno & UE_ADDR);
 777
 778         /* check if we should prepend a setup message */
 779
 780         if (xfer->flags_int.control_xfr) {
 781                 if (xfer->flags_int.control_hdr) {
 782
 783                         temp.func = &avr32dci_setup_rx;
 784                         temp.len = xfer->frlengths[0];
 785                         temp.pc = xfer->frbuffers + 0;
 786                         temp.short_pkt = temp.len ? 1 : 0;
 787                         /* check for last frame */
 788                         if (xfer->nframes == 1) {
 789                                 /* no STATUS stage yet, SETUP is last */
 790                                 if (xfer->flags_int.control_act)
 791                                         temp.setup_alt_next = 0;
 792                         }
 793                         avr32dci_setup_standard_chain_sub(&temp);
 794                 }
 795                 x = 1;
 796         } else {
 797                 x = 0;
 798         }
 799
 800         if (x != xfer->nframes) {
 801                 if (xfer->endpointno & UE_DIR_IN) {
 802                         temp.func = &avr32dci_data_tx;
 803                         need_sync = 1;
 804                 } else {
 805                         temp.func = &avr32dci_data_rx;
 806                         need_sync = 0;
 807                 }
 808
 809                 /* setup "pc" pointer */
 810                 temp.pc = xfer->frbuffers + x;
 811         } else {
 812                 need_sync = 0;
 813         }
 814         while (x != xfer->nframes) {
 815
 816                 /* DATA0 / DATA1 message */
 817
 818                 temp.len = xfer->frlengths[x];
 819
 820                 x++;
 821
 822                 if (x == xfer->nframes) {
 823                         if (xfer->flags_int.control_xfr) {
 824                                 if (xfer->flags_int.control_act) {
 825                                         temp.setup_alt_next = 0;
 826                                 }
 827                         } else {
 828                                 temp.setup_alt_next = 0;
 829                         }
 830                 }
 831                 if (temp.len == 0) {
 832
 833                         /* make sure that we send an USB packet */
 834
 835                         temp.short_pkt = 0;
 836
 837                 } else {
 838
 839                         /* regular data transfer */
 840
 841                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
 842                 }
 843
 844                 avr32dci_setup_standard_chain_sub(&temp);
 845
 846                 if (xfer->flags_int.isochronous_xfr) {
 847                         temp.offset += temp.len;
 848                 } else {
 849                         /* get next Page Cache pointer */
 850                         temp.pc = xfer->frbuffers + x;
 851                 }
 852         }
 853
 854         if (xfer->flags_int.control_xfr) {
 855
 856                 /* always setup a valid "pc" pointer for status and sync */
 857                 temp.pc = xfer->frbuffers + 0;
 858                 temp.len = 0;
 859                 temp.short_pkt = 0;
 860                 temp.setup_alt_next = 0;
 861
 862                 /* check if we need to sync */
 863                 if (need_sync) {
 864                         /* we need a SYNC point after TX */
 865                         temp.func = &avr32dci_data_tx_sync;
 866                         avr32dci_setup_standard_chain_sub(&temp);
 867                 }
 868                 /* check if we should append a status stage */
 869                 if (!xfer->flags_int.control_act) {
 870
 871                         /*
 872                          * Send a DATA1 message and invert the current
 873                          * endpoint direction.
 874                          */
 875                         if (xfer->endpointno & UE_DIR_IN) {
 876                                 temp.func = &avr32dci_data_rx;
 877                                 need_sync = 0;
 878                         } else {
 879                                 temp.func = &avr32dci_data_tx;
 880                                 need_sync = 1;
 881                         }
 882
 883                         avr32dci_setup_standard_chain_sub(&temp);
 884                         if (need_sync) {
 885                                 /* we need a SYNC point after TX */
 886                                 temp.func = &avr32dci_data_tx_sync;
 887                                 avr32dci_setup_standard_chain_sub(&temp);
 888                         }
 889                 }
 890         }
 891         /* must have at least one frame! */
 892         td = temp.td;
 893         xfer->td_transfer_last = td;
 894 }
 895
 896 static void
 897 avr32dci_timeout(void *arg)
 898 {
 899         struct usb_xfer *xfer = arg;
 900
 901         DPRINTF("xfer=%p\n", xfer);
 902
 903         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
 904
 905         /* transfer is transferred */
 906         avr32dci_device_done(xfer, USB_ERR_TIMEOUT);
 907 }
 908
 909 static void
 910 avr32dci_start_standard_chain(struct usb_xfer *xfer)
 911 {
 912         DPRINTFN(9, "\n");
 913
 914         /* poll one time - will turn on interrupts */
 915         if (avr32dci_xfer_do_fifo(xfer)) {
 916                 uint8_t ep_no = xfer->endpointno & UE_ADDR;
 917                 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
 918
 919                 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0);
 920
 921                 /* put transfer on interrupt queue */
 922                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
 923
 924                 /* start timeout, if any */
 925                 if (xfer->timeout != 0) {
 926                         usbd_transfer_timeout_ms(xfer,
 927                             &avr32dci_timeout, xfer->timeout);
 928                 }
 929         }
 930 }
 931
 932 static void
 933 avr32dci_root_intr(struct avr32dci_softc *sc)
 934 {
 935         DPRINTFN(9, "\n");
 936
 937         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
 938
 939         /* set port bit */
 940         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
 941
 942         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
 943             sizeof(sc->sc_hub_idata));
 944 }
 945
 946 static usb_error_t
 947 avr32dci_standard_done_sub(struct usb_xfer *xfer)
 948 {
 949         struct avr32dci_td *td;
 950         uint32_t len;
 951         uint8_t error;
 952
 953         DPRINTFN(9, "\n");
 954
 955         td = xfer->td_transfer_cache;
 956
 957         do {
 958                 len = td->remainder;
 959
 960                 if (xfer->aframes != xfer->nframes) {
 961                         /*
 962                          * Verify the length and subtract
 963                          * the remainder from "frlengths[]":
 964                          */
 965                         if (len > xfer->frlengths[xfer->aframes]) {
 966                                 td->error = 1;
 967                         } else {
 968                                 xfer->frlengths[xfer->aframes] -= len;
 969                         }
 970                 }
 971                 /* Check for transfer error */
 972                 if (td->error) {
 973                         /* the transfer is finished */
 974                         error = 1;
 975                         td = NULL;
 976                         break;
 977                 }
 978                 /* Check for short transfer */
 979                 if (len > 0) {
 980                         if (xfer->flags_int.short_frames_ok) {
 981                                 /* follow alt next */
 982                                 if (td->alt_next) {
 983                                         td = td->obj_next;
 984                                 } else {
 985                                         td = NULL;
 986                                 }
 987                         } else {
 988                                 /* the transfer is finished */
 989                                 td = NULL;
 990                         }
 991                         error = 0;
 992                         break;
 993                 }
 994                 td = td->obj_next;
 995
 996                 /* this USB frame is complete */
 997                 error = 0;
 998                 break;
 999
1000         } while (0);
1001
1002         /* update transfer cache */
1003
1004         xfer->td_transfer_cache = td;
1005
1006         return (error ?
1007             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1008 }
1009
1010 static void
1011 avr32dci_standard_done(struct usb_xfer *xfer)
1012 {
1013         usb_error_t err = 0;
1014
1015         DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
1016             xfer, xfer->endpoint);
1017
1018         /* reset scanner */
1019
1020         xfer->td_transfer_cache = xfer->td_transfer_first;
1021
1022         if (xfer->flags_int.control_xfr) {
1023
1024                 if (xfer->flags_int.control_hdr) {
1025
1026                         err = avr32dci_standard_done_sub(xfer);
1027                 }
1028                 xfer->aframes = 1;
1029
1030                 if (xfer->td_transfer_cache == NULL) {
1031                         goto done;
1032                 }
1033         }
1034         while (xfer->aframes != xfer->nframes) {
1035
1036                 err = avr32dci_standard_done_sub(xfer);
1037                 xfer->aframes++;
1038
1039                 if (xfer->td_transfer_cache == NULL) {
1040                         goto done;
1041                 }
1042         }
1043
1044         if (xfer->flags_int.control_xfr &&
1045             !xfer->flags_int.control_act) {
1046
1047                 err = avr32dci_standard_done_sub(xfer);
1048         }
1049 done:
1050         avr32dci_device_done(xfer, err);
1051 }
1052
1053 /*------------------------------------------------------------------------*
1054  *      avr32dci_device_done
1055  *
1056  * NOTE: this function can be called more than one time on the
1057  * same USB transfer!
1058  *------------------------------------------------------------------------*/
1059 static void
1060 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1061 {
1062         struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1063         uint8_t ep_no;
1064
1065         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1066
1067         DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n",
1068             xfer, xfer->endpoint, error);
1069
1070         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1071                 ep_no = (xfer->endpointno & UE_ADDR);
1072
1073                 /* disable endpoint interrupt */
1074                 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no));
1075
1076                 DPRINTFN(15, "disabled interrupts!\n");
1077         }
1078         /* dequeue transfer and start next transfer */
1079         usbd_transfer_done(xfer, error);
1080 }
1081
1082 static void
1083 avr32dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1084     struct usb_endpoint *pipe, uint8_t *did_stall)
1085 {
1086         struct avr32dci_softc *sc;
1087         uint8_t ep_no;
1088
1089         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1090
1091         DPRINTFN(5, "pipe=%p\n", pipe);
1092
1093         if (xfer) {
1094                 /* cancel any ongoing transfers */
1095                 avr32dci_device_done(xfer, USB_ERR_STALLED);
1096         }
1097         sc = AVR32_BUS2SC(udev->bus);
1098         /* get endpoint number */
1099         ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1100         /* set stall */
1101         AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1102 }
1103
1104 static void
1105 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no,
1106     uint8_t ep_type, uint8_t ep_dir)
1107 {
1108         const struct usb_hw_ep_profile *pf;
1109         uint32_t temp;
1110         uint32_t epsize;
1111         uint8_t n;
1112
1113         if (ep_type == UE_CONTROL) {
1114                 /* clearing stall is not needed */
1115                 return;
1116         }
1117         /* set endpoint reset */
1118         AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no));
1119
1120         /* set stall */
1121         AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1122
1123         /* reset data toggle */
1124         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ);
1125
1126         /* clear stall */
1127         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1128
1129         if (ep_type == UE_BULK) {
1130                 temp = AVR32_EPTCFG_TYPE_BULK;
1131         } else if (ep_type == UE_INTERRUPT) {
1132                 temp = AVR32_EPTCFG_TYPE_INTR;
1133         } else {
1134                 temp = AVR32_EPTCFG_TYPE_ISOC |
1135                     AVR32_EPTCFG_NB_TRANS(1);
1136         }
1137         if (ep_dir & UE_DIR_IN) {
1138                 temp |= AVR32_EPTCFG_EPDIR_IN;
1139         }
1140         avr32dci_get_hw_ep_profile(NULL, &pf, ep_no);
1141
1142         /* compute endpoint size (use maximum) */
1143         epsize = pf->max_in_frame_size | pf->max_out_frame_size;
1144         n = 0;
1145         while ((epsize /= 2))
1146                 n++;
1147         temp |= AVR32_EPTCFG_EPSIZE(n);
1148
1149         /* use the maximum number of banks supported */
1150         if (ep_no < 1)
1151                 temp |= AVR32_EPTCFG_NBANK(1);
1152         else if (ep_no < 3)
1153                 temp |= AVR32_EPTCFG_NBANK(2);
1154         else
1155                 temp |= AVR32_EPTCFG_NBANK(3);
1156
1157         AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp);
1158
1159         temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no));
1160
1161         if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1162                 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n");
1163         } else {
1164                 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no),
1165                     AVR32_EPTCTL_EPT_ENABL);
1166         }
1167 }
1168
1169 static void
1170 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe)
1171 {
1172         struct avr32dci_softc *sc;
1173         struct usb_endpoint_descriptor *ed;
1174
1175         DPRINTFN(5, "pipe=%p\n", pipe);
1176
1177         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1178
1179         /* check mode */
1180         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1181                 /* not supported */
1182                 return;
1183         }
1184         /* get softc */
1185         sc = AVR32_BUS2SC(udev->bus);
1186
1187         /* get endpoint descriptor */
1188         ed = pipe->edesc;
1189
1190         /* reset endpoint */
1191         avr32dci_clear_stall_sub(sc,
1192             (ed->bEndpointAddress & UE_ADDR),
1193             (ed->bmAttributes & UE_XFERTYPE),
1194             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1195 }
1196
1197 usb_error_t
1198 avr32dci_init(struct avr32dci_softc *sc)
1199 {
1200         uint8_t n;
1201
1202         DPRINTF("start\n");
1203
1204         /* set up the bus structure */
1205         sc->sc_bus.usbrev = USB_REV_1_1;
1206         sc->sc_bus.methods = &avr32dci_bus_methods;
1207
1208         USB_BUS_LOCK(&sc->sc_bus);
1209
1210         /* make sure USB is enabled */
1211         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
1212
1213         /* turn on clocks */
1214         (sc->sc_clocks_on) (&sc->sc_bus);
1215
1216         /* make sure device is re-enumerated */
1217         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
1218
1219         /* wait a little for things to stabilise */
1220         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1221
1222         /* disable interrupts */
1223         avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1224
1225         /* enable interrupts */
1226         avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
1227             AVR32_INT_ENDRESET, 0);
1228
1229         /* reset all endpoints */
1230         AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1);
1231
1232         /* disable all endpoints */
1233         for (n = 0; n != AVR32_EP_MAX; n++) {
1234                 /* disable endpoint */
1235                 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1236         }
1237
1238         /* turn off clocks */
1239
1240         avr32dci_clocks_off(sc);
1241
1242         USB_BUS_UNLOCK(&sc->sc_bus);
1243
1244         /* catch any lost interrupts */
1245
1246         avr32dci_do_poll(&sc->sc_bus);
1247
1248         return (0);                     /* success */
1249 }
1250
1251 void
1252 avr32dci_uninit(struct avr32dci_softc *sc)
1253 {
1254         uint8_t n;
1255
1256         USB_BUS_LOCK(&sc->sc_bus);
1257
1258         /* turn on clocks */
1259         (sc->sc_clocks_on) (&sc->sc_bus);
1260
1261         /* disable interrupts */
1262         avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1263
1264         /* reset all endpoints */
1265         AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1);
1266
1267         /* disable all endpoints */
1268         for (n = 0; n != AVR32_EP_MAX; n++) {
1269                 /* disable endpoint */
1270                 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1271         }
1272
1273         sc->sc_flags.port_powered = 0;
1274         sc->sc_flags.status_vbus = 0;
1275         sc->sc_flags.status_bus_reset = 0;
1276         sc->sc_flags.status_suspend = 0;
1277         sc->sc_flags.change_suspend = 0;
1278         sc->sc_flags.change_connect = 1;
1279
1280         avr32dci_pull_down(sc);
1281         avr32dci_clocks_off(sc);
1282
1283         USB_BUS_UNLOCK(&sc->sc_bus);
1284 }
1285
1286 static void
1287 avr32dci_suspend(struct avr32dci_softc *sc)
1288 {
1289         /* TODO */
1290 }
1291
1292 static void
1293 avr32dci_resume(struct avr32dci_softc *sc)
1294 {
1295         /* TODO */
1296 }
1297
1298 static void
1299 avr32dci_do_poll(struct usb_bus *bus)
1300 {
1301         struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
1302
1303         USB_BUS_LOCK(&sc->sc_bus);
1304         avr32dci_interrupt_poll(sc);
1305         USB_BUS_UNLOCK(&sc->sc_bus);
1306 }
1307
1308 /*------------------------------------------------------------------------*
1309  * at91dci bulk support
1310  * at91dci control support
1311  * at91dci interrupt support
1312  *------------------------------------------------------------------------*/
1313 static void
1314 avr32dci_device_non_isoc_open(struct usb_xfer *xfer)
1315 {
1316         return;
1317 }
1318
1319 static void
1320 avr32dci_device_non_isoc_close(struct usb_xfer *xfer)
1321 {
1322         avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1323 }
1324
1325 static void
1326 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer)
1327 {
1328         return;
1329 }
1330
1331 static void
1332 avr32dci_device_non_isoc_start(struct usb_xfer *xfer)
1333 {
1334         /* setup TDs */
1335         avr32dci_setup_standard_chain(xfer);
1336         avr32dci_start_standard_chain(xfer);
1337 }
1338
1339 struct usb_pipe_methods avr32dci_device_non_isoc_methods =
1340 {
1341         .open = avr32dci_device_non_isoc_open,
1342         .close = avr32dci_device_non_isoc_close,
1343         .enter = avr32dci_device_non_isoc_enter,
1344         .start = avr32dci_device_non_isoc_start,
1345 };
1346
1347 /*------------------------------------------------------------------------*
1348  * at91dci full speed isochronous support
1349  *------------------------------------------------------------------------*/
1350 static void
1351 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer)
1352 {
1353         return;
1354 }
1355
1356 static void
1357 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer)
1358 {
1359         avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1360 }
1361
1362 static void
1363 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1364 {
1365         struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1366         uint32_t temp;
1367         uint32_t nframes;
1368         uint8_t ep_no;
1369
1370         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1371             xfer, xfer->endpoint->isoc_next, xfer->nframes);
1372
1373         /* get the current frame index */
1374         ep_no = xfer->endpointno & UE_ADDR;
1375         nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8);
1376
1377         nframes &= AVR32_FRAME_MASK;
1378
1379         /*
1380          * check if the frame index is within the window where the frames
1381          * will be inserted
1382          */
1383         temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK;
1384
1385         if ((xfer->endpoint->is_synced == 0) ||
1386             (temp < xfer->nframes)) {
1387                 /*
1388                  * If there is data underflow or the pipe queue is
1389                  * empty we schedule the transfer a few frames ahead
1390                  * of the current frame position. Else two isochronous
1391                  * transfers might overlap.
1392                  */
1393                 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
1394                 xfer->endpoint->is_synced = 1;
1395                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1396         }
1397         /*
1398          * compute how many milliseconds the insertion is ahead of the
1399          * current frame position:
1400          */
1401         temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK;
1402
1403         /*
1404          * pre-compute when the isochronous transfer will be finished:
1405          */
1406         xfer->isoc_time_complete =
1407             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1408             xfer->nframes;
1409
1410         /* compute frame number for next insertion */
1411         xfer->endpoint->isoc_next += xfer->nframes;
1412
1413         /* setup TDs */
1414         avr32dci_setup_standard_chain(xfer);
1415 }
1416
1417 static void
1418 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer)
1419 {
1420         /* start TD chain */
1421         avr32dci_start_standard_chain(xfer);
1422 }
1423
1424 struct usb_pipe_methods avr32dci_device_isoc_fs_methods =
1425 {
1426         .open = avr32dci_device_isoc_fs_open,
1427         .close = avr32dci_device_isoc_fs_close,
1428         .enter = avr32dci_device_isoc_fs_enter,
1429         .start = avr32dci_device_isoc_fs_start,
1430 };
1431
1432 /*------------------------------------------------------------------------*
1433  * at91dci root control support
1434  *------------------------------------------------------------------------*
1435  * Simulate a hardware HUB by handling all the necessary requests.
1436  *------------------------------------------------------------------------*/
1437
1438 static const struct usb_device_descriptor avr32dci_devd = {
1439         .bLength = sizeof(struct usb_device_descriptor),
1440         .bDescriptorType = UDESC_DEVICE,
1441         .bcdUSB = {0x00, 0x02},
1442         .bDeviceClass = UDCLASS_HUB,
1443         .bDeviceSubClass = UDSUBCLASS_HUB,
1444         .bDeviceProtocol = UDPROTO_HSHUBSTT,
1445         .bMaxPacketSize = 64,
1446         .bcdDevice = {0x00, 0x01},
1447         .iManufacturer = 1,
1448         .iProduct = 2,
1449         .bNumConfigurations = 1,
1450 };
1451
1452 static const struct usb_device_qualifier avr32dci_odevd = {
1453         .bLength = sizeof(struct usb_device_qualifier),
1454         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1455         .bcdUSB = {0x00, 0x02},
1456         .bDeviceClass = UDCLASS_HUB,
1457         .bDeviceSubClass = UDSUBCLASS_HUB,
1458         .bDeviceProtocol = UDPROTO_FSHUB,
1459         .bMaxPacketSize0 = 0,
1460         .bNumConfigurations = 0,
1461 };
1462
1463 static const struct avr32dci_config_desc avr32dci_confd = {
1464         .confd = {
1465                 .bLength = sizeof(struct usb_config_descriptor),
1466                 .bDescriptorType = UDESC_CONFIG,
1467                 .wTotalLength[0] = sizeof(avr32dci_confd),
1468                 .bNumInterface = 1,
1469                 .bConfigurationValue = 1,
1470                 .iConfiguration = 0,
1471                 .bmAttributes = UC_SELF_POWERED,
1472                 .bMaxPower = 0,
1473         },
1474         .ifcd = {
1475                 .bLength = sizeof(struct usb_interface_descriptor),
1476                 .bDescriptorType = UDESC_INTERFACE,
1477                 .bNumEndpoints = 1,
1478                 .bInterfaceClass = UICLASS_HUB,
1479                 .bInterfaceSubClass = UISUBCLASS_HUB,
1480                 .bInterfaceProtocol = 0,
1481         },
1482         .endpd = {
1483                 .bLength = sizeof(struct usb_endpoint_descriptor),
1484                 .bDescriptorType = UDESC_ENDPOINT,
1485                 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT),
1486                 .bmAttributes = UE_INTERRUPT,
1487                 .wMaxPacketSize[0] = 8,
1488                 .bInterval = 255,
1489         },
1490 };
1491
1492 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1493
1494 static const struct usb_hub_descriptor_min avr32dci_hubd = {
1495         .bDescLength = sizeof(avr32dci_hubd),
1496         .bDescriptorType = UDESC_HUB,
1497         .bNbrPorts = 1,
1498         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1499         .bPwrOn2PwrGood = 50,
1500         .bHubContrCurrent = 0,
1501         .DeviceRemovable = {0},         /* port is removable */
1502 };
1503
1504 #define STRING_LANG \
1505   0x09, 0x04,                           /* American English */
1506
1507 #define STRING_VENDOR \
1508   'A', 0, 'V', 0, 'R', 0, '3', 0, '2', 0
1509
1510 #define STRING_PRODUCT \
1511   'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1512   'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1513   'U', 0, 'B', 0,
1514
1515 USB_MAKE_STRING_DESC(STRING_LANG, avr32dci_langtab);
1516 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor);
1517 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product);
1518
1519 static usb_error_t
1520 avr32dci_roothub_exec(struct usb_device *udev,
1521     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1522 {
1523         struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
1524         const void *ptr;
1525         uint16_t len;
1526         uint16_t value;
1527         uint16_t index;
1528         uint32_t temp;
1529         usb_error_t err;
1530
1531         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1532
1533         /* buffer reset */
1534         ptr = (const void *)&sc->sc_hub_temp;
1535         len = 0;
1536         err = 0;
1537
1538         value = UGETW(req->wValue);
1539         index = UGETW(req->wIndex);
1540
1541         /* demultiplex the control request */
1542
1543         switch (req->bmRequestType) {
1544         case UT_READ_DEVICE:
1545                 switch (req->bRequest) {
1546                 case UR_GET_DESCRIPTOR:
1547                         goto tr_handle_get_descriptor;
1548                 case UR_GET_CONFIG:
1549                         goto tr_handle_get_config;
1550                 case UR_GET_STATUS:
1551                         goto tr_handle_get_status;
1552                 default:
1553                         goto tr_stalled;
1554                 }
1555                 break;
1556
1557         case UT_WRITE_DEVICE:
1558                 switch (req->bRequest) {
1559                 case UR_SET_ADDRESS:
1560                         goto tr_handle_set_address;
1561                 case UR_SET_CONFIG:
1562                         goto tr_handle_set_config;
1563                 case UR_CLEAR_FEATURE:
1564                         goto tr_valid;  /* nop */
1565                 case UR_SET_DESCRIPTOR:
1566                         goto tr_valid;  /* nop */
1567                 case UR_SET_FEATURE:
1568                 default:
1569                         goto tr_stalled;
1570                 }
1571                 break;
1572
1573         case UT_WRITE_ENDPOINT:
1574                 switch (req->bRequest) {
1575                 case UR_CLEAR_FEATURE:
1576                         switch (UGETW(req->wValue)) {
1577                         case UF_ENDPOINT_HALT:
1578                                 goto tr_handle_clear_halt;
1579                         case UF_DEVICE_REMOTE_WAKEUP:
1580                                 goto tr_handle_clear_wakeup;
1581                         default:
1582                                 goto tr_stalled;
1583                         }
1584                         break;
1585                 case UR_SET_FEATURE:
1586                         switch (UGETW(req->wValue)) {
1587                         case UF_ENDPOINT_HALT:
1588                                 goto tr_handle_set_halt;
1589                         case UF_DEVICE_REMOTE_WAKEUP:
1590                                 goto tr_handle_set_wakeup;
1591                         default:
1592                                 goto tr_stalled;
1593                         }
1594                         break;
1595                 case UR_SYNCH_FRAME:
1596                         goto tr_valid;  /* nop */
1597                 default:
1598                         goto tr_stalled;
1599                 }
1600                 break;
1601
1602         case UT_READ_ENDPOINT:
1603                 switch (req->bRequest) {
1604                 case UR_GET_STATUS:
1605                         goto tr_handle_get_ep_status;
1606                 default:
1607                         goto tr_stalled;
1608                 }
1609                 break;
1610
1611         case UT_WRITE_INTERFACE:
1612                 switch (req->bRequest) {
1613                 case UR_SET_INTERFACE:
1614                         goto tr_handle_set_interface;
1615                 case UR_CLEAR_FEATURE:
1616                         goto tr_valid;  /* nop */
1617                 case UR_SET_FEATURE:
1618                 default:
1619                         goto tr_stalled;
1620                 }
1621                 break;
1622
1623         case UT_READ_INTERFACE:
1624                 switch (req->bRequest) {
1625                 case UR_GET_INTERFACE:
1626                         goto tr_handle_get_interface;
1627                 case UR_GET_STATUS:
1628                         goto tr_handle_get_iface_status;
1629                 default:
1630                         goto tr_stalled;
1631                 }
1632                 break;
1633
1634         case UT_WRITE_CLASS_INTERFACE:
1635         case UT_WRITE_VENDOR_INTERFACE:
1636                 /* XXX forward */
1637                 break;
1638
1639         case UT_READ_CLASS_INTERFACE:
1640         case UT_READ_VENDOR_INTERFACE:
1641                 /* XXX forward */
1642                 break;
1643
1644         case UT_WRITE_CLASS_DEVICE:
1645                 switch (req->bRequest) {
1646                 case UR_CLEAR_FEATURE:
1647                         goto tr_valid;
1648                 case UR_SET_DESCRIPTOR:
1649                 case UR_SET_FEATURE:
1650                         break;
1651                 default:
1652                         goto tr_stalled;
1653                 }
1654                 break;
1655
1656         case UT_WRITE_CLASS_OTHER:
1657                 switch (req->bRequest) {
1658                 case UR_CLEAR_FEATURE:
1659                         goto tr_handle_clear_port_feature;
1660                 case UR_SET_FEATURE:
1661                         goto tr_handle_set_port_feature;
1662                 case UR_CLEAR_TT_BUFFER:
1663                 case UR_RESET_TT:
1664                 case UR_STOP_TT:
1665                         goto tr_valid;
1666
1667                 default:
1668                         goto tr_stalled;
1669                 }
1670                 break;
1671
1672         case UT_READ_CLASS_OTHER:
1673                 switch (req->bRequest) {
1674                 case UR_GET_TT_STATE:
1675                         goto tr_handle_get_tt_state;
1676                 case UR_GET_STATUS:
1677                         goto tr_handle_get_port_status;
1678                 default:
1679                         goto tr_stalled;
1680                 }
1681                 break;
1682
1683         case UT_READ_CLASS_DEVICE:
1684                 switch (req->bRequest) {
1685                 case UR_GET_DESCRIPTOR:
1686                         goto tr_handle_get_class_descriptor;
1687                 case UR_GET_STATUS:
1688                         goto tr_handle_get_class_status;
1689
1690                 default:
1691                         goto tr_stalled;
1692                 }
1693                 break;
1694         default:
1695                 goto tr_stalled;
1696         }
1697         goto tr_valid;
1698
1699 tr_handle_get_descriptor:
1700         switch (value >> 8) {
1701         case UDESC_DEVICE:
1702                 if (value & 0xff) {
1703                         goto tr_stalled;
1704                 }
1705                 len = sizeof(avr32dci_devd);
1706                 ptr = (const void *)&avr32dci_devd;
1707                 goto tr_valid;
1708         case UDESC_CONFIG:
1709                 if (value & 0xff) {
1710                         goto tr_stalled;
1711                 }
1712                 len = sizeof(avr32dci_confd);
1713                 ptr = (const void *)&avr32dci_confd;
1714                 goto tr_valid;
1715         case UDESC_STRING:
1716                 switch (value & 0xff) {
1717                 case 0:         /* Language table */
1718                         len = sizeof(avr32dci_langtab);
1719                         ptr = (const void *)&avr32dci_langtab;
1720                         goto tr_valid;
1721
1722                 case 1:         /* Vendor */
1723                         len = sizeof(avr32dci_vendor);
1724                         ptr = (const void *)&avr32dci_vendor;
1725                         goto tr_valid;
1726
1727                 case 2:         /* Product */
1728                         len = sizeof(avr32dci_product);
1729                         ptr = (const void *)&avr32dci_product;
1730                         goto tr_valid;
1731                 default:
1732                         break;
1733                 }
1734                 break;
1735         default:
1736                 goto tr_stalled;
1737         }
1738         goto tr_stalled;
1739
1740 tr_handle_get_config:
1741         len = 1;
1742         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1743         goto tr_valid;
1744
1745 tr_handle_get_status:
1746         len = 2;
1747         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1748         goto tr_valid;
1749
1750 tr_handle_set_address:
1751         if (value & 0xFF00) {
1752                 goto tr_stalled;
1753         }
1754         sc->sc_rt_addr = value;
1755         goto tr_valid;
1756
1757 tr_handle_set_config:
1758         if (value >= 2) {
1759                 goto tr_stalled;
1760         }
1761         sc->sc_conf = value;
1762         goto tr_valid;
1763
1764 tr_handle_get_interface:
1765         len = 1;
1766         sc->sc_hub_temp.wValue[0] = 0;
1767         goto tr_valid;
1768
1769 tr_handle_get_tt_state:
1770 tr_handle_get_class_status:
1771 tr_handle_get_iface_status:
1772 tr_handle_get_ep_status:
1773         len = 2;
1774         USETW(sc->sc_hub_temp.wValue, 0);
1775         goto tr_valid;
1776
1777 tr_handle_set_halt:
1778 tr_handle_set_interface:
1779 tr_handle_set_wakeup:
1780 tr_handle_clear_wakeup:
1781 tr_handle_clear_halt:
1782         goto tr_valid;
1783
1784 tr_handle_clear_port_feature:
1785         if (index != 1) {
1786                 goto tr_stalled;
1787         }
1788         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1789
1790         switch (value) {
1791         case UHF_PORT_SUSPEND:
1792                 avr32dci_wakeup_peer(sc);
1793                 break;
1794
1795         case UHF_PORT_ENABLE:
1796                 sc->sc_flags.port_enabled = 0;
1797                 break;
1798
1799         case UHF_PORT_TEST:
1800         case UHF_PORT_INDICATOR:
1801         case UHF_C_PORT_ENABLE:
1802         case UHF_C_PORT_OVER_CURRENT:
1803         case UHF_C_PORT_RESET:
1804                 /* nops */
1805                 break;
1806         case UHF_PORT_POWER:
1807                 sc->sc_flags.port_powered = 0;
1808                 avr32dci_pull_down(sc);
1809                 avr32dci_clocks_off(sc);
1810                 break;
1811         case UHF_C_PORT_CONNECTION:
1812                 /* clear connect change flag */
1813                 sc->sc_flags.change_connect = 0;
1814
1815                 if (!sc->sc_flags.status_bus_reset) {
1816                         /* we are not connected */
1817                         break;
1818                 }
1819                 /* configure the control endpoint */
1820                 /* set endpoint reset */
1821                 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0));
1822
1823                 /* set stall */
1824                 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL);
1825
1826                 /* reset data toggle */
1827                 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ);
1828
1829                 /* clear stall */
1830                 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL);
1831
1832                 /* configure */
1833                 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL |
1834                     AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6));
1835
1836                 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0));
1837
1838                 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1839                         device_printf(sc->sc_bus.bdev,
1840                             "Chip rejected configuration\n");
1841                 } else {
1842                         AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0),
1843                             AVR32_EPTCTL_EPT_ENABL);
1844                 }
1845                 break;
1846         case UHF_C_PORT_SUSPEND:
1847                 sc->sc_flags.change_suspend = 0;
1848                 break;
1849         default:
1850                 err = USB_ERR_IOERROR;
1851                 goto done;
1852         }
1853         goto tr_valid;
1854
1855 tr_handle_set_port_feature:
1856         if (index != 1) {
1857                 goto tr_stalled;
1858         }
1859         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1860
1861         switch (value) {
1862         case UHF_PORT_ENABLE:
1863                 sc->sc_flags.port_enabled = 1;
1864                 break;
1865         case UHF_PORT_SUSPEND:
1866         case UHF_PORT_RESET:
1867         case UHF_PORT_TEST:
1868         case UHF_PORT_INDICATOR:
1869                 /* nops */
1870                 break;
1871         case UHF_PORT_POWER:
1872                 sc->sc_flags.port_powered = 1;
1873                 break;
1874         default:
1875                 err = USB_ERR_IOERROR;
1876                 goto done;
1877         }
1878         goto tr_valid;
1879
1880 tr_handle_get_port_status:
1881
1882         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1883
1884         if (index != 1) {
1885                 goto tr_stalled;
1886         }
1887         if (sc->sc_flags.status_vbus) {
1888                 avr32dci_clocks_on(sc);
1889                 avr32dci_pull_up(sc);
1890         } else {
1891                 avr32dci_pull_down(sc);
1892                 avr32dci_clocks_off(sc);
1893         }
1894
1895         /* Select Device Side Mode */
1896
1897         value = UPS_PORT_MODE_DEVICE;
1898
1899         /* Check for High Speed */
1900         if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED)
1901                 value |= UPS_HIGH_SPEED;
1902
1903         if (sc->sc_flags.port_powered) {
1904                 value |= UPS_PORT_POWER;
1905         }
1906         if (sc->sc_flags.port_enabled) {
1907                 value |= UPS_PORT_ENABLED;
1908         }
1909         if (sc->sc_flags.status_vbus &&
1910             sc->sc_flags.status_bus_reset) {
1911                 value |= UPS_CURRENT_CONNECT_STATUS;
1912         }
1913         if (sc->sc_flags.status_suspend) {
1914                 value |= UPS_SUSPEND;
1915         }
1916         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1917
1918         value = 0;
1919
1920         if (sc->sc_flags.change_connect) {
1921                 value |= UPS_C_CONNECT_STATUS;
1922         }
1923         if (sc->sc_flags.change_suspend) {
1924                 value |= UPS_C_SUSPEND;
1925         }
1926         USETW(sc->sc_hub_temp.ps.wPortChange, value);
1927         len = sizeof(sc->sc_hub_temp.ps);
1928         goto tr_valid;
1929
1930 tr_handle_get_class_descriptor:
1931         if (value & 0xFF) {
1932                 goto tr_stalled;
1933         }
1934         ptr = (const void *)&avr32dci_hubd;
1935         len = sizeof(avr32dci_hubd);
1936         goto tr_valid;
1937
1938 tr_stalled:
1939         err = USB_ERR_STALLED;
1940 tr_valid:
1941 done:
1942         *plength = len;
1943         *pptr = ptr;
1944         return (err);
1945 }
1946
1947 static void
1948 avr32dci_xfer_setup(struct usb_setup_params *parm)
1949 {
1950         const struct usb_hw_ep_profile *pf;
1951         struct avr32dci_softc *sc;
1952         struct usb_xfer *xfer;
1953         void *last_obj;
1954         uint32_t ntd;
1955         uint32_t n;
1956         uint8_t ep_no;
1957
1958         sc = AVR32_BUS2SC(parm->udev->bus);
1959         xfer = parm->curr_xfer;
1960
1961         /*
1962          * NOTE: This driver does not use any of the parameters that
1963          * are computed from the following values. Just set some
1964          * reasonable dummies:
1965          */
1966         parm->hc_max_packet_size = 0x400;
1967         parm->hc_max_packet_count = 1;
1968         parm->hc_max_frame_size = 0x400;
1969
1970         usbd_transfer_setup_sub(parm);
1971
1972         /*
1973          * compute maximum number of TDs
1974          */
1975         if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
1976
1977                 ntd = xfer->nframes + 1 /* STATUS */ + 1        /* SYNC 1 */
1978                     + 1 /* SYNC 2 */ ;
1979         } else {
1980
1981                 ntd = xfer->nframes + 1 /* SYNC */ ;
1982         }
1983
1984         /*
1985          * check if "usbd_transfer_setup_sub" set an error
1986          */
1987         if (parm->err)
1988                 return;
1989
1990         /*
1991          * allocate transfer descriptors
1992          */
1993         last_obj = NULL;
1994
1995         /*
1996          * get profile stuff
1997          */
1998         ep_no = xfer->endpointno & UE_ADDR;
1999         avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2000
2001         if (pf == NULL) {
2002                 /* should not happen */
2003                 parm->err = USB_ERR_INVAL;
2004                 return;
2005         }
2006         /* align data */
2007         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2008
2009         for (n = 0; n != ntd; n++) {
2010
2011                 struct avr32dci_td *td;
2012
2013                 if (parm->buf) {
2014                         uint32_t temp;
2015
2016                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2017
2018                         /* init TD */
2019                         td->max_packet_size = xfer->max_packet_size;
2020                         td->ep_no = ep_no;
2021                         temp = pf->max_in_frame_size | pf->max_out_frame_size;
2022                         td->bank_shift = 0;
2023                         while ((temp /= 2))
2024                                 td->bank_shift++;
2025                         if (pf->support_multi_buffer) {
2026                                 td->support_multi_buffer = 1;
2027                         }
2028                         td->obj_next = last_obj;
2029
2030                         last_obj = td;
2031                 }
2032                 parm->size[0] += sizeof(*td);
2033         }
2034
2035         xfer->td_start[0] = last_obj;
2036 }
2037
2038 static void
2039 avr32dci_xfer_unsetup(struct usb_xfer *xfer)
2040 {
2041         return;
2042 }
2043
2044 static void
2045 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2046     struct usb_endpoint *pipe)
2047 {
2048         struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
2049
2050         DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2051             pipe, udev->address,
2052             edesc->bEndpointAddress, udev->flags.usb_mode,
2053             sc->sc_rt_addr, udev->device_index);
2054
2055         if (udev->device_index != sc->sc_rt_addr) {
2056
2057                 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2058                         /* not supported */
2059                         return;
2060                 }
2061                 if ((udev->speed != USB_SPEED_FULL) &&
2062                     (udev->speed != USB_SPEED_HIGH)) {
2063                         /* not supported */
2064                         return;
2065                 }
2066                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2067                         pipe->methods = &avr32dci_device_isoc_fs_methods;
2068                 else
2069                         pipe->methods = &avr32dci_device_non_isoc_methods;
2070         }
2071 }
2072
2073 static void
2074 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2075 {
2076         struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
2077
2078         switch (state) {
2079         case USB_HW_POWER_SUSPEND:
2080                 avr32dci_suspend(sc);
2081                 break;
2082         case USB_HW_POWER_SHUTDOWN:
2083                 avr32dci_uninit(sc);
2084                 break;
2085         case USB_HW_POWER_RESUME:
2086                 avr32dci_resume(sc);
2087                 break;
2088         default:
2089                 break;
2090         }
2091 }
2092
2093 struct usb_bus_methods avr32dci_bus_methods =
2094 {
2095         .endpoint_init = &avr32dci_ep_init,
2096         .xfer_setup = &avr32dci_xfer_setup,
2097         .xfer_unsetup = &avr32dci_xfer_unsetup,
2098         .get_hw_ep_profile = &avr32dci_get_hw_ep_profile,
2099         .set_stall = &avr32dci_set_stall,
2100         .clear_stall = &avr32dci_clear_stall,
2101         .roothub_exec = &avr32dci_roothub_exec,
2102         .xfer_poll = &avr32dci_do_poll,
2103         .set_hw_power_sleep = &avr32dci_set_hw_power_sleep,
2104 };