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33 #include <dev/vxge/vxgehal/vxgehal.h>
36 * vxge_hal_mgmt_about - Retrieve about info.
37 * @devh: HAL device handle.
38 * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}.
39 * @size: Pointer to buffer containing the Size of the @buffer_info.
40 * HAL will return an error if the size is smaller than
41 * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field
43 * Retrieve information such as PCI device and vendor IDs, board
44 * revision number, HAL version number, etc.
46 * Returns: VXGE_HAL_OK - success;
47 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
48 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
49 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
50 * VXGE_HAL_FAIL - Failed to retrieve the information.
52 * See also: vxge_hal_mgmt_about_info_t {}.
55 vxge_hal_mgmt_about(vxge_hal_device_h devh,
56 vxge_hal_mgmt_about_info_t *about_info,
59 __hal_device_t *hldev = (__hal_device_t *) devh;
61 vxge_assert((hldev != NULL) && (about_info != NULL) && (size != NULL));
63 vxge_hal_trace_log_device("==> %s:%s:%d",
64 __FILE__, __func__, __LINE__);
66 vxge_hal_trace_log_device(
67 "hldev = 0x"VXGE_OS_STXFMT", about_info = 0x"VXGE_OS_STXFMT", "
68 "size = 0x"VXGE_OS_STXFMT,
69 (ptr_t) hldev, (ptr_t) about_info, (ptr_t) size);
71 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
72 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
73 __FILE__, __func__, __LINE__,
74 VXGE_HAL_ERR_INVALID_DEVICE);
75 return (VXGE_HAL_ERR_INVALID_DEVICE);
78 if (*size < sizeof(vxge_hal_mgmt_about_info_t)) {
79 *size = sizeof(vxge_hal_mgmt_about_info_t);
80 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
81 __FILE__, __func__, __LINE__,
82 VXGE_HAL_ERR_OUT_OF_SPACE);
83 return (VXGE_HAL_ERR_OUT_OF_SPACE);
86 about_info->vendor = hldev->pci_config_space_bios.vendor_id;
87 about_info->device = hldev->pci_config_space_bios.device_id;
88 about_info->subsys_vendor =
89 hldev->pci_config_space_bios.subsystem_vendor_id;
90 about_info->subsys_device = hldev->pci_config_space_bios.subsystem_id;
91 about_info->board_rev = hldev->pci_config_space_bios.revision;
93 vxge_os_strlcpy(about_info->vendor_name, VXGE_DRIVER_VENDOR,
94 sizeof(about_info->vendor_name));
95 vxge_os_strlcpy(about_info->chip_name, VXGE_CHIP_FAMILY,
96 sizeof(about_info->chip_name));
97 vxge_os_strlcpy(about_info->media, VXGE_SUPPORTED_MEDIA_0,
98 sizeof(about_info->media));
100 (void) vxge_os_snprintf(about_info->hal_major,
101 sizeof(about_info->hal_major), "%d", VXGE_HAL_VERSION_MAJOR);
102 (void) vxge_os_snprintf(about_info->hal_minor,
103 sizeof(about_info->hal_minor), "%d", VXGE_HAL_VERSION_MINOR);
104 (void) vxge_os_snprintf(about_info->hal_fix,
105 sizeof(about_info->hal_fix), "%d", VXGE_HAL_VERSION_FIX);
106 (void) vxge_os_snprintf(about_info->hal_build,
107 sizeof(about_info->hal_build), "%d", VXGE_HAL_VERSION_BUILD);
109 (void) vxge_os_snprintf(about_info->ll_major,
110 sizeof(about_info->ll_major), "%d", XGELL_VERSION_MAJOR);
111 (void) vxge_os_snprintf(about_info->ll_minor,
112 sizeof(about_info->ll_minor), "%d", XGELL_VERSION_MINOR);
113 (void) vxge_os_snprintf(about_info->ll_fix,
114 sizeof(about_info->ll_fix), "%d", XGELL_VERSION_FIX);
115 (void) vxge_os_snprintf(about_info->ll_build,
116 sizeof(about_info->ll_build), "%d", XGELL_VERSION_BUILD);
118 *size = sizeof(vxge_hal_mgmt_about_info_t);
120 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
121 __FILE__, __func__, __LINE__);
123 return (VXGE_HAL_OK);
127 * vxge_hal_mgmt_pci_config - Retrieve PCI configuration.
128 * @devh: HAL device handle.
129 * @buffer: Buffer to return pci config.
130 * @size: Pointer to buffer containing the Size of the @buffer.
131 * HAL will return an error if the size is smaller than
132 * sizeof(vxge_hal_pci_config_t) and returns required size in this field
134 * Get PCI configuration. Permits to retrieve at run-time configuration
135 * values that were used to configure the device at load-time.
137 * Returns: VXGE_HAL_OK - success.
138 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
139 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
140 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
144 vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size)
147 vxge_hal_pci_config_t *pci_config = (vxge_hal_pci_config_t *) buffer;
148 __hal_device_t *hldev = (__hal_device_t *) devh;
150 vxge_assert((hldev != NULL) && (buffer != NULL) && (size != NULL));
152 vxge_hal_trace_log_device("==> %s:%s:%d",
153 __FILE__, __func__, __LINE__);
155 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT", "
156 "buffer = 0x"VXGE_OS_STXFMT", "
157 "size = 0x"VXGE_OS_STXFMT,
158 (ptr_t) hldev, (ptr_t) buffer, (ptr_t) size);
160 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
161 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
162 __FILE__, __func__, __LINE__,
163 VXGE_HAL_ERR_INVALID_DEVICE);
164 return (VXGE_HAL_ERR_INVALID_DEVICE);
167 if (*size < sizeof(vxge_hal_pci_config_t)) {
168 *size = sizeof(vxge_hal_pci_config_t);
169 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
170 __FILE__, __func__, __LINE__,
171 VXGE_HAL_ERR_OUT_OF_SPACE);
172 return (VXGE_HAL_ERR_OUT_OF_SPACE);
175 /* refresh PCI config space */
176 for (i = 0; i < VXGE_HAL_PCI_CONFIG_SPACE_SIZE / 4; i++) {
177 (void) __hal_vpath_pci_read(hldev,
181 (u32 *) ((void *)&hldev->pci_config_space) + i);
184 vxge_os_memcpy(pci_config, &hldev->pci_config_space,
185 sizeof(vxge_hal_pci_config_t));
187 *size = sizeof(vxge_hal_pci_config_t);
189 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
190 __FILE__, __func__, __LINE__);
192 return (VXGE_HAL_OK);
196 * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities
197 * @devh: HAL device handle.
198 * @msi_cap: MSI Capabilities
200 * Return the msi capabilities
203 vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
204 vxge_hal_mgmt_msi_cap_t *msi_cap)
208 __hal_device_t *hldev = (__hal_device_t *) devh;
210 vxge_assert((hldev != NULL) && (msi_cap != NULL));
212 vxge_hal_trace_log_device("==> %s:%s:%d",
213 __FILE__, __func__, __LINE__);
215 vxge_hal_trace_log_device(
216 "hldev = 0x"VXGE_OS_STXFMT", msi_cap = 0x"VXGE_OS_STXFMT,
217 (ptr_t) hldev, (ptr_t) msi_cap);
219 if (hldev->pci_caps.msi_cap_offset == 0) {
220 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
221 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
222 return (VXGE_HAL_FAIL);
225 vxge_os_memzero(msi_cap, sizeof(vxge_hal_mgmt_msi_cap_t));
227 (void) __hal_vpath_pci_read(hldev,
229 hldev->pci_caps.msi_cap_offset +
230 vxge_offsetof(vxge_hal_msi_capability_le_t, msi_control),
234 if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_ENABLE)
237 if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_PVMASK)
238 msi_cap->is_pvm_capable = 1;
240 if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_64BIT)
241 msi_cap->is_64bit_addr_capable = 1;
243 msi_cap->vectors_allocated =
244 (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_QSIZE) >> 4;
246 msi_cap->max_vectors_capable =
247 (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_QMASK) >> 1;
249 if (msi_cap->is_64bit_addr_capable) {
250 if (msi_cap->is_pvm_capable) {
251 (void) __hal_vpath_pci_read(hldev,
253 hldev->pci_caps.msi_cap_offset +
254 vxge_offsetof(vxge_hal_msi_capability_le_t,
255 au.ma64_pvm.msi_addr_hi),
258 msi_cap->address = ((u64) addr32) << 32;
260 (void) __hal_vpath_pci_read(hldev,
262 hldev->pci_caps.msi_cap_offset +
263 vxge_offsetof(vxge_hal_msi_capability_le_t,
264 au.ma64_pvm.msi_addr_lo),
267 msi_cap->address |= (u64) addr32;
269 (void) __hal_vpath_pci_read(hldev,
271 hldev->pci_caps.msi_cap_offset +
272 vxge_offsetof(vxge_hal_msi_capability_le_t,
273 au.ma64_pvm.msi_data),
276 (void) __hal_vpath_pci_read(hldev,
278 hldev->pci_caps.msi_cap_offset +
279 vxge_offsetof(vxge_hal_msi_capability_le_t,
280 au.ma64_pvm.msi_mask),
281 4, &msi_cap->mask_bits);
283 (void) __hal_vpath_pci_read(hldev,
285 hldev->pci_caps.msi_cap_offset +
286 vxge_offsetof(vxge_hal_msi_capability_le_t,
287 au.ma64_pvm.msi_pending),
288 4, &msi_cap->pending_bits);
290 (void) __hal_vpath_pci_read(hldev,
292 hldev->pci_caps.msi_cap_offset +
293 vxge_offsetof(vxge_hal_msi_capability_le_t,
294 au.ma64_no_pvm.msi_addr_hi),
297 msi_cap->address = ((u64) addr32) << 32;
299 (void) __hal_vpath_pci_read(hldev,
301 hldev->pci_caps.msi_cap_offset +
302 vxge_offsetof(vxge_hal_msi_capability_le_t,
303 au.ma64_no_pvm.msi_addr_lo),
306 msi_cap->address |= (u64) addr32;
308 (void) __hal_vpath_pci_read(hldev,
310 hldev->pci_caps.msi_cap_offset +
311 vxge_offsetof(vxge_hal_msi_capability_le_t,
312 au.ma64_no_pvm.msi_data),
317 if (msi_cap->is_pvm_capable) {
318 (void) __hal_vpath_pci_read(hldev,
320 hldev->pci_caps.msi_cap_offset +
321 vxge_offsetof(vxge_hal_msi_capability_le_t,
322 au.ma32_pvm.msi_addr),
325 msi_cap->address = (u64) addr32;
327 (void) __hal_vpath_pci_read(hldev,
329 hldev->pci_caps.msi_cap_offset +
330 vxge_offsetof(vxge_hal_msi_capability_le_t,
331 au.ma32_pvm.msi_data),
334 (void) __hal_vpath_pci_read(hldev,
336 hldev->pci_caps.msi_cap_offset +
337 vxge_offsetof(vxge_hal_msi_capability_le_t,
338 au.ma32_pvm.msi_mask),
339 4, &msi_cap->mask_bits);
341 (void) __hal_vpath_pci_read(hldev,
343 hldev->pci_caps.msi_cap_offset +
344 vxge_offsetof(vxge_hal_msi_capability_le_t,
345 au.ma32_pvm.msi_pending),
346 4, &msi_cap->pending_bits);
349 (void) __hal_vpath_pci_read(hldev,
351 hldev->pci_caps.msi_cap_offset +
352 vxge_offsetof(vxge_hal_msi_capability_le_t,
353 au.ma32_no_pvm.msi_addr),
356 msi_cap->address = (u64) addr32;
358 (void) __hal_vpath_pci_read(hldev,
360 hldev->pci_caps.msi_cap_offset +
361 vxge_offsetof(vxge_hal_msi_capability_le_t,
362 au.ma32_no_pvm.msi_data),
367 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
368 __FILE__, __func__, __LINE__);
369 return (VXGE_HAL_OK);
373 * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities
374 * @devh: HAL device handle.
375 * @msi_cap: MSI Capabilities
377 * Sets the msi capabilities
380 vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
381 vxge_hal_mgmt_msi_cap_t *msi_cap)
385 __hal_device_t *hldev = (__hal_device_t *) devh;
387 vxge_assert((hldev != NULL) && (msi_cap != NULL));
389 vxge_hal_trace_log_device("==> %s:%s:%d",
390 __FILE__, __func__, __LINE__);
392 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT","
393 "msi_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) msi_cap);
395 if (hldev->pci_caps.msi_cap_offset == 0) {
396 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
397 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
398 return (VXGE_HAL_FAIL);
401 (void) __hal_vpath_pci_read(hldev,
403 hldev->pci_caps.msi_cap_offset +
404 vxge_offsetof(vxge_hal_msi_capability_le_t, msi_control),
405 2, &msi_control_reg);
408 msi_control_reg |= VXGE_HAL_PCI_MSI_FLAGS_ENABLE;
410 msi_control_reg &= ~VXGE_HAL_PCI_MSI_FLAGS_ENABLE;
412 if (msi_cap->vectors_allocated >
413 (u32) ((msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_QMASK) >> 1)) {
414 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
415 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
416 return (VXGE_HAL_FAIL);
419 msi_control_reg &= ~VXGE_HAL_PCI_MSI_FLAGS_QSIZE;
421 msi_control_reg |= (msi_cap->vectors_allocated & 0x7) << 4;
423 if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_64BIT) {
424 if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_PVMASK) {
426 addr32 = (u32) (msi_cap->address >> 32);
428 vxge_os_pci_write32(hldev->header.pdev,
430 hldev->pci_caps.msi_cap_offset +
431 vxge_offsetof(vxge_hal_msi_capability_le_t,
432 au.ma64_pvm.msi_addr_hi), addr32);
434 addr32 = (u32) msi_cap->address;
436 vxge_os_pci_write32(hldev->header.pdev,
438 hldev->pci_caps.msi_cap_offset +
439 vxge_offsetof(vxge_hal_msi_capability_le_t,
440 au.ma64_pvm.msi_addr_lo), addr32);
442 vxge_os_pci_write16(hldev->header.pdev,
444 hldev->pci_caps.msi_cap_offset +
445 vxge_offsetof(vxge_hal_msi_capability_le_t,
446 au.ma64_pvm.msi_data), msi_cap->data);
448 vxge_os_pci_write32(hldev->header.pdev,
450 hldev->pci_caps.msi_cap_offset +
451 vxge_offsetof(vxge_hal_msi_capability_le_t,
452 au.ma64_pvm.msi_mask), msi_cap->mask_bits);
454 vxge_os_pci_write32(hldev->header.pdev,
456 hldev->pci_caps.msi_cap_offset +
457 vxge_offsetof(vxge_hal_msi_capability_le_t,
458 au.ma64_pvm.msi_pending), msi_cap->pending_bits);
460 addr32 = (u32) (msi_cap->address >> 32);
462 vxge_os_pci_write32(hldev->header.pdev,
464 hldev->pci_caps.msi_cap_offset +
465 vxge_offsetof(vxge_hal_msi_capability_le_t,
466 au.ma64_no_pvm.msi_addr_hi), addr32);
468 addr32 = (u32) msi_cap->address;
470 vxge_os_pci_write32(hldev->header.pdev,
472 hldev->pci_caps.msi_cap_offset +
473 vxge_offsetof(vxge_hal_msi_capability_le_t,
474 au.ma64_no_pvm.msi_addr_lo), addr32);
476 vxge_os_pci_write16(hldev->header.pdev,
478 hldev->pci_caps.msi_cap_offset +
479 vxge_offsetof(vxge_hal_msi_capability_le_t,
480 au.ma64_no_pvm.msi_data), msi_cap->data);
484 if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_PVMASK) {
486 addr32 = (u32) msi_cap->address;
488 vxge_os_pci_write32(hldev->header.pdev,
490 hldev->pci_caps.msi_cap_offset +
491 vxge_offsetof(vxge_hal_msi_capability_le_t,
492 au.ma32_pvm.msi_addr), addr32);
494 vxge_os_pci_write16(hldev->header.pdev,
496 hldev->pci_caps.msi_cap_offset +
497 vxge_offsetof(vxge_hal_msi_capability_le_t,
498 au.ma32_pvm.msi_data), msi_cap->data);
500 vxge_os_pci_write32(hldev->header.pdev,
502 hldev->pci_caps.msi_cap_offset +
503 vxge_offsetof(vxge_hal_msi_capability_le_t,
504 au.ma32_pvm.msi_mask), msi_cap->mask_bits);
506 vxge_os_pci_write32(hldev->header.pdev,
508 hldev->pci_caps.msi_cap_offset +
509 vxge_offsetof(vxge_hal_msi_capability_le_t,
510 au.ma32_pvm.msi_pending), msi_cap->pending_bits);
513 addr32 = (u32) msi_cap->address;
515 vxge_os_pci_write32(hldev->header.pdev,
517 hldev->pci_caps.msi_cap_offset +
518 vxge_offsetof(vxge_hal_msi_capability_le_t,
519 au.ma32_no_pvm.msi_addr), addr32);
521 vxge_os_pci_write16(hldev->header.pdev,
523 hldev->pci_caps.msi_cap_offset +
524 vxge_offsetof(vxge_hal_msi_capability_le_t,
525 au.ma32_no_pvm.msi_data), msi_cap->data);
529 vxge_os_pci_write16(hldev->header.pdev, hldev->header.cfgh,
530 hldev->pci_caps.msi_cap_offset +
531 vxge_offsetof(vxge_hal_msi_capability_le_t, msi_control),
534 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
535 __FILE__, __func__, __LINE__);
537 return (VXGE_HAL_OK);
541 * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities
542 * @devh: HAL device handle.
543 * @msix_cap: MSIX Capabilities
545 * Return the msix capabilities
548 vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
549 vxge_hal_mgmt_msix_cap_t *msix_cap)
551 u16 msix_control_reg;
553 __hal_device_t *hldev = (__hal_device_t *) devh;
555 vxge_assert((hldev != NULL) && (msix_cap != NULL));
557 vxge_hal_trace_log_device("==> %s:%s:%d",
558 __FILE__, __func__, __LINE__);
560 vxge_hal_trace_log_device(
561 "hldev = 0x"VXGE_OS_STXFMT", msix_cap = 0x"VXGE_OS_STXFMT,
562 (ptr_t) hldev, (ptr_t) msix_cap);
564 if (hldev->pci_caps.msix_cap_offset == 0) {
565 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
566 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
567 return (VXGE_HAL_FAIL);
570 vxge_os_memzero(msix_cap, sizeof(vxge_hal_mgmt_msix_cap_t));
572 (void) __hal_vpath_pci_read(hldev,
574 hldev->pci_caps.msix_cap_offset +
575 vxge_offsetof(vxge_hal_msix_capability_le_t, msix_control),
576 2, &msix_control_reg);
578 if (msix_control_reg & VXGE_HAL_PCI_MSIX_FLAGS_ENABLE)
579 msix_cap->enable = 1;
581 if (msix_control_reg & VXGE_HAL_PCI_MSIX_FLAGS_MASK)
582 msix_cap->mask_all_vect = 1;
584 msix_cap->table_size =
585 (msix_control_reg & VXGE_HAL_PCI_MSIX_FLAGS_TSIZE) + 1;
587 (void) __hal_vpath_pci_read(hldev,
589 hldev->pci_caps.msix_cap_offset +
590 vxge_offsetof(vxge_hal_msix_capability_le_t, table_offset),
593 msix_cap->table_offset =
594 (msix_offset & VXGE_HAL_PCI_MSIX_TABLE_OFFSET) >> 3;
596 msix_cap->table_bir = msix_offset & VXGE_HAL_PCI_MSIX_TABLE_BIR;
598 (void) __hal_vpath_pci_read(hldev,
600 hldev->pci_caps.msix_cap_offset +
601 vxge_offsetof(vxge_hal_msix_capability_le_t, pba_offset),
604 msix_cap->pba_offset =
605 (msix_offset & VXGE_HAL_PCI_MSIX_PBA_OFFSET) >> 3;
607 msix_cap->pba_bir = msix_offset & VXGE_HAL_PCI_MSIX_PBA_BIR;
609 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
610 __FILE__, __func__, __LINE__);
611 return (VXGE_HAL_OK);
615 * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities
616 * @devh: HAL device handle.
617 * @pm_cap: pm Capabilities
619 * Return the pm capabilities
622 vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
623 vxge_hal_mgmt_pm_cap_t *pm_cap)
629 __hal_device_t *hldev = (__hal_device_t *) devh;
631 vxge_assert((hldev != NULL) && (pm_cap != NULL));
633 vxge_hal_trace_log_device("==> %s:%s:%d",
634 __FILE__, __func__, __LINE__);
636 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT", "
637 "pm_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) pm_cap);
639 if (hldev->pci_caps.pm_cap_offset == 0) {
640 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
641 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
642 return (VXGE_HAL_FAIL);
645 vxge_os_memzero(pm_cap, sizeof(vxge_hal_mgmt_pm_cap_t));
647 (void) __hal_vpath_pci_read(hldev,
649 hldev->pci_caps.pm_cap_offset +
650 vxge_offsetof(vxge_hal_pm_capability_le_t, capabilities_reg),
654 (u32) (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_VER_MASK);
656 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_CLOCK)
657 pm_cap->pm_cap_pme_clock = 1;
659 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_AUX_POWER)
660 pm_cap->pm_cap_aux_power = 1;
662 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_DSI)
663 pm_cap->pm_cap_dsi = 1;
665 if (pm_cap_reg & VXGE_HAL_PCI_PM_AUX_CURRENT)
666 pm_cap->pm_cap_aux_current = 1;
668 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_D1)
669 pm_cap->pm_cap_cap_d0 = 1;
671 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_D2)
672 pm_cap->pm_cap_cap_d1 = 1;
674 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D0)
675 pm_cap->pm_cap_pme_d0 = 1;
677 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D1)
678 pm_cap->pm_cap_pme_d1 = 1;
680 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D2)
681 pm_cap->pm_cap_pme_d2 = 1;
683 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D3_HOT)
684 pm_cap->pm_cap_pme_d3_hot = 1;
686 if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D3_COLD)
687 pm_cap->pm_cap_pme_d3_cold = 1;
689 (void) __hal_vpath_pci_read(hldev,
691 hldev->pci_caps.pm_cap_offset +
692 vxge_offsetof(vxge_hal_pm_capability_le_t, pm_ctrl),
695 pm_cap->pm_ctrl_state =
696 pm_control_reg & VXGE_HAL_PCI_PM_CTRL_STATE_MASK;
698 if (pm_cap_reg & VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET)
699 pm_cap->pm_ctrl_no_soft_reset = 1;
701 if (pm_cap_reg & VXGE_HAL_PCI_PM_CTRL_PME_ENABLE)
702 pm_cap->pm_ctrl_pme_enable = 1;
704 pm_cap->pm_ctrl_pme_data_sel =
705 (u32) (pm_control_reg & VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK) >> 10;
707 pm_cap->pm_ctrl_pme_data_scale =
708 (u32) (pm_control_reg & VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK) >> 13;
710 if (pm_cap_reg & VXGE_HAL_PCI_PM_CTRL_PME_STATUS)
711 pm_cap->pm_ctrl_pme_status = 1;
713 (void) __hal_vpath_pci_read(hldev,
715 hldev->pci_caps.pm_cap_offset +
716 vxge_offsetof(vxge_hal_pm_capability_le_t, pm_ctrl),
719 if (pm_ppb_ext & VXGE_HAL_PCI_PM_PPB_B2_B3)
720 pm_cap->pm_ppb_ext_b2_b3 = 1;
722 if (pm_ppb_ext & VXGE_HAL_PCI_PM_BPCC_ENABLE)
723 pm_cap->pm_ppb_ext_ecc_en = 1;
725 (void) __hal_vpath_pci_read(hldev,
727 hldev->pci_caps.pm_cap_offset +
728 vxge_offsetof(vxge_hal_pm_capability_le_t, pm_data_reg),
731 pm_cap->pm_data_reg = (u32) pm_data_reg;
733 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
734 __FILE__, __func__, __LINE__);
735 return (VXGE_HAL_OK);
739 * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities
740 * @devh: HAL device handle.
741 * @sid_cap: Slot Id Capabilities
743 * Return the Slot Id capabilities
746 vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
747 vxge_hal_mgmt_sid_cap_t *sid_cap)
751 __hal_device_t *hldev = (__hal_device_t *) devh;
753 vxge_assert((hldev != NULL) && (sid_cap != NULL));
755 vxge_hal_trace_log_device("==> %s:%s:%d",
756 __FILE__, __func__, __LINE__);
758 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT
759 ", sid_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) sid_cap);
761 if (hldev->pci_caps.sid_cap_offset == 0) {
762 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
763 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
764 return (VXGE_HAL_FAIL);
767 vxge_os_memzero(sid_cap, sizeof(vxge_hal_mgmt_sid_cap_t));
769 (void) __hal_vpath_pci_read(hldev,
771 hldev->pci_caps.sid_cap_offset +
772 vxge_offsetof(vxge_hal_sid_capability_le_t, sid_esr),
775 sid_cap->sid_number_of_slots =
776 (u32) (slot_num_reg & VXGE_HAL_PCI_SID_ESR_NSLOTS);
778 if (slot_num_reg & VXGE_HAL_PCI_SID_ESR_FIC)
779 sid_cap->sid_number_of_slots = 1;
781 (void) __hal_vpath_pci_read(hldev,
783 hldev->pci_caps.sid_cap_offset +
784 vxge_offsetof(vxge_hal_sid_capability_le_t, sid_chasis_nr),
787 sid_cap->sid_chasis_number = (u32) chasis_num_reg;
789 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
790 __FILE__, __func__, __LINE__);
792 return (VXGE_HAL_OK);
796 * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities
797 * @devh: HAL device handle.
798 * @err_cap: PCI-E Extended Error Capabilities
800 * Return the PCI-E Extended Error capabilities
803 vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
804 vxge_hal_pci_err_cap_t *err_cap)
806 __hal_device_t *hldev = (__hal_device_t *) devh;
808 vxge_assert((hldev != NULL) && (err_cap != NULL));
810 vxge_hal_trace_log_device("==> %s:%s:%d",
811 __FILE__, __func__, __LINE__);
813 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT
814 ",sid_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) err_cap);
816 if (hldev->pci_e_ext_caps.err_cap_offset == 0) {
817 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
818 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
819 return (VXGE_HAL_FAIL);
822 vxge_os_memzero(err_cap, sizeof(vxge_hal_pci_err_cap_t));
824 (void) __hal_vpath_pci_read(hldev,
826 hldev->pci_e_ext_caps.err_cap_offset +
827 vxge_offsetof(vxge_hal_err_capability_t, pci_err_header),
829 &err_cap->pci_err_header);
831 (void) __hal_vpath_pci_read(hldev,
833 hldev->pci_e_ext_caps.err_cap_offset +
834 vxge_offsetof(vxge_hal_err_capability_t, pci_err_uncor_status),
836 &err_cap->pci_err_uncor_status);
838 (void) __hal_vpath_pci_read(hldev,
840 hldev->pci_e_ext_caps.err_cap_offset +
841 vxge_offsetof(vxge_hal_err_capability_t, pci_err_uncor_mask),
843 &err_cap->pci_err_uncor_mask);
845 (void) __hal_vpath_pci_read(hldev,
847 hldev->pci_e_ext_caps.err_cap_offset +
848 vxge_offsetof(vxge_hal_err_capability_t, pci_err_uncor_server),
850 &err_cap->pci_err_uncor_server);
852 (void) __hal_vpath_pci_read(hldev,
854 hldev->pci_e_ext_caps.err_cap_offset +
855 vxge_offsetof(vxge_hal_err_capability_t, pci_err_cor_status),
857 &err_cap->pci_err_cor_status);
859 (void) __hal_vpath_pci_read(hldev,
861 hldev->pci_e_ext_caps.err_cap_offset +
862 vxge_offsetof(vxge_hal_err_capability_t, pci_err_cap),
864 &err_cap->pci_err_cap);
866 (void) __hal_vpath_pci_read(hldev,
868 hldev->pci_e_ext_caps.err_cap_offset +
869 vxge_offsetof(vxge_hal_err_capability_t, err_header_log),
871 &err_cap->err_header_log);
873 (void) __hal_vpath_pci_read(hldev,
875 hldev->pci_e_ext_caps.err_cap_offset +
876 vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_command),
878 &err_cap->pci_err_root_command);
880 (void) __hal_vpath_pci_read(hldev,
882 hldev->pci_e_ext_caps.err_cap_offset +
883 vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_status),
885 &err_cap->pci_err_root_status);
887 (void) __hal_vpath_pci_read(hldev,
889 hldev->pci_e_ext_caps.err_cap_offset +
890 vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_cor_src),
892 &err_cap->pci_err_root_cor_src);
894 (void) __hal_vpath_pci_read(hldev,
896 hldev->pci_e_ext_caps.err_cap_offset +
897 vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_src),
899 &err_cap->pci_err_root_src);
901 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
902 __FILE__, __func__, __LINE__);
904 return (VXGE_HAL_OK);
908 * vxge_hal_mgmt_driver_config - Retrieve driver configuration.
909 * @drv_config: Device configuration, see vxge_hal_driver_config_t {}.
910 * @size: Pointer to buffer containing the Size of the @drv_config.
911 * HAL will return an error if the size is smaller than
912 * sizeof(vxge_hal_driver_config_t) and returns required size in this field
914 * Get driver configuration. Permits to retrieve at run-time configuration
915 * values that were used to configure the device at load-time.
917 * Returns: VXGE_HAL_OK - success.
918 * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized.
919 * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching.
920 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
922 * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config().
925 vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size)
928 vxge_assert((drv_config != NULL) && (size != NULL));
930 vxge_hal_trace_log_driver("==> %s:%s:%d",
931 __FILE__, __func__, __LINE__);
933 vxge_hal_trace_log_driver(
934 "drv_config = 0x"VXGE_OS_STXFMT", size = 0x"VXGE_OS_STXFMT,
935 (ptr_t) drv_config, (ptr_t) size);
937 if (g_vxge_hal_driver == NULL) {
938 vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
939 __FILE__, __func__, __LINE__,
940 VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED);
941 return (VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED);
944 if (*size < sizeof(vxge_hal_driver_config_t)) {
945 *size = sizeof(vxge_hal_driver_config_t);
946 vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
947 __FILE__, __func__, __LINE__,
948 VXGE_HAL_ERR_OUT_OF_SPACE);
949 return (VXGE_HAL_ERR_OUT_OF_SPACE);
952 vxge_os_memcpy(drv_config, &g_vxge_hal_driver->config,
953 sizeof(vxge_hal_driver_config_t));
955 *size = sizeof(vxge_hal_driver_config_t);
957 vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
958 __FILE__, __func__, __LINE__);
960 return (VXGE_HAL_OK);
965 * vxge_hal_mgmt_device_config - Retrieve device configuration.
966 * @devh: HAL device handle.
967 * @dev_config: Device configuration, see vxge_hal_device_config_t {}.
968 * @size: Pointer to buffer containing the Size of the @dev_config.
969 * HAL will return an error if the size is smaller than
970 * sizeof(vxge_hal_device_config_t) and returns required size in this field
972 * Get device configuration. Permits to retrieve at run-time configuration
973 * values that were used to initialize and configure the device.
975 * Returns: VXGE_HAL_OK - success.
976 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
977 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
978 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
980 * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config().
983 vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
984 vxge_hal_device_config_t *dev_config, u32 *size)
986 vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
988 vxge_assert((devh != NULL) && (dev_config != NULL) && (size != NULL));
990 vxge_hal_trace_log_device("==> %s:%s:%d",
991 __FILE__, __func__, __LINE__);
993 vxge_hal_trace_log_device(
994 "devh = 0x"VXGE_OS_STXFMT", dev_config = 0x"VXGE_OS_STXFMT", "
995 "size = 0x"VXGE_OS_STXFMT, (ptr_t) devh, (ptr_t) dev_config,
998 if (hldev->magic != VXGE_HAL_DEVICE_MAGIC) {
999 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
1000 __FILE__, __func__, __LINE__,
1001 VXGE_HAL_ERR_INVALID_DEVICE);
1002 return (VXGE_HAL_ERR_INVALID_DEVICE);
1005 if (*size < sizeof(vxge_hal_device_config_t)) {
1006 *size = sizeof(vxge_hal_device_config_t);
1007 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
1008 __FILE__, __func__, __LINE__,
1009 VXGE_HAL_ERR_OUT_OF_SPACE);
1010 return (VXGE_HAL_ERR_OUT_OF_SPACE);
1013 vxge_os_memcpy(dev_config, &hldev->config,
1014 sizeof(vxge_hal_device_config_t));
1016 *size = sizeof(vxge_hal_device_config_t);
1018 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
1019 __FILE__, __func__, __LINE__);
1021 return (VXGE_HAL_OK);
1025 * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified
1027 * @devh: HAL device handle.
1028 * @offset: Offset in the 256 byte PCI configuration space.
1029 * @value_bits: 8, 16, or 32 (bits) to read.
1030 * @value: Value returned by HAL.
1032 * Read PCI configuration, given device and offset in the PCI space.
1034 * Returns: VXGE_HAL_OK - success.
1035 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1036 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
1038 * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid
1043 vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
1044 int value_bits, u32 *value)
1046 __hal_device_t *hldev = (__hal_device_t *) devh;
1048 vxge_assert((devh != NULL) && (value != NULL));
1050 vxge_hal_trace_log_device("==> %s:%s:%d",
1051 __FILE__, __func__, __LINE__);
1053 vxge_hal_trace_log_device(
1054 "devh = 0x"VXGE_OS_STXFMT", offset = %d, value_bits = %d, "
1055 "value = 0x"VXGE_OS_STXFMT, (ptr_t) devh, offset,
1056 value_bits, (ptr_t) value);
1058 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1059 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
1060 __FILE__, __func__, __LINE__,
1061 VXGE_HAL_ERR_INVALID_DEVICE);
1062 return (VXGE_HAL_ERR_INVALID_DEVICE);
1065 if (offset > sizeof(vxge_hal_pci_config_t) - value_bits / 8) {
1066 vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
1067 __FILE__, __func__, __LINE__,
1068 VXGE_HAL_ERR_INVALID_DEVICE);
1069 return (VXGE_HAL_ERR_INVALID_OFFSET);
1072 (void) __hal_vpath_pci_read(hldev,
1078 vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
1079 __FILE__, __func__, __LINE__);
1081 return (VXGE_HAL_OK);
1085 * vxge_hal_mgmt_reg_read - Read X3100 register.
1086 * @devh: HAL device handle.
1087 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
1088 * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
1089 * ignored for others
1090 * @offset: Register offset in the register space qualified by the type and
1092 * @value: Register value. Returned by HAL.
1093 * Read X3100 register.
1095 * Returns: VXGE_HAL_OK - success.
1096 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1097 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
1098 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
1099 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
1103 vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
1104 vxge_hal_mgmt_reg_type_e type,
1109 vxge_hal_status_e status = VXGE_HAL_OK;
1110 __hal_device_t *hldev = (__hal_device_t *) devh;
1112 vxge_assert((devh != NULL) && (value != NULL));
1114 vxge_hal_trace_log_device("==> %s:%s:%d",
1115 __FILE__, __func__, __LINE__);
1117 vxge_hal_trace_log_device(
1118 "devh = 0x"VXGE_OS_STXFMT", type = %d, "
1119 "vp_id = %d, offset = %d, value = 0x"VXGE_OS_STXFMT,
1120 (ptr_t) devh, type, vp_id, offset, (ptr_t) value);
1122 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1123 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1124 __FILE__, __func__, __LINE__,
1125 VXGE_HAL_ERR_INVALID_DEVICE);
1126 return (VXGE_HAL_ERR_INVALID_DEVICE);
1130 case vxge_hal_mgmt_reg_type_legacy:
1131 if (offset > sizeof(vxge_hal_legacy_reg_t) - 8) {
1132 status = VXGE_HAL_ERR_INVALID_OFFSET;
1135 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1136 hldev->header.regh0,
1137 (void *)(((ptr_t) hldev->legacy_reg) + offset));
1139 case vxge_hal_mgmt_reg_type_toc:
1140 if (offset > sizeof(vxge_hal_toc_reg_t) - 8) {
1141 status = VXGE_HAL_ERR_INVALID_OFFSET;
1144 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1145 hldev->header.regh0,
1146 (void *)(((ptr_t) hldev->toc_reg) + offset));
1148 case vxge_hal_mgmt_reg_type_common:
1149 if (offset > sizeof(vxge_hal_common_reg_t) - 8) {
1150 status = VXGE_HAL_ERR_INVALID_OFFSET;
1153 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1154 hldev->header.regh0,
1155 (void *)(((ptr_t) hldev->common_reg) + offset));
1157 case vxge_hal_mgmt_reg_type_memrepair:
1158 if (!(hldev->access_rights &
1159 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1160 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1163 if (offset > sizeof(vxge_hal_memrepair_reg_t) - 8) {
1164 status = VXGE_HAL_ERR_INVALID_OFFSET;
1167 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1168 hldev->header.regh0,
1169 (void *)(((ptr_t) hldev->memrepair_reg) + offset));
1171 case vxge_hal_mgmt_reg_type_pcicfgmgmt:
1172 if (!(hldev->access_rights &
1173 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1174 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1177 if (vp_id > VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES - 1) {
1178 status = VXGE_HAL_ERR_INVALID_INDEX;
1181 if (offset > sizeof(vxge_hal_pcicfgmgmt_reg_t) - 8) {
1182 status = VXGE_HAL_ERR_INVALID_OFFSET;
1185 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1186 hldev->header.regh0,
1187 (void *)(((ptr_t) hldev->pcicfgmgmt_reg[vp_id]) + offset));
1189 case vxge_hal_mgmt_reg_type_mrpcim:
1190 if (!(hldev->access_rights &
1191 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1192 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1195 if (offset > sizeof(vxge_hal_mrpcim_reg_t) - 8) {
1196 status = VXGE_HAL_ERR_INVALID_OFFSET;
1199 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1200 hldev->header.regh0,
1201 (void *)(((ptr_t) hldev->mrpcim_reg) + offset));
1203 case vxge_hal_mgmt_reg_type_srpcim:
1204 if (!(hldev->access_rights &
1205 VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
1206 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1209 if (vp_id > VXGE_HAL_TITAN_SRPCIM_REG_SPACES - 1) {
1210 status = VXGE_HAL_ERR_INVALID_INDEX;
1213 if (offset > sizeof(vxge_hal_srpcim_reg_t) - 8) {
1214 status = VXGE_HAL_ERR_INVALID_OFFSET;
1217 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1218 hldev->header.regh0,
1219 (void *)(((ptr_t) hldev->srpcim_reg[vp_id]) + offset));
1221 case vxge_hal_mgmt_reg_type_vpmgmt:
1222 if ((vp_id > VXGE_HAL_TITAN_VPMGMT_REG_SPACES - 1) ||
1223 (!(hldev->vpath_assignments & mBIT(vp_id)))) {
1224 status = VXGE_HAL_ERR_INVALID_INDEX;
1227 if (offset > sizeof(vxge_hal_vpmgmt_reg_t) - 8) {
1228 status = VXGE_HAL_ERR_INVALID_OFFSET;
1231 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1232 hldev->header.regh0,
1233 (void *)(((ptr_t) hldev->vpmgmt_reg[vp_id]) + offset));
1235 case vxge_hal_mgmt_reg_type_vpath:
1236 if ((vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) ||
1237 (!(hldev->vpath_assignments & mBIT(vp_id)))) {
1238 status = VXGE_HAL_ERR_INVALID_INDEX;
1241 if (vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) {
1242 status = VXGE_HAL_ERR_INVALID_INDEX;
1245 if (offset > sizeof(vxge_hal_vpath_reg_t) - 8) {
1246 status = VXGE_HAL_ERR_INVALID_OFFSET;
1249 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1250 hldev->header.regh0,
1251 (void *)(((ptr_t) hldev->vpath_reg[vp_id]) + offset));
1254 status = VXGE_HAL_ERR_INVALID_TYPE;
1258 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1259 __FILE__, __func__, __LINE__, status);
1264 * vxge_hal_mgmt_reg_Write - Write X3100 register.
1265 * @devh: HAL device handle.
1266 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
1267 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
1268 * ignored for others
1269 * @offset: Register offset in the register space qualified by the type and
1271 * @value: Register value to be written.
1272 * Write X3100 register.
1274 * Returns: VXGE_HAL_OK - success.
1275 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1276 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
1277 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
1278 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
1282 vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
1283 vxge_hal_mgmt_reg_type_e type,
1288 vxge_hal_status_e status = VXGE_HAL_OK;
1289 __hal_device_t *hldev = (__hal_device_t *) devh;
1291 vxge_assert(devh != NULL);
1293 vxge_hal_trace_log_device("==> %s:%s:%d",
1294 __FILE__, __func__, __LINE__);
1296 vxge_hal_trace_log_device(
1297 "devh = 0x"VXGE_OS_STXFMT", type = %d, "
1298 "index = %d, offset = %d, value = 0x"VXGE_OS_STXFMT,
1299 (ptr_t) devh, type, vp_id, offset, (ptr_t) value);
1301 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1302 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1303 __FILE__, __func__, __LINE__,
1304 VXGE_HAL_ERR_INVALID_DEVICE);
1306 return (VXGE_HAL_ERR_INVALID_DEVICE);
1310 case vxge_hal_mgmt_reg_type_legacy:
1311 if (offset > sizeof(vxge_hal_legacy_reg_t) - 8) {
1312 status = VXGE_HAL_ERR_INVALID_OFFSET;
1315 vxge_os_pio_mem_write64(hldev->header.pdev,
1316 hldev->header.regh0,
1318 (void *)(((ptr_t) hldev->legacy_reg) + offset));
1320 case vxge_hal_mgmt_reg_type_toc:
1321 if (offset > sizeof(vxge_hal_toc_reg_t) - 8) {
1322 status = VXGE_HAL_ERR_INVALID_OFFSET;
1325 vxge_os_pio_mem_write64(hldev->header.pdev,
1326 hldev->header.regh0,
1328 (void *)(((ptr_t) hldev->toc_reg) + offset));
1330 case vxge_hal_mgmt_reg_type_common:
1331 if (offset > sizeof(vxge_hal_common_reg_t) - 8) {
1332 status = VXGE_HAL_ERR_INVALID_OFFSET;
1335 vxge_os_pio_mem_write64(hldev->header.pdev,
1336 hldev->header.regh0,
1338 (void *)(((ptr_t) hldev->common_reg) + offset));
1340 case vxge_hal_mgmt_reg_type_memrepair:
1341 if (!(hldev->access_rights &
1342 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1343 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1346 if (offset > sizeof(vxge_hal_memrepair_reg_t) - 8) {
1347 status = VXGE_HAL_ERR_INVALID_OFFSET;
1350 vxge_os_pio_mem_write64(hldev->header.pdev,
1351 hldev->header.regh0,
1353 (void *)(((ptr_t) hldev->memrepair_reg) + offset));
1355 case vxge_hal_mgmt_reg_type_pcicfgmgmt:
1356 if (!(hldev->access_rights &
1357 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1358 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1361 if (vp_id > VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES - 1) {
1362 status = VXGE_HAL_ERR_INVALID_INDEX;
1365 if (offset > sizeof(vxge_hal_pcicfgmgmt_reg_t) - 8) {
1366 status = VXGE_HAL_ERR_INVALID_OFFSET;
1369 vxge_os_pio_mem_write64(hldev->header.pdev,
1370 hldev->header.regh0,
1372 (void *)(((ptr_t) hldev->pcicfgmgmt_reg[vp_id]) + offset));
1374 case vxge_hal_mgmt_reg_type_mrpcim:
1375 if (!(hldev->access_rights &
1376 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1377 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1380 if (offset > sizeof(vxge_hal_mrpcim_reg_t) - 8) {
1381 status = VXGE_HAL_ERR_INVALID_OFFSET;
1384 vxge_os_pio_mem_write64(hldev->header.pdev,
1385 hldev->header.regh0,
1387 (void *)(((ptr_t) hldev->mrpcim_reg) + offset));
1389 case vxge_hal_mgmt_reg_type_srpcim:
1390 if (!(hldev->access_rights &
1391 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1392 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1395 if (vp_id > VXGE_HAL_TITAN_SRPCIM_REG_SPACES - 1) {
1396 status = VXGE_HAL_ERR_INVALID_INDEX;
1399 if (offset > sizeof(vxge_hal_srpcim_reg_t) - 8) {
1400 status = VXGE_HAL_ERR_INVALID_OFFSET;
1403 vxge_os_pio_mem_write64(hldev->header.pdev,
1404 hldev->header.regh0,
1406 (void *)(((ptr_t) hldev->srpcim_reg[vp_id]) + offset));
1408 case vxge_hal_mgmt_reg_type_vpmgmt:
1409 if ((vp_id > VXGE_HAL_TITAN_VPMGMT_REG_SPACES - 1) ||
1410 (!(hldev->vpath_assignments & mBIT(vp_id)))) {
1411 status = VXGE_HAL_ERR_INVALID_INDEX;
1414 if (offset > sizeof(vxge_hal_vpmgmt_reg_t) - 8) {
1415 status = VXGE_HAL_ERR_INVALID_OFFSET;
1418 vxge_os_pio_mem_write64(hldev->header.pdev,
1419 hldev->header.regh0,
1421 (void *)(((ptr_t) hldev->vpmgmt_reg[vp_id]) + offset));
1423 case vxge_hal_mgmt_reg_type_vpath:
1424 if ((vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) ||
1425 (!(hldev->vpath_assignments & mBIT(vp_id)))) {
1426 status = VXGE_HAL_ERR_INVALID_INDEX;
1429 if (offset > sizeof(vxge_hal_vpath_reg_t) - 8) {
1430 status = VXGE_HAL_ERR_INVALID_OFFSET;
1433 vxge_os_pio_mem_write64(hldev->header.pdev,
1434 hldev->header.regh0,
1436 (void *)(((ptr_t) hldev->vpath_reg[vp_id]) + offset));
1439 status = VXGE_HAL_ERR_INVALID_TYPE;
1443 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1444 __FILE__, __func__, __LINE__, status);
1449 * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset
1451 * @devh: HAL device handle.
1452 * @offset: Register offset from bar0
1453 * @value: Register value. Returned by HAL.
1454 * Read X3100 register.
1456 * Returns: VXGE_HAL_OK - success.
1457 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1458 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
1462 vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
1466 vxge_hal_status_e status = VXGE_HAL_OK;
1467 __hal_device_t *hldev = (__hal_device_t *) devh;
1469 vxge_assert(devh != NULL);
1471 vxge_hal_trace_log_device("==> %s:%s:%d",
1472 __FILE__, __func__, __LINE__);
1474 vxge_hal_trace_log_device(
1475 "devh = 0x"VXGE_OS_STXFMT", offset = %d, value = 0x"VXGE_OS_STXFMT,
1476 (ptr_t) devh, offset, (ptr_t) value);
1478 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1479 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1480 __FILE__, __func__, __LINE__,
1481 VXGE_HAL_ERR_INVALID_DEVICE);
1482 return (VXGE_HAL_ERR_INVALID_DEVICE);
1485 if (((ptr_t) hldev->header.bar0 + offset) >
1486 ((ptr_t) hldev->vpath_reg[VXGE_HAL_MAX_VIRTUAL_PATHS - 1] +
1487 sizeof(vxge_hal_vpath_reg_t) - 8)) {
1488 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1489 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_OFFSET);
1490 return (VXGE_HAL_ERR_INVALID_OFFSET);
1493 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1494 hldev->header.regh0,
1495 (void *)(((ptr_t) hldev->header.bar0) + offset));
1497 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1498 __FILE__, __func__, __LINE__, status);
1503 * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset
1505 * @devh: HAL device handle.
1506 * @offset: Register offset from bar1
1507 * @value: Register value. Returned by HAL.
1508 * Read X3100 register.
1510 * Returns: VXGE_HAL_OK - success.
1511 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1515 vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
1519 vxge_hal_status_e status = VXGE_HAL_OK;
1520 __hal_device_t *hldev = (__hal_device_t *) devh;
1522 vxge_assert(devh != NULL);
1524 vxge_hal_trace_log_device("==> %s:%s:%d",
1525 __FILE__, __func__, __LINE__);
1527 vxge_hal_trace_log_device(
1528 "devh = 0x"VXGE_OS_STXFMT", offset = %d, value = 0x"VXGE_OS_STXFMT,
1529 (ptr_t) devh, offset, (ptr_t) value);
1531 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1532 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1533 __FILE__, __func__, __LINE__,
1534 VXGE_HAL_ERR_INVALID_DEVICE);
1535 return (VXGE_HAL_ERR_INVALID_DEVICE);
1538 *value = vxge_os_pio_mem_read64(hldev->header.pdev,
1539 hldev->header.regh0,
1540 (void *)(((ptr_t) hldev->header.bar1) + offset));
1542 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1543 __FILE__, __func__, __LINE__, status);
1548 * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset
1550 * @devh: HAL device handle.
1551 * @offset: Register offset from bar0
1552 * @value: Register value to be written.
1553 * Write X3100 register.
1555 * Returns: VXGE_HAL_OK - success.
1556 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1557 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
1561 vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
1565 vxge_hal_status_e status = VXGE_HAL_OK;
1566 __hal_device_t *hldev = (__hal_device_t *) devh;
1568 vxge_assert(devh != NULL);
1570 vxge_hal_trace_log_device("==> %s:%s:%d",
1571 __FILE__, __func__, __LINE__);
1573 vxge_hal_trace_log_device(
1574 "devh = 0x"VXGE_OS_STXFMT", offset = %d, value = 0x"VXGE_OS_STXFMT,
1575 (ptr_t) devh, offset, (ptr_t) value);
1577 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1578 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1579 __FILE__, __func__, __LINE__,
1580 VXGE_HAL_ERR_INVALID_DEVICE);
1581 return (VXGE_HAL_ERR_INVALID_DEVICE);
1583 if (((ptr_t) hldev->header.bar0 + offset) >
1584 ((ptr_t) hldev->vpath_reg[VXGE_HAL_MAX_VIRTUAL_PATHS - 1] +
1585 sizeof(vxge_hal_vpath_reg_t) - 8)) {
1586 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1587 __FILE__, __func__, __LINE__,
1588 VXGE_HAL_ERR_INVALID_OFFSET);
1589 return (VXGE_HAL_ERR_INVALID_OFFSET);
1592 vxge_os_pio_mem_write64(hldev->header.pdev,
1593 hldev->header.regh0,
1595 (void *)(((ptr_t) hldev->header.bar0) + offset));
1597 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1598 __FILE__, __func__, __LINE__, status);
1603 * vxge_hal_mgmt_register_config - Retrieve register configuration.
1604 * @devh: HAL device handle.
1605 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
1606 * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
1607 * ignored for others
1608 * @config: Device configuration, see vxge_hal_device_config_t {}.
1609 * @size: Pointer to buffer containing the Size of the @reg_config.
1610 * HAL will return an error if the size is smaller than
1611 * requested register space and returns required size in this field
1613 * Get register configuration. Permits to retrieve register values.
1615 * Returns: VXGE_HAL_OK - success.
1616 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
1617 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
1618 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
1619 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
1623 vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
1624 vxge_hal_mgmt_reg_type_e type, u32 vp_id, u8 *config, u32 *size)
1627 u64 *reg_config = (u64 *) ((void *)config);
1628 vxge_hal_status_e status = VXGE_HAL_OK;
1629 __hal_device_t *hldev = (__hal_device_t *) devh;
1631 vxge_assert((devh != NULL) && (reg_config != NULL) && (size != NULL));
1633 vxge_hal_trace_log_device("==> %s:%s:%d",
1634 __FILE__, __func__, __LINE__);
1636 vxge_hal_trace_log_device(
1637 "devh = 0x"VXGE_OS_STXFMT", type = %d, index = %d, "
1638 "reg_config = 0x"VXGE_OS_STXFMT", size = 0x"VXGE_OS_STXFMT,
1639 (ptr_t) devh, type, vp_id, (ptr_t) reg_config, (ptr_t) size);
1641 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1642 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1643 __FILE__, __func__, __LINE__,
1644 VXGE_HAL_ERR_INVALID_DEVICE);
1645 return (VXGE_HAL_ERR_INVALID_DEVICE);
1649 case vxge_hal_mgmt_reg_type_legacy:
1650 if (*size < sizeof(vxge_hal_legacy_reg_t)) {
1651 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1652 *size = sizeof(vxge_hal_legacy_reg_t);
1656 for (offset = 0; offset < sizeof(vxge_hal_legacy_reg_t);
1658 *reg_config++ = vxge_os_pio_mem_read64(
1660 hldev->header.regh0,
1661 (void *)(((ptr_t) hldev->legacy_reg) + offset));
1663 *size = sizeof(vxge_hal_legacy_reg_t);
1666 case vxge_hal_mgmt_reg_type_toc:
1667 if (*size < sizeof(vxge_hal_toc_reg_t)) {
1668 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1669 *size = sizeof(vxge_hal_toc_reg_t);
1673 for (offset = 0; offset < sizeof(vxge_hal_toc_reg_t);
1675 *reg_config++ = vxge_os_pio_mem_read64(
1677 hldev->header.regh0,
1678 (void *)(((ptr_t) hldev->toc_reg) + offset));
1680 *size = sizeof(vxge_hal_toc_reg_t);
1683 case vxge_hal_mgmt_reg_type_common:
1684 if (*size < sizeof(vxge_hal_common_reg_t)) {
1685 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1686 *size = sizeof(vxge_hal_common_reg_t);
1690 for (offset = 0; offset < sizeof(vxge_hal_common_reg_t);
1692 *reg_config++ = vxge_os_pio_mem_read64(
1694 hldev->header.regh0,
1695 (void *)(((ptr_t) hldev->common_reg) + offset));
1697 *size = sizeof(vxge_hal_common_reg_t);
1700 case vxge_hal_mgmt_reg_type_memrepair:
1701 if (!(hldev->access_rights &
1702 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1703 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1707 if (*size < sizeof(vxge_hal_memrepair_reg_t)) {
1708 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1709 *size = sizeof(vxge_hal_memrepair_reg_t);
1714 offset < sizeof(vxge_hal_memrepair_reg_t); offset += 8) {
1715 *reg_config++ = vxge_os_pio_mem_read64(
1717 hldev->header.regh0,
1718 (void *)(((ptr_t) hldev->memrepair_reg) + offset));
1720 *size = sizeof(vxge_hal_memrepair_reg_t);
1723 case vxge_hal_mgmt_reg_type_pcicfgmgmt:
1724 if (!(hldev->access_rights &
1725 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1726 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1730 if (vp_id > VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES - 1) {
1731 status = VXGE_HAL_ERR_INVALID_INDEX;
1735 if (*size < sizeof(vxge_hal_pcicfgmgmt_reg_t)) {
1736 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1737 *size = sizeof(vxge_hal_pcicfgmgmt_reg_t);
1741 for (offset = 0; offset < sizeof(vxge_hal_pcicfgmgmt_reg_t);
1743 *reg_config++ = vxge_os_pio_mem_read64(
1745 hldev->header.regh0,
1746 (void *)(((ptr_t) hldev->pcicfgmgmt_reg[vp_id]) + offset));
1748 *size = sizeof(vxge_hal_pcicfgmgmt_reg_t);
1751 case vxge_hal_mgmt_reg_type_mrpcim:
1752 if (!(hldev->access_rights &
1753 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1754 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1758 if (*size < sizeof(vxge_hal_mrpcim_reg_t)) {
1759 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1760 *size = sizeof(vxge_hal_mrpcim_reg_t);
1764 for (offset = 0; offset < sizeof(vxge_hal_mrpcim_reg_t);
1766 *reg_config++ = vxge_os_pio_mem_read64(
1768 hldev->header.regh0,
1769 (void *)(((ptr_t) hldev->mrpcim_reg) + offset));
1771 *size = sizeof(vxge_hal_mrpcim_reg_t);
1774 case vxge_hal_mgmt_reg_type_srpcim:
1775 if (!(hldev->access_rights &
1776 VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
1777 status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
1781 if (vp_id > VXGE_HAL_TITAN_SRPCIM_REG_SPACES - 1) {
1782 status = VXGE_HAL_ERR_INVALID_INDEX;
1786 if (*size < sizeof(vxge_hal_srpcim_reg_t)) {
1787 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1788 *size = sizeof(vxge_hal_srpcim_reg_t);
1792 for (offset = 0; offset < sizeof(vxge_hal_srpcim_reg_t);
1794 *reg_config++ = vxge_os_pio_mem_read64(
1796 hldev->header.regh0,
1797 (void *)(((ptr_t) hldev->srpcim_reg[vp_id]) + offset));
1799 *size = sizeof(vxge_hal_srpcim_reg_t);
1802 case vxge_hal_mgmt_reg_type_vpmgmt:
1803 if ((vp_id > VXGE_HAL_TITAN_VPMGMT_REG_SPACES - 1) ||
1804 (!(hldev->vpath_assignments & mBIT(vp_id)))) {
1805 status = VXGE_HAL_ERR_INVALID_INDEX;
1809 if (*size < sizeof(vxge_hal_vpmgmt_reg_t)) {
1810 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1811 *size = sizeof(vxge_hal_vpmgmt_reg_t);
1815 for (offset = 0; offset < sizeof(vxge_hal_vpmgmt_reg_t);
1817 *reg_config++ = vxge_os_pio_mem_read64(
1819 hldev->header.regh0,
1820 (void *)(((ptr_t) hldev->vpmgmt_reg[vp_id]) + offset));
1822 *size = sizeof(vxge_hal_vpmgmt_reg_t);
1825 case vxge_hal_mgmt_reg_type_vpath:
1826 if ((vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) ||
1827 (!(hldev->vpath_assignments & mBIT(vp_id)))) {
1828 status = VXGE_HAL_ERR_INVALID_INDEX;
1832 if (vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) {
1833 status = VXGE_HAL_ERR_INVALID_INDEX;
1837 if (*size < sizeof(vxge_hal_vpath_reg_t)) {
1838 status = VXGE_HAL_ERR_OUT_OF_SPACE;
1839 *size = sizeof(vxge_hal_vpath_reg_t);
1843 for (offset = 0; offset < sizeof(vxge_hal_vpath_reg_t);
1845 *reg_config++ = vxge_os_pio_mem_read64(
1847 hldev->header.regh0,
1848 (void *)(((ptr_t) hldev->vpath_reg[vp_id]) + offset));
1850 *size = sizeof(vxge_hal_vpath_reg_t);
1854 status = VXGE_HAL_ERR_INVALID_TYPE;
1858 vxge_hal_trace_log_device("<== %s:%s:%d Result: %d",
1859 __FILE__, __func__, __LINE__, status);
1864 * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port
1865 * @hldev: HAL device handle.
1866 * @port: Port number
1868 * This routine only gets the temperature for XFP modules. Also, updating of the
1869 * NVRAM can sometimes fail and so the reading we might get may not be uptodate.
1872 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port)
1874 u16 val1, val2, count = 0;
1876 vxge_hal_status_e status;
1877 __hal_device_t *hldev = (__hal_device_t *) devh;
1879 vxge_assert(devh != NULL);
1881 vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
1882 __FILE__, __func__, __LINE__);
1884 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT", port = %d",
1885 (ptr_t) devh, port);
1887 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
1888 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1889 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
1890 return (VXGE_HAL_ERR_INVALID_DEVICE);
1893 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1894 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1895 __FILE__, __func__, __LINE__,
1896 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
1897 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
1900 val1 = VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_256_BYTES;
1902 status = __hal_mrpcim_mdio_access(devh, port,
1903 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE,
1904 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
1905 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL,
1908 if (status != VXGE_HAL_OK) {
1909 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1910 __FILE__, __func__, __LINE__, status);
1914 /* Now wait for the transfer to complete */
1916 vxge_os_mdelay(50); /* wait 50 milliseonds */
1918 status = __hal_mrpcim_mdio_access(devh, port,
1919 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
1920 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
1921 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL,
1924 if (status != VXGE_HAL_OK) {
1925 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1926 __FILE__, __func__, __LINE__, status);
1931 /* waited 500 ms which should be plenty of time */
1936 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK)
1937 == VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_PROGRESS);
1940 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK) ==
1941 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_FAILED) {
1942 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1943 __FILE__, __func__, __LINE__, status);
1944 return (VXGE_HAL_FAIL);
1947 status = __hal_mrpcim_mdio_access(devh, port,
1948 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
1949 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
1950 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_1,
1953 if (status != VXGE_HAL_OK) {
1954 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1955 __FILE__, __func__, __LINE__, status);
1959 status = __hal_mrpcim_mdio_access(devh, port,
1960 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
1961 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
1962 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_2,
1965 if (status != VXGE_HAL_OK) {
1966 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1967 __FILE__, __func__, __LINE__, status);
1971 actual = ((val1 << 8) | val2);
1973 if (actual >= 32768)
1974 actual = actual - 65536;
1976 actual = actual / 256;
1978 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
1979 __FILE__, __func__, __LINE__, status);
1986 * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback
1987 * @devh: HAL device handle.
1988 * @port: Port number
1989 * @enable:Boolean set to 1 to enable and 0 to disable.
1991 * Enable or disable PMA loopback.
1996 vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable)
1999 vxge_hal_status_e status;
2000 __hal_device_t *hldev = (__hal_device_t *) devh;
2002 vxge_assert(devh != NULL);
2004 vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
2005 __FILE__, __func__, __LINE__);
2007 vxge_hal_trace_log_mrpcim(
2008 "devh = 0x"VXGE_OS_STXFMT", port = %d, enable = %d",
2009 (ptr_t) devh, port, enable);
2011 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
2012 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
2013 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
2014 return (VXGE_HAL_ERR_INVALID_DEVICE);
2017 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2018 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
2019 __FILE__, __func__, __LINE__,
2020 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
2021 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
2024 status = __hal_mrpcim_mdio_access(devh, port,
2025 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
2026 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
2027 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1,
2030 if (status != VXGE_HAL_OK) {
2031 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
2032 __FILE__, __func__, __LINE__, status);
2038 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK;
2041 ~VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK;
2043 status = __hal_mrpcim_mdio_access(devh, port,
2044 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE,
2045 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
2046 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1,
2049 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
2050 __FILE__, __func__, __LINE__, status);
2052 return (VXGE_HAL_OK);
2056 * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback
2057 * @devh: HAL device handle.
2058 * @port: Port number
2059 * @enable:Boolean set to 1 to enable and 0 to disable.
2061 * Enable or disable xgmii loopback.
2066 vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable)
2069 __hal_device_t *hldev = (__hal_device_t *) devh;
2071 vxge_assert(devh != NULL);
2073 vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
2074 __FILE__, __func__, __LINE__);
2076 vxge_hal_trace_log_mrpcim(
2077 "devh = 0x"VXGE_OS_STXFMT", port = %d, enable = %d",
2078 (ptr_t) devh, port, enable);
2080 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
2081 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
2082 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
2083 return (VXGE_HAL_ERR_INVALID_DEVICE);
2086 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2087 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d",
2088 __FILE__, __func__, __LINE__,
2089 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
2090 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
2093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2094 hldev->header.regh0,
2095 &hldev->mrpcim_reg->xmac_cfg_port[port]);
2097 val64 |= VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK;
2099 val64 &= ~VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK;
2101 vxge_os_pio_mem_write64(hldev->header.pdev,
2102 hldev->header.regh0,
2104 &hldev->mrpcim_reg->xmac_cfg_port[port]);
2106 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
2107 __FILE__, __func__, __LINE__);
2109 return (VXGE_HAL_OK);