sys/mips/atheros/ar724x_chip.c

   1 /*-
   2  * Copyright (c) 2010 Adrian Chadd
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_ddb.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/cons.h>
  38 #include <sys/kdb.h>
  39 #include <sys/reboot.h>
  40
  41 #include <vm/vm.h>
  42 #include <vm/vm_page.h>
  43
  44 #include <net/ethernet.h>
  45
  46 #include <machine/clock.h>
  47 #include <machine/cpu.h>
  48 #include <machine/cpuregs.h>
  49 #include <machine/hwfunc.h>
  50 #include <machine/md_var.h>
  51 #include <machine/trap.h>
  52 #include <machine/vmparam.h>
  53
  54 #include <mips/atheros/ar71xxreg.h>
  55 #include <mips/atheros/ar724xreg.h>
  56
  57 #include <mips/atheros/ar71xx_cpudef.h>
  58 #include <mips/atheros/ar71xx_setup.h>
  59 #include <mips/atheros/ar724x_chip.h>
  60
  61 #include <mips/sentry5/s5reg.h>
  62
  63 static void
  64 ar724x_chip_detect_mem_size(void)
  65 {
  66 }
  67
  68 static void
  69 ar724x_chip_detect_sys_frequency(void)
  70 {
  71         uint32_t pll;
  72         uint32_t freq;
  73         uint32_t div;
  74
  75         pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
  76
  77         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
  78         freq = div * AR724X_BASE_FREQ;
  79
  80         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
  81         freq *= div;
  82
  83         u_ar71xx_cpu_freq = freq;
  84
  85         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
  86         u_ar71xx_ddr_freq = freq / div;
  87
  88         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
  89         u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
  90 }
  91
  92 static void
  93 ar724x_chip_device_stop(uint32_t mask)
  94 {
  95         uint32_t mask_inv, reg;
  96
  97         mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
  98         reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
  99         reg |= mask;
 100         reg &= ~mask_inv;
 101         ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
 102 }
 103
 104 static void
 105 ar724x_chip_device_start(uint32_t mask)
 106 {
 107         uint32_t mask_inv, reg;
 108
 109         mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
 110         reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
 111         reg &= ~mask;
 112         reg |= mask_inv;
 113         ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
 114 }
 115
 116 static int
 117 ar724x_chip_device_stopped(uint32_t mask)
 118 {
 119         uint32_t reg;
 120
 121         reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
 122         return ((reg & mask) == mask);
 123 }
 124
 125 static void
 126 ar724x_chip_set_pll_ge0(int speed)
 127 {
 128 }
 129
 130 static void
 131 ar724x_chip_set_pll_ge1(int speed)
 132 {
 133 }
 134
 135 static void
 136 ar724x_chip_ddr_flush_ge0(void)
 137 {
 138         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
 139 }
 140
 141 static void
 142 ar724x_chip_ddr_flush_ge1(void)
 143 {
 144         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
 145 }
 146
 147 static void
 148 ar724x_chip_ddr_flush_ip2(void)
 149 {
 150         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
 151 }
 152
 153
 154 static uint32_t
 155 ar724x_chip_get_eth_pll(unsigned int mac, int speed)
 156 {
 157         return 0;
 158 }
 159
 160 static void
 161 ar724x_chip_init_usb_peripheral(void)
 162 {
 163
 164         switch (ar71xx_soc) {
 165                 case AR71XX_SOC_AR7240:
 166
 167                         ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
 168                             AR724X_RESET_USB_HOST);
 169                         DELAY(1000);
 170
 171                         ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
 172                             AR724X_RESET_USB_HOST);
 173                         DELAY(1000);
 174
 175                         /*
 176                          * WAR for HW bug. Here it adjusts the duration
 177                          * between two SOFS.
 178                          */
 179                         ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
 180                             (3 << USB_CTRL_FLADJ_A0_SHIFT));
 181
 182                         break;
 183
 184                 case AR71XX_SOC_AR7241:
 185                 case AR71XX_SOC_AR7242:
 186
 187                         ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
 188                         DELAY(100);
 189
 190                         ar71xx_device_start(AR724X_RESET_USB_HOST);
 191                         DELAY(100);
 192
 193                         ar71xx_device_start(AR724X_RESET_USB_PHY);
 194                         DELAY(100);
 195
 196                         break;
 197
 198                 default:
 199                         /* fallthrough */
 200                         break;
 201         }
 202 }
 203
 204 struct ar71xx_cpu_def ar724x_chip_def = {
 205         &ar724x_chip_detect_mem_size,
 206         &ar724x_chip_detect_sys_frequency,
 207         &ar724x_chip_device_stop,
 208         &ar724x_chip_device_start,
 209         &ar724x_chip_device_stopped,
 210         &ar724x_chip_set_pll_ge0,
 211         &ar724x_chip_set_pll_ge1,
 212         &ar724x_chip_ddr_flush_ge0,
 213         &ar724x_chip_ddr_flush_ge1,
 214         &ar724x_chip_get_eth_pll,
 215         &ar724x_chip_ddr_flush_ip2,
 216         &ar724x_chip_init_usb_peripheral
 217 };