sys/mips/atheros/ar91xx_chip.c

   1 /*-
   2  * Copyright (c) 2010 Adrian Chadd
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_ddb.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/cons.h>
  38 #include <sys/kdb.h>
  39 #include <sys/reboot.h>
  40
  41 #include <vm/vm.h>
  42 #include <vm/vm_page.h>
  43
  44 #include <net/ethernet.h>
  45
  46 #include <machine/clock.h>
  47 #include <machine/cpu.h>
  48 #include <machine/cpuregs.h>
  49 #include <machine/hwfunc.h>
  50 #include <machine/md_var.h>
  51 #include <machine/trap.h>
  52 #include <machine/vmparam.h>
  53
  54 #include <mips/atheros/ar71xxreg.h>
  55 #include <mips/atheros/ar91xxreg.h>
  56
  57 #include <mips/atheros/ar71xx_cpudef.h>
  58 #include <mips/atheros/ar91xx_chip.h>
  59
  60 #include <mips/sentry5/s5reg.h>
  61
  62 static void
  63 ar91xx_chip_detect_mem_size(void)
  64 {
  65 }
  66
  67 static void
  68 ar91xx_chip_detect_sys_frequency(void)
  69 {
  70         uint32_t pll;
  71         uint32_t freq;
  72         uint32_t div;
  73
  74         pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
  75
  76         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
  77         freq = div * AR91XX_BASE_FREQ;
  78
  79         u_ar71xx_cpu_freq = freq;
  80
  81         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
  82         u_ar71xx_ddr_freq = freq / div;
  83
  84         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
  85         u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
  86 }
  87
  88 static void
  89 ar91xx_chip_device_stop(uint32_t mask)
  90 {
  91         uint32_t reg;
  92
  93         reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
  94         ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
  95 }
  96
  97 static void
  98 ar91xx_chip_device_start(uint32_t mask)
  99 {
 100         uint32_t reg;
 101
 102         reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
 103         ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
 104 }
 105
 106 static int
 107 ar91xx_chip_device_stopped(uint32_t mask)
 108 {
 109         uint32_t reg;
 110
 111         reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
 112         return ((reg & mask) == mask);
 113 }
 114
 115 static void
 116 ar91xx_chip_set_pll_ge0(int speed)
 117 {
 118         uint32_t pll;
 119
 120         switch(speed) {
 121                 case 10:
 122                         pll = AR91XX_PLL_VAL_10;
 123                         break;
 124                 case 100:
 125                         pll = AR91XX_PLL_VAL_100;
 126                         break;
 127                 case 1000:
 128                         pll = AR91XX_PLL_VAL_1000;
 129                         break;
 130                 default:
 131                         printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
 132                             speed);
 133                         return;
 134         }
 135         ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
 136             AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT);
 137 }
 138
 139 static void
 140 ar91xx_chip_set_pll_ge1(int speed)
 141 {
 142         uint32_t pll;
 143
 144         switch(speed) {
 145                 case 10:
 146                         pll = AR91XX_PLL_VAL_10;
 147                         break;
 148                 case 100:
 149                         pll = AR91XX_PLL_VAL_100;
 150                         break;
 151                 case 1000:
 152                         pll = AR91XX_PLL_VAL_1000;
 153                         break;
 154                 default:
 155                         printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
 156                             speed);
 157                         return;
 158         }
 159         ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
 160             AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT);
 161 }
 162
 163 static void
 164 ar91xx_chip_ddr_flush_ge0(void)
 165 {
 166         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
 167 }
 168
 169 static void
 170 ar91xx_chip_ddr_flush_ge1(void)
 171 {
 172         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
 173 }
 174
 175 static void
 176 ar91xx_chip_ddr_flush_ip2(void)
 177 {
 178         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
 179 }
 180
 181
 182 static uint32_t
 183 ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
 184 {
 185         return 0;
 186 }
 187
 188 static void
 189 ar91xx_chip_init_usb_peripheral(void)
 190 {
 191         ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
 192         DELAY(100);
 193
 194         ar71xx_device_start(RST_RESET_USB_HOST);
 195         DELAY(100);
 196
 197         ar71xx_device_start(RST_RESET_USB_PHY);
 198         DELAY(100);
 199
 200         /* Wireless */
 201         ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
 202         DELAY(1000);
 203
 204         ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
 205         DELAY(1000);
 206 }
 207
 208 struct ar71xx_cpu_def ar91xx_chip_def = {
 209         &ar91xx_chip_detect_mem_size,
 210         &ar91xx_chip_detect_sys_frequency,
 211         &ar91xx_chip_device_stop,
 212         &ar91xx_chip_device_start,
 213         &ar91xx_chip_device_stopped,
 214         &ar91xx_chip_set_pll_ge0,
 215         &ar91xx_chip_set_pll_ge1,
 216         &ar91xx_chip_ddr_flush_ge0,
 217         &ar91xx_chip_ddr_flush_ge1,
 218         &ar91xx_chip_get_eth_pll,
 219         &ar91xx_chip_ddr_flush_ip2,
 220         &ar91xx_chip_init_usb_peripheral,
 221 };