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32 #ifndef __NLM_HAL_MMIO_H__
33 #define __NLM_HAL_MMIO_H__
36 * This file contains platform specific memory mapped IO implementation
37 * and will provide a way to read 32/64 bit memory mapped registers in
42 * For o32 compilation, we have to disable interrupts and enable KX bit to
43 * access 64 bit addresses or data.
45 * We need to disable interrupts because we save just the lower 32 bits of
46 * registers in interrupt handling. So if we get hit by an interrupt while
47 * using the upper 32 bits of a register, we lose.
49 static inline uint32_t nlm_save_flags_kx(void)
51 uint32_t sr = mips_rd_status();
53 mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX);
57 static inline uint32_t nlm_save_flags_cop2(void)
59 uint32_t sr = mips_rd_status();
61 mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
65 static inline void nlm_restore_flags(uint32_t sr)
70 static inline uint32_t
71 nlm_load_word(uint64_t addr)
73 volatile uint32_t *p = (volatile uint32_t *)(long)addr;
79 nlm_store_word(uint64_t addr, uint32_t val)
81 volatile uint32_t *p = (volatile uint32_t *)(long)addr;
86 #if defined(__mips_n64) || defined(__mips_n32)
87 static inline uint64_t
88 nlm_load_dword(volatile uint64_t addr)
90 volatile uint64_t *p = (volatile uint64_t *)(long)addr;
96 nlm_store_dword(volatile uint64_t addr, uint64_t val)
98 volatile uint64_t *p = (volatile uint64_t *)(long)addr;
104 static inline uint64_t
105 nlm_load_dword(uint64_t addr)
107 volatile uint64_t *p = (volatile uint64_t *)(long)addr;
108 uint32_t valhi, vallo, sr;
110 sr = nlm_save_flags_kx();
111 __asm__ __volatile__(
115 "dsra32 %0, $8, 0\n\t"
118 : "=r"(valhi), "=r"(vallo)
121 nlm_restore_flags(sr);
123 return ((uint64_t)valhi << 32) | vallo;
127 nlm_store_dword(uint64_t addr, uint64_t val)
129 volatile uint64_t *p = (volatile uint64_t *)(long)addr;
130 uint32_t valhi, vallo, sr;
133 vallo = val & 0xffffffff;
135 sr = nlm_save_flags_kx();
136 __asm__ __volatile__(
139 "dsll32 $8, %1, 0\n\t"
140 "dsll32 $9, %2, 0\n\t" /* get rid of the */
141 "dsrl32 $9, $9, 0\n\t" /* sign extend */
145 : : "r"(p), "r"(valhi), "r"(vallo)
146 : "$8", "$9", "memory");
147 nlm_restore_flags(sr);
151 #if defined(__mips_n64)
152 static inline uint64_t
153 nlm_load_word_daddr(uint64_t addr)
155 volatile uint32_t *p = (volatile uint32_t *)(long)addr;
161 nlm_store_word_daddr(uint64_t addr, uint32_t val)
163 volatile uint32_t *p = (volatile uint32_t *)(long)addr;
168 static inline uint64_t
169 nlm_load_dword_daddr(uint64_t addr)
171 volatile uint64_t *p = (volatile uint64_t *)(long)addr;
177 nlm_store_dword_daddr(uint64_t addr, uint64_t val)
179 volatile uint64_t *p = (volatile uint64_t *)(long)addr;
184 #elif defined(__mips_n32)
186 static inline uint64_t
187 nlm_load_word_daddr(uint64_t addr)
191 __asm__ __volatile__(
203 nlm_store_word_daddr(uint64_t addr, uint32_t val)
205 __asm__ __volatile__(
210 : : "r"(val), "r"(addr)
214 static inline uint64_t
215 nlm_load_dword_daddr(uint64_t addr)
219 __asm__ __volatile__(
230 nlm_store_dword_daddr(uint64_t addr, uint64_t val)
232 __asm__ __volatile__(
237 : : "r"(val), "r"(addr)
242 static inline uint64_t
243 nlm_load_word_daddr(uint64_t addr)
245 uint32_t val, addrhi, addrlo, sr;
248 addrlo = addr & 0xffffffff;
250 sr = nlm_save_flags_kx();
251 __asm__ __volatile__(
254 "dsll32 $8, %1, 0\n\t"
255 "dsll32 $9, %2, 0\n\t"
256 "dsrl32 $9, $9, 0\n\t"
261 : "r"(addrhi), "r"(addrlo)
263 nlm_restore_flags(sr);
270 nlm_store_word_daddr(uint64_t addr, uint32_t val)
272 uint32_t addrhi, addrlo, sr;
275 addrlo = addr & 0xffffffff;
277 sr = nlm_save_flags_kx();
278 __asm__ __volatile__(
281 "dsll32 $8, %1, 0\n\t"
282 "dsll32 $9, %2, 0\n\t"
283 "dsrl32 $9, $9, 0\n\t"
287 : : "r"(val), "r"(addrhi), "r"(addrlo)
288 : "$8", "$9", "memory");
289 nlm_restore_flags(sr);
292 static inline uint64_t
293 nlm_load_dword_daddr(uint64_t addr)
295 uint32_t addrh, addrl, sr;
299 addrl = addr & 0xffffffff;
301 sr = nlm_save_flags_kx();
302 __asm__ __volatile__(
305 "dsll32 $8, %2, 0\n\t"
306 "dsll32 $9, %3, 0\n\t"
307 "dsrl32 $9, $9, 0\n\t"
310 "dsra32 %0, $8, 0\n\t"
313 : "=r"(valh), "=r"(vall)
314 : "r"(addrh), "r"(addrl)
316 nlm_restore_flags(sr);
318 return ((uint64_t)valh << 32) | vall;
322 nlm_store_dword_daddr(uint64_t addr, uint64_t val)
324 uint32_t addrh, addrl, sr;
328 addrl = addr & 0xffffffff;
330 vall = val & 0xffffffff;
332 sr = nlm_save_flags_kx();
333 __asm__ __volatile__(
336 "dsll32 $8, %2, 0\n\t"
337 "dsll32 $9, %3, 0\n\t"
338 "dsrl32 $9, $9, 0\n\t"
340 "dsll32 $8, %0, 0\n\t"
341 "dsll32 $10, %1, 0\n\t"
342 "dsrl32 $10, $10, 0\n\t"
346 : : "r"(valh), "r"(vall), "r"(addrh), "r"(addrl)
347 : "$8", "$9", "memory");
348 nlm_restore_flags(sr);
350 #endif /* __mips_n64 */
352 static inline uint32_t
353 nlm_read_reg(uint64_t base, uint32_t reg)
355 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
361 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
363 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
368 static inline uint64_t
369 nlm_read_reg64(uint64_t base, uint32_t reg)
371 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
373 return nlm_load_dword(addr);
377 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
379 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
381 return nlm_store_dword(addr, val);
385 * Routines to store 32/64 bit values to 64 bit addresses,
386 * used when going thru XKPHYS to access registers
388 static inline uint32_t
389 nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
391 uint64_t addr = base + reg * sizeof(uint32_t);
393 return nlm_load_word_daddr(addr);
397 nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
399 uint64_t addr = base + reg * sizeof(uint32_t);
400 return nlm_store_word_daddr(addr, val);
403 static inline uint64_t
404 nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
406 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
408 return nlm_load_dword_daddr(addr);
412 nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
414 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
416 return nlm_store_dword_daddr(addr, val);
419 /* Location where IO base is mapped */
420 extern uint64_t xlp_io_base;
422 static inline uint64_t
423 nlm_pcicfg_base(uint32_t devoffset)
425 return xlp_io_base + devoffset;
428 static inline uint64_t
429 nlm_xkphys_map_pcibar0(uint64_t pcibase)
433 paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
434 return (uint64_t)0x9000000000000000 | paddr;