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32 #ifndef __XLP_PCIBUS_H__
33 #define __XLP_PCIBUS_H__
35 #define MSI_MIPS_ADDR_BASE 0xfee00000
37 #define MSI_MIPS_ADDR_DEST 0x000ff000
38 #define MSI_MIPS_ADDR_RH 0x00000008
39 #define MSI_MIPS_ADDR_RH_OFF 0x00000000
40 #define MSI_MIPS_ADDR_RH_ON 0x00000008
41 #define MSI_MIPS_ADDR_DM 0x00000004
42 #define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
43 #define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
45 /* Fields in data for Intel MSI messages. */
46 #define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
47 #define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
48 #define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
50 #define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
51 #define MSI_MIPS_DATA_DEASSERT 0x00000000
52 #define MSI_MIPS_DATA_ASSERT 0x00004000
54 #define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
55 #define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
56 #define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
58 #define MSI_MIPS_DATA_INTVEC 0x000000ff
61 * Build Intel MSI message and data values from a source. AMD64 systems
62 * seem to be compatible, so we use the same function for both.
64 #define MIPS_MSI_ADDR(cpu) \
65 (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
66 MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
68 #define MIPS_MSI_DATA(irq) \
69 (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
70 MSI_MIPS_DATA_ASSERT | (irq))
72 #define PCIE_BRIDGE_CMD 0x1
73 #define PCIE_BRIDGE_MSI_CAP 0x14
74 #define PCIE_BRIDGE_MSI_ADDRL 0x15
75 #define PCIE_BRIDGE_MSI_ADDRH 0x16
76 #define PCIE_BRIDGE_MSI_DATA 0x17
78 /* XLP Global PCIE configuration space registers */
79 #define PCIE_MSI_STATUS 0x25A
80 #define PCIE_MSI_EN 0x25B
81 #define PCIE_INT_EN0 0x261
84 #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
87 #define PCIE_MSI_INT_EN (1 << 9)
89 #endif /* __XLP_PCIBUS_H__ */