2 * Copyright (c) 2003-2009 RMI Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of RMI Corporation, nor the names of its contributors,
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * The XLR device supports upto four 10/100/1000 Ethernet MACs and upto
33 * two 10G Ethernet MACs (of XGMII). Alternatively, each 10G port can used
34 * as a SPI-4 interface, with 8 ports per such interface. The MACs are
35 * encapsulated in another hardware block referred to as network accelerator,
36 * such that there are three instances of these in a XLR. One of them controls
37 * the four 1G RGMII ports while one each of the others controls an XGMII port.
38 * Enabling MACs requires configuring the corresponding network accelerator
39 * and the individual port.
40 * The XLS device supports upto 8 10/100/1000 Ethernet MACs or max 2 10G
41 * Ethernet MACs. The 1G MACs are of SGMII and 10G MACs are of XAUI
42 * interface. These ports are part of two network accelerators.
43 * The nlge driver configures and initializes non-SPI4 Ethernet ports in the
44 * XLR/XLS devices and enables data transfer on them.
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
50 #ifdef HAVE_KERNEL_OPTION_HEADERS
51 #include "opt_device_polling.h"
54 #include <sys/endian.h>
55 #include <sys/systm.h>
56 #include <sys/sockio.h>
57 #include <sys/param.h>
59 #include <sys/mutex.h>
61 #include <sys/limits.h>
64 #include <sys/malloc.h>
65 #include <sys/kernel.h>
66 #include <sys/module.h>
67 #include <sys/socket.h>
68 #define __RMAN_RESOURCE_VISIBLE
70 #include <sys/taskqueue.h>
72 #include <sys/sysctl.h>
75 #include <net/if_arp.h>
76 #include <net/ethernet.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/if_vlan_var.h>
83 #include <netinet/in_systm.h>
84 #include <netinet/in.h>
85 #include <netinet/ip.h>
91 #include <machine/reg.h>
92 #include <machine/cpu.h>
93 #include <machine/mips_opcode.h>
94 #include <machine/asm.h>
95 #include <machine/cpuregs.h>
96 #include <machine/param.h>
97 #include <machine/intr_machdep.h>
98 #include <machine/clock.h> /* for DELAY */
99 #include <machine/bus.h>
100 #include <machine/resource.h>
102 #include <mips/rmi/interrupt.h>
103 #include <mips/rmi/msgring.h>
104 #include <mips/rmi/iomap.h>
105 #include <mips/rmi/pic.h>
106 #include <mips/rmi/board.h>
107 #include <mips/rmi/rmi_mips_exts.h>
108 #include <mips/rmi/rmi_boot_info.h>
109 #include <mips/rmi/dev/xlr/atx_cpld.h>
110 #include <mips/rmi/dev/xlr/xgmac_mdio.h>
112 #include <dev/mii/mii.h>
113 #include <dev/mii/miivar.h>
115 #include <dev/mii/brgphyreg.h>
116 #include "miibus_if.h"
118 #include <mips/rmi/dev/nlge/if_nlge.h>
120 MODULE_DEPEND(nlna, nlge, 1, 1, 1);
121 MODULE_DEPEND(nlge, ether, 1, 1, 1);
122 MODULE_DEPEND(nlge, miibus, 1, 1, 1);
124 /* Network accelarator entry points */
125 static int nlna_probe(device_t);
126 static int nlna_attach(device_t);
127 static int nlna_detach(device_t);
128 static int nlna_suspend(device_t);
129 static int nlna_resume(device_t);
130 static int nlna_shutdown(device_t);
132 /* GMAC port entry points */
133 static int nlge_probe(device_t);
134 static int nlge_attach(device_t);
135 static int nlge_detach(device_t);
136 static int nlge_suspend(device_t);
137 static int nlge_resume(device_t);
138 static void nlge_init(void *);
139 static int nlge_ioctl(struct ifnet *, u_long, caddr_t);
140 static int nlge_tx(struct ifnet *ifp, struct mbuf *m);
141 static void nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len);
143 static int nlge_mii_write(struct device *, int, int, int);
144 static int nlge_mii_read(struct device *, int, int);
145 static void nlge_mac_mii_statchg(device_t);
146 static int nlge_mediachange(struct ifnet *ifp);
147 static void nlge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
149 /* Other internal/helper functions */
150 static void *get_buf(void);
152 static void nlna_add_to_port_set(struct nlge_port_set *pset,
153 struct nlge_softc *sc);
154 static void nlna_config_pde(struct nlna_softc *);
155 static void nlna_config_parser(struct nlna_softc *);
156 static void nlna_config_classifier(struct nlna_softc *);
157 static void nlna_config_fifo_spill_area(struct nlna_softc *sc);
158 static void nlna_config_translate_table(struct nlna_softc *sc);
159 static void nlna_config_common(struct nlna_softc *);
160 static void nlna_disable_ports(struct nlna_softc *sc);
161 static void nlna_enable_intr(struct nlna_softc *sc);
162 static void nlna_disable_intr(struct nlna_softc *sc);
163 static void nlna_enable_ports(struct nlna_softc *sc);
164 static void nlna_get_all_softc(device_t iodi_dev,
165 struct nlna_softc **sc_vec, uint32_t vec_sz);
166 static void nlna_hw_init(struct nlna_softc *sc);
167 static int nlna_is_last_active_na(struct nlna_softc *sc);
168 static void nlna_media_specific_config(struct nlna_softc *sc);
169 static void nlna_reset_ports(struct nlna_softc *sc,
170 struct xlr_gmac_block_t *blk);
171 static struct nlna_softc *nlna_sc_init(device_t dev,
172 struct xlr_gmac_block_t *blk);
173 static void nlna_setup_intr(struct nlna_softc *sc);
174 static void nlna_smp_update_pde(void *dummy __unused);
175 static void nlna_submit_rx_free_desc(struct nlna_softc *sc,
178 static int nlge_gmac_config_speed(struct nlge_softc *, int quick);
179 static void nlge_hw_init(struct nlge_softc *sc);
180 static int nlge_if_init(struct nlge_softc *sc);
181 static void nlge_intr(void *arg);
182 static int nlge_irq_init(struct nlge_softc *sc);
183 static void nlge_irq_fini(struct nlge_softc *sc);
184 static void nlge_media_specific_init(struct nlge_softc *sc);
185 static void nlge_mii_init(device_t dev, struct nlge_softc *sc);
186 static int nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr,
188 static void nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr,
189 int regidx, int regval);
190 void nlge_msgring_handler(int bucket, int size, int code,
191 int stid, struct msgrng_msg *msg, void *data);
192 static void nlge_port_disable(struct nlge_softc *sc);
193 static void nlge_port_enable(struct nlge_softc *sc);
194 static void nlge_read_mac_addr(struct nlge_softc *sc);
195 static void nlge_sc_init(struct nlge_softc *sc, device_t dev,
196 struct xlr_gmac_port *port_info);
197 static void nlge_set_mac_addr(struct nlge_softc *sc);
198 static void nlge_set_port_attribs(struct nlge_softc *,
199 struct xlr_gmac_port *);
200 static void nlge_mac_set_rx_mode(struct nlge_softc *sc);
201 static void nlge_sgmii_init(struct nlge_softc *sc);
202 static int nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc,
205 static int prepare_fmn_message(struct nlge_softc *sc,
206 struct msgrng_msg *msg, uint32_t *n_entries, struct mbuf *m_head,
207 uint64_t fr_stid, struct nlge_tx_desc **tx_desc);
209 static void release_tx_desc(vm_paddr_t phy_addr);
210 static int send_fmn_msg_tx(struct nlge_softc *, struct msgrng_msg *,
215 static int mac_debug = 1;
217 #define PDEBUG(fmt, args...) \
220 printf("[%s@%d|%s]: cpu_%d: " fmt, \
221 __FILE__, __LINE__, __FUNCTION__, PCPU_GET(cpuid), ##args);\
225 /* Debug/dump functions */
226 static void dump_reg(xlr_reg_t *addr, uint32_t offset, char *name);
227 static void dump_gmac_registers(struct nlge_softc *);
228 static void dump_na_registers(xlr_reg_t *base, int port_id);
229 static void dump_mac_stats(struct nlge_softc *sc);
230 static void dump_mii_regs(struct nlge_softc *sc) __attribute__((used));
231 static void dump_mii_data(struct mii_data *mii) __attribute__((used));
232 static void dump_board_info(struct xlr_board_info *);
233 static void dump_pcs_regs(struct nlge_softc *sc, int phy);
237 #define PDEBUG(fmt, args...)
238 #define dump_reg(a, o, n) /* nop */
239 #define dump_gmac_registers(a) /* nop */
240 #define dump_na_registers(a, p) /* nop */
241 #define dump_board_info(b) /* nop */
242 #define dump_mac_stats(sc) /* nop */
243 #define dump_mii_regs(sc) /* nop */
244 #define dump_mii_data(mii) /* nop */
245 #define dump_pcs_regs(sc, phy) /* nop */
248 /* Wrappers etc. to export the driver entry points. */
249 static device_method_t nlna_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, nlna_probe),
252 DEVMETHOD(device_attach, nlna_attach),
253 DEVMETHOD(device_detach, nlna_detach),
254 DEVMETHOD(device_shutdown, nlna_shutdown),
255 DEVMETHOD(device_suspend, nlna_suspend),
256 DEVMETHOD(device_resume, nlna_resume),
258 /* bus interface : TBD : what are these for ? */
259 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
264 static driver_t nlna_driver = {
267 sizeof(struct nlna_softc)
270 static devclass_t nlna_devclass;
272 static device_method_t nlge_methods[] = {
273 /* Device interface */
274 DEVMETHOD(device_probe, nlge_probe),
275 DEVMETHOD(device_attach, nlge_attach),
276 DEVMETHOD(device_detach, nlge_detach),
277 DEVMETHOD(device_shutdown, bus_generic_shutdown),
278 DEVMETHOD(device_suspend, nlge_suspend),
279 DEVMETHOD(device_resume, nlge_resume),
282 DEVMETHOD(miibus_readreg, nlge_mii_read),
283 DEVMETHOD(miibus_writereg, nlge_mii_write),
284 DEVMETHOD(miibus_statchg, nlge_mac_mii_statchg),
289 static driver_t nlge_driver = {
292 sizeof(struct nlge_softc)
295 static devclass_t nlge_devclass;
297 DRIVER_MODULE(nlna, iodi, nlna_driver, nlna_devclass, 0, 0);
298 DRIVER_MODULE(nlge, nlna, nlge_driver, nlge_devclass, 0, 0);
299 DRIVER_MODULE(miibus, nlge, miibus_driver, miibus_devclass, 0, 0);
301 static uma_zone_t nl_tx_desc_zone;
304 static int flow_classification = 0;
305 TUNABLE_INT("hw.nlge.flow_classification", &flow_classification);
307 #define NLGE_HW_CHKSUM 1
310 atomic_incr_long(unsigned long *addr)
312 /* XXX: fix for 64 bit */
313 unsigned int *iaddr = (unsigned int *)addr;
315 xlr_ldaddwu(1, iaddr);
319 nlna_probe(device_t dev)
321 return (BUS_PROBE_DEFAULT);
325 * Add all attached GMAC/XGMAC ports to the device tree. Port
326 * configuration is spread in two regions - common configuration
327 * for all ports in the NA and per-port configuration in MAC-specific
328 * region. This function does the following:
329 * - adds the ports to the device tree
331 * - do all the common initialization
332 * - invoke bus_generic_attach for per-port configuration
333 * - supply initial free rx descriptors to ports
334 * - initialize s/w data structures
335 * - finally, enable interrupts (only in the last NA).
337 * For reference, sample address space for common and per-port
338 * registers is given below.
340 * The address map for RNA0 is: (typical value)
342 * XLR_IO_BASE +--------------------------------------+ 0xbef0_0000
349 * GMAC0 ---> +--------------------------------------+ 0xbef0_c000
352 * (common) -> |......................................| 0xbef0_c400
354 * | (RGMII/SGMII: common registers) |
356 * GMAC1 ---> |--------------------------------------| 0xbef0_d000
359 * (common) -> |......................................| 0xbef0_d400
361 * | (RGMII/SGMII: common registers) |
363 * |......................................|
366 * Ref: Figure 14-3 and Table 14-1 of XLR PRM
369 nlna_attach(device_t dev)
371 struct xlr_gmac_block_t *block_info;
373 struct nlna_softc *sc;
378 id = device_get_unit(dev);
379 block_info = device_get_ivars(dev);
380 if (!block_info->enabled) {
385 dump_board_info(&xlr_board_info);
387 /* Initialize nlna state in softc structure */
388 sc = nlna_sc_init(dev, block_info);
390 /* Add device's for the ports controlled by this NA. */
391 if (block_info->type == XLR_GMAC) {
392 KASSERT(id < 2, ("No GMACs supported with this network"
393 "accelerator: %d", id));
394 for (i = 0; i < sc->num_ports; i++) {
395 gmac_dev = device_add_child(dev, "nlge", -1);
396 device_set_ivars(gmac_dev, &block_info->gmac_port[i]);
398 } else if (block_info->type == XLR_XGMAC) {
399 KASSERT(id > 0 && id <= 2, ("No XGMACs supported with this"
400 "network accelerator: %d", id));
401 gmac_dev = device_add_child(dev, "nlge", -1);
402 device_set_ivars(gmac_dev, &block_info->gmac_port[0]);
403 } else if (block_info->type == XLR_SPI4) {
404 /* SPI4 is not supported here */
405 device_printf(dev, "Unsupported: NA with SPI4 type");
409 nlna_reset_ports(sc, block_info);
411 /* Initialize Network Accelarator registers. */
414 error = bus_generic_attach(dev);
416 device_printf(dev, "failed to attach port(s)\n");
420 /* Send out the initial pool of free-descriptors for the rx path */
421 nlna_submit_rx_free_desc(sc, MAX_FRIN_SPILL);
423 /* S/w data structure initializations shared by all NA's. */
424 if (nl_tx_desc_zone == NULL) {
425 /* Create a zone for allocating tx descriptors */
426 nl_tx_desc_zone = uma_zcreate("NL Tx Desc",
427 sizeof(struct nlge_tx_desc), NULL, NULL, NULL, NULL,
428 XLR_CACHELINE_SIZE, 0);
431 /* Enable NA interrupts */
441 nlna_detach(device_t dev)
443 struct nlna_softc *sc;
445 sc = device_get_softc(dev);
446 if (device_is_alive(dev)) {
447 nlna_disable_intr(sc);
448 /* This will make sure that per-port detach is complete
449 * and all traffic on the ports has been stopped. */
450 bus_generic_detach(dev);
451 uma_zdestroy(nl_tx_desc_zone);
458 nlna_suspend(device_t dev)
465 nlna_resume(device_t dev)
472 nlna_shutdown(device_t dev)
478 /* GMAC port entry points */
480 nlge_probe(device_t dev)
482 struct nlge_softc *sc;
483 struct xlr_gmac_port *port_info;
485 char *desc[] = { "RGMII", "SGMII", "RGMII/SGMII", "XGMAC", "XAUI",
488 port_info = device_get_ivars(dev);
489 index = (port_info->type < XLR_RGMII || port_info->type > XLR_XAUI) ?
491 device_set_desc_copy(dev, desc[index]);
493 sc = device_get_softc(dev);
494 nlge_sc_init(sc, dev, port_info);
496 nlge_port_disable(sc);
502 nlge_attach(device_t dev)
504 struct nlge_softc *sc;
505 struct nlna_softc *nsc;
508 sc = device_get_softc(dev);
511 nlge_mii_init(dev, sc);
512 error = nlge_irq_init(sc);
517 nsc = (struct nlna_softc *)device_get_softc(device_get_parent(dev));
518 nsc->child_sc[sc->instance] = sc;
524 nlge_detach(device_t dev)
526 struct nlge_softc *sc;
529 sc = device_get_softc(dev);
532 if (device_is_attached(dev)) {
533 nlge_port_disable(sc);
536 bus_generic_detach(dev);
545 nlge_suspend(device_t dev)
551 nlge_resume(device_t dev)
557 nlge_init(void *addr)
559 struct nlge_softc *sc;
562 sc = (struct nlge_softc *)addr;
565 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
568 nlge_gmac_config_speed(sc, 1);
569 ifp->if_drv_flags |= IFF_DRV_RUNNING;
570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
571 nlge_port_enable(sc);
573 if (sc->port_type == XLR_SGMII) {
574 dump_pcs_regs(sc, 27);
576 dump_gmac_registers(sc);
581 nlge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
583 struct mii_data *mii;
584 struct nlge_softc *sc;
590 ifr = (struct ifreq *)data;
595 if (ifp->if_flags & IFF_UP) {
596 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
599 if (ifp->if_flags & IFF_PROMISC &&
600 !(sc->if_flags & IFF_PROMISC)) {
601 sc->if_flags |= IFF_PROMISC;
602 nlge_mac_set_rx_mode(sc);
603 } else if (!(ifp->if_flags & IFF_PROMISC) &&
604 sc->if_flags & IFF_PROMISC) {
605 sc->if_flags &= IFF_PROMISC;
606 nlge_mac_set_rx_mode(sc);
609 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
610 nlge_port_disable(sc);
613 sc->if_flags = ifp->if_flags;
620 if (sc->mii_bus != NULL) {
621 mii = (struct mii_data *)device_get_softc(sc->mii_bus);
622 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
628 error = ether_ioctl(ifp, command, data);
635 /* This function is called from an interrupt handler */
637 nlge_msgring_handler(int bucket, int size, int code, int stid,
638 struct msgrng_msg *msg, void *data)
640 struct nlna_softc *na_sc;
641 struct nlge_softc *sc;
644 vm_paddr_t phys_addr;
653 length = (msg->msg0 >> 40) & 0x3fff;
654 na_sc = (struct nlna_softc *)data;
656 ctrl = CTRL_REG_FREE;
657 phys_addr = msg->msg0 & 0xffffffffffULL;
658 port = (msg->msg0 >> 54) & 0x0f;
659 is_p2p = (msg->msg0 >> 62) & 0x1;
660 tx_error = (msg->msg0 >> 58) & 0xf;
663 phys_addr = msg->msg0 & 0xffffffffe0ULL;
664 length = length - BYTE_OFFSET - MAC_CRC_LEN;
665 port = msg->msg0 & 0x0f;
668 sc = na_sc->child_sc[port];
670 printf("Message (of %d len) with softc=NULL on %d port (type=%s)\n",
671 length, port, (ctrl == CTRL_SNGL ? "Pkt rx" :
672 "Freeback for tx packet"));
676 if (ctrl == CTRL_REG_FREE || ctrl == CTRL_JUMBO_FREE) {
680 release_tx_desc(phys_addr);
683 m = (struct mbuf *)(uintptr_t)xlr_paddr_ld(phys_addr);
686 m = (struct mbuf *)(uintptr_t)phys_addr;
691 if (ifp->if_drv_flags & IFF_DRV_OACTIVE){
692 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
696 printf("ERROR: Tx fb error (%d) on port %d\n", tx_error,
699 atomic_incr_long((tx_error) ? &ifp->if_oerrors: &ifp->if_opackets);
700 } else if (ctrl == CTRL_SNGL || ctrl == CTRL_START) {
703 nlge_rx(sc, phys_addr, length);
704 nlna_submit_rx_free_desc(na_sc, 1); /* return free descr to NA */
706 printf("[%s]: unrecognized ctrl=%d!\n", __func__, ctrl);
712 nlge_tx(struct ifnet *ifp, struct mbuf *m)
714 return (nlge_start_locked(ifp, ifp->if_softc, m));
718 nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc, struct mbuf *m)
720 struct msgrng_msg msg;
721 struct nlge_tx_desc *tx_desc;
733 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) ||
734 ifp->if_drv_flags & IFF_DRV_OACTIVE) {
736 goto fail; // note: mbuf will get free'd
741 /* H/w threads [0, 2] --> bucket 6 and [1, 3] --> bucket 7 */
742 fr_stid = cpu * 8 + 6 + (tid % 2);
745 * First, remove some freeback messages before transmitting
746 * any new packets. However, cap the number of messages
747 * drained to permit this thread to continue with its
750 * Mask for buckets {6, 7} is 0xc0
752 xlr_msgring_handler(0xc0, 4);
754 ret = prepare_fmn_message(sc, &msg, &n_entries, m, fr_stid, &tx_desc);
756 error = (ret == 2) ? ENOBUFS : ENOTSUP;
759 ret = send_fmn_msg_tx(sc, &msg, n_entries);
768 if (tx_desc != NULL) {
769 uma_zfree(nl_tx_desc_zone, tx_desc);
772 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
774 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
778 atomic_incr_long(&ifp->if_iqdrops);
784 nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len)
791 sr = xlr_enable_kx();
792 tm = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE);
793 mag = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE + sizeof(uint64_t));
796 m = (struct mbuf *)(intptr_t)tm;
797 if (mag != 0xf00bad) {
798 /* somebody else's packet. Error - FIXME in intialization */
799 printf("cpu %d: *ERROR* Not my packet paddr %jx\n",
800 xlr_core_id(), (uintmax_t)paddr);
806 #ifdef NLGE_HW_CHKSUM
807 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
808 if (m->m_data[10] & 0x2) {
809 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
810 if (m->m_data[10] & 0x1) {
811 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
813 m->m_pkthdr.csum_data = htons(0xffff);
816 m->m_data += NLGE_PREPAD_LEN;
817 len -= NLGE_PREPAD_LEN;
819 m->m_pkthdr.csum_flags = 0;
823 m->m_data += BYTE_OFFSET ;
824 m->m_pkthdr.len = m->m_len = len;
825 m->m_pkthdr.rcvif = ifp;
827 atomic_incr_long(&ifp->if_ipackets);
828 (*ifp->if_input)(ifp, m);
832 nlge_mii_write(struct device *dev, int phyaddr, int regidx, int regval)
834 struct nlge_softc *sc;
836 sc = device_get_softc(dev);
837 if (sc->port_type != XLR_XGMII)
838 nlge_mii_write_internal(sc->mii_base, phyaddr, regidx, regval);
844 nlge_mii_read(struct device *dev, int phyaddr, int regidx)
846 struct nlge_softc *sc;
849 sc = device_get_softc(dev);
850 val = (sc->port_type == XLR_XGMII) ? (0xffff) :
851 nlge_mii_read_internal(sc->mii_base, phyaddr, regidx);
857 nlge_mac_mii_statchg(device_t dev)
862 nlge_mediachange(struct ifnet *ifp)
868 nlge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
870 struct nlge_softc *sc;
876 md = device_get_softc(sc->mii_bus);
878 ifmr->ifm_status = IFM_AVALID;
879 ifmr->ifm_active = IFM_ETHER;
881 if (sc->link == xlr_mac_link_down)
885 ifmr->ifm_active = md->mii_media.ifm_cur->ifm_media;
886 ifmr->ifm_status |= IFM_ACTIVE;
889 static struct nlna_softc *
890 nlna_sc_init(device_t dev, struct xlr_gmac_block_t *blk)
892 struct nlna_softc *sc;
894 sc = device_get_softc(dev);
895 memset(sc, 0, sizeof(*sc));
897 sc->base = xlr_io_mmio(blk->baseaddr);
898 sc->rfrbucket = blk->station_rfr;
899 sc->station_id = blk->station_id;
900 sc->na_type = blk->type;
901 sc->mac_type = blk->mode;
902 sc->num_ports = blk->num_ports;
904 sc->mdio_set.port_vec = sc->mdio_sc;
905 sc->mdio_set.vec_sz = XLR_MAX_MACS;
912 * - Initialize common GMAC registers (index range 0x100-0x3ff).
915 nlna_hw_init(struct nlna_softc *sc)
919 * Register message ring handler for the NA block, messages from
920 * the GMAC will have source station id to the first bucket of the
921 * NA FMN station, so register just that station id.
923 if (register_msgring_handler(sc->station_id, sc->station_id + 1,
924 nlge_msgring_handler, sc)) {
925 panic("Couldn't register msgring handler\n");
927 nlna_config_fifo_spill_area(sc);
929 nlna_config_common(sc);
930 nlna_config_parser(sc);
931 nlna_config_classifier(sc);
935 * Enable interrupts on all the ports controlled by this NA. For now, we
936 * only care about the MII interrupt and this has to be enabled only
939 * This function is not in-sync with the regular way of doing things - it
940 * executes only in the context of the last active network accelerator (and
941 * thereby has some ugly accesses in the device tree). Though inelegant, it
942 * is necessary to do it this way as the per-port interrupts can be
943 * setup/enabled only after all the network accelerators have been
947 nlna_setup_intr(struct nlna_softc *sc)
949 struct nlna_softc *na_sc[XLR_MAX_NLNA];
950 struct nlge_port_set *pset;
951 struct xlr_gmac_port *port_info;
955 if (!nlna_is_last_active_na(sc))
958 /* Collect all nlna softc pointers */
959 memset(na_sc, 0, sizeof(*na_sc) * XLR_MAX_NLNA);
960 iodi_dev = device_get_parent(sc->nlna_dev);
961 nlna_get_all_softc(iodi_dev, na_sc, XLR_MAX_NLNA);
963 /* Setup the MDIO interrupt lists. */
965 * MDIO interrupts are coarse - a single interrupt line provides
966 * information about one of many possible ports. To figure out the
967 * exact port on which action is to be taken, all of the ports
968 * linked to an MDIO interrupt should be read. To enable this,
969 * ports need to add themselves to port sets.
971 for (i = 0; i < XLR_MAX_NLNA; i++) {
972 if (na_sc[i] == NULL)
974 for (j = 0; j < na_sc[i]->num_ports; j++) {
975 /* processing j-th port on i-th NA */
976 port_info = device_get_ivars(
977 na_sc[i]->child_sc[j]->nlge_dev);
978 pset = &na_sc[port_info->mdint_id]->mdio_set;
979 nlna_add_to_port_set(pset, na_sc[i]->child_sc[j]);
983 /* Enable interrupts */
984 for (i = 0; i < XLR_MAX_NLNA; i++) {
985 if (na_sc[i] != NULL && na_sc[i]->na_type != XLR_XGMAC) {
986 nlna_enable_intr(na_sc[i]);
992 nlna_add_to_port_set(struct nlge_port_set *pset, struct nlge_softc *sc)
996 /* step past the non-NULL elements */
997 for (i = 0; i < pset->vec_sz && pset->port_vec[i] != NULL; i++) ;
998 if (i < pset->vec_sz)
999 pset->port_vec[i] = sc;
1001 printf("warning: internal error: out-of-bounds for MDIO array");
1005 nlna_enable_intr(struct nlna_softc *sc)
1009 for (i = 0; i < sc->num_ports; i++) {
1010 if (sc->child_sc[i]->instance == 0)
1011 NLGE_WRITE(sc->child_sc[i]->base, R_INTMASK,
1012 (1 << O_INTMASK__MDInt));
1017 nlna_disable_intr(struct nlna_softc *sc)
1021 for (i = 0; i < sc->num_ports; i++) {
1022 if (sc->child_sc[i]->instance == 0)
1023 NLGE_WRITE(sc->child_sc[i]->base, R_INTMASK, 0);
1028 nlna_is_last_active_na(struct nlna_softc *sc)
1032 id = device_get_unit(sc->nlna_dev);
1033 return (id == 2 || xlr_board_info.gmac_block[id + 1].enabled == 0);
1037 nlna_submit_rx_free_desc(struct nlna_softc *sc, uint32_t n_desc)
1039 struct msgrng_msg msg;
1041 uint32_t msgrng_flags;
1042 int i, n, stid, ret, code;
1045 PDEBUG("Sending %d free-in descriptors to station=%d\n", n_desc,
1049 stid = sc->rfrbucket;
1050 code = (sc->na_type == XLR_XGMAC) ? MSGRNG_CODE_XGMAC : MSGRNG_CODE_MAC;
1051 memset(&msg, 0, sizeof(msg));
1053 for (i = 0; i < n_desc; i++) {
1057 device_printf(sc->nlna_dev, "Cannot allocate mbuf\n");
1061 /* Send the free Rx desc to the MAC */
1062 msg.msg0 = vtophys(ptr) & 0xffffffffe0ULL;
1065 msgrng_flags = msgrng_access_enable();
1066 ret = message_send(1, code, stid, &msg);
1067 msgrng_restore(msgrng_flags);
1068 KASSERT(n++ < 100000, ("Too many credit fails in rx path\n"));
1073 static __inline__ void *
1074 nlna_config_spill(xlr_reg_t *base, int reg_start_0, int reg_start_1,
1075 int reg_size, int size)
1079 uint32_t spill_size;
1082 spill = contigmalloc((spill_size + XLR_CACHELINE_SIZE), M_DEVBUF,
1083 M_NOWAIT | M_ZERO, 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
1084 if (spill == NULL || ((vm_offset_t) spill & (XLR_CACHELINE_SIZE - 1))) {
1085 panic("Unable to allocate memory for spill area!\n");
1087 phys_addr = vtophys(spill);
1088 PDEBUG("Allocated spill %d bytes at %llx\n", size, phys_addr);
1089 NLGE_WRITE(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
1090 NLGE_WRITE(base, reg_start_1, (phys_addr >> 37) & 0x07);
1091 NLGE_WRITE(base, reg_size, spill_size);
1097 * Configure the 6 FIFO's that are used by the network accelarator to
1098 * communicate with the rest of the XLx device. 4 of the FIFO's are for
1099 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
1100 * the NA with free descriptors.
1103 nlna_config_fifo_spill_area(struct nlna_softc *sc)
1105 sc->frin_spill = nlna_config_spill(sc->base,
1106 R_REG_FRIN_SPILL_MEM_START_0,
1107 R_REG_FRIN_SPILL_MEM_START_1,
1108 R_REG_FRIN_SPILL_MEM_SIZE,
1110 sizeof(struct fr_desc));
1111 sc->frout_spill = nlna_config_spill(sc->base,
1112 R_FROUT_SPILL_MEM_START_0,
1113 R_FROUT_SPILL_MEM_START_1,
1114 R_FROUT_SPILL_MEM_SIZE,
1116 sizeof(struct fr_desc));
1117 sc->class_0_spill = nlna_config_spill(sc->base,
1118 R_CLASS0_SPILL_MEM_START_0,
1119 R_CLASS0_SPILL_MEM_START_1,
1120 R_CLASS0_SPILL_MEM_SIZE,
1122 sizeof(union rx_tx_desc));
1123 sc->class_1_spill = nlna_config_spill(sc->base,
1124 R_CLASS1_SPILL_MEM_START_0,
1125 R_CLASS1_SPILL_MEM_START_1,
1126 R_CLASS1_SPILL_MEM_SIZE,
1128 sizeof(union rx_tx_desc));
1129 sc->class_2_spill = nlna_config_spill(sc->base,
1130 R_CLASS2_SPILL_MEM_START_0,
1131 R_CLASS2_SPILL_MEM_START_1,
1132 R_CLASS2_SPILL_MEM_SIZE,
1134 sizeof(union rx_tx_desc));
1135 sc->class_3_spill = nlna_config_spill(sc->base,
1136 R_CLASS3_SPILL_MEM_START_0,
1137 R_CLASS3_SPILL_MEM_START_1,
1138 R_CLASS3_SPILL_MEM_SIZE,
1140 sizeof(union rx_tx_desc));
1143 /* Set the CPU buckets that receive packets from the NA class FIFOs. */
1145 nlna_config_pde(struct nlna_softc *sc)
1147 uint64_t bucket_map;
1154 * rge may be called before SMP start in a BOOTP/NFSROOT
1155 * setup. we will distribute packets to other cpus only when
1156 * the SMP is started.
1159 cpumask = xlr_hw_thread_mask;
1162 for (i = 0; i < 32; i++) {
1163 if (cpumask & (1 << i)) {
1165 /* use bucket 0 and 1 on every core for NA msgs */
1167 bucket_map |= (3ULL << bucket);
1171 NLGE_WRITE(sc->base, R_PDE_CLASS_0, (bucket_map & 0xffffffff));
1172 NLGE_WRITE(sc->base, R_PDE_CLASS_0 + 1, ((bucket_map >> 32) & 0xffffffff));
1174 NLGE_WRITE(sc->base, R_PDE_CLASS_1, (bucket_map & 0xffffffff));
1175 NLGE_WRITE(sc->base, R_PDE_CLASS_1 + 1, ((bucket_map >> 32) & 0xffffffff));
1177 NLGE_WRITE(sc->base, R_PDE_CLASS_2, (bucket_map & 0xffffffff));
1178 NLGE_WRITE(sc->base, R_PDE_CLASS_2 + 1, ((bucket_map >> 32) & 0xffffffff));
1180 NLGE_WRITE(sc->base, R_PDE_CLASS_3, (bucket_map & 0xffffffff));
1181 NLGE_WRITE(sc->base, R_PDE_CLASS_3 + 1, ((bucket_map >> 32) & 0xffffffff));
1185 * Update the network accelerator packet distribution engine for SMP.
1186 * On bootup, we have just the boot hw thread handling all packets, on SMP
1187 * start, we can start distributing packets across all the cores which are up.
1190 nlna_smp_update_pde(void *dummy __unused)
1193 struct nlna_softc *na_sc[XLR_MAX_NLNA];
1196 printf("Updating packet distribution for SMP\n");
1198 iodi_dev = devclass_get_device(devclass_find("iodi"), 0);
1199 nlna_get_all_softc(iodi_dev, na_sc, XLR_MAX_NLNA);
1201 for (i = 0; i < XLR_MAX_NLNA; i++) {
1202 if (na_sc[i] == NULL)
1204 nlna_disable_ports(na_sc[i]);
1205 nlna_config_pde(na_sc[i]);
1206 nlna_config_translate_table(na_sc[i]);
1207 nlna_enable_ports(na_sc[i]);
1211 SYSINIT(nlna_smp_update_pde, SI_SUB_SMP, SI_ORDER_ANY, nlna_smp_update_pde,
1215 nlna_config_translate_table(struct nlna_softc *sc)
1219 int bkts[32]; /* one bucket is assumed for each cpu */
1220 int b1, b2, c1, c2, i, j, k;
1223 if (!flow_classification)
1228 cpu_mask = xlr_hw_thread_mask;
1232 printf("Using %s-based distribution\n", (use_bkt) ? "bucket" : "class");
1235 for(i = 0; i < 32; i++) {
1236 if ((1 << i) & cpu_mask){
1237 /* for each cpu, mark the 4+threadid bucket */
1238 bkts[j] = ((i / 4) * 8) + (i % 4);
1243 /*configure the 128 * 9 Translation table to send to available buckets*/
1247 for(i = 0; i < 64; i++) {
1248 /* Get the next 2 pairs of (class, bucket):
1251 c1, c2 limited to {0, 1, 2, 3}
1252 i.e, the 4 classes defined by h/w
1253 b1, b2 limited to { bkts[i], where 0 <= i < j}
1254 i.e, the set of buckets computed in the
1264 PDEBUG("Translation table[%d] b1=%d b2=%d c1=%d c2=%d\n",
1266 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
1267 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
1268 NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, val);
1274 nlna_config_parser(struct nlna_softc *sc)
1279 * Mark it as ETHERNET type.
1281 NLGE_WRITE(sc->base, R_L2TYPE_0, 0x01);
1283 #ifndef NLGE_HW_CHKSUM
1284 if (!flow_classification)
1288 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
1289 NLGE_WRITE(sc->base, R_PARSERCONFIGREG, ((0x7f << 8) | (1 << 1)));
1291 /* configure the parser : L2 Type is configured in the bootloader */
1292 /* extract IP: src, dest protocol */
1293 NLGE_WRITE(sc->base, R_L3CTABLE,
1294 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
1296 NLGE_WRITE(sc->base, R_L3CTABLE + 1,
1297 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) | (16 << 4) | 4);
1298 #ifdef NLGE_HW_CHKSUM
1299 device_printf(sc->nlna_dev, "Enabled h/w support to compute TCP/IP"
1303 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
1304 NLGE_WRITE(sc->base, R_L4CTABLE, 6);
1305 NLGE_WRITE(sc->base, R_L4CTABLE + 2, 17);
1306 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
1307 NLGE_WRITE(sc->base, R_L4CTABLE + 1, val);
1308 NLGE_WRITE(sc->base, R_L4CTABLE + 3, val);
1312 nlna_config_classifier(struct nlna_softc *sc)
1316 if (sc->mac_type == XLR_XGMII) { /* TBD: XGMII init sequence */
1317 /* xgmac translation table doesn't have sane values on reset */
1318 for (i = 0; i < 64; i++)
1319 NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, 0x0);
1322 * use upper 7 bits of the parser extract to index the
1325 NLGE_WRITE(sc->base, R_PARSERCONFIGREG, 0x0);
1330 * Complete a bunch of h/w register initializations that are common for all the
1331 * ports controlled by a NA.
1334 nlna_config_common(struct nlna_softc *sc)
1336 struct xlr_gmac_block_t *block_info;
1337 struct stn_cc *gmac_cc_config;
1340 block_info = device_get_ivars(sc->nlna_dev);
1341 gmac_cc_config = block_info->credit_config;
1342 for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
1343 NLGE_WRITE(sc->base, R_CC_CPU0_0 + i,
1344 gmac_cc_config->counters[i >> 3][i & 0x07]);
1347 NLGE_WRITE(sc->base, R_MSG_TX_THRESHOLD, 3);
1349 NLGE_WRITE(sc->base, R_DMACR0, 0xffffffff);
1350 NLGE_WRITE(sc->base, R_DMACR1, 0xffffffff);
1351 NLGE_WRITE(sc->base, R_DMACR2, 0xffffffff);
1352 NLGE_WRITE(sc->base, R_DMACR3, 0xffffffff);
1353 NLGE_WRITE(sc->base, R_FREEQCARVE, 0);
1355 nlna_media_specific_config(sc);
1359 nlna_media_specific_config(struct nlna_softc *sc)
1361 struct bucket_size *bucket_sizes;
1363 bucket_sizes = xlr_board_info.bucket_sizes;
1364 switch (sc->mac_type) {
1368 NLGE_WRITE(sc->base, R_GMAC_JFR0_BUCKET_SIZE,
1369 bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_0]);
1370 NLGE_WRITE(sc->base, R_GMAC_RFR0_BUCKET_SIZE,
1371 bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_0]);
1372 NLGE_WRITE(sc->base, R_GMAC_JFR1_BUCKET_SIZE,
1373 bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_1]);
1374 NLGE_WRITE(sc->base, R_GMAC_RFR1_BUCKET_SIZE,
1375 bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_1]);
1377 if (sc->mac_type == XLR_XAUI) {
1378 NLGE_WRITE(sc->base, R_TXDATAFIFO0, (224 << 16));
1383 NLGE_WRITE(sc->base, R_XGS_RFR_BUCKET_SIZE,
1384 bucket_sizes->bucket[sc->rfrbucket]);
1392 nlna_reset_ports(struct nlna_softc *sc, struct xlr_gmac_block_t *blk)
1398 /* Refer Section 13.9.3 in the PRM for the reset sequence */
1400 for (i = 0; i < sc->num_ports; i++) {
1401 addr = xlr_io_mmio(blk->gmac_port[i].base_addr);
1403 /* 1. Reset RxEnable in MAC_CONFIG */
1404 switch (sc->mac_type) {
1407 NLGE_UPDATE(addr, R_MAC_CONFIG_1, 0,
1408 (1 << O_MAC_CONFIG_1__rxen));
1412 NLGE_UPDATE(addr, R_RX_CONTROL, 0,
1413 (1 << O_RX_CONTROL__RxEnable));
1416 printf("Error: Unsupported port_type=%d\n",
1420 /* 1.1 Wait for RxControl.RxHalt to be set */
1422 rx_ctrl = NLGE_READ(addr, R_RX_CONTROL);
1423 } while (!(rx_ctrl & 0x2));
1425 /* 2. Set the soft reset bit in RxControl */
1426 NLGE_UPDATE(addr, R_RX_CONTROL, (1 << O_RX_CONTROL__SoftReset),
1427 (1 << O_RX_CONTROL__SoftReset));
1429 /* 2.1 Wait for RxControl.SoftResetDone to be set */
1431 rx_ctrl = NLGE_READ(addr, R_RX_CONTROL);
1432 } while (!(rx_ctrl & 0x8));
1434 /* 3. Clear the soft reset bit in RxControl */
1435 NLGE_UPDATE(addr, R_RX_CONTROL, 0,
1436 (1 << O_RX_CONTROL__SoftReset));
1438 /* Turn off tx/rx on the port. */
1439 NLGE_UPDATE(addr, R_RX_CONTROL, 0,
1440 (1 << O_RX_CONTROL__RxEnable));
1441 NLGE_UPDATE(addr, R_TX_CONTROL, 0,
1442 (1 << O_TX_CONTROL__TxEnable));
1447 nlna_disable_ports(struct nlna_softc *sc)
1451 for (i = 0; i < sc->num_ports; i++) {
1452 if (sc->child_sc[i] != NULL)
1453 nlge_port_disable(sc->child_sc[i]);
1458 nlna_enable_ports(struct nlna_softc *sc)
1460 device_t nlge_dev, *devlist;
1461 struct nlge_softc *port_sc;
1464 device_get_children(sc->nlna_dev, &devlist, &numdevs);
1465 for (i = 0; i < numdevs; i++) {
1466 nlge_dev = devlist[i];
1467 if (nlge_dev == NULL)
1469 port_sc = device_get_softc(nlge_dev);
1470 if (port_sc->nlge_if->if_drv_flags & IFF_DRV_RUNNING)
1471 nlge_port_enable(port_sc);
1473 free(devlist, M_TEMP);
1477 nlna_get_all_softc(device_t iodi_dev, struct nlna_softc **sc_vec,
1483 for (i = 0; i < vec_sz; i++) {
1485 na_dev = device_find_child(iodi_dev, "nlna", i);
1487 sc_vec[i] = device_get_softc(na_dev);
1492 nlge_port_disable(struct nlge_softc *sc)
1500 port_type = sc->port_type;
1504 NLGE_UPDATE(base, R_RX_CONTROL, 0x0, 1 << O_RX_CONTROL__RxEnable);
1506 rd = NLGE_READ(base, R_RX_CONTROL);
1507 } while (!(rd & (1 << O_RX_CONTROL__RxHalt)));
1509 NLGE_UPDATE(base, R_TX_CONTROL, 0, 1 << O_TX_CONTROL__TxEnable);
1511 rd = NLGE_READ(base, R_TX_CONTROL);
1512 } while (!(rd & (1 << O_TX_CONTROL__TxIdle)));
1514 switch (port_type) {
1517 NLGE_UPDATE(base, R_MAC_CONFIG_1, 0,
1518 ((1 << O_MAC_CONFIG_1__rxen) |
1519 (1 << O_MAC_CONFIG_1__txen)));
1523 NLGE_UPDATE(base, R_XGMAC_CONFIG_1, 0,
1524 ((1 << O_XGMAC_CONFIG_1__hsttfen) |
1525 (1 << O_XGMAC_CONFIG_1__hstrfen)));
1528 panic("Unknown MAC type on port %d\n", id);
1532 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1537 nlge_port_enable(struct nlge_softc *sc)
1539 struct xlr_gmac_port *self;
1543 self = device_get_ivars(sc->nlge_dev);
1544 if (xlr_board_info.is_xls && sc->port_type == XLR_RGMII)
1545 NLGE_UPDATE(base, R_RX_CONTROL, (1 << O_RX_CONTROL__RGMII),
1546 (1 << O_RX_CONTROL__RGMII));
1548 NLGE_UPDATE(base, R_RX_CONTROL, (1 << O_RX_CONTROL__RxEnable),
1549 (1 << O_RX_CONTROL__RxEnable));
1550 NLGE_UPDATE(base, R_TX_CONTROL,
1551 (1 << O_TX_CONTROL__TxEnable | RGE_TX_THRESHOLD_BYTES),
1552 (1 << O_TX_CONTROL__TxEnable | 0x3fff));
1553 switch (sc->port_type) {
1556 NLGE_UPDATE(base, R_MAC_CONFIG_1,
1557 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen)),
1558 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen)));
1562 NLGE_UPDATE(base, R_XGMAC_CONFIG_1,
1563 ((1 << O_XGMAC_CONFIG_1__hsttfen) | (1 << O_XGMAC_CONFIG_1__hstrfen)),
1564 ((1 << O_XGMAC_CONFIG_1__hsttfen) | (1 << O_XGMAC_CONFIG_1__hstrfen)));
1567 panic("Unknown MAC type on port %d\n", sc->id);
1572 nlge_mac_set_rx_mode(struct nlge_softc *sc)
1576 regval = NLGE_READ(sc->base, R_MAC_FILTER_CONFIG);
1578 if (sc->if_flags & IFF_PROMISC) {
1579 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
1580 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
1581 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
1582 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
1584 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
1585 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
1588 NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG, regval);
1592 nlge_sgmii_init(struct nlge_softc *sc)
1594 xlr_reg_t *mmio_gpio;
1597 if (sc->port_type != XLR_SGMII)
1600 nlge_mii_write_internal(sc->serdes_addr, 26, 0, 0x6DB0);
1601 nlge_mii_write_internal(sc->serdes_addr, 26, 1, 0xFFFF);
1602 nlge_mii_write_internal(sc->serdes_addr, 26, 2, 0xB6D0);
1603 nlge_mii_write_internal(sc->serdes_addr, 26, 3, 0x00FF);
1604 nlge_mii_write_internal(sc->serdes_addr, 26, 4, 0x0000);
1605 nlge_mii_write_internal(sc->serdes_addr, 26, 5, 0x0000);
1606 nlge_mii_write_internal(sc->serdes_addr, 26, 6, 0x0005);
1607 nlge_mii_write_internal(sc->serdes_addr, 26, 7, 0x0001);
1608 nlge_mii_write_internal(sc->serdes_addr, 26, 8, 0x0000);
1609 nlge_mii_write_internal(sc->serdes_addr, 26, 9, 0x0000);
1610 nlge_mii_write_internal(sc->serdes_addr, 26,10, 0x0000);
1612 /* program GPIO values for serdes init parameters */
1614 mmio_gpio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
1615 xlr_write_reg(mmio_gpio, 0x20, 0x7e6802);
1616 xlr_write_reg(mmio_gpio, 0x10, 0x7104);
1620 * This kludge is needed to setup serdes (?) clock correctly on some
1623 if ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI ||
1624 xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII) &&
1625 xlr_boot1_info.board_minor_version == 4) {
1626 /* use 125 Mhz instead of 156.25Mhz ref clock */
1628 xlr_write_reg(mmio_gpio, 0x10, 0x7103);
1629 xlr_write_reg(mmio_gpio, 0x21, 0x7103);
1633 /* enable autoneg - more magic */
1634 phy = sc->phy_addr % 4 + 27;
1635 nlge_mii_write_internal(sc->pcs_addr, phy, 0, 0x1000);
1637 nlge_mii_write_internal(sc->pcs_addr, phy, 0, 0x0200);
1642 nlge_intr(void *arg)
1644 struct nlge_port_set *pset;
1645 struct nlge_softc *sc;
1646 struct nlge_softc *port_sc;
1649 uint32_t intr_status;
1654 printf("warning: No port registered for interrupt\n");
1659 intreg = NLGE_READ(base, R_INTREG);
1660 if (intreg & (1 << O_INTREG__MDInt)) {
1661 pset = sc->mdio_pset;
1663 printf("warning: No ports for MDIO interrupt\n");
1666 for (i = 0; i < pset->vec_sz; i++) {
1667 port_sc = pset->port_vec[i];
1669 if (port_sc == NULL)
1672 /* Ack phy interrupt - clear on read*/
1673 intr_status = nlge_mii_read_internal(port_sc->mii_base,
1674 port_sc->phy_addr, 26);
1675 PDEBUG("Phy_%d: int_status=0x%08x\n", port_sc->phy_addr,
1678 if (!(intr_status & 0x8000)) {
1679 /* no interrupt for this port */
1683 if (intr_status & 0x2410) {
1684 /* update link status for port */
1685 nlge_gmac_config_speed(port_sc, 1);
1687 printf("%s: Unsupported phy interrupt"
1689 device_get_nameunit(port_sc->nlge_dev),
1695 /* Clear the NA interrupt */
1696 xlr_write_reg(base, R_INTREG, 0xffffffff);
1702 nlge_irq_init(struct nlge_softc *sc)
1704 struct resource irq_res;
1705 struct nlna_softc *na_sc;
1706 struct xlr_gmac_block_t *block_info;
1711 na_dev = device_get_parent(sc->nlge_dev);
1712 block_info = device_get_ivars(na_dev);
1714 irq_num = block_info->baseirq + sc->instance;
1715 irq_res.__r_i = (struct resource_i *)(intptr_t) (irq_num);
1716 ret = bus_setup_intr(sc->nlge_dev, &irq_res,
1717 INTR_TYPE_NET | INTR_MPSAFE, NULL, nlge_intr, sc, NULL);
1719 nlge_detach(sc->nlge_dev);
1720 device_printf(sc->nlge_dev, "couldn't set up irq: error=%d\n",
1724 PDEBUG("Setup intr for dev=%s, irq=%d\n",
1725 device_get_nameunit(sc->nlge_dev), irq_num);
1727 if (sc->instance == 0) {
1728 na_sc = device_get_softc(na_dev);
1729 sc->mdio_pset = &na_sc->mdio_set;
1735 nlge_irq_fini(struct nlge_softc *sc)
1740 nlge_hw_init(struct nlge_softc *sc)
1742 struct xlr_gmac_port *port_info;
1746 port_info = device_get_ivars(sc->nlge_dev);
1747 sc->tx_bucket_id = port_info->tx_bucket_id;
1749 /* each packet buffer is 1536 bytes */
1750 NLGE_WRITE(base, R_DESC_PACK_CTRL,
1751 (1 << O_DESC_PACK_CTRL__MaxEntry) |
1752 #ifdef NLGE_HW_CHKSUM
1753 (1 << O_DESC_PACK_CTRL__PrePadEnable) |
1755 (MAX_FRAME_SIZE << O_DESC_PACK_CTRL__RegularSize));
1756 NLGE_WRITE(base, R_STATCTRL, ((1 << O_STATCTRL__Sten) |
1757 (1 << O_STATCTRL__ClrCnt)));
1758 NLGE_WRITE(base, R_L2ALLOCCTRL, 0xffffffff);
1759 NLGE_WRITE(base, R_INTMASK, 0);
1760 nlge_set_mac_addr(sc);
1761 nlge_media_specific_init(sc);
1765 nlge_sc_init(struct nlge_softc *sc, device_t dev,
1766 struct xlr_gmac_port *port_info)
1768 memset(sc, 0, sizeof(*sc));
1770 sc->id = device_get_unit(dev);
1771 nlge_set_port_attribs(sc, port_info);
1775 nlge_media_specific_init(struct nlge_softc *sc)
1777 struct mii_data *media;
1778 struct bucket_size *bucket_sizes;
1780 bucket_sizes = xlr_board_info.bucket_sizes;
1781 switch (sc->port_type) {
1785 NLGE_UPDATE(sc->base, R_DESC_PACK_CTRL,
1786 (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset),
1787 (W_DESC_PACK_CTRL__ByteOffset <<
1788 O_DESC_PACK_CTRL__ByteOffset));
1789 NLGE_WRITE(sc->base, R_GMAC_TX0_BUCKET_SIZE + sc->instance,
1790 bucket_sizes->bucket[sc->tx_bucket_id]);
1791 if (sc->port_type != XLR_XAUI) {
1792 nlge_gmac_config_speed(sc, 1);
1794 media = (struct mii_data *)device_get_softc(
1801 NLGE_WRITE(sc->base, R_BYTEOFFSET0, 0x2);
1802 NLGE_WRITE(sc->base, R_XGMACPADCALIBRATION, 0x30);
1803 NLGE_WRITE(sc->base, R_XGS_TX0_BUCKET_SIZE,
1804 bucket_sizes->bucket[sc->tx_bucket_id]);
1812 * Read the MAC address from the XLR boot registers. All port addresses
1813 * are identical except for the lowest octet.
1816 nlge_read_mac_addr(struct nlge_softc *sc)
1820 for (i = 0, j = 40; i < ETHER_ADDR_LEN && j >= 0; i++, j-= 8)
1821 sc->dev_addr[i] = (xlr_boot1_info.mac_addr >> j) & 0xff;
1823 sc->dev_addr[i - 1] += sc->id; /* last octet is port-specific */
1827 * Write the MAC address to the XLR MAC port. Also, set the address
1828 * masks and MAC filter configuration.
1831 nlge_set_mac_addr(struct nlge_softc *sc)
1833 NLGE_WRITE(sc->base, R_MAC_ADDR0,
1834 ((sc->dev_addr[5] << 24) | (sc->dev_addr[4] << 16) |
1835 (sc->dev_addr[3] << 8) | (sc->dev_addr[2])));
1836 NLGE_WRITE(sc->base, R_MAC_ADDR0 + 1,
1837 ((sc->dev_addr[1] << 24) | (sc-> dev_addr[0] << 16)));
1839 NLGE_WRITE(sc->base, R_MAC_ADDR_MASK2, 0xffffffff);
1840 NLGE_WRITE(sc->base, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
1841 NLGE_WRITE(sc->base, R_MAC_ADDR_MASK3, 0xffffffff);
1842 NLGE_WRITE(sc->base, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
1844 NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG,
1845 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
1846 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
1847 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
1849 if (sc->port_type == XLR_RGMII || sc->port_type == XLR_SGMII) {
1850 NLGE_UPDATE(sc->base, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
1855 nlge_if_init(struct nlge_softc *sc)
1863 NLGE_LOCK_INIT(sc, device_get_nameunit(dev));
1865 ifp = sc->nlge_if = if_alloc(IFT_ETHER);
1867 device_printf(dev, "can not if_alloc()\n");
1872 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1873 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1874 ifp->if_capabilities = 0;
1875 ifp->if_capenable = ifp->if_capabilities;
1876 ifp->if_ioctl = nlge_ioctl;
1877 ifp->if_init = nlge_init;
1878 ifp->if_hwassist = 0;
1879 ifp->if_snd.ifq_drv_maxlen = RGE_TX_Q_SIZE;
1880 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1881 IFQ_SET_READY(&ifp->if_snd);
1883 ifmedia_init(&sc->nlge_mii.mii_media, 0, nlge_mediachange,
1885 ifmedia_add(&sc->nlge_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL);
1886 ifmedia_set(&sc->nlge_mii.mii_media, IFM_ETHER | IFM_AUTO);
1887 sc->nlge_mii.mii_media.ifm_media = sc->nlge_mii.mii_media.ifm_cur->ifm_media;
1888 nlge_read_mac_addr(sc);
1890 ether_ifattach(ifp, sc->dev_addr);
1892 /* override if_transmit : per ifnet(9), do it after if_attach */
1893 ifp->if_transmit = nlge_tx;
1900 nlge_mii_init(device_t dev, struct nlge_softc *sc)
1904 if (sc->port_type != XLR_XAUI && sc->port_type != XLR_XGMII) {
1905 NLGE_WRITE(sc->mii_base, R_MII_MGMT_CONFIG, 0x07);
1907 error = mii_attach(dev, &sc->mii_bus, sc->nlge_if, nlge_mediachange,
1908 nlge_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, MII_OFFSET_ANY,
1911 device_printf(dev, "attaching PHYs failed\n");
1914 if (sc->mii_bus != NULL) {
1916 * Enable all MDIO interrupts in the phy. RX_ER bit seems to get
1917 * set about every 1 sec in GigE mode, ignore it for now...
1919 nlge_mii_write_internal(sc->mii_base, sc->phy_addr, 25,
1925 * Read a PHY register.
1928 * mii_base - Base address of MII
1929 * phyaddr - PHY's address
1930 * regidx = index of register to read
1933 * value read, or 0 if an error occurred.
1937 nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr, int regidx)
1941 /* setup the phy reg to be used */
1942 NLGE_WRITE(mii_base, R_MII_MGMT_ADDRESS,
1943 (phyaddr << 8) | (regidx << 0));
1944 /* Issue the read command */
1945 NLGE_WRITE(mii_base, R_MII_MGMT_COMMAND,
1946 (1 << O_MII_MGMT_COMMAND__rstat));
1948 /* poll for the read cycle to complete */
1949 for (i = 0; i < PHY_STATUS_RETRIES; i++) {
1950 if (NLGE_READ(mii_base, R_MII_MGMT_INDICATORS) == 0)
1954 /* clear the read cycle */
1955 NLGE_WRITE(mii_base, R_MII_MGMT_COMMAND, 0);
1957 if (i == PHY_STATUS_RETRIES) {
1958 return (0xffffffff);
1961 val = NLGE_READ(mii_base, R_MII_MGMT_STATUS);
1967 * Write a value to a PHY register.
1970 * mii_base - Base address of MII
1971 * phyaddr - PHY to use
1972 * regidx - register within the PHY
1973 * regval - data to write to register
1979 nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr, int regidx,
1984 NLGE_WRITE(mii_base, R_MII_MGMT_ADDRESS,
1985 (phyaddr << 8) | (regidx << 0));
1987 /* Write the data which starts the write cycle */
1988 NLGE_WRITE(mii_base, R_MII_MGMT_WRITE_DATA, regval);
1990 /* poll for the write cycle to complete */
1991 for (i = 0; i < PHY_STATUS_RETRIES; i++) {
1992 if (NLGE_READ(mii_base, R_MII_MGMT_INDICATORS) == 0)
1998 * Function to optimize the use of p2d descriptors for the given PDU.
1999 * As it is on the fast-path (called during packet transmission), it
2000 * described in more detail than the initialization functions.
2002 * Input: mbuf chain (MC), pointer to fmn message
2003 * Input constraints: None
2004 * Output: FMN message to transmit the data in MC
2005 * Return values: 0 - success
2006 * 1 - MC cannot be handled (see Limitations below)
2007 * 2 - MC cannot be handled presently (maybe worth re-trying)
2008 * Other output: Number of entries filled in the FMN message
2010 * Output structure/constraints:
2011 * 1. Max 3 p2d's + 1 zero-len (ZL) p2d with virtual address of MC.
2012 * 2. 3 p2d's + 1 p2p with max 14 p2d's (ZL p2d not required in this case).
2013 * 3. Each p2d points to physically contiguous chunk of data (subject to
2014 * entire MC requiring max 17 p2d's).
2016 * 1. MC's that require more than 17 p2d's are not handled.
2017 * Benefits: MC's that require <= 3 p2d's avoid the overhead of allocating
2018 * the p2p structure. Small packets (which typically give low
2019 * performance) are expected to have a small MC that takes
2020 * advantage of this.
2023 prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
2024 uint32_t *n_entries, struct mbuf *mbuf_chain, uint64_t fb_stn_id,
2025 struct nlge_tx_desc **tx_desc)
2028 struct nlge_tx_desc *p2p;
2033 int msg_sz, p2p_sz, len, frag_sz;
2034 /* Num entries per FMN msg is 4 for XLR/XLS */
2035 const int FMN_SZ = sizeof(*fmn_msg) / sizeof(uint64_t);
2037 msg_sz = p2p_sz = 0;
2039 cur_p2d = &fmn_msg->msg0;
2041 for (m = mbuf_chain; m != NULL; m = m->m_next) {
2042 buf = (vm_offset_t) m->m_data;
2046 if (msg_sz == (FMN_SZ - 1)) {
2047 p2p = uma_zalloc(nl_tx_desc_zone, M_NOWAIT);
2052 * Save the virtual address in the descriptor,
2053 * it makes freeing easy.
2055 p2p->frag[XLR_MAX_TX_FRAGS] =
2056 (uint64_t)(vm_offset_t)p2p;
2057 cur_p2d = &p2p->frag[0];
2058 } else if (msg_sz == (FMN_SZ - 2 + XLR_MAX_TX_FRAGS)) {
2059 uma_zfree(nl_tx_desc_zone, p2p);
2062 paddr = vtophys(buf);
2063 frag_sz = PAGE_SIZE - (buf & PAGE_MASK);
2066 *cur_p2d++ = (127ULL << 54) | ((uint64_t)frag_sz << 40)
2077 printf("Zero-length mbuf chain ??\n");
2078 *n_entries = msg_sz ;
2082 /* set eop in most-recent p2d */
2083 cur_p2d[-1] |= (1ULL << 63);
2087 * On n64, we cannot store our mbuf pointer(64 bit) in the freeback
2088 * message (40bit available), so we put the mbuf in m_nextpkt and
2089 * use the physical addr of that in freeback message.
2091 mbuf_chain->m_nextpkt = mbuf_chain;
2092 fbpaddr = vtophys(&mbuf_chain->m_nextpkt);
2094 /* Careful, don't sign extend when going to 64bit */
2095 fbpaddr = (uint64_t)(uintptr_t)mbuf_chain;
2097 *cur_p2d = (1ULL << 63) | ((uint64_t)fb_stn_id << 54) | fbpaddr;
2101 paddr = vtophys(p2p);
2103 fmn_msg->msg3 = (1ULL << 62) | ((uint64_t)fb_stn_id << 54) |
2104 ((uint64_t)(p2p_sz * 8) << 40) | paddr;
2105 *n_entries = FMN_SZ;
2107 *n_entries = msg_sz + 1;
2114 send_fmn_msg_tx(struct nlge_softc *sc, struct msgrng_msg *msg,
2117 uint32_t msgrng_flags;
2122 msgrng_flags = msgrng_access_enable();
2123 ret = message_send(n_entries, MSGRNG_CODE_MAC,
2124 sc->tx_bucket_id, msg);
2125 msgrng_restore(msgrng_flags);
2129 } while (i < 100000);
2131 device_printf(sc->nlge_dev, "Too many credit fails in tx path\n");
2137 release_tx_desc(vm_paddr_t paddr)
2139 struct nlge_tx_desc *tx_desc;
2143 paddr += (XLR_MAX_TX_FRAGS * sizeof(uint64_t));
2144 sr = xlr_enable_kx();
2145 vaddr = xlr_paddr_ld(paddr);
2148 tx_desc = (struct nlge_tx_desc*)(intptr_t)vaddr;
2149 uma_zfree(nl_tx_desc_zone, tx_desc);
2158 vm_paddr_t temp1, temp2;
2161 if ((m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR)) == NULL)
2163 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2164 m_adj(m_new, XLR_CACHELINE_SIZE - ((uintptr_t)m_new->m_data & 0x1f));
2165 md = (uint64_t *)m_new->m_data;
2166 md[0] = (intptr_t)m_new; /* Back Ptr */
2168 m_adj(m_new, XLR_CACHELINE_SIZE);
2171 temp1 = vtophys((vm_offset_t) m_new->m_data);
2172 temp2 = vtophys((vm_offset_t) m_new->m_data + 1536);
2173 if ((temp1 + 1536) != temp2)
2174 panic("ALLOCED BUFFER IS NOT CONTIGUOUS\n");
2177 return ((void *)m_new->m_data);
2181 nlge_gmac_config_speed(struct nlge_softc *sc, int quick)
2183 struct mii_data *md;
2185 int bmsr, n_tries, max_tries;
2186 int core_ctl[] = { 0x2, 0x1, 0x0, 0x1 };
2187 int sgmii_speed[] = { SGMII_SPEED_10,
2190 SGMII_SPEED_100 }; /* default to 100Mbps */
2191 char *speed_str[] = { "10",
2194 "unknown, defaulting to 100" };
2195 int link_state = LINK_STATE_DOWN;
2197 if (sc->port_type == XLR_XAUI || sc->port_type == XLR_XGMII)
2202 if (sc->mii_base != NULL) {
2203 max_tries = (quick == 1) ? 100 : 4000;
2205 for (n_tries = 0; n_tries < max_tries; n_tries++) {
2206 bmsr = nlge_mii_read_internal(sc->mii_base,
2207 sc->phy_addr, MII_BMSR);
2208 if ((bmsr & BMSR_ACOMP) && (bmsr & BMSR_LINK))
2209 break; /* Auto-negotiation is complete
2214 sc->link = (bmsr == 0) ? xlr_mac_link_down : xlr_mac_link_up;
2215 sc->speed = nlge_mii_read_internal(sc->mii_base, sc->phy_addr, 28);
2216 sc->speed = (sc->speed >> 3) & 0x03;
2217 if (sc->link == xlr_mac_link_up) {
2218 link_state = LINK_STATE_UP;
2219 nlge_sgmii_init(sc);
2222 md = (struct mii_data *)device_get_softc(sc->mii_bus);
2225 if (sc->port_type != XLR_RGMII)
2226 NLGE_WRITE(mmio, R_INTERFACE_CONTROL, sgmii_speed[sc->speed]);
2227 if (sc->speed == xlr_mac_speed_10 || sc->speed == xlr_mac_speed_100 ||
2228 sc->speed == xlr_mac_speed_rsvd) {
2229 NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7117);
2230 } else if (sc->speed == xlr_mac_speed_1000) {
2231 NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7217);
2233 ifmedia_set(&md->mii_media, IFM_MAKEWORD(IFM_ETHER,
2234 IFM_1000_T, IFM_FDX, md->mii_instance));
2237 NLGE_WRITE(mmio, R_CORECONTROL, core_ctl[sc->speed]);
2238 if_link_state_change(sc->nlge_if, link_state);
2239 printf("%s: [%sMbps]\n", device_get_nameunit(sc->nlge_dev),
2240 speed_str[sc->speed]);
2246 * This function is called for each port that was added to the device tree
2247 * and it initializes the following port attributes:
2249 * - base (base address to access port-specific registers)
2254 nlge_set_port_attribs(struct nlge_softc *sc,
2255 struct xlr_gmac_port *port_info)
2257 sc->instance = port_info->instance % 4; /* TBD: will not work for SPI-4 */
2258 sc->port_type = port_info->type;
2259 sc->base = xlr_io_mmio(port_info->base_addr);
2260 sc->mii_base = xlr_io_mmio(port_info->mii_addr);
2261 if (port_info->pcs_addr != 0)
2262 sc->pcs_addr = xlr_io_mmio(port_info->pcs_addr);
2263 if (port_info->serdes_addr != 0)
2264 sc->serdes_addr = xlr_io_mmio(port_info->serdes_addr);
2265 sc->phy_addr = port_info->phy_addr;
2267 PDEBUG("Port%d: base=%p, mii_base=%p, phy_addr=%d\n", sc->id, sc->base,
2268 sc->mii_base, sc->phy_addr);
2271 /* ------------------------------------------------------------------------ */
2273 /* Debug dump functions */
2278 dump_reg(xlr_reg_t *base, uint32_t offset, char *name)
2282 val = NLGE_READ(base, offset);
2283 printf("%-30s: 0x%8x 0x%8x\n", name, offset, val);
2286 #define STRINGIFY(x) #x
2289 dump_na_registers(xlr_reg_t *base_addr, int port_id)
2291 PDEBUG("Register dump for NA (of port=%d)\n", port_id);
2292 dump_reg(base_addr, R_PARSERCONFIGREG, STRINGIFY(R_PARSERCONFIGREG));
2293 PDEBUG("Tx bucket sizes\n");
2294 dump_reg(base_addr, R_GMAC_JFR0_BUCKET_SIZE,
2295 STRINGIFY(R_GMAC_JFR0_BUCKET_SIZE));
2296 dump_reg(base_addr, R_GMAC_RFR0_BUCKET_SIZE,
2297 STRINGIFY(R_GMAC_RFR0_BUCKET_SIZE));
2298 dump_reg(base_addr, R_GMAC_TX0_BUCKET_SIZE,
2299 STRINGIFY(R_GMAC_TX0_BUCKET_SIZE));
2300 dump_reg(base_addr, R_GMAC_TX1_BUCKET_SIZE,
2301 STRINGIFY(R_GMAC_TX1_BUCKET_SIZE));
2302 dump_reg(base_addr, R_GMAC_TX2_BUCKET_SIZE,
2303 STRINGIFY(R_GMAC_TX2_BUCKET_SIZE));
2304 dump_reg(base_addr, R_GMAC_TX3_BUCKET_SIZE,
2305 STRINGIFY(R_GMAC_TX3_BUCKET_SIZE));
2306 dump_reg(base_addr, R_GMAC_JFR1_BUCKET_SIZE,
2307 STRINGIFY(R_GMAC_JFR1_BUCKET_SIZE));
2308 dump_reg(base_addr, R_GMAC_RFR1_BUCKET_SIZE,
2309 STRINGIFY(R_GMAC_RFR1_BUCKET_SIZE));
2310 dump_reg(base_addr, R_TXDATAFIFO0, STRINGIFY(R_TXDATAFIFO0));
2311 dump_reg(base_addr, R_TXDATAFIFO1, STRINGIFY(R_TXDATAFIFO1));
2315 dump_gmac_registers(struct nlge_softc *sc)
2317 xlr_reg_t *base_addr = sc->base;
2318 int port_id = sc->instance;
2320 PDEBUG("Register dump for port=%d\n", port_id);
2321 if (sc->port_type == XLR_RGMII || sc->port_type == XLR_SGMII) {
2322 dump_reg(base_addr, R_MAC_CONFIG_1, STRINGIFY(R_MAC_CONFIG_1));
2323 dump_reg(base_addr, R_MAC_CONFIG_2, STRINGIFY(R_MAC_CONFIG_2));
2324 dump_reg(base_addr, R_IPG_IFG, STRINGIFY(R_IPG_IFG));
2325 dump_reg(base_addr, R_HALF_DUPLEX, STRINGIFY(R_HALF_DUPLEX));
2326 dump_reg(base_addr, R_MAXIMUM_FRAME_LENGTH,
2327 STRINGIFY(R_MAXIMUM_FRAME_LENGTH));
2328 dump_reg(base_addr, R_TEST, STRINGIFY(R_TEST));
2329 dump_reg(base_addr, R_MII_MGMT_CONFIG,
2330 STRINGIFY(R_MII_MGMT_CONFIG));
2331 dump_reg(base_addr, R_MII_MGMT_COMMAND,
2332 STRINGIFY(R_MII_MGMT_COMMAND));
2333 dump_reg(base_addr, R_MII_MGMT_ADDRESS,
2334 STRINGIFY(R_MII_MGMT_ADDRESS));
2335 dump_reg(base_addr, R_MII_MGMT_WRITE_DATA,
2336 STRINGIFY(R_MII_MGMT_WRITE_DATA));
2337 dump_reg(base_addr, R_MII_MGMT_STATUS,
2338 STRINGIFY(R_MII_MGMT_STATUS));
2339 dump_reg(base_addr, R_MII_MGMT_INDICATORS,
2340 STRINGIFY(R_MII_MGMT_INDICATORS));
2341 dump_reg(base_addr, R_INTERFACE_CONTROL,
2342 STRINGIFY(R_INTERFACE_CONTROL));
2343 dump_reg(base_addr, R_INTERFACE_STATUS,
2344 STRINGIFY(R_INTERFACE_STATUS));
2345 } else if (sc->port_type == XLR_XAUI || sc->port_type == XLR_XGMII) {
2346 dump_reg(base_addr, R_XGMAC_CONFIG_0,
2347 STRINGIFY(R_XGMAC_CONFIG_0));
2348 dump_reg(base_addr, R_XGMAC_CONFIG_1,
2349 STRINGIFY(R_XGMAC_CONFIG_1));
2350 dump_reg(base_addr, R_XGMAC_CONFIG_2,
2351 STRINGIFY(R_XGMAC_CONFIG_2));
2352 dump_reg(base_addr, R_XGMAC_CONFIG_3,
2353 STRINGIFY(R_XGMAC_CONFIG_3));
2354 dump_reg(base_addr, R_XGMAC_STATION_ADDRESS_LS,
2355 STRINGIFY(R_XGMAC_STATION_ADDRESS_LS));
2356 dump_reg(base_addr, R_XGMAC_STATION_ADDRESS_MS,
2357 STRINGIFY(R_XGMAC_STATION_ADDRESS_MS));
2358 dump_reg(base_addr, R_XGMAC_MAX_FRAME_LEN,
2359 STRINGIFY(R_XGMAC_MAX_FRAME_LEN));
2360 dump_reg(base_addr, R_XGMAC_REV_LEVEL,
2361 STRINGIFY(R_XGMAC_REV_LEVEL));
2362 dump_reg(base_addr, R_XGMAC_MIIM_COMMAND,
2363 STRINGIFY(R_XGMAC_MIIM_COMMAND));
2364 dump_reg(base_addr, R_XGMAC_MIIM_FILED,
2365 STRINGIFY(R_XGMAC_MIIM_FILED));
2366 dump_reg(base_addr, R_XGMAC_MIIM_CONFIG,
2367 STRINGIFY(R_XGMAC_MIIM_CONFIG));
2368 dump_reg(base_addr, R_XGMAC_MIIM_LINK_FAIL_VECTOR,
2369 STRINGIFY(R_XGMAC_MIIM_LINK_FAIL_VECTOR));
2370 dump_reg(base_addr, R_XGMAC_MIIM_INDICATOR,
2371 STRINGIFY(R_XGMAC_MIIM_INDICATOR));
2374 dump_reg(base_addr, R_MAC_ADDR0, STRINGIFY(R_MAC_ADDR0));
2375 dump_reg(base_addr, R_MAC_ADDR0 + 1, STRINGIFY(R_MAC_ADDR0+1));
2376 dump_reg(base_addr, R_MAC_ADDR1, STRINGIFY(R_MAC_ADDR1));
2377 dump_reg(base_addr, R_MAC_ADDR2, STRINGIFY(R_MAC_ADDR2));
2378 dump_reg(base_addr, R_MAC_ADDR3, STRINGIFY(R_MAC_ADDR3));
2379 dump_reg(base_addr, R_MAC_ADDR_MASK2, STRINGIFY(R_MAC_ADDR_MASK2));
2380 dump_reg(base_addr, R_MAC_ADDR_MASK3, STRINGIFY(R_MAC_ADDR_MASK3));
2381 dump_reg(base_addr, R_MAC_FILTER_CONFIG, STRINGIFY(R_MAC_FILTER_CONFIG));
2382 dump_reg(base_addr, R_TX_CONTROL, STRINGIFY(R_TX_CONTROL));
2383 dump_reg(base_addr, R_RX_CONTROL, STRINGIFY(R_RX_CONTROL));
2384 dump_reg(base_addr, R_DESC_PACK_CTRL, STRINGIFY(R_DESC_PACK_CTRL));
2385 dump_reg(base_addr, R_STATCTRL, STRINGIFY(R_STATCTRL));
2386 dump_reg(base_addr, R_L2ALLOCCTRL, STRINGIFY(R_L2ALLOCCTRL));
2387 dump_reg(base_addr, R_INTMASK, STRINGIFY(R_INTMASK));
2388 dump_reg(base_addr, R_INTREG, STRINGIFY(R_INTREG));
2389 dump_reg(base_addr, R_TXRETRY, STRINGIFY(R_TXRETRY));
2390 dump_reg(base_addr, R_CORECONTROL, STRINGIFY(R_CORECONTROL));
2391 dump_reg(base_addr, R_BYTEOFFSET0, STRINGIFY(R_BYTEOFFSET0));
2392 dump_reg(base_addr, R_BYTEOFFSET1, STRINGIFY(R_BYTEOFFSET1));
2393 dump_reg(base_addr, R_L2TYPE_0, STRINGIFY(R_L2TYPE_0));
2394 dump_na_registers(base_addr, port_id);
2398 dump_fmn_cpu_credits_for_gmac(struct xlr_board_info *board, int gmac_id)
2401 int gmac_bucket_ids[] = { 97, 98, 99, 100, 101, 103 };
2405 n_gmac_buckets = sizeof (gmac_bucket_ids) / sizeof (gmac_bucket_ids[0]);
2406 for (j = 0; j < 8; j++) { // for each cpu
2407 cc = board->credit_configs[j];
2408 printf("Credits for Station CPU_%d ---> GMAC buckets (tx path)\n", j);
2409 for (k = 0; k < n_gmac_buckets; k++) {
2410 r = gmac_bucket_ids[k] / 8;
2411 c = gmac_bucket_ids[k] % 8;
2412 printf (" --> gmac%d_bucket_%-3d: credits=%d\n", gmac_id,
2413 gmac_bucket_ids[k], cc->counters[r][c]);
2419 dump_fmn_gmac_credits(struct xlr_board_info *board, int gmac_id)
2424 cc = board->gmac_block[gmac_id].credit_config;
2425 printf("Credits for Station: GMAC_%d ---> CPU buckets (rx path)\n", gmac_id);
2426 for (j = 0; j < 8; j++) { // for each cpu
2427 printf(" ---> cpu_%d\n", j);
2428 for (k = 0; k < 8; k++) { // for each bucket in cpu
2429 printf(" ---> bucket_%d: credits=%d\n", j * 8 + k,
2430 cc->counters[j][k]);
2436 dump_board_info(struct xlr_board_info *board)
2438 struct xlr_gmac_block_t *gm;
2441 printf("cpu=%x ", xlr_revision());
2442 printf("board_version: major=%llx, minor=%llx\n",
2443 xlr_boot1_info.board_major_version,
2444 xlr_boot1_info.board_minor_version);
2445 printf("is_xls=%d, nr_cpus=%d, usb=%s, cfi=%s, ata=%s\npci_irq=%d,"
2446 "gmac_ports=%d\n", board->is_xls, board->nr_cpus,
2447 board->usb ? "Yes" : "No", board->cfi ? "Yes": "No",
2448 board->ata ? "Yes" : "No", board->pci_irq, board->gmacports);
2449 printf("FMN: Core-station bucket sizes\n");
2450 for (i = 0; i < 128; i++) {
2451 if (i && ((i % 16) == 0))
2453 printf ("b[%d] = %d ", i, board->bucket_sizes->bucket[i]);
2456 for (i = 0; i < 3; i++) {
2457 gm = &board->gmac_block[i];
2458 printf("RNA_%d: type=%d, enabled=%s, mode=%d, station_id=%d,"
2459 "station_txbase=%d, station_rfr=%d ", i, gm->type,
2460 gm->enabled ? "Yes" : "No", gm->mode, gm->station_id,
2461 gm->station_txbase, gm->station_rfr);
2462 printf("n_ports=%d, baseaddr=%p, baseirq=%d, baseinst=%d\n",
2463 gm->num_ports, (xlr_reg_t *)gm->baseaddr, gm->baseirq,
2466 for (k = 0; k < 3; k++) { // for each NA
2467 dump_fmn_cpu_credits_for_gmac(board, k);
2468 dump_fmn_gmac_credits(board, k);
2473 dump_mac_stats(struct nlge_softc *sc)
2476 uint32_t pkts_tx, pkts_rx;
2479 pkts_rx = NLGE_READ(sc->base, R_RPKT);
2480 pkts_tx = NLGE_READ(sc->base, R_TPKT);
2482 printf("[nlge_%d mac stats]: pkts_tx=%u, pkts_rx=%u\n", sc->id, pkts_tx,
2487 /* dump all rx counters. we need this because pkts_rx includes
2489 for (r = R_RFCS; r <= R_ROVR; r++)
2490 printf("[nlge_%d mac stats]: [0x%x]=%u\n", sc->id, r,
2491 NLGE_READ(sc->base, r));
2496 /* dump all tx counters. might be useful for debugging. */
2497 for (r = R_TMCA; r <= R_TFRG; r++) {
2498 if ((r == (R_TNCL + 1)) || (r == (R_TNCL + 2)))
2500 printf("[nlge_%d mac stats]: [0x%x]=%u\n", sc->id, r,
2501 NLGE_READ(sc->base, r));
2508 dump_mii_regs(struct nlge_softc *sc)
2510 uint32_t mii_regs[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
2511 0x8, 0x9, 0xa, 0xf, 0x10, 0x11, 0x12, 0x13,
2512 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
2516 if (sc->mii_base == NULL || sc->mii_bus == NULL)
2519 n_regs = sizeof (mii_regs) / sizeof (mii_regs[0]);
2520 for (i = 0; i < n_regs; i++) {
2521 printf("[mii_0x%x] = %x\n", mii_regs[i],
2522 nlge_mii_read_internal(sc->mii_base, sc->phy_addr,
2528 dump_ifmedia(struct ifmedia *ifm)
2530 printf("ifm_mask=%08x, ifm_media=%08x, cur=%p\n", ifm->ifm_mask,
2531 ifm->ifm_media, ifm->ifm_cur);
2532 if (ifm->ifm_cur != NULL) {
2533 printf("Cur attribs: ifmedia_entry.ifm_media=%08x,"
2534 " ifmedia_entry.ifm_data=%08x\n", ifm->ifm_cur->ifm_media,
2535 ifm->ifm_cur->ifm_data);
2540 dump_mii_data(struct mii_data *mii)
2542 dump_ifmedia(&mii->mii_media);
2543 printf("ifp=%p, mii_instance=%d, mii_media_status=%08x,"
2544 " mii_media_active=%08x\n", mii->mii_ifp, mii->mii_instance,
2545 mii->mii_media_status, mii->mii_media_active);
2549 dump_pcs_regs(struct nlge_softc *sc, int phy)
2553 printf("PCS regs from %p for phy=%d\n", sc->pcs_addr, phy);
2554 for (i = 0; i < 18; i++) {
2555 if (i == 2 || i == 3 || (i >= 9 && i <= 14))
2557 val = nlge_mii_read_internal(sc->pcs_addr, phy, i);
2558 printf("PHY:%d pcs[0x%x] is 0x%x\n", phy, i, val);