2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/if_vlan.h>
39 #include <linux/mlx4/device.h>
40 #include <linux/mlx4/cmd.h>
43 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
44 u64 mac, u64 clear, u8 mode)
46 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
47 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
50 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, u32 *vlans)
52 struct mlx4_cmd_mailbox *mailbox;
53 struct mlx4_set_vlan_fltr_mbox *filter;
57 mailbox = mlx4_alloc_cmd_mailbox(dev);
59 return PTR_ERR(mailbox);
61 filter = mailbox->buf;
62 memset(filter, 0, sizeof *filter);
64 for (i = 0, j = VLAN_FLTR_SIZE - 1; i < VLAN_FLTR_SIZE;
66 filter->entry[j] = cpu_to_be32(vlans[i]);
67 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_VLAN_FLTR,
68 MLX4_CMD_TIME_CLASS_B);
69 mlx4_free_cmd_mailbox(dev, mailbox);
74 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
75 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
77 struct mlx4_cmd_mailbox *mailbox;
78 struct mlx4_set_port_general_context *context;
82 mailbox = mlx4_alloc_cmd_mailbox(dev);
84 return PTR_ERR(mailbox);
85 context = mailbox->buf;
86 memset(context, 0, sizeof *context);
88 context->flags = SET_PORT_GEN_ALL_VALID;
89 context->mtu = cpu_to_be16(mtu);
90 context->pptx = (pptx * (!pfctx)) << 7;
91 context->pfctx = pfctx;
92 context->pprx = (pprx * (!pfcrx)) << 7;
93 context->pfcrx = pfcrx;
95 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
96 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
97 MLX4_CMD_TIME_CLASS_B);
99 mlx4_free_cmd_mailbox(dev, mailbox);
103 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
106 struct mlx4_cmd_mailbox *mailbox;
107 struct mlx4_set_port_rqp_calc_context *context;
111 mailbox = mlx4_alloc_cmd_mailbox(dev);
113 return PTR_ERR(mailbox);
114 context = mailbox->buf;
115 memset(context, 0, sizeof *context);
117 context->base_qpn = cpu_to_be32(base_qpn);
118 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_EN_SHIFT | base_qpn);
119 context->mcast = cpu_to_be32((dev->caps.mc_promisc_mode <<
120 SET_PORT_PROMISC_MODE_SHIFT) | base_qpn);
121 context->intra_no_vlan = 0;
122 context->no_vlan = MLX4_NO_VLAN_IDX;
123 context->intra_vlan_miss = 0;
124 context->vlan_miss = MLX4_VLAN_MISS_IDX;
126 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
127 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
128 MLX4_CMD_TIME_CLASS_B);
130 mlx4_free_cmd_mailbox(dev, mailbox);
134 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
136 struct mlx4_en_query_port_context *qport_context;
137 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
138 struct mlx4_en_port_state *state = &priv->port_state;
139 struct mlx4_cmd_mailbox *mailbox;
142 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
144 return PTR_ERR(mailbox);
145 memset(mailbox->buf, 0, sizeof(*qport_context));
146 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
147 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B);
150 qport_context = mailbox->buf;
152 /* This command is always accessed from Ethtool context
153 * already synchronized, no need in locking */
154 state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
155 switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
156 case MLX4_EN_1G_SPEED:
157 state->link_speed = 1000;
159 case MLX4_EN_10G_SPEED_XAUI:
160 case MLX4_EN_10G_SPEED_XFI:
161 state->link_speed = 10000;
163 case MLX4_EN_40G_SPEED:
164 state->link_speed = 40000;
167 state->link_speed = -1;
170 state->transciver = qport_context->transceiver;
171 if (be32_to_cpu(qport_context->transceiver_code_hi) & 0x400)
172 state->transciver = 0x80;
175 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
179 static int read_iboe_counters(struct mlx4_dev *dev, int index, u64 counters[])
181 struct mlx4_cmd_mailbox *mailbox;
184 struct mlx4_counters_ext *ext;
185 struct mlx4_counters *reg;
187 mailbox = mlx4_alloc_cmd_mailbox(dev);
191 err = mlx4_cmd_box(dev, 0, mailbox->dma, index, 0,
192 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C);
196 mode = be32_to_cpu(((struct mlx4_counters *)mailbox->buf)->counter_mode) & 0xf;
200 counters[0] = be64_to_cpu(reg->rx_frames);
201 counters[1] = be64_to_cpu(reg->tx_frames);
202 counters[2] = be64_to_cpu(reg->rx_bytes);
203 counters[3] = be64_to_cpu(reg->tx_bytes);
207 counters[0] = be64_to_cpu(ext->rx_uni_frames);
208 counters[1] = be64_to_cpu(ext->tx_uni_frames);
209 counters[2] = be64_to_cpu(ext->rx_uni_bytes);
210 counters[3] = be64_to_cpu(ext->tx_uni_bytes);
217 mlx4_free_cmd_mailbox(dev, mailbox);
221 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
223 struct mlx4_en_stat_out_mbox *mlx4_en_stats;
224 struct net_device *dev;
225 struct mlx4_en_priv *priv;
226 struct mlx4_cmd_mailbox *mailbox;
227 u64 in_mod = reset << 8 | port;
228 unsigned long oerror;
229 unsigned long ierror;
235 dev = mdev->pndev[port];
236 priv = netdev_priv(dev);
237 memset(counters, 0, sizeof counters);
238 counter = mlx4_get_iboe_counter(priv->mdev->dev, port);
240 err = read_iboe_counters(priv->mdev->dev, counter, counters);
242 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
244 return PTR_ERR(mailbox);
245 memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
246 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
247 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
251 mlx4_en_stats = mailbox->buf;
253 spin_lock(&priv->stats_lock);
256 dev->if_ipackets = counters[0];
257 dev->if_ibytes = counters[2];
258 for (i = 0; i < priv->rx_ring_num; i++) {
259 dev->if_ipackets += priv->rx_ring[i].packets;
260 dev->if_ibytes += priv->rx_ring[i].bytes;
261 ierror += priv->rx_ring[i].errors;
263 dev->if_opackets = counters[1];
264 dev->if_obytes = counters[3];
265 for (i = 0; i <= priv->tx_ring_num; i++) {
266 dev->if_opackets += priv->tx_ring[i].packets;
267 dev->if_obytes += priv->tx_ring[i].bytes;
268 oerror += priv->tx_ring[i].errors;
271 dev->if_ierrors = be32_to_cpu(mlx4_en_stats->RDROP) + ierror;
272 dev->if_oerrors = be32_to_cpu(mlx4_en_stats->TDROP) + oerror;
273 dev->if_imcasts = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
274 be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
275 be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
276 be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
277 be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
278 be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
279 be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
280 be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
281 be64_to_cpu(mlx4_en_stats->MCAST_novlan);
282 dev->if_omcasts = be64_to_cpu(mlx4_en_stats->TMCAST_prio_0) +
283 be64_to_cpu(mlx4_en_stats->TMCAST_prio_1) +
284 be64_to_cpu(mlx4_en_stats->TMCAST_prio_2) +
285 be64_to_cpu(mlx4_en_stats->TMCAST_prio_3) +
286 be64_to_cpu(mlx4_en_stats->TMCAST_prio_4) +
287 be64_to_cpu(mlx4_en_stats->TMCAST_prio_5) +
288 be64_to_cpu(mlx4_en_stats->TMCAST_prio_6) +
289 be64_to_cpu(mlx4_en_stats->TMCAST_prio_7) +
290 be64_to_cpu(mlx4_en_stats->TMCAST_novlan);
291 dev->if_collisions = 0;
293 priv->pkstats.broadcast =
294 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
295 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
296 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
297 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
298 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
299 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
300 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
301 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
302 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
303 priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
304 priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
305 priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
306 priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
307 priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
308 priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
309 priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
310 priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
311 priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
312 priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
313 priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
314 priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
315 priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
316 priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
317 priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
318 priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
319 spin_unlock(&priv->stats_lock);
322 mlx4_free_cmd_mailbox(mdev->dev, mailbox);