2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/io-mapping.h>
43 #include <linux/mlx4/device.h>
44 #include <linux/mlx4/doorbell.h>
50 MODULE_AUTHOR("Roland Dreier");
51 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
52 MODULE_LICENSE("Dual BSD/GPL");
53 MODULE_VERSION(DRV_VERSION);
55 struct workqueue_struct *mlx4_wq;
57 #ifdef CONFIG_MLX4_DEBUG
59 int mlx4_debug_level = 0;
60 module_param_named(debug_level, mlx4_debug_level, int, 0644);
61 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
63 #endif /* CONFIG_MLX4_DEBUG */
66 module_param_named(block_loopback, mlx4_blck_lb, int, 0644);
67 MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0");
72 module_param(msi_x, int, 0444);
73 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
75 #else /* CONFIG_PCI_MSI */
79 #endif /* CONFIG_PCI_MSI */
81 static char mlx4_version[] __devinitdata =
82 DRV_NAME ": Mellanox ConnectX core driver v"
83 DRV_VERSION " (" DRV_RELDATE ")\n";
85 struct mutex drv_mutex;
87 static struct mlx4_profile default_profile = {
90 .rdmarc_per_qp = 1 << 4,
97 static int log_num_mac = 2;
98 module_param_named(log_num_mac, log_num_mac, int, 0444);
99 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
102 module_param_named(use_prio, use_prio, bool, 0444);
103 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
106 static struct mlx4_profile mod_param_profile = { 0 };
108 module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444);
109 MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA");
111 module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444);
112 MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA");
114 module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int, 0444);
115 MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP");
117 module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444);
118 MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA");
120 module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444);
121 MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA");
123 module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444);
124 MODULE_PARM_DESC(log_num_mpt,
125 "log maximum number of memory protection table entries per HCA");
127 module_param_named(log_num_mtt, mod_param_profile.num_mtt, int, 0444);
128 MODULE_PARM_DESC(log_num_mtt,
129 "log maximum number of memory translation table segments per HCA");
131 static int log_mtts_per_seg = 0;
132 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
133 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
135 static void process_mod_param_profile(void)
137 default_profile.num_qp = (mod_param_profile.num_qp ?
138 1 << mod_param_profile.num_qp :
139 default_profile.num_qp);
140 default_profile.num_srq = (mod_param_profile.num_srq ?
141 1 << mod_param_profile.num_srq :
142 default_profile.num_srq);
143 default_profile.rdmarc_per_qp = (mod_param_profile.rdmarc_per_qp ?
144 1 << mod_param_profile.rdmarc_per_qp :
145 default_profile.rdmarc_per_qp);
146 default_profile.num_cq = (mod_param_profile.num_cq ?
147 1 << mod_param_profile.num_cq :
148 default_profile.num_cq);
149 default_profile.num_mcg = (mod_param_profile.num_mcg ?
150 1 << mod_param_profile.num_mcg :
151 default_profile.num_mcg);
152 default_profile.num_mpt = (mod_param_profile.num_mpt ?
153 1 << mod_param_profile.num_mpt :
154 default_profile.num_mpt);
155 default_profile.num_mtt = (mod_param_profile.num_mtt ?
156 1 << mod_param_profile.num_mtt :
157 default_profile.num_mtt);
160 struct mlx4_port_config
162 struct list_head list;
163 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
164 struct pci_dev *pdev;
166 static LIST_HEAD(config_list);
168 static void mlx4_config_cleanup(void)
170 struct mlx4_port_config *config, *tmp;
172 list_for_each_entry_safe(config, tmp, &config_list, list) {
173 list_del(&config->list);
178 void *mlx4_get_prot_dev(struct mlx4_dev *dev, enum mlx4_prot proto, int port)
180 return mlx4_find_get_prot_dev(dev, proto, port);
182 EXPORT_SYMBOL(mlx4_get_prot_dev);
184 void mlx4_set_iboe_counter(struct mlx4_dev *dev, int index, u8 port)
186 struct mlx4_priv *priv = mlx4_priv(dev);
188 priv->iboe_counter_index[port - 1] = index;
190 EXPORT_SYMBOL(mlx4_set_iboe_counter);
192 int mlx4_get_iboe_counter(struct mlx4_dev *dev, u8 port)
194 struct mlx4_priv *priv = mlx4_priv(dev);
196 return priv->iboe_counter_index[port - 1];
198 EXPORT_SYMBOL(mlx4_get_iboe_counter);
200 int mlx4_check_port_params(struct mlx4_dev *dev,
201 enum mlx4_port_type *port_type)
205 for (i = 0; i < dev->caps.num_ports - 1; i++) {
206 if (port_type[i] != port_type[i + 1]) {
207 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
208 mlx4_err(dev, "Only same port types supported "
209 "on this HCA, aborting.\n");
215 for (i = 0; i < dev->caps.num_ports; i++) {
216 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
217 mlx4_err(dev, "Requested port type for port %d is not "
218 "supported on this HCA\n", i + 1);
225 static void mlx4_set_port_mask(struct mlx4_dev *dev)
229 for (i = 1; i <= dev->caps.num_ports; ++i)
230 dev->caps.port_mask[i] = dev->caps.port_type[i];
233 static u8 get_counters_mode(u64 flags)
235 switch (flags >> 48 & 3) {
238 return MLX4_CUNTERS_EXT;
240 return MLX4_CUNTERS_BASIC;
242 return MLX4_CUNTERS_DISABLED;
246 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
251 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
253 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
257 if (dev_cap->min_page_sz > PAGE_SIZE) {
258 mlx4_err(dev, "HCA minimum page size of %d bigger than "
259 "kernel PAGE_SIZE of %d, aborting.\n",
260 dev_cap->min_page_sz, PAGE_SIZE);
263 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
264 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
266 dev_cap->num_ports, MLX4_MAX_PORTS);
270 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
271 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
272 "PCI resource 2 size of 0x%llx, aborting.\n",
274 (unsigned long long) pci_resource_len(dev->pdev, 2));
278 dev->caps.num_ports = dev_cap->num_ports;
279 for (i = 1; i <= dev->caps.num_ports; ++i) {
280 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
281 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
282 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
283 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
284 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
285 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
286 dev->caps.def_mac[i] = dev_cap->def_mac[i];
287 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
288 dev->caps.trans_type[i] = dev_cap->trans_type[i];
289 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
290 dev->caps.wavelength[i] = dev_cap->wavelength[i];
291 dev->caps.trans_code[i] = dev_cap->trans_code[i];
294 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
295 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
296 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
297 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
298 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
299 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
300 dev->caps.max_wqes = dev_cap->max_qp_sz;
301 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
302 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
303 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
304 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
305 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
306 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
307 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
309 * Subtract 1 from the limit because we need to allocate a
310 * spare CQE so the HCA HW can tell the difference between an
311 * empty CQ and a full CQ.
313 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
314 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
315 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
316 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
317 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
318 dev->caps.mtts_per_seg);
319 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
320 dev->caps.reserved_uars = dev_cap->reserved_uars;
321 dev->caps.reserved_pds = dev_cap->reserved_pds;
322 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
323 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
324 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
325 dev->caps.flags = dev_cap->flags;
326 dev->caps.bmme_flags = dev_cap->bmme_flags;
327 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
328 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
329 dev->caps.udp_rss = dev_cap->udp_rss;
330 dev->caps.loopback_support = dev_cap->loopback_support;
331 dev->caps.wol = dev_cap->wol;
332 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
333 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
334 dev_cap->reserved_xrcds : 0;
335 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
336 dev_cap->max_xrcds : 0;
338 dev->caps.log_num_macs = log_num_mac;
339 dev->caps.log_num_prios = use_prio ? 3 : 0;
341 for (i = 1; i <= dev->caps.num_ports; ++i) {
342 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
343 if (dev->caps.supported_type[i]) {
344 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
345 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
347 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
349 dev->caps.possible_type[i] = dev->caps.port_type[i];
350 mlx4_priv(dev)->sense.sense_allowed[i] =
351 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
353 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
354 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
355 mlx4_warn(dev, "Requested number of MACs is too much "
356 "for port %d, reducing to %d.\n",
357 i, 1 << dev->caps.log_num_macs);
359 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
362 dev->caps.counters_mode = get_counters_mode(dev_cap->flags);
363 dev->caps.max_basic_counters = 1 << ilog2(dev_cap->max_basic_counters);
364 dev->caps.max_ext_counters = 1 << ilog2(dev_cap->max_ext_counters);
366 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
367 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
369 (1 << dev->caps.log_num_macs) *
370 (1 << dev->caps.log_num_vlans) *
371 (1 << dev->caps.log_num_prios) *
374 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
376 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR];
381 static int mlx4_save_config(struct mlx4_dev *dev)
383 struct mlx4_port_config *config;
386 list_for_each_entry(config, &config_list, list) {
387 if (config->pdev == dev->pdev) {
388 for (i = 1; i <= dev->caps.num_ports; i++)
389 config->port_type[i] = dev->caps.possible_type[i];
394 config = kmalloc(sizeof(struct mlx4_port_config), GFP_KERNEL);
398 config->pdev = dev->pdev;
399 for (i = 1; i <= dev->caps.num_ports; i++)
400 config->port_type[i] = dev->caps.possible_type[i];
402 list_add_tail(&config->list, &config_list);
408 * Change the port configuration of the device.
409 * Every user of this function must hold the port mutex.
411 int mlx4_change_port_types(struct mlx4_dev *dev,
412 enum mlx4_port_type *port_types)
418 for (port = 0; port < dev->caps.num_ports; port++) {
419 /* Change the port type only if the new type is different
420 * from the current, and not set to Auto */
421 if (port_types[port] != dev->caps.port_type[port + 1]) {
423 dev->caps.port_type[port + 1] = port_types[port];
427 mlx4_unregister_device(dev);
428 for (port = 1; port <= dev->caps.num_ports; port++) {
429 mlx4_CLOSE_PORT(dev, port);
430 err = mlx4_SET_PORT(dev, port);
432 mlx4_err(dev, "Failed to set port %d, "
437 mlx4_set_port_mask(dev);
438 mlx4_save_config(dev);
439 err = mlx4_register_device(dev);
446 static ssize_t show_port_type(struct device *dev,
447 struct device_attribute *attr,
450 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
452 struct mlx4_dev *mdev = info->dev;
456 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
458 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
459 sprintf(buf, "auto (%s)\n", type);
461 sprintf(buf, "%s\n", type);
466 static ssize_t set_port_type(struct device *dev,
467 struct device_attribute *attr,
468 const char *buf, size_t count)
470 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
472 struct mlx4_dev *mdev = info->dev;
473 struct mlx4_priv *priv = mlx4_priv(mdev);
474 enum mlx4_port_type types[MLX4_MAX_PORTS];
475 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
479 if (!strcmp(buf, "ib\n"))
480 info->tmp_type = MLX4_PORT_TYPE_IB;
481 else if (!strcmp(buf, "eth\n"))
482 info->tmp_type = MLX4_PORT_TYPE_ETH;
483 else if (!strcmp(buf, "auto\n"))
484 info->tmp_type = MLX4_PORT_TYPE_AUTO;
486 mlx4_err(mdev, "%s is not supported port type\n", buf);
490 mlx4_stop_sense(mdev);
491 mutex_lock(&priv->port_mutex);
492 /* Possible type is always the one that was delivered */
493 mdev->caps.possible_type[info->port] = info->tmp_type;
495 for (i = 0; i < mdev->caps.num_ports; i++) {
496 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
497 mdev->caps.possible_type[i+1];
498 if (types[i] == MLX4_PORT_TYPE_AUTO)
499 types[i] = mdev->caps.port_type[i+1];
503 if (++priv->changed_ports < mdev->caps.num_ports)
506 priv->trig = priv->changed_ports = 0;
509 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
510 for (i = 1; i <= mdev->caps.num_ports; i++) {
511 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
512 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
518 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
519 "Set only 'eth' or 'ib' for both ports "
520 "(should be the same)\n");
524 mlx4_do_sense_ports(mdev, new_types, types);
526 err = mlx4_check_port_params(mdev, new_types);
530 /* We are about to apply the changes after the configuration
531 * was verified, no need to remember the temporary types
533 for (i = 0; i < mdev->caps.num_ports; i++)
534 priv->port[i + 1].tmp_type = 0;
536 err = mlx4_change_port_types(mdev, new_types);
539 mlx4_start_sense(mdev);
540 mutex_unlock(&priv->port_mutex);
541 return err ? err : count;
544 static ssize_t trigger_port(struct device *dev, struct device_attribute *attr,
545 const char *buf, size_t count)
547 struct pci_dev *pdev = to_pci_dev(dev);
548 struct mlx4_dev *mdev = pci_get_drvdata(pdev);
549 struct mlx4_priv *priv = container_of(mdev, struct mlx4_priv, dev);
554 mutex_lock(&priv->port_mutex);
556 mutex_unlock(&priv->port_mutex);
559 DEVICE_ATTR(port_trigger, S_IWUGO, NULL, trigger_port);
561 static int mlx4_load_fw(struct mlx4_dev *dev)
563 struct mlx4_priv *priv = mlx4_priv(dev);
566 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
567 GFP_HIGHUSER | __GFP_NOWARN, 0);
568 if (!priv->fw.fw_icm) {
569 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
573 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
575 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
579 err = mlx4_RUN_FW(dev);
581 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
591 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
595 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
598 struct mlx4_priv *priv = mlx4_priv(dev);
601 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
603 ((u64) (MLX4_CMPT_TYPE_QP *
604 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
605 cmpt_entry_sz, dev->caps.num_qps,
606 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
611 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
613 ((u64) (MLX4_CMPT_TYPE_SRQ *
614 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
615 cmpt_entry_sz, dev->caps.num_srqs,
616 dev->caps.reserved_srqs, 0, 0);
620 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
622 ((u64) (MLX4_CMPT_TYPE_CQ *
623 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
624 cmpt_entry_sz, dev->caps.num_cqs,
625 dev->caps.reserved_cqs, 0, 0);
629 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
631 ((u64) (MLX4_CMPT_TYPE_EQ *
632 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
634 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
641 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
644 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
647 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
653 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
654 struct mlx4_init_hca_param *init_hca, u64 icm_size)
656 struct mlx4_priv *priv = mlx4_priv(dev);
660 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
662 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
666 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
667 (unsigned long long) icm_size >> 10,
668 (unsigned long long) aux_pages << 2);
670 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
671 GFP_HIGHUSER | __GFP_NOWARN, 0);
672 if (!priv->fw.aux_icm) {
673 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
677 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
679 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
683 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
685 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
689 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
690 init_hca->eqc_base, dev_cap->eqc_entry_sz,
691 dev->caps.num_eqs, dev->caps.num_eqs,
694 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
699 * Reserved MTT entries must be aligned up to a cacheline
700 * boundary, since the FW will write to them, while the driver
701 * writes to all other MTT entries. (The variable
702 * dev->caps.mtt_entry_sz below is really the MTT segment
703 * size, not the raw entry size)
705 dev->caps.reserved_mtts =
706 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
707 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
709 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
711 dev->caps.mtt_entry_sz,
712 dev->caps.num_mtt_segs,
713 dev->caps.reserved_mtts, 1, 0);
715 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
719 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
721 dev_cap->dmpt_entry_sz,
723 dev->caps.reserved_mrws, 1, 1);
725 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
729 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
731 dev_cap->qpc_entry_sz,
733 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
736 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
740 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
742 dev_cap->aux_entry_sz,
744 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
747 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
751 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
753 dev_cap->altc_entry_sz,
755 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
758 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
762 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
763 init_hca->rdmarc_base,
764 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
766 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
769 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
773 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
775 dev_cap->cqc_entry_sz,
777 dev->caps.reserved_cqs, 0, 0);
779 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
780 goto err_unmap_rdmarc;
783 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
785 dev_cap->srq_entry_sz,
787 dev->caps.reserved_srqs, 0, 0);
789 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
794 * It's not strictly required, but for simplicity just map the
795 * whole multicast group table now. The table isn't very big
796 * and it's a lot easier than trying to track ref counts.
798 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
799 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
800 dev->caps.num_mgms + dev->caps.num_amgms,
801 dev->caps.num_mgms + dev->caps.num_amgms,
804 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
811 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
814 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
817 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
820 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
823 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
826 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
829 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
832 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
835 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
838 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
839 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
840 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
841 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
844 mlx4_UNMAP_ICM_AUX(dev);
847 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
852 static void mlx4_free_icms(struct mlx4_dev *dev)
854 struct mlx4_priv *priv = mlx4_priv(dev);
856 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
857 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
858 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
859 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
860 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
861 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
862 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
863 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
864 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
865 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
866 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
867 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
868 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
869 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
871 mlx4_UNMAP_ICM_AUX(dev);
872 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
875 static int map_bf_area(struct mlx4_dev *dev)
877 struct mlx4_priv *priv = mlx4_priv(dev);
878 resource_size_t bf_start;
879 resource_size_t bf_len;
882 bf_start = pci_resource_start(dev->pdev, 2) + (dev->caps.num_uars << PAGE_SHIFT);
883 bf_len = pci_resource_len(dev->pdev, 2) - (dev->caps.num_uars << PAGE_SHIFT);
884 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
885 if (!priv->bf_mapping)
891 static void unmap_bf_area(struct mlx4_dev *dev)
893 if (mlx4_priv(dev)->bf_mapping)
894 io_mapping_free(mlx4_priv(dev)->bf_mapping);
897 static void mlx4_close_hca(struct mlx4_dev *dev)
900 mlx4_CLOSE_HCA(dev, 0);
903 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
906 static int mlx4_init_hca(struct mlx4_dev *dev)
908 struct mlx4_priv *priv = mlx4_priv(dev);
909 struct mlx4_adapter adapter;
910 struct mlx4_dev_cap dev_cap;
911 struct mlx4_mod_stat_cfg mlx4_cfg;
912 struct mlx4_profile profile;
913 struct mlx4_init_hca_param init_hca;
914 struct mlx4_port_config *config;
919 err = mlx4_QUERY_FW(dev);
922 mlx4_info(dev, "non-primary physical function, skipping.\n");
924 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
928 err = mlx4_load_fw(dev);
930 mlx4_err(dev, "Failed to start FW, aborting.\n");
934 mlx4_cfg.log_pg_sz_m = 1;
935 mlx4_cfg.log_pg_sz = 0;
936 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
938 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
940 err = mlx4_dev_cap(dev, &dev_cap);
942 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
946 process_mod_param_profile();
947 profile = default_profile;
949 list_for_each_entry(config, &config_list, list) {
950 if (config->pdev == dev->pdev) {
951 for (i = 1; i <= dev->caps.num_ports; i++) {
952 dev->caps.possible_type[i] = config->port_type[i];
953 if (config->port_type[i] != MLX4_PORT_TYPE_AUTO)
954 dev->caps.port_type[i] = config->port_type[i];
959 mlx4_set_port_mask(dev);
960 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
961 if ((long long) icm_size < 0) {
966 if (map_bf_area(dev))
967 mlx4_dbg(dev, "Kernel support for blue flame is not available for kernels < 2.6.28\n");
969 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
971 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
975 err = mlx4_INIT_HCA(dev, &init_hca);
977 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
981 err = mlx4_QUERY_ADAPTER(dev, &adapter);
983 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
987 priv->eq_table.inta_pin = adapter.inta_pin;
988 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
993 mlx4_CLOSE_HCA(dev, 0);
1001 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1006 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1008 struct mlx4_priv *priv = mlx4_priv(dev);
1012 switch (dev->caps.counters_mode) {
1013 case MLX4_CUNTERS_BASIC:
1014 nent = dev->caps.max_basic_counters;
1016 case MLX4_CUNTERS_EXT:
1017 nent = dev->caps.max_ext_counters;
1022 err = mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1029 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1031 switch (dev->caps.counters_mode) {
1032 case MLX4_CUNTERS_BASIC:
1033 case MLX4_CUNTERS_EXT:
1034 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1041 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1043 struct mlx4_priv *priv = mlx4_priv(dev);
1045 switch (dev->caps.counters_mode) {
1046 case MLX4_CUNTERS_BASIC:
1047 case MLX4_CUNTERS_EXT:
1048 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1056 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1058 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1060 switch (dev->caps.counters_mode) {
1061 case MLX4_CUNTERS_BASIC:
1062 case MLX4_CUNTERS_EXT:
1063 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1069 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1071 static int mlx4_setup_hca(struct mlx4_dev *dev)
1073 struct mlx4_priv *priv = mlx4_priv(dev);
1076 __be32 ib_port_default_caps;
1078 err = mlx4_init_uar_table(dev);
1080 mlx4_err(dev, "Failed to initialize "
1081 "user access region table, aborting.\n");
1085 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1087 mlx4_err(dev, "Failed to allocate driver access region, "
1089 goto err_uar_table_free;
1092 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1094 mlx4_err(dev, "Couldn't map kernel access region, "
1100 err = mlx4_init_pd_table(dev);
1102 mlx4_err(dev, "Failed to initialize "
1103 "protection domain table, aborting.\n");
1107 err = mlx4_init_xrcd_table(dev);
1109 mlx4_err(dev, "Failed to initialize extended "
1110 "reliably connected domain table, aborting.\n");
1111 goto err_pd_table_free;
1114 err = mlx4_init_mr_table(dev);
1116 mlx4_err(dev, "Failed to initialize "
1117 "memory region table, aborting.\n");
1118 goto err_xrcd_table_free;
1121 err = mlx4_init_eq_table(dev);
1123 mlx4_err(dev, "Failed to initialize "
1124 "event queue table, aborting.\n");
1125 goto err_mr_table_free;
1128 err = mlx4_cmd_use_events(dev);
1130 mlx4_err(dev, "Failed to switch to event-driven "
1131 "firmware commands, aborting.\n");
1132 goto err_eq_table_free;
1135 err = mlx4_NOP(dev);
1137 if (dev->flags & MLX4_FLAG_MSI_X) {
1138 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1139 "interrupt IRQ %d).\n",
1140 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1141 mlx4_warn(dev, "Trying again without MSI-X.\n");
1143 mlx4_err(dev, "NOP command failed to generate interrupt "
1144 "(IRQ %d), aborting.\n",
1145 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1146 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1152 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1154 err = mlx4_init_cq_table(dev);
1156 mlx4_err(dev, "Failed to initialize "
1157 "completion queue table, aborting.\n");
1161 err = mlx4_init_srq_table(dev);
1163 mlx4_err(dev, "Failed to initialize "
1164 "shared receive queue table, aborting.\n");
1165 goto err_cq_table_free;
1168 err = mlx4_init_qp_table(dev);
1170 mlx4_err(dev, "Failed to initialize "
1171 "queue pair table, aborting.\n");
1172 goto err_srq_table_free;
1175 err = mlx4_init_mcg_table(dev);
1177 mlx4_err(dev, "Failed to initialize "
1178 "multicast group table, aborting.\n");
1179 goto err_qp_table_free;
1182 err = mlx4_init_counters_table(dev);
1183 if (err && err != -ENOENT) {
1184 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1185 goto err_mcg_table_free;
1188 for (port = 1; port <= dev->caps.num_ports; port++) {
1189 ib_port_default_caps = 0;
1190 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
1192 mlx4_warn(dev, "failed to get port %d default "
1193 "ib capabilities (%d). Continuing with "
1194 "caps = 0\n", port, err);
1195 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1196 err = mlx4_SET_PORT(dev, port);
1198 mlx4_err(dev, "Failed to set port %d, aborting\n",
1200 goto err_counters_table_free;
1206 err_counters_table_free:
1207 mlx4_cleanup_counters_table(dev);
1210 mlx4_cleanup_mcg_table(dev);
1213 mlx4_cleanup_qp_table(dev);
1216 mlx4_cleanup_srq_table(dev);
1219 mlx4_cleanup_cq_table(dev);
1222 mlx4_cmd_use_polling(dev);
1225 mlx4_cleanup_eq_table(dev);
1228 mlx4_cleanup_mr_table(dev);
1230 err_xrcd_table_free:
1231 mlx4_cleanup_xrcd_table(dev);
1234 mlx4_cleanup_pd_table(dev);
1240 mlx4_uar_free(dev, &priv->driver_uar);
1243 mlx4_cleanup_uar_table(dev);
1247 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1249 struct mlx4_priv *priv = mlx4_priv(dev);
1250 struct msix_entry *entries;
1256 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1257 num_possible_cpus() + 1);
1258 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1262 for (i = 0; i < nreq; ++i)
1263 entries[i].entry = i;
1266 err = pci_enable_msix(dev->pdev, entries, nreq);
1268 /* Try again if at least 2 vectors are available */
1270 mlx4_info(dev, "Requested %d vectors, "
1271 "but only %d MSI-X vectors available, "
1272 "trying again\n", nreq, err);
1280 dev->caps.num_comp_vectors = nreq - 1;
1281 for (i = 0; i < nreq; ++i)
1282 priv->eq_table.eq[i].irq = entries[i].vector;
1284 dev->flags |= MLX4_FLAG_MSI_X;
1291 dev->caps.num_comp_vectors = 1;
1293 for (i = 0; i < 2; ++i)
1294 priv->eq_table.eq[i].irq = dev->pdev->irq;
1297 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1299 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1304 mlx4_init_mac_table(dev, &info->mac_table);
1305 mlx4_init_vlan_table(dev, &info->vlan_table);
1307 sprintf(info->dev_name, "mlx4_port%d", port);
1308 info->port_attr.attr.name = info->dev_name;
1309 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1310 info->port_attr.show = show_port_type;
1311 info->port_attr.store = set_port_type;
1313 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1315 mlx4_err(dev, "Failed to create file for port %d\n", port);
1322 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1327 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1330 static int mlx4_init_trigger(struct mlx4_priv *priv)
1332 memcpy(&priv->trigger_attr, &dev_attr_port_trigger,
1333 sizeof(struct device_attribute));
1334 return device_create_file(&priv->dev.pdev->dev, &priv->trigger_attr);
1337 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1339 struct mlx4_priv *priv;
1340 struct mlx4_dev *dev;
1345 printk(KERN_INFO PFX "Initializing %s\n",
1348 err = pci_enable_device(pdev);
1350 dev_err(&pdev->dev, "Cannot enable PCI device, "
1356 * Check for BARs. We expect 0: 1MB
1358 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1359 pci_resource_len(pdev, 0) != 1 << 20) {
1360 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1362 goto err_disable_pdev;
1364 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1365 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1367 goto err_disable_pdev;
1370 err = pci_request_region(pdev, 0, DRV_NAME);
1372 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
1373 goto err_disable_pdev;
1376 err = pci_request_region(pdev, 2, DRV_NAME);
1378 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
1379 goto err_release_bar0;
1382 pci_set_master(pdev);
1384 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1386 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1387 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1389 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1390 goto err_release_bar2;
1393 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1395 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1396 "consistent PCI DMA mask.\n");
1397 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1399 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1401 goto err_release_bar2;
1405 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1407 dev_err(&pdev->dev, "Device struct alloc failed, "
1410 goto err_release_bar2;
1415 INIT_LIST_HEAD(&priv->ctx_list);
1416 spin_lock_init(&priv->ctx_lock);
1418 mutex_init(&priv->port_mutex);
1420 INIT_LIST_HEAD(&priv->pgdir_list);
1421 mutex_init(&priv->pgdir_mutex);
1422 for (i = 0; i < MLX4_MAX_PORTS; ++i)
1423 priv->iboe_counter_index[i] = -1;
1425 INIT_LIST_HEAD(&priv->bf_list);
1426 mutex_init(&priv->bf_mutex);
1429 * Now reset the HCA before we touch the PCI capabilities or
1430 * attempt a firmware command, since a boot ROM may have left
1431 * the HCA in an undefined state.
1433 err = mlx4_reset(dev);
1435 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1439 if (mlx4_cmd_init(dev)) {
1440 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1444 err = mlx4_init_hca(dev);
1448 err = mlx4_alloc_eq_table(dev);
1452 mlx4_enable_msi_x(dev);
1454 err = mlx4_setup_hca(dev);
1455 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1456 dev->flags &= ~MLX4_FLAG_MSI_X;
1457 pci_disable_msix(pdev);
1458 err = mlx4_setup_hca(dev);
1464 for (port = 1; port <= dev->caps.num_ports; port++) {
1465 err = mlx4_init_port_info(dev, port);
1470 err = mlx4_register_device(dev);
1474 err = mlx4_init_trigger(priv);
1478 err = mlx4_sense_init(dev);
1482 mlx4_start_sense(dev);
1484 pci_set_drvdata(pdev, dev);
1489 device_remove_file(&dev->pdev->dev, &priv->trigger_attr);
1491 mlx4_unregister_device(dev);
1493 for (--port; port >= 1; --port)
1494 mlx4_cleanup_port_info(&priv->port[port]);
1496 mlx4_cleanup_counters_table(dev);
1497 mlx4_cleanup_mcg_table(dev);
1498 mlx4_cleanup_qp_table(dev);
1499 mlx4_cleanup_srq_table(dev);
1500 mlx4_cleanup_cq_table(dev);
1501 mlx4_cmd_use_polling(dev);
1502 mlx4_cleanup_eq_table(dev);
1503 mlx4_cleanup_mr_table(dev);
1504 mlx4_cleanup_xrcd_table(dev);
1505 mlx4_cleanup_pd_table(dev);
1506 mlx4_cleanup_uar_table(dev);
1509 mlx4_free_eq_table(dev);
1512 if (dev->flags & MLX4_FLAG_MSI_X)
1513 pci_disable_msix(pdev);
1515 mlx4_close_hca(dev);
1518 mlx4_cmd_cleanup(dev);
1524 pci_release_region(pdev, 2);
1527 pci_release_region(pdev, 0);
1530 pci_disable_device(pdev);
1531 pci_set_drvdata(pdev, NULL);
1535 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1536 const struct pci_device_id *id)
1538 static int mlx4_version_printed;
1540 if (!mlx4_version_printed) {
1541 printk(KERN_INFO "%s", mlx4_version);
1542 ++mlx4_version_printed;
1545 return __mlx4_init_one(pdev, id);
1548 static void mlx4_remove_one(struct pci_dev *pdev)
1550 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1551 struct mlx4_priv *priv = mlx4_priv(dev);
1555 mlx4_sense_cleanup(dev);
1556 mlx4_unregister_device(dev);
1557 device_remove_file(&dev->pdev->dev, &priv->trigger_attr);
1559 for (p = 1; p <= dev->caps.num_ports; p++) {
1560 mlx4_cleanup_port_info(&priv->port[p]);
1561 mlx4_CLOSE_PORT(dev, p);
1564 mlx4_cleanup_counters_table(dev);
1565 mlx4_cleanup_mcg_table(dev);
1566 mlx4_cleanup_qp_table(dev);
1567 mlx4_cleanup_srq_table(dev);
1568 mlx4_cleanup_cq_table(dev);
1569 mlx4_cmd_use_polling(dev);
1570 mlx4_cleanup_eq_table(dev);
1571 mlx4_cleanup_mr_table(dev);
1572 mlx4_cleanup_xrcd_table(dev);
1573 mlx4_cleanup_pd_table(dev);
1576 mlx4_uar_free(dev, &priv->driver_uar);
1577 mlx4_cleanup_uar_table(dev);
1578 mlx4_free_eq_table(dev);
1579 mlx4_close_hca(dev);
1580 mlx4_cmd_cleanup(dev);
1582 if (dev->flags & MLX4_FLAG_MSI_X)
1583 pci_disable_msix(pdev);
1586 pci_release_region(pdev, 2);
1587 pci_release_region(pdev, 0);
1588 pci_disable_device(pdev);
1589 pci_set_drvdata(pdev, NULL);
1593 int mlx4_restart_one(struct pci_dev *pdev)
1595 mlx4_remove_one(pdev);
1596 return __mlx4_init_one(pdev, NULL);
1599 static struct pci_device_id mlx4_pci_table[] = {
1600 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1601 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1602 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1603 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1604 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1605 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1606 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1607 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1608 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1609 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2 */
1610 { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX VPI PCIe 2.0 5GT/s - IB QDR / 10GigE Virt+ */
1611 { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX EN 40GigE PCIe 2.0 5GT/s */
1612 { PCI_VDEVICE(MELLANOX, 0x6778) }, /* MT26488 ConnectX VPI PCIe 2.0 5GT/s - IB DDR / 10GigE Virt+ */
1613 { PCI_VDEVICE(MELLANOX, 0x1000) },
1614 { PCI_VDEVICE(MELLANOX, 0x1001) },
1615 { PCI_VDEVICE(MELLANOX, 0x1002) },
1616 { PCI_VDEVICE(MELLANOX, 0x1003) },
1617 { PCI_VDEVICE(MELLANOX, 0x1004) },
1618 { PCI_VDEVICE(MELLANOX, 0x1005) },
1619 { PCI_VDEVICE(MELLANOX, 0x1006) },
1620 { PCI_VDEVICE(MELLANOX, 0x1007) },
1621 { PCI_VDEVICE(MELLANOX, 0x1008) },
1622 { PCI_VDEVICE(MELLANOX, 0x1009) },
1623 { PCI_VDEVICE(MELLANOX, 0x100a) },
1624 { PCI_VDEVICE(MELLANOX, 0x100b) },
1625 { PCI_VDEVICE(MELLANOX, 0x100c) },
1626 { PCI_VDEVICE(MELLANOX, 0x100d) },
1627 { PCI_VDEVICE(MELLANOX, 0x100e) },
1628 { PCI_VDEVICE(MELLANOX, 0x100f) },
1632 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1634 static struct pci_driver mlx4_driver = {
1636 .id_table = mlx4_pci_table,
1637 .probe = mlx4_init_one,
1638 .remove = __devexit_p(mlx4_remove_one)
1641 static int __init mlx4_verify_params(void)
1643 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1644 printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac);
1648 if (log_mtts_per_seg == 0)
1649 log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
1650 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1651 printk(KERN_WARNING "mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1658 static int __init mlx4_init(void)
1662 mutex_init(&drv_mutex);
1664 if (mlx4_verify_params())
1669 mlx4_wq = create_singlethread_workqueue("mlx4");
1673 ret = pci_register_driver(&mlx4_driver);
1674 return ret < 0 ? ret : 0;
1677 static void __exit mlx4_cleanup(void)
1679 mutex_lock(&drv_mutex);
1680 mlx4_config_cleanup();
1681 pci_unregister_driver(&mlx4_driver);
1682 mutex_unlock(&drv_mutex);
1683 destroy_workqueue(mlx4_wq);
1686 module_init_order(mlx4_init, SI_ORDER_MIDDLE);
1687 module_exit(mlx4_cleanup);
1689 #undef MODULE_VERSION
1690 #include <sys/module.h>
1692 mlx4_evhand(module_t mod, int event, void *arg)
1697 static moduledata_t mlx4_mod = {
1699 .evhand = mlx4_evhand,
1701 MODULE_VERSION(mlx4, 1);
1702 DECLARE_MODULE(mlx4, mlx4_mod, SI_SUB_SMP, SI_ORDER_ANY);