sys/ofed/include/linux/mlx4/qp.h

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_QP_H
  34 #define MLX4_QP_H
  35
  36 #include <linux/types.h>
  37
  38 #include <linux/mlx4/device.h>
  39
  40 #define MLX4_INVALID_LKEY       0x100
  41
  42 enum mlx4_qp_optpar {
  43         MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  44         MLX4_QP_OPTPAR_RRE                      = 1 << 1,
  45         MLX4_QP_OPTPAR_RAE                      = 1 << 2,
  46         MLX4_QP_OPTPAR_RWE                      = 1 << 3,
  47         MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  48         MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
  49         MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  50         MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  51         MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  52         MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  53         MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
  54         MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  55         MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  56         MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  57         MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
  58         MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20
  59 };
  60
  61 enum mlx4_qp_state {
  62         MLX4_QP_STATE_RST                       = 0,
  63         MLX4_QP_STATE_INIT                      = 1,
  64         MLX4_QP_STATE_RTR                       = 2,
  65         MLX4_QP_STATE_RTS                       = 3,
  66         MLX4_QP_STATE_SQER                      = 4,
  67         MLX4_QP_STATE_SQD                       = 5,
  68         MLX4_QP_STATE_ERR                       = 6,
  69         MLX4_QP_STATE_SQ_DRAINING               = 7,
  70         MLX4_QP_NUM_STATE
  71 };
  72
  73 enum {
  74         MLX4_QP_ST_RC                           = 0x0,
  75         MLX4_QP_ST_UC                           = 0x1,
  76         MLX4_QP_ST_RD                           = 0x2,
  77         MLX4_QP_ST_UD                           = 0x3,
  78         MLX4_QP_ST_XRC                          = 0x6,
  79         MLX4_QP_ST_MLX                          = 0x7
  80 };
  81
  82 enum {
  83         MLX4_QP_PM_MIGRATED                     = 0x3,
  84         MLX4_QP_PM_ARMED                        = 0x0,
  85         MLX4_QP_PM_REARM                        = 0x1
  86 };
  87
  88 enum {
  89         /* params1 */
  90         MLX4_QP_BIT_SRE                         = 1 << 15,
  91         MLX4_QP_BIT_SWE                         = 1 << 14,
  92         MLX4_QP_BIT_SAE                         = 1 << 13,
  93         /* params2 */
  94         MLX4_QP_BIT_RRE                         = 1 << 15,
  95         MLX4_QP_BIT_RWE                         = 1 << 14,
  96         MLX4_QP_BIT_RAE                         = 1 << 13,
  97         MLX4_QP_BIT_RIC                         = 1 <<  4,
  98 };
  99
 100 struct mlx4_qp_path {
 101         u8                      fl;
 102         u8                      reserved1[2];
 103         u8                      pkey_index;
 104         u8                      counter_index;
 105         u8                      grh_mylmc;
 106         __be16                  rlid;
 107         u8                      ackto;
 108         u8                      mgid_index;
 109         u8                      static_rate;
 110         u8                      hop_limit;
 111         __be32                  tclass_flowlabel;
 112         u8                      rgid[16];
 113         u8                      sched_queue;
 114         u8                      vlan_index;
 115         u8                      reserved3[2];
 116         u8                      reserved4[2];
 117         u8                      dmac[6];
 118 };
 119
 120 struct mlx4_qp_context {
 121         __be32                  flags;
 122         __be32                  pd;
 123         u8                      mtu_msgmax;
 124         u8                      rq_size_stride;
 125         u8                      sq_size_stride;
 126         u8                      rlkey;
 127         __be32                  usr_page;
 128         __be32                  local_qpn;
 129         __be32                  remote_qpn;
 130         struct                  mlx4_qp_path pri_path;
 131         struct                  mlx4_qp_path alt_path;
 132         __be32                  params1;
 133         u32                     reserved1;
 134         __be32                  next_send_psn;
 135         __be32                  cqn_send;
 136         u32                     reserved2[2];
 137         __be32                  last_acked_psn;
 138         __be32                  ssn;
 139         __be32                  params2;
 140         __be32                  rnr_nextrecvpsn;
 141         __be32                  xrcd;
 142         __be32                  cqn_recv;
 143         __be64                  db_rec_addr;
 144         __be32                  qkey;
 145         __be32                  srqn;
 146         __be32                  msn;
 147         __be16                  rq_wqe_counter;
 148         __be16                  sq_wqe_counter;
 149         u32                     reserved3[2];
 150         __be32                  param3;
 151         __be32                  nummmcpeers_basemkey;
 152         u8                      log_page_size;
 153         u8                      reserved4[2];
 154         u8                      mtt_base_addr_h;
 155         __be32                  mtt_base_addr_l;
 156         u8                      VE;
 157         u8                      reserved5;
 158         __be16                  VFT_id_prio;
 159         u8                      reserved6;
 160         u8                      exch_size;
 161         __be16                  exch_base;
 162         u8                      VFT_hop_cnt;
 163         u8                      my_fc_id_idx;
 164         __be16                  reserved7;
 165         u32                     reserved8[7];
 166 };
 167
 168 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
 169 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
 170
 171 enum {
 172         MLX4_WQE_CTRL_NEC               = 1 << 29,
 173         MLX4_WQE_CTRL_FENCE             = 1 << 6,
 174         MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
 175         MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
 176         MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
 177         MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
 178         MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
 179         MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
 180         MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
 181 };
 182
 183 struct mlx4_wqe_ctrl_seg {
 184         __be32                  owner_opcode;
 185         __be16                  vlan_tag;
 186         u8                      ins_vlan;
 187         u8                      fence_size;
 188         /*
 189          * High 24 bits are SRC remote buffer; low 8 bits are flags:
 190          * [7]   SO (strong ordering)
 191          * [5]   TCP/UDP checksum
 192          * [4]   IP checksum
 193          * [3:2] C (generate completion queue entry)
 194          * [1]   SE (solicited event)
 195          */
 196         __be32                  srcrb_flags;
 197         /*
 198          * imm is immediate data for send/RDMA write w/ immediate;
 199          * also invalidation key for send with invalidate; input
 200          * modifier for WQEs on CCQs.
 201          */
 202         __be32                  imm;
 203 };
 204
 205 enum {
 206         MLX4_WQE_MLX_VL15       = 1 << 17,
 207         MLX4_WQE_MLX_SLR        = 1 << 16,
 208         MLX4_WQE_MLX_ICRC       = 1 << 4
 209 };
 210
 211 struct mlx4_wqe_mlx_seg {
 212         u8                      owner;
 213         u8                      reserved1[2];
 214         u8                      opcode;
 215         u8                      reserved2[3];
 216         u8                      size;
 217         /*
 218          * [17]    VL15
 219          * [16]    SLR
 220          * [15:12] static rate
 221          * [11:8]  SL
 222          * [4]     ICRC
 223          * [3:2]   C
 224          * [0]     FL (force loopback)
 225          */
 226         __be32                  flags;
 227         __be16                  rlid;
 228         u16                     reserved3;
 229 };
 230
 231 struct mlx4_wqe_datagram_seg {
 232         __be32                  av[8];
 233         __be32                  dqpn;
 234         __be32                  qkey;
 235         __be16                  vlan;
 236         u8                      mac[6];
 237 };
 238
 239 struct mlx4_wqe_lso_seg {
 240         __be32                  mss_hdr_size;
 241         __be32                  header[0];
 242 };
 243
 244 struct mlx4_wqe_bind_seg {
 245         __be32                  flags1;
 246         __be32                  flags2;
 247         __be32                  new_rkey;
 248         __be32                  lkey;
 249         __be64                  addr;
 250         __be64                  length;
 251 };
 252
 253 enum {
 254         MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 255         MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 256         MLX4_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 257         MLX4_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 258         MLX4_WQE_FMR_PERM_ATOMIC        = 1 << 31
 259 };
 260
 261 struct mlx4_wqe_fmr_seg {
 262         __be32                  flags;
 263         __be32                  mem_key;
 264         __be64                  buf_list;
 265         __be64                  start_addr;
 266         __be64                  reg_len;
 267         __be32                  offset;
 268         __be32                  page_size;
 269         u32                     reserved[2];
 270 };
 271
 272 struct mlx4_wqe_fmr_ext_seg {
 273         u8                      flags;
 274         u8                      reserved;
 275         __be16                  app_mask;
 276         __be16                  wire_app_tag;
 277         __be16                  mem_app_tag;
 278         __be32                  wire_ref_tag_base;
 279         __be32                  mem_ref_tag_base;
 280 };
 281
 282 struct mlx4_wqe_local_inval_seg {
 283         __be32                  flags;
 284         u32                     reserved1;
 285         __be32                  mem_key;
 286         u32                     reserved2[2];
 287         __be32                  guest_id;
 288         __be64                  pa;
 289 };
 290
 291 struct mlx4_wqe_raddr_seg {
 292         __be64                  raddr;
 293         __be32                  rkey;
 294         u32                     reserved;
 295 };
 296
 297 struct mlx4_wqe_atomic_seg {
 298         __be64                  swap_add;
 299         __be64                  compare;
 300 };
 301
 302 struct mlx4_wqe_masked_atomic_seg {
 303         __be64                  swap_add;
 304         __be64                  compare;
 305         __be64                  swap_add_mask;
 306         __be64                  compare_mask;
 307 };
 308
 309 struct mlx4_wqe_data_seg {
 310         __be32                  byte_count;
 311         __be32                  lkey;
 312         __be64                  addr;
 313 };
 314
 315 enum {
 316         MLX4_INLINE_ALIGN       = 64,
 317         MLX4_INLINE_SEG         = 1 << 31,
 318 };
 319
 320 struct mlx4_wqe_inline_seg {
 321         __be32                  byte_count;
 322 };
 323
 324 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 325                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 326                    struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
 327                    int sqd_event, struct mlx4_qp *qp);
 328
 329 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 330                   struct mlx4_qp_context *context);
 331
 332 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 333                      struct mlx4_qp_context *context,
 334                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
 335
 336 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 337 {
 338         return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
 339 }
 340
 341 struct mlx4_qp *mlx4_qp_lookup_lock(struct mlx4_dev *dev, u32 qpn);
 342 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
 343 int mlx4_qp_get_region(struct mlx4_dev *dev, enum mlx4_qp_region region,
 344                         int *base_qpn, int *cnt);
 345
 346 #endif /* MLX4_QP_H */