2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
121 #include <sys/queue.h>
122 #include <sys/cpuset.h>
124 #include <sys/lock.h>
125 #include <sys/msgbuf.h>
126 #include <sys/mutex.h>
127 #include <sys/proc.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
130 #include <sys/systm.h>
131 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
143 #include <vm/vm_pager.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/bat.h>
149 #include <machine/frame.h>
150 #include <machine/md_var.h>
151 #include <machine/psl.h>
152 #include <machine/pte.h>
153 #include <machine/smp.h>
154 #include <machine/sr.h>
155 #include <machine/mmuvar.h>
161 #define TODO panic("%s: not implemented", __func__);
163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
164 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
165 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
174 extern unsigned char _etext[];
175 extern unsigned char _end[];
177 extern int dumpsys_minidump;
180 * Map of physical memory regions.
182 static struct mem_region *regions;
183 static struct mem_region *pregions;
184 static u_int phys_avail_count;
185 static int regions_sz, pregions_sz;
186 static struct ofw_map *translations;
189 * Lock for the pteg and pvo tables.
191 struct mtx moea_table_mutex;
192 struct mtx moea_vsid_mutex;
194 /* tlbie instruction synchronization */
195 static struct mtx tlbie_mtx;
200 static struct pteg *moea_pteg_table;
201 u_int moea_pteg_count;
202 u_int moea_pteg_mask;
207 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
208 struct pvo_head moea_pvo_kunmanaged =
209 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
211 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
212 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
214 #define BPVO_POOL_SIZE 32768
215 static struct pvo_entry *moea_bpvo_pool;
216 static int moea_bpvo_pool_index = 0;
218 #define VSID_NBPW (sizeof(u_int32_t) * 8)
219 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
221 static boolean_t moea_initialized = FALSE;
226 u_int moea_pte_valid = 0;
227 u_int moea_pte_overflow = 0;
228 u_int moea_pte_replacements = 0;
229 u_int moea_pvo_entries = 0;
230 u_int moea_pvo_enter_calls = 0;
231 u_int moea_pvo_remove_calls = 0;
232 u_int moea_pte_spills = 0;
233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
235 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
236 &moea_pte_overflow, 0, "");
237 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
238 &moea_pte_replacements, 0, "");
239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
241 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
242 &moea_pvo_enter_calls, 0, "");
243 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
244 &moea_pvo_remove_calls, 0, "");
245 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
246 &moea_pte_spills, 0, "");
249 * Allocate physical memory for use in moea_bootstrap.
251 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
256 static int moea_pte_insert(u_int, struct pte *);
261 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
262 vm_offset_t, vm_offset_t, u_int, int);
263 static void moea_pvo_remove(struct pvo_entry *, int);
264 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
265 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
270 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
271 vm_prot_t, boolean_t);
272 static void moea_syncicache(vm_offset_t, vm_size_t);
273 static boolean_t moea_query_bit(vm_page_t, int);
274 static u_int moea_clear_bit(vm_page_t, int);
275 static void moea_kremove(mmu_t, vm_offset_t);
276 int moea_pte_spill(vm_offset_t);
279 * Kernel MMU interface
281 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
282 void moea_clear_modify(mmu_t, vm_page_t);
283 void moea_clear_reference(mmu_t, vm_page_t);
284 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
285 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
286 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
287 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
288 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
290 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
291 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
292 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
293 void moea_init(mmu_t);
294 boolean_t moea_is_modified(mmu_t, vm_page_t);
295 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
296 boolean_t moea_is_referenced(mmu_t, vm_page_t);
297 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
298 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
299 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
300 int moea_page_wired_mappings(mmu_t, vm_page_t);
301 void moea_pinit(mmu_t, pmap_t);
302 void moea_pinit0(mmu_t, pmap_t);
303 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
304 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
305 void moea_qremove(mmu_t, vm_offset_t, int);
306 void moea_release(mmu_t, pmap_t);
307 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
308 void moea_remove_all(mmu_t, vm_page_t);
309 void moea_remove_write(mmu_t, vm_page_t);
310 void moea_zero_page(mmu_t, vm_page_t);
311 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
312 void moea_zero_page_idle(mmu_t, vm_page_t);
313 void moea_activate(mmu_t, struct thread *);
314 void moea_deactivate(mmu_t, struct thread *);
315 void moea_cpu_bootstrap(mmu_t, int);
316 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
317 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
318 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
319 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
320 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
321 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
322 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
323 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
324 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
325 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
326 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
328 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev);
330 static mmu_method_t moea_methods[] = {
331 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
332 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
333 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
334 MMUMETHOD(mmu_copy_page, moea_copy_page),
335 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
336 MMUMETHOD(mmu_enter, moea_enter),
337 MMUMETHOD(mmu_enter_object, moea_enter_object),
338 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
339 MMUMETHOD(mmu_extract, moea_extract),
340 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
341 MMUMETHOD(mmu_init, moea_init),
342 MMUMETHOD(mmu_is_modified, moea_is_modified),
343 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
344 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
345 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
346 MMUMETHOD(mmu_map, moea_map),
347 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
348 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
349 MMUMETHOD(mmu_pinit, moea_pinit),
350 MMUMETHOD(mmu_pinit0, moea_pinit0),
351 MMUMETHOD(mmu_protect, moea_protect),
352 MMUMETHOD(mmu_qenter, moea_qenter),
353 MMUMETHOD(mmu_qremove, moea_qremove),
354 MMUMETHOD(mmu_release, moea_release),
355 MMUMETHOD(mmu_remove, moea_remove),
356 MMUMETHOD(mmu_remove_all, moea_remove_all),
357 MMUMETHOD(mmu_remove_write, moea_remove_write),
358 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
359 MMUMETHOD(mmu_zero_page, moea_zero_page),
360 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
361 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
362 MMUMETHOD(mmu_activate, moea_activate),
363 MMUMETHOD(mmu_deactivate, moea_deactivate),
364 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
366 /* Internal interfaces */
367 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
368 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
369 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
370 MMUMETHOD(mmu_mapdev, moea_mapdev),
371 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
372 MMUMETHOD(mmu_kextract, moea_kextract),
373 MMUMETHOD(mmu_kenter, moea_kenter),
374 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
375 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
376 MMUMETHOD(mmu_scan_md, moea_scan_md),
377 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
382 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
384 static __inline uint32_t
385 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
390 if (ma != VM_MEMATTR_DEFAULT) {
392 case VM_MEMATTR_UNCACHEABLE:
393 return (PTE_I | PTE_G);
394 case VM_MEMATTR_WRITE_COMBINING:
395 case VM_MEMATTR_WRITE_BACK:
396 case VM_MEMATTR_PREFETCHABLE:
398 case VM_MEMATTR_WRITE_THROUGH:
399 return (PTE_W | PTE_M);
404 * Assume the page is cache inhibited and access is guarded unless
405 * it's in our available memory array.
407 pte_lo = PTE_I | PTE_G;
408 for (i = 0; i < pregions_sz; i++) {
409 if ((pa >= pregions[i].mr_start) &&
410 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
420 tlbie(vm_offset_t va)
423 mtx_lock_spin(&tlbie_mtx);
424 __asm __volatile("ptesync");
425 __asm __volatile("tlbie %0" :: "r"(va));
426 __asm __volatile("eieio; tlbsync; ptesync");
427 mtx_unlock_spin(&tlbie_mtx);
435 for (va = 0; va < 0x00040000; va += 0x00001000) {
436 __asm __volatile("tlbie %0" :: "r"(va));
439 __asm __volatile("tlbsync");
444 va_to_sr(u_int *sr, vm_offset_t va)
446 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
449 static __inline u_int
450 va_to_pteg(u_int sr, vm_offset_t addr)
454 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
456 return (hash & moea_pteg_mask);
459 static __inline struct pvo_head *
460 vm_page_to_pvoh(vm_page_t m)
463 return (&m->md.mdpg_pvoh);
467 moea_attr_clear(vm_page_t m, int ptebit)
470 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
471 m->md.mdpg_attrs &= ~ptebit;
475 moea_attr_fetch(vm_page_t m)
478 return (m->md.mdpg_attrs);
482 moea_attr_save(vm_page_t m, int ptebit)
485 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
486 m->md.mdpg_attrs |= ptebit;
490 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
492 if (pt->pte_hi == pvo_pt->pte_hi)
499 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
501 return (pt->pte_hi & ~PTE_VALID) ==
502 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
503 ((va >> ADDR_API_SHFT) & PTE_API) | which);
507 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
510 mtx_assert(&moea_table_mutex, MA_OWNED);
513 * Construct a PTE. Default to IMB initially. Valid bit only gets
514 * set when the real pte is set in memory.
516 * Note: Don't set the valid bit for correct operation of tlb update.
518 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
519 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
524 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
527 mtx_assert(&moea_table_mutex, MA_OWNED);
528 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
532 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
535 mtx_assert(&moea_table_mutex, MA_OWNED);
538 * As shown in Section 7.6.3.2.3
540 pt->pte_lo &= ~ptebit;
545 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
548 mtx_assert(&moea_table_mutex, MA_OWNED);
549 pvo_pt->pte_hi |= PTE_VALID;
552 * Update the PTE as defined in section 7.6.3.1.
553 * Note that the REF/CHG bits are from pvo_pt and thus should havce
554 * been saved so this routine can restore them (if desired).
556 pt->pte_lo = pvo_pt->pte_lo;
558 pt->pte_hi = pvo_pt->pte_hi;
564 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
567 mtx_assert(&moea_table_mutex, MA_OWNED);
568 pvo_pt->pte_hi &= ~PTE_VALID;
571 * Force the reg & chg bits back into the PTEs.
576 * Invalidate the pte.
578 pt->pte_hi &= ~PTE_VALID;
583 * Save the reg & chg bits.
585 moea_pte_synch(pt, pvo_pt);
590 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
596 moea_pte_unset(pt, pvo_pt, va);
597 moea_pte_set(pt, pvo_pt);
601 * Quick sort callout for comparing memory regions.
603 static int om_cmp(const void *a, const void *b);
606 om_cmp(const void *a, const void *b)
608 const struct ofw_map *mapa;
609 const struct ofw_map *mapb;
613 if (mapa->om_pa < mapb->om_pa)
615 else if (mapa->om_pa > mapb->om_pa)
622 moea_cpu_bootstrap(mmu_t mmup, int ap)
629 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
630 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
632 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
633 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
637 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
638 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
641 __asm __volatile("mtibatu 1,%0" :: "r"(0));
642 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
643 __asm __volatile("mtibatu 2,%0" :: "r"(0));
644 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
645 __asm __volatile("mtibatu 3,%0" :: "r"(0));
648 for (i = 0; i < 16; i++)
649 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
652 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
653 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
660 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
663 phandle_t chosen, mmu;
666 vm_size_t size, physsz, hwphyssz;
667 vm_offset_t pa, va, off;
672 * Set up BAT0 to map the lowest 256 MB area
674 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
675 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
678 * Map PCI memory space.
680 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
681 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
683 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
684 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
686 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
687 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
689 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
690 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
695 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
696 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
699 * Use an IBAT and a DBAT to map the bottom segment of memory
700 * where we are. Turn off instruction relocation temporarily
701 * to prevent faults while reprogramming the IBAT.
704 mtmsr(msr & ~PSL_IR);
705 __asm (".balign 32; \n"
706 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
707 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
708 :: "r"(battable[0].batu), "r"(battable[0].batl));
712 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
713 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
716 /* set global direct map flag */
719 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
720 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
722 for (i = 0; i < pregions_sz; i++) {
726 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
727 pregions[i].mr_start,
728 pregions[i].mr_start + pregions[i].mr_size,
729 pregions[i].mr_size);
731 * Install entries into the BAT table to allow all
732 * of physmem to be convered by on-demand BAT entries.
733 * The loop will sometimes set the same battable element
734 * twice, but that's fine since they won't be used for
737 pa = pregions[i].mr_start & 0xf0000000;
738 end = pregions[i].mr_start + pregions[i].mr_size;
740 u_int n = pa >> ADDR_SR_SHFT;
742 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
743 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
744 pa += SEGMENT_LENGTH;
748 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
749 panic("moea_bootstrap: phys_avail too small");
751 phys_avail_count = 0;
754 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
755 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
756 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
757 regions[i].mr_start + regions[i].mr_size,
760 (physsz + regions[i].mr_size) >= hwphyssz) {
761 if (physsz < hwphyssz) {
762 phys_avail[j] = regions[i].mr_start;
763 phys_avail[j + 1] = regions[i].mr_start +
770 phys_avail[j] = regions[i].mr_start;
771 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
773 physsz += regions[i].mr_size;
775 physmem = btoc(physsz);
778 * Allocate PTEG table.
781 moea_pteg_count = PTEGCOUNT;
783 moea_pteg_count = 0x1000;
785 while (moea_pteg_count < physmem)
786 moea_pteg_count <<= 1;
788 moea_pteg_count >>= 1;
789 #endif /* PTEGCOUNT */
791 size = moea_pteg_count * sizeof(struct pteg);
792 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
794 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
795 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
796 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
797 moea_pteg_mask = moea_pteg_count - 1;
800 * Allocate pv/overflow lists.
802 size = sizeof(struct pvo_head) * moea_pteg_count;
803 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
805 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
806 for (i = 0; i < moea_pteg_count; i++)
807 LIST_INIT(&moea_pvo_table[i]);
810 * Initialize the lock that synchronizes access to the pteg and pvo
813 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
815 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
817 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
820 * Initialise the unmanaged pvo pool.
822 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
823 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
824 moea_bpvo_pool_index = 0;
827 * Make sure kernel vsid is allocated as well as VSID 0.
829 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
830 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
831 moea_vsid_bitmap[0] |= 1;
834 * Initialize the kernel pmap (which is statically allocated).
836 PMAP_LOCK_INIT(kernel_pmap);
837 for (i = 0; i < 16; i++)
838 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
839 CPU_FILL(&kernel_pmap->pm_active);
840 LIST_INIT(&kernel_pmap->pmap_pvo);
843 * Set up the Open Firmware mappings
845 if ((chosen = OF_finddevice("/chosen")) == -1)
846 panic("moea_bootstrap: can't find /chosen");
847 OF_getprop(chosen, "mmu", &mmui, 4);
848 if ((mmu = OF_instance_to_package(mmui)) == -1)
849 panic("moea_bootstrap: can't get mmu package");
850 if ((sz = OF_getproplen(mmu, "translations")) == -1)
851 panic("moea_bootstrap: can't get ofw translation count");
853 for (i = 0; phys_avail[i] != 0; i += 2) {
854 if (phys_avail[i + 1] >= sz) {
855 translations = (struct ofw_map *)phys_avail[i];
859 if (translations == NULL)
860 panic("moea_bootstrap: no space to copy translations");
861 bzero(translations, sz);
862 if (OF_getprop(mmu, "translations", translations, sz) == -1)
863 panic("moea_bootstrap: can't get ofw translations");
864 CTR0(KTR_PMAP, "moea_bootstrap: translations");
865 sz /= sizeof(*translations);
866 qsort(translations, sz, sizeof (*translations), om_cmp);
867 for (i = 0; i < sz; i++) {
868 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
869 translations[i].om_pa, translations[i].om_va,
870 translations[i].om_len);
873 * If the mapping is 1:1, let the RAM and device on-demand
874 * BAT tables take care of the translation.
876 if (translations[i].om_va == translations[i].om_pa)
879 /* Enter the pages */
880 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE)
881 moea_kenter(mmup, translations[i].om_va + off,
882 translations[i].om_pa + off);
886 * Calculate the last available physical address.
888 for (i = 0; phys_avail[i + 2] != 0; i += 2)
890 Maxmem = powerpc_btop(phys_avail[i + 1]);
892 moea_cpu_bootstrap(mmup,0);
897 * Set the start and end of kva.
899 virtual_avail = VM_MIN_KERNEL_ADDRESS;
900 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
903 * Allocate a kernel stack with a guard page for thread0 and map it
904 * into the kernel page map.
906 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
907 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
908 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
909 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
910 thread0.td_kstack = va;
911 thread0.td_kstack_pages = KSTACK_PAGES;
912 for (i = 0; i < KSTACK_PAGES; i++) {
913 moea_kenter(mmup, va, pa);
919 * Allocate virtual address space for the message buffer.
921 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
922 msgbufp = (struct msgbuf *)virtual_avail;
924 virtual_avail += round_page(msgbufsize);
925 while (va < virtual_avail) {
926 moea_kenter(mmup, va, pa);
932 * Allocate virtual address space for the dynamic percpu area.
934 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
935 dpcpu = (void *)virtual_avail;
937 virtual_avail += DPCPU_SIZE;
938 while (va < virtual_avail) {
939 moea_kenter(mmup, va, pa);
943 dpcpu_init(dpcpu, 0);
947 * Activate a user pmap. The pmap must be activated before it's address
948 * space can be accessed in any way.
951 moea_activate(mmu_t mmu, struct thread *td)
956 * Load all the data we need up front to encourage the compiler to
957 * not issue any loads while we have interrupts disabled below.
959 pm = &td->td_proc->p_vmspace->vm_pmap;
962 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
963 PCPU_SET(curpmap, pmr);
967 moea_deactivate(mmu_t mmu, struct thread *td)
971 pm = &td->td_proc->p_vmspace->vm_pmap;
972 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
973 PCPU_SET(curpmap, NULL);
977 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
979 struct pvo_entry *pvo;
982 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
986 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
987 pm->pm_stats.wired_count++;
988 pvo->pvo_vaddr |= PVO_WIRED;
990 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
991 pm->pm_stats.wired_count--;
992 pvo->pvo_vaddr &= ~PVO_WIRED;
999 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1004 dst = VM_PAGE_TO_PHYS(mdst);
1005 src = VM_PAGE_TO_PHYS(msrc);
1007 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1011 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1012 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1015 vm_offset_t a_pg_offset, b_pg_offset;
1018 while (xfersize > 0) {
1019 a_pg_offset = a_offset & PAGE_MASK;
1020 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1021 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1023 b_pg_offset = b_offset & PAGE_MASK;
1024 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1025 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1027 bcopy(a_cp, b_cp, cnt);
1035 * Zero a page of physical memory by temporarily mapping it into the tlb.
1038 moea_zero_page(mmu_t mmu, vm_page_t m)
1040 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1041 void *va = (void *)pa;
1043 bzero(va, PAGE_SIZE);
1047 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1049 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1050 void *va = (void *)(pa + off);
1056 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1058 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1059 void *va = (void *)pa;
1061 bzero(va, PAGE_SIZE);
1065 * Map the given physical page at the specified virtual address in the
1066 * target pmap with the protection requested. If specified the page
1067 * will be wired down.
1070 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1074 vm_page_lock_queues();
1076 moea_enter_locked(pmap, va, m, prot, wired);
1077 vm_page_unlock_queues();
1082 * Map the given physical page at the specified virtual address in the
1083 * target pmap with the protection requested. If specified the page
1084 * will be wired down.
1086 * The page queues and pmap must be locked.
1089 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1092 struct pvo_head *pvo_head;
1095 u_int pte_lo, pvo_flags;
1098 if (!moea_initialized) {
1099 pvo_head = &moea_pvo_kunmanaged;
1100 zone = moea_upvo_zone;
1104 pvo_head = vm_page_to_pvoh(m);
1106 zone = moea_mpvo_zone;
1107 pvo_flags = PVO_MANAGED;
1109 if (pmap_bootstrapped)
1110 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1111 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1112 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1113 VM_OBJECT_LOCKED(m->object),
1114 ("moea_enter_locked: page %p is not busy", m));
1116 /* XXX change the pvo head for fake pages */
1117 if ((m->oflags & VPO_UNMANAGED) != 0) {
1118 pvo_flags &= ~PVO_MANAGED;
1119 pvo_head = &moea_pvo_kunmanaged;
1120 zone = moea_upvo_zone;
1123 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1125 if (prot & VM_PROT_WRITE) {
1127 if (pmap_bootstrapped &&
1128 (m->oflags & VPO_UNMANAGED) == 0)
1129 vm_page_aflag_set(m, PGA_WRITEABLE);
1133 if (prot & VM_PROT_EXECUTE)
1134 pvo_flags |= PVO_EXECUTABLE;
1137 pvo_flags |= PVO_WIRED;
1139 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1143 * Flush the real page from the instruction cache. This has be done
1144 * for all user mappings to prevent information leakage via the
1145 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1146 * mapping for a page.
1148 if (pmap != kernel_pmap && error == ENOENT &&
1149 (pte_lo & (PTE_I | PTE_G)) == 0)
1150 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1154 * Maps a sequence of resident pages belonging to the same object.
1155 * The sequence begins with the given page m_start. This page is
1156 * mapped at the given virtual address start. Each subsequent page is
1157 * mapped at a virtual address that is offset from start by the same
1158 * amount as the page is offset from m_start within the object. The
1159 * last page in the sequence is the page with the largest offset from
1160 * m_start that can be mapped at a virtual address less than the given
1161 * virtual address end. Not every virtual page between start and end
1162 * is mapped; only those for which a resident page exists with the
1163 * corresponding offset from m_start are mapped.
1166 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1167 vm_page_t m_start, vm_prot_t prot)
1170 vm_pindex_t diff, psize;
1172 psize = atop(end - start);
1174 vm_page_lock_queues();
1176 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1177 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1178 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1179 m = TAILQ_NEXT(m, listq);
1181 vm_page_unlock_queues();
1186 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1190 vm_page_lock_queues();
1192 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1194 vm_page_unlock_queues();
1199 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1201 struct pvo_entry *pvo;
1205 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1209 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1215 * Atomically extract and hold the physical page with the given
1216 * pmap and virtual address pair if that mapping permits the given
1220 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1222 struct pvo_entry *pvo;
1230 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1231 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1232 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1233 (prot & VM_PROT_WRITE) == 0)) {
1234 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1236 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1245 moea_init(mmu_t mmu)
1248 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1249 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1250 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1251 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1252 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1253 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1254 moea_initialized = TRUE;
1258 moea_is_referenced(mmu_t mmu, vm_page_t m)
1261 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1262 ("moea_is_referenced: page %p is not managed", m));
1263 return (moea_query_bit(m, PTE_REF));
1267 moea_is_modified(mmu_t mmu, vm_page_t m)
1270 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1271 ("moea_is_modified: page %p is not managed", m));
1274 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1275 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1276 * is clear, no PTEs can have PTE_CHG set.
1278 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1279 if ((m->oflags & VPO_BUSY) == 0 &&
1280 (m->aflags & PGA_WRITEABLE) == 0)
1282 return (moea_query_bit(m, PTE_CHG));
1286 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1288 struct pvo_entry *pvo;
1292 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1293 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1299 moea_clear_reference(mmu_t mmu, vm_page_t m)
1302 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1303 ("moea_clear_reference: page %p is not managed", m));
1304 moea_clear_bit(m, PTE_REF);
1308 moea_clear_modify(mmu_t mmu, vm_page_t m)
1311 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1312 ("moea_clear_modify: page %p is not managed", m));
1313 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1314 KASSERT((m->oflags & VPO_BUSY) == 0,
1315 ("moea_clear_modify: page %p is busy", m));
1318 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1319 * set. If the object containing the page is locked and the page is
1320 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1322 if ((m->aflags & PGA_WRITEABLE) == 0)
1324 moea_clear_bit(m, PTE_CHG);
1328 * Clear the write and modified bits in each of the given page's mappings.
1331 moea_remove_write(mmu_t mmu, vm_page_t m)
1333 struct pvo_entry *pvo;
1338 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1339 ("moea_remove_write: page %p is not managed", m));
1342 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1343 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1344 * is clear, no page table entries need updating.
1346 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1347 if ((m->oflags & VPO_BUSY) == 0 &&
1348 (m->aflags & PGA_WRITEABLE) == 0)
1350 vm_page_lock_queues();
1351 lo = moea_attr_fetch(m);
1353 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1354 pmap = pvo->pvo_pmap;
1356 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1357 pt = moea_pvo_to_pte(pvo, -1);
1358 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1359 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1361 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1362 lo |= pvo->pvo_pte.pte.pte_lo;
1363 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1364 moea_pte_change(pt, &pvo->pvo_pte.pte,
1366 mtx_unlock(&moea_table_mutex);
1371 if ((lo & PTE_CHG) != 0) {
1372 moea_attr_clear(m, PTE_CHG);
1375 vm_page_aflag_clear(m, PGA_WRITEABLE);
1376 vm_page_unlock_queues();
1380 * moea_ts_referenced:
1382 * Return a count of reference bits for a page, clearing those bits.
1383 * It is not necessary for every reference bit to be cleared, but it
1384 * is necessary that 0 only be returned when there are truly no
1385 * reference bits set.
1387 * XXX: The exact number of bits to check and clear is a matter that
1388 * should be tested and standardized at some point in the future for
1389 * optimal aging of shared pages.
1392 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1395 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1396 ("moea_ts_referenced: page %p is not managed", m));
1397 return (moea_clear_bit(m, PTE_REF));
1401 * Modify the WIMG settings of all mappings for a page.
1404 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1406 struct pvo_entry *pvo;
1407 struct pvo_head *pvo_head;
1412 if ((m->oflags & VPO_UNMANAGED) != 0) {
1413 m->md.mdpg_cache_attrs = ma;
1417 vm_page_lock_queues();
1418 pvo_head = vm_page_to_pvoh(m);
1419 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1421 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1422 pmap = pvo->pvo_pmap;
1424 pt = moea_pvo_to_pte(pvo, -1);
1425 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1426 pvo->pvo_pte.pte.pte_lo |= lo;
1428 moea_pte_change(pt, &pvo->pvo_pte.pte,
1430 if (pvo->pvo_pmap == kernel_pmap)
1433 mtx_unlock(&moea_table_mutex);
1436 m->md.mdpg_cache_attrs = ma;
1437 vm_page_unlock_queues();
1441 * Map a wired page into kernel virtual address space.
1444 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1447 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1451 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1457 if (va < VM_MIN_KERNEL_ADDRESS)
1458 panic("moea_kenter: attempt to enter non-kernel address %#x",
1462 pte_lo = moea_calc_wimg(pa, ma);
1464 PMAP_LOCK(kernel_pmap);
1465 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1466 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1468 if (error != 0 && error != ENOENT)
1469 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1472 PMAP_UNLOCK(kernel_pmap);
1476 * Extract the physical page address associated with the given kernel virtual
1480 moea_kextract(mmu_t mmu, vm_offset_t va)
1482 struct pvo_entry *pvo;
1486 * Allow direct mappings on 32-bit OEA
1488 if (va < VM_MIN_KERNEL_ADDRESS) {
1492 PMAP_LOCK(kernel_pmap);
1493 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1494 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1495 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1496 PMAP_UNLOCK(kernel_pmap);
1501 * Remove a wired page from kernel virtual address space.
1504 moea_kremove(mmu_t mmu, vm_offset_t va)
1507 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1511 * Map a range of physical addresses into kernel virtual address space.
1513 * The value passed in *virt is a suggested virtual address for the mapping.
1514 * Architectures which can support a direct-mapped physical to virtual region
1515 * can return the appropriate address within that region, leaving '*virt'
1516 * unchanged. We cannot and therefore do not; *virt is updated with the
1517 * first usable address after the mapped region.
1520 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1521 vm_offset_t pa_end, int prot)
1523 vm_offset_t sva, va;
1527 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1528 moea_kenter(mmu, va, pa_start);
1534 * Returns true if the pmap's pv is one of the first
1535 * 16 pvs linked to from this page. This count may
1536 * be changed upwards or downwards in the future; it
1537 * is only necessary that true be returned for a small
1538 * subset of pmaps for proper page aging.
1541 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1544 struct pvo_entry *pvo;
1547 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1548 ("moea_page_exists_quick: page %p is not managed", m));
1551 vm_page_lock_queues();
1552 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1553 if (pvo->pvo_pmap == pmap) {
1560 vm_page_unlock_queues();
1565 * Return the number of managed mappings to the given physical page
1569 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1571 struct pvo_entry *pvo;
1575 if ((m->oflags & VPO_UNMANAGED) != 0)
1577 vm_page_lock_queues();
1578 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1579 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1581 vm_page_unlock_queues();
1585 static u_int moea_vsidcontext;
1588 moea_pinit(mmu_t mmu, pmap_t pmap)
1593 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1594 PMAP_LOCK_INIT(pmap);
1595 LIST_INIT(&pmap->pmap_pvo);
1598 __asm __volatile("mftb %0" : "=r"(entropy));
1600 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1602 pmap->pmap_phys = pmap;
1606 mtx_lock(&moea_vsid_mutex);
1608 * Allocate some segment registers for this pmap.
1610 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1614 * Create a new value by mutiplying by a prime and adding in
1615 * entropy from the timebase register. This is to make the
1616 * VSID more random so that the PT hash function collides
1617 * less often. (Note that the prime casues gcc to do shifts
1618 * instead of a multiply.)
1620 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1621 hash = moea_vsidcontext & (NPMAPS - 1);
1622 if (hash == 0) /* 0 is special, avoid it */
1625 mask = 1 << (hash & (VSID_NBPW - 1));
1626 hash = (moea_vsidcontext & 0xfffff);
1627 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1628 /* anything free in this bucket? */
1629 if (moea_vsid_bitmap[n] == 0xffffffff) {
1630 entropy = (moea_vsidcontext >> 20);
1633 i = ffs(~moea_vsid_bitmap[n]) - 1;
1635 hash &= 0xfffff & ~(VSID_NBPW - 1);
1638 moea_vsid_bitmap[n] |= mask;
1639 for (i = 0; i < 16; i++)
1640 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1641 mtx_unlock(&moea_vsid_mutex);
1645 mtx_unlock(&moea_vsid_mutex);
1646 panic("moea_pinit: out of segments");
1650 * Initialize the pmap associated with process 0.
1653 moea_pinit0(mmu_t mmu, pmap_t pm)
1656 moea_pinit(mmu, pm);
1657 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1661 * Set the physical protection on the specified range of this map as requested.
1664 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1667 struct pvo_entry *pvo;
1671 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1672 ("moea_protect: non current pmap"));
1674 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1675 moea_remove(mmu, pm, sva, eva);
1679 vm_page_lock_queues();
1681 for (; sva < eva; sva += PAGE_SIZE) {
1682 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1686 if ((prot & VM_PROT_EXECUTE) == 0)
1687 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1690 * Grab the PTE pointer before we diddle with the cached PTE
1693 pt = moea_pvo_to_pte(pvo, pteidx);
1695 * Change the protection of the page.
1697 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1698 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1701 * If the PVO is in the page table, update that pte as well.
1704 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1705 mtx_unlock(&moea_table_mutex);
1708 vm_page_unlock_queues();
1713 * Map a list of wired pages into kernel virtual address space. This is
1714 * intended for temporary mappings which do not need page modification or
1715 * references recorded. Existing mappings in the region are overwritten.
1718 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1723 while (count-- > 0) {
1724 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1731 * Remove page mappings from kernel virtual address space. Intended for
1732 * temporary mappings entered by moea_qenter.
1735 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1740 while (count-- > 0) {
1741 moea_kremove(mmu, va);
1747 moea_release(mmu_t mmu, pmap_t pmap)
1752 * Free segment register's VSID
1754 if (pmap->pm_sr[0] == 0)
1755 panic("moea_release");
1757 mtx_lock(&moea_vsid_mutex);
1758 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1759 mask = 1 << (idx % VSID_NBPW);
1761 moea_vsid_bitmap[idx] &= ~mask;
1762 mtx_unlock(&moea_vsid_mutex);
1763 PMAP_LOCK_DESTROY(pmap);
1767 * Remove the given range of addresses from the specified map.
1770 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1772 struct pvo_entry *pvo, *tpvo;
1775 vm_page_lock_queues();
1777 if ((eva - sva)/PAGE_SIZE < 10) {
1778 for (; sva < eva; sva += PAGE_SIZE) {
1779 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1781 moea_pvo_remove(pvo, pteidx);
1784 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) {
1785 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva)
1787 moea_pvo_remove(pvo, -1);
1791 vm_page_unlock_queues();
1795 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1796 * will reflect changes in pte's back to the vm_page.
1799 moea_remove_all(mmu_t mmu, vm_page_t m)
1801 struct pvo_head *pvo_head;
1802 struct pvo_entry *pvo, *next_pvo;
1805 vm_page_lock_queues();
1806 pvo_head = vm_page_to_pvoh(m);
1807 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1808 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1810 pmap = pvo->pvo_pmap;
1812 moea_pvo_remove(pvo, -1);
1815 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) {
1816 moea_attr_clear(m, PTE_CHG);
1819 vm_page_aflag_clear(m, PGA_WRITEABLE);
1820 vm_page_unlock_queues();
1824 * Allocate a physical page of memory directly from the phys_avail map.
1825 * Can only be called from moea_bootstrap before avail start and end are
1829 moea_bootstrap_alloc(vm_size_t size, u_int align)
1834 size = round_page(size);
1835 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1837 s = (phys_avail[i] + align - 1) & ~(align - 1);
1842 if (s < phys_avail[i] || e > phys_avail[i + 1])
1845 if (s == phys_avail[i]) {
1846 phys_avail[i] += size;
1847 } else if (e == phys_avail[i + 1]) {
1848 phys_avail[i + 1] -= size;
1850 for (j = phys_avail_count * 2; j > i; j -= 2) {
1851 phys_avail[j] = phys_avail[j - 2];
1852 phys_avail[j + 1] = phys_avail[j - 1];
1855 phys_avail[i + 3] = phys_avail[i + 1];
1856 phys_avail[i + 1] = s;
1857 phys_avail[i + 2] = e;
1863 panic("moea_bootstrap_alloc: could not allocate memory");
1867 moea_syncicache(vm_offset_t pa, vm_size_t len)
1869 __syncicache((void *)pa, len);
1873 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1874 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1876 struct pvo_entry *pvo;
1883 moea_pvo_enter_calls++;
1888 * Compute the PTE Group index.
1891 sr = va_to_sr(pm->pm_sr, va);
1892 ptegidx = va_to_pteg(sr, va);
1895 * Remove any existing mapping for this page. Reuse the pvo entry if
1896 * there is a mapping.
1898 mtx_lock(&moea_table_mutex);
1899 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1900 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1901 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1902 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1903 (pte_lo & PTE_PP)) {
1904 mtx_unlock(&moea_table_mutex);
1907 moea_pvo_remove(pvo, -1);
1913 * If we aren't overwriting a mapping, try to allocate.
1915 if (moea_initialized) {
1916 pvo = uma_zalloc(zone, M_NOWAIT);
1918 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1919 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1920 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1921 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1923 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1924 moea_bpvo_pool_index++;
1929 mtx_unlock(&moea_table_mutex);
1934 pvo->pvo_vaddr = va;
1936 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1937 pvo->pvo_vaddr &= ~ADDR_POFF;
1938 if (flags & VM_PROT_EXECUTE)
1939 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1940 if (flags & PVO_WIRED)
1941 pvo->pvo_vaddr |= PVO_WIRED;
1942 if (pvo_head != &moea_pvo_kunmanaged)
1943 pvo->pvo_vaddr |= PVO_MANAGED;
1945 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1947 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1952 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink);
1955 * Remember if the list was empty and therefore will be the first
1958 if (LIST_FIRST(pvo_head) == NULL)
1960 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1962 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1963 pm->pm_stats.wired_count++;
1964 pm->pm_stats.resident_count++;
1967 * We hope this succeeds but it isn't required.
1969 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1971 PVO_PTEGIDX_SET(pvo, i);
1973 panic("moea_pvo_enter: overflow");
1974 moea_pte_overflow++;
1976 mtx_unlock(&moea_table_mutex);
1978 return (first ? ENOENT : 0);
1982 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1987 * If there is an active pte entry, we need to deactivate it (and
1988 * save the ref & cfg bits).
1990 pt = moea_pvo_to_pte(pvo, pteidx);
1992 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1993 mtx_unlock(&moea_table_mutex);
1994 PVO_PTEGIDX_CLR(pvo);
1996 moea_pte_overflow--;
2000 * Update our statistics.
2002 pvo->pvo_pmap->pm_stats.resident_count--;
2003 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2004 pvo->pvo_pmap->pm_stats.wired_count--;
2007 * Save the REF/CHG bits into their cache if the page is managed.
2009 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2012 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2014 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2015 (PTE_REF | PTE_CHG));
2020 * Remove this PVO from the PV and pmap lists.
2022 LIST_REMOVE(pvo, pvo_vlink);
2023 LIST_REMOVE(pvo, pvo_plink);
2026 * Remove this from the overflow list and return it to the pool
2027 * if we aren't going to reuse it.
2029 LIST_REMOVE(pvo, pvo_olink);
2030 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2031 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2032 moea_upvo_zone, pvo);
2034 moea_pvo_remove_calls++;
2038 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2043 * We can find the actual pte entry without searching by grabbing
2044 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2045 * noticing the HID bit.
2047 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2048 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2049 pteidx ^= moea_pteg_mask * 8;
2054 static struct pvo_entry *
2055 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2057 struct pvo_entry *pvo;
2062 sr = va_to_sr(pm->pm_sr, va);
2063 ptegidx = va_to_pteg(sr, va);
2065 mtx_lock(&moea_table_mutex);
2066 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2067 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2069 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2073 mtx_unlock(&moea_table_mutex);
2079 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2084 * If we haven't been supplied the ptegidx, calculate it.
2090 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2091 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2092 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2095 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2096 mtx_lock(&moea_table_mutex);
2098 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2099 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2100 "valid pte index", pvo);
2103 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2104 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2105 "pvo but no valid pte", pvo);
2108 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2109 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2110 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2111 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2114 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2116 panic("moea_pvo_to_pte: pvo %p pte does not match "
2117 "pte %p in moea_pteg_table", pvo, pt);
2120 mtx_assert(&moea_table_mutex, MA_OWNED);
2124 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2125 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2126 "moea_pteg_table but valid in pvo", pvo, pt);
2129 mtx_unlock(&moea_table_mutex);
2134 * XXX: THIS STUFF SHOULD BE IN pte.c?
2137 moea_pte_spill(vm_offset_t addr)
2139 struct pvo_entry *source_pvo, *victim_pvo;
2140 struct pvo_entry *pvo;
2149 ptegidx = va_to_pteg(sr, addr);
2152 * Have to substitute some entry. Use the primary hash for this.
2153 * Use low bits of timebase as random generator.
2155 pteg = &moea_pteg_table[ptegidx];
2156 mtx_lock(&moea_table_mutex);
2157 __asm __volatile("mftb %0" : "=r"(i));
2163 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2165 * We need to find a pvo entry for this address.
2167 if (source_pvo == NULL &&
2168 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2169 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2171 * Now found an entry to be spilled into the pteg.
2172 * The PTE is now valid, so we know it's active.
2174 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2177 PVO_PTEGIDX_SET(pvo, j);
2178 moea_pte_overflow--;
2179 mtx_unlock(&moea_table_mutex);
2185 if (victim_pvo != NULL)
2190 * We also need the pvo entry of the victim we are replacing
2191 * so save the R & C bits of the PTE.
2193 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2194 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2196 if (source_pvo != NULL)
2201 if (source_pvo == NULL) {
2202 mtx_unlock(&moea_table_mutex);
2206 if (victim_pvo == NULL) {
2207 if ((pt->pte_hi & PTE_HID) == 0)
2208 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2212 * If this is a secondary PTE, we need to search it's primary
2213 * pvo bucket for the matching PVO.
2215 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2218 * We also need the pvo entry of the victim we are
2219 * replacing so save the R & C bits of the PTE.
2221 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2227 if (victim_pvo == NULL)
2228 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2233 * We are invalidating the TLB entry for the EA we are replacing even
2234 * though it's valid. If we don't, we lose any ref/chg bit changes
2235 * contained in the TLB entry.
2237 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2239 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2240 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2242 PVO_PTEGIDX_CLR(victim_pvo);
2243 PVO_PTEGIDX_SET(source_pvo, i);
2244 moea_pte_replacements++;
2246 mtx_unlock(&moea_table_mutex);
2251 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2256 mtx_assert(&moea_table_mutex, MA_OWNED);
2259 * First try primary hash.
2261 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2262 if ((pt->pte_hi & PTE_VALID) == 0) {
2263 pvo_pt->pte_hi &= ~PTE_HID;
2264 moea_pte_set(pt, pvo_pt);
2270 * Now try secondary hash.
2272 ptegidx ^= moea_pteg_mask;
2274 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2275 if ((pt->pte_hi & PTE_VALID) == 0) {
2276 pvo_pt->pte_hi |= PTE_HID;
2277 moea_pte_set(pt, pvo_pt);
2282 panic("moea_pte_insert: overflow");
2287 moea_query_bit(vm_page_t m, int ptebit)
2289 struct pvo_entry *pvo;
2292 if (moea_attr_fetch(m) & ptebit)
2295 vm_page_lock_queues();
2296 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2299 * See if we saved the bit off. If so, cache it and return
2302 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2303 moea_attr_save(m, ptebit);
2304 vm_page_unlock_queues();
2310 * No luck, now go through the hard part of looking at the PTEs
2311 * themselves. Sync so that any pending REF/CHG bits are flushed to
2315 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2318 * See if this pvo has a valid PTE. if so, fetch the
2319 * REF/CHG bits from the valid PTE. If the appropriate
2320 * ptebit is set, cache it and return success.
2322 pt = moea_pvo_to_pte(pvo, -1);
2324 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2325 mtx_unlock(&moea_table_mutex);
2326 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2327 moea_attr_save(m, ptebit);
2328 vm_page_unlock_queues();
2334 vm_page_unlock_queues();
2339 moea_clear_bit(vm_page_t m, int ptebit)
2342 struct pvo_entry *pvo;
2345 vm_page_lock_queues();
2348 * Clear the cached value.
2350 moea_attr_clear(m, ptebit);
2353 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2354 * we can reset the right ones). note that since the pvo entries and
2355 * list heads are accessed via BAT0 and are never placed in the page
2356 * table, we don't have to worry about further accesses setting the
2362 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2363 * valid pte clear the ptebit from the valid pte.
2366 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2367 pt = moea_pvo_to_pte(pvo, -1);
2369 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2370 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2372 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2374 mtx_unlock(&moea_table_mutex);
2376 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2379 vm_page_unlock_queues();
2384 * Return true if the physical range is encompassed by the battable[idx]
2387 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2395 * Return immediately if not a valid mapping
2397 if (!(battable[idx].batu & BAT_Vs))
2401 * The BAT entry must be cache-inhibited, guarded, and r/w
2402 * so it can function as an i/o page
2404 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2405 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2409 * The address should be within the BAT range. Assume that the
2410 * start address in the BAT has the correct alignment (thus
2411 * not requiring masking)
2413 start = battable[idx].batl & BAT_PBS;
2414 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2415 end = start | (bat_ble << 15) | 0x7fff;
2417 if ((pa < start) || ((pa + size) > end))
2424 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2429 * This currently does not work for entries that
2430 * overlap 256M BAT segments.
2433 for(i = 0; i < 16; i++)
2434 if (moea_bat_mapped(i, pa, size) == 0)
2441 * Map a set of physical memory pages into the kernel virtual
2442 * address space. Return a pointer to where it is mapped. This
2443 * routine is intended to be used for mapping device memory,
2447 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2450 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2454 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2456 vm_offset_t va, tmpva, ppa, offset;
2459 ppa = trunc_page(pa);
2460 offset = pa & PAGE_MASK;
2461 size = roundup(offset + size, PAGE_SIZE);
2464 * If the physical address lies within a valid BAT table entry,
2465 * return the 1:1 mapping. This currently doesn't work
2466 * for regions that overlap 256M BAT segments.
2468 for (i = 0; i < 16; i++) {
2469 if (moea_bat_mapped(i, pa, size) == 0)
2470 return ((void *) pa);
2473 va = kmem_alloc_nofault(kernel_map, size);
2475 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2477 for (tmpva = va; size > 0;) {
2478 moea_kenter_attr(mmu, tmpva, ppa, ma);
2485 return ((void *)(va + offset));
2489 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2491 vm_offset_t base, offset;
2494 * If this is outside kernel virtual space, then it's a
2495 * battable entry and doesn't require unmapping
2497 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2498 base = trunc_page(va);
2499 offset = va & PAGE_MASK;
2500 size = roundup(offset + size, PAGE_SIZE);
2501 kmem_free(kernel_map, base, size);
2506 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2508 struct pvo_entry *pvo;
2515 lim = round_page(va);
2516 len = MIN(lim - va, sz);
2517 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2519 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2521 moea_syncicache(pa, len);
2530 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2533 if (md->md_vaddr == ~0UL)
2534 return (md->md_paddr + ofs);
2536 return (md->md_vaddr + ofs);
2540 moea_scan_md(mmu_t mmu, struct pmap_md *prev)
2542 static struct pmap_md md;
2543 struct pvo_entry *pvo;
2546 if (dumpsys_minidump) {
2547 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2549 /* 1st: kernel .data and .bss. */
2551 md.md_vaddr = trunc_page((uintptr_t)_etext);
2552 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2555 switch (prev->md_index) {
2557 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2559 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2560 md.md_size = round_page(msgbufp->msg_size);
2563 /* 3rd: kernel VM. */
2564 va = prev->md_vaddr + prev->md_size;
2565 /* Find start of next chunk (from va). */
2566 while (va < virtual_end) {
2567 /* Don't dump the buffer cache. */
2568 if (va >= kmi.buffer_sva &&
2569 va < kmi.buffer_eva) {
2570 va = kmi.buffer_eva;
2573 pvo = moea_pvo_find_va(kernel_pmap,
2574 va & ~ADDR_POFF, NULL);
2576 (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2580 if (va < virtual_end) {
2583 /* Find last page in chunk. */
2584 while (va < virtual_end) {
2585 /* Don't run into the buffer cache. */
2586 if (va == kmi.buffer_sva)
2588 pvo = moea_pvo_find_va(kernel_pmap,
2589 va & ~ADDR_POFF, NULL);
2591 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2595 md.md_size = va - md.md_vaddr;
2603 } else { /* minidumps */
2604 mem_regions(&pregions, &pregions_sz,
2605 ®ions, ®ions_sz);
2608 /* first physical chunk. */
2609 md.md_paddr = pregions[0].mr_start;
2610 md.md_size = pregions[0].mr_size;
2613 } else if (md.md_index < pregions_sz) {
2614 md.md_paddr = pregions[md.md_index].mr_start;
2615 md.md_size = pregions[md.md_index].mr_size;
2619 /* There's no next physical chunk. */