2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_compat.h"
118 #include "opt_kstack_pages.h"
120 #include <sys/param.h>
121 #include <sys/kernel.h>
122 #include <sys/queue.h>
123 #include <sys/cpuset.h>
125 #include <sys/lock.h>
126 #include <sys/msgbuf.h>
127 #include <sys/mutex.h>
128 #include <sys/proc.h>
129 #include <sys/rwlock.h>
130 #include <sys/sched.h>
131 #include <sys/sysctl.h>
132 #include <sys/systm.h>
133 #include <sys/vmmeter.h>
137 #include <dev/ofw/openfirm.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
150 #include <machine/_inttypes.h>
151 #include <machine/cpu.h>
152 #include <machine/platform.h>
153 #include <machine/frame.h>
154 #include <machine/md_var.h>
155 #include <machine/psl.h>
156 #include <machine/bat.h>
157 #include <machine/hid.h>
158 #include <machine/pte.h>
159 #include <machine/sr.h>
160 #include <machine/trap.h>
161 #include <machine/mmuvar.h>
163 #include "mmu_oea64.h"
165 #include "moea64_if.h"
167 void moea64_release_vsid(uint64_t vsid);
168 uintptr_t moea64_get_unique_vsid(void);
170 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
171 #define ENABLE_TRANS(msr) mtmsr(msr)
173 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
174 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
175 #define VSID_HASH_MASK 0x0000007fffffffffULL
179 * -- Read lock: if no modifications are being made to either the PVO lists
180 * or page table or if any modifications being made result in internal
181 * changes (e.g. wiring, protection) such that the existence of the PVOs
182 * is unchanged and they remain associated with the same pmap (in which
183 * case the changes should be protected by the pmap lock)
184 * -- Write lock: required if PTEs/PVOs are being inserted or removed.
187 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
188 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
189 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
190 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
201 * Map of physical memory regions.
203 static struct mem_region *regions;
204 static struct mem_region *pregions;
205 static u_int phys_avail_count;
206 static int regions_sz, pregions_sz;
208 extern void bs_remap_earlyboot(void);
211 * Lock for the pteg and pvo tables.
213 struct rwlock moea64_table_lock;
214 struct mtx moea64_slb_mutex;
219 u_int moea64_pteg_count;
220 u_int moea64_pteg_mask;
225 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
226 struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */
227 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged);
229 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
230 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
232 #define BPVO_POOL_SIZE 327680
233 static struct pvo_entry *moea64_bpvo_pool;
234 static int moea64_bpvo_pool_index = 0;
236 #define VSID_NBPW (sizeof(u_int32_t) * 8)
238 #define NVSIDS (NPMAPS * 16)
239 #define VSID_HASHMASK 0xffffffffUL
241 #define NVSIDS NPMAPS
242 #define VSID_HASHMASK 0xfffffUL
244 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
246 static boolean_t moea64_initialized = FALSE;
251 u_int moea64_pte_valid = 0;
252 u_int moea64_pte_overflow = 0;
253 u_int moea64_pvo_entries = 0;
254 u_int moea64_pvo_enter_calls = 0;
255 u_int moea64_pvo_remove_calls = 0;
256 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
257 &moea64_pte_valid, 0, "");
258 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
259 &moea64_pte_overflow, 0, "");
260 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
261 &moea64_pvo_entries, 0, "");
262 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
263 &moea64_pvo_enter_calls, 0, "");
264 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
265 &moea64_pvo_remove_calls, 0, "");
267 vm_offset_t moea64_scratchpage_va[2];
268 struct pvo_entry *moea64_scratchpage_pvo[2];
269 uintptr_t moea64_scratchpage_pte[2];
270 struct mtx moea64_scratchpage_mtx;
272 uint64_t moea64_large_page_mask = 0;
273 int moea64_large_page_size = 0;
274 int moea64_large_page_shift = 0;
279 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
280 vm_offset_t, vm_offset_t, uint64_t, int);
281 static void moea64_pvo_remove(mmu_t, struct pvo_entry *);
282 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
287 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
288 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
289 static void moea64_kremove(mmu_t, vm_offset_t);
290 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
291 vm_offset_t pa, vm_size_t sz);
294 * Kernel MMU interface
296 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
297 void moea64_clear_modify(mmu_t, vm_page_t);
298 void moea64_clear_reference(mmu_t, vm_page_t);
299 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
300 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
301 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
302 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
303 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
305 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
306 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
307 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
308 void moea64_init(mmu_t);
309 boolean_t moea64_is_modified(mmu_t, vm_page_t);
310 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
311 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
312 boolean_t moea64_ts_referenced(mmu_t, vm_page_t);
313 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
314 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
315 int moea64_page_wired_mappings(mmu_t, vm_page_t);
316 void moea64_pinit(mmu_t, pmap_t);
317 void moea64_pinit0(mmu_t, pmap_t);
318 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
319 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
320 void moea64_qremove(mmu_t, vm_offset_t, int);
321 void moea64_release(mmu_t, pmap_t);
322 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
323 void moea64_remove_pages(mmu_t, pmap_t);
324 void moea64_remove_all(mmu_t, vm_page_t);
325 void moea64_remove_write(mmu_t, vm_page_t);
326 void moea64_zero_page(mmu_t, vm_page_t);
327 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
328 void moea64_zero_page_idle(mmu_t, vm_page_t);
329 void moea64_activate(mmu_t, struct thread *);
330 void moea64_deactivate(mmu_t, struct thread *);
331 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t);
332 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
333 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
334 vm_offset_t moea64_kextract(mmu_t, vm_offset_t);
335 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
336 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
337 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t);
338 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
339 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
341 static mmu_method_t moea64_methods[] = {
342 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
343 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
344 MMUMETHOD(mmu_clear_reference, moea64_clear_reference),
345 MMUMETHOD(mmu_copy_page, moea64_copy_page),
346 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
347 MMUMETHOD(mmu_enter, moea64_enter),
348 MMUMETHOD(mmu_enter_object, moea64_enter_object),
349 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
350 MMUMETHOD(mmu_extract, moea64_extract),
351 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
352 MMUMETHOD(mmu_init, moea64_init),
353 MMUMETHOD(mmu_is_modified, moea64_is_modified),
354 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
355 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
356 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
357 MMUMETHOD(mmu_map, moea64_map),
358 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
359 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
360 MMUMETHOD(mmu_pinit, moea64_pinit),
361 MMUMETHOD(mmu_pinit0, moea64_pinit0),
362 MMUMETHOD(mmu_protect, moea64_protect),
363 MMUMETHOD(mmu_qenter, moea64_qenter),
364 MMUMETHOD(mmu_qremove, moea64_qremove),
365 MMUMETHOD(mmu_release, moea64_release),
366 MMUMETHOD(mmu_remove, moea64_remove),
367 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
368 MMUMETHOD(mmu_remove_all, moea64_remove_all),
369 MMUMETHOD(mmu_remove_write, moea64_remove_write),
370 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
371 MMUMETHOD(mmu_zero_page, moea64_zero_page),
372 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
373 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
374 MMUMETHOD(mmu_activate, moea64_activate),
375 MMUMETHOD(mmu_deactivate, moea64_deactivate),
376 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
378 /* Internal interfaces */
379 MMUMETHOD(mmu_mapdev, moea64_mapdev),
380 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
381 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
382 MMUMETHOD(mmu_kextract, moea64_kextract),
383 MMUMETHOD(mmu_kenter, moea64_kenter),
384 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
385 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
390 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
392 static __inline u_int
393 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
398 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
399 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
401 return (hash & moea64_pteg_mask);
404 static __inline struct pvo_head *
405 vm_page_to_pvoh(vm_page_t m)
408 return (&m->md.mdpg_pvoh);
412 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
413 uint64_t pte_lo, int flags)
417 * Construct a PTE. Default to IMB initially. Valid bit only gets
418 * set when the real pte is set in memory.
420 * Note: Don't set the valid bit for correct operation of tlb update.
422 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
423 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
425 if (flags & PVO_LARGE)
426 pt->pte_hi |= LPTE_BIG;
431 static __inline uint64_t
432 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
437 if (ma != VM_MEMATTR_DEFAULT) {
439 case VM_MEMATTR_UNCACHEABLE:
440 return (LPTE_I | LPTE_G);
441 case VM_MEMATTR_WRITE_COMBINING:
442 case VM_MEMATTR_WRITE_BACK:
443 case VM_MEMATTR_PREFETCHABLE:
445 case VM_MEMATTR_WRITE_THROUGH:
446 return (LPTE_W | LPTE_M);
451 * Assume the page is cache inhibited and access is guarded unless
452 * it's in our available memory array.
454 pte_lo = LPTE_I | LPTE_G;
455 for (i = 0; i < pregions_sz; i++) {
456 if ((pa >= pregions[i].mr_start) &&
457 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
458 pte_lo &= ~(LPTE_I | LPTE_G);
468 * Quick sort callout for comparing memory regions.
470 static int om_cmp(const void *a, const void *b);
473 om_cmp(const void *a, const void *b)
475 const struct ofw_map *mapa;
476 const struct ofw_map *mapb;
480 if (mapa->om_pa_hi < mapb->om_pa_hi)
482 else if (mapa->om_pa_hi > mapb->om_pa_hi)
484 else if (mapa->om_pa_lo < mapb->om_pa_lo)
486 else if (mapa->om_pa_lo > mapb->om_pa_lo)
493 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
495 struct ofw_map translations[sz/sizeof(struct ofw_map)];
501 bzero(translations, sz);
502 if (OF_getprop(mmu, "translations", translations, sz) == -1)
503 panic("moea64_bootstrap: can't get ofw translations");
505 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
506 sz /= sizeof(*translations);
507 qsort(translations, sz, sizeof (*translations), om_cmp);
509 for (i = 0; i < sz; i++) {
510 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
511 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va,
512 translations[i].om_len);
514 if (translations[i].om_pa_lo % PAGE_SIZE)
515 panic("OFW translation not page-aligned!");
517 pa_base = translations[i].om_pa_lo;
520 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32;
522 if (translations[i].om_pa_hi)
523 panic("OFW translations above 32-bit boundary!");
526 /* Now enter the pages for this mapping */
529 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
530 if (moea64_pvo_find_va(kernel_pmap,
531 translations[i].om_va + off) != NULL)
534 moea64_kenter(mmup, translations[i].om_va + off,
543 moea64_probe_large_page(void)
545 uint16_t pvr = mfpvr() >> 16;
551 powerpc_sync(); isync();
552 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
553 powerpc_sync(); isync();
557 moea64_large_page_size = 0x1000000; /* 16 MB */
558 moea64_large_page_shift = 24;
561 moea64_large_page_size = 0;
564 moea64_large_page_mask = moea64_large_page_size - 1;
568 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
575 cache = PCPU_GET(slb);
576 esid = va >> ADDR_SR_SHFT;
577 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
579 for (i = 0; i < 64; i++) {
580 if (cache[i].slbe == (slbe | i))
585 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
587 entry.slbv |= SLBV_L;
589 slb_insert_kernel(entry.slbe, entry.slbv);
594 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
595 vm_offset_t kernelend)
599 vm_offset_t size, off;
603 if (moea64_large_page_size == 0)
609 PMAP_LOCK(kernel_pmap);
610 for (i = 0; i < pregions_sz; i++) {
611 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
612 pregions[i].mr_size; pa += moea64_large_page_size) {
616 * Set memory access as guarded if prefetch within
617 * the page could exit the available physmem area.
619 if (pa & moea64_large_page_mask) {
620 pa &= moea64_large_page_mask;
623 if (pa + moea64_large_page_size >
624 pregions[i].mr_start + pregions[i].mr_size)
627 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
628 &moea64_pvo_kunmanaged, pa, pa,
629 pte_lo, PVO_WIRED | PVO_LARGE);
632 PMAP_UNLOCK(kernel_pmap);
635 size = sizeof(struct pvo_head) * moea64_pteg_count;
636 off = (vm_offset_t)(moea64_pvo_table);
637 for (pa = off; pa < off + size; pa += PAGE_SIZE)
638 moea64_kenter(mmup, pa, pa);
639 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
640 off = (vm_offset_t)(moea64_bpvo_pool);
641 for (pa = off; pa < off + size; pa += PAGE_SIZE)
642 moea64_kenter(mmup, pa, pa);
645 * Map certain important things, like ourselves.
647 * NOTE: We do not map the exception vector space. That code is
648 * used only in real mode, and leaving it unmapped allows us to
649 * catch NULL pointer deferences, instead of making NULL a valid
653 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
655 moea64_kenter(mmup, pa, pa);
660 * Allow user to override unmapped_buf_allowed for testing.
661 * XXXKIB Only direct map implementation was tested.
663 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
664 &unmapped_buf_allowed))
665 unmapped_buf_allowed = hw_direct_map;
669 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
672 vm_size_t physsz, hwphyssz;
674 #ifndef __powerpc64__
675 /* We don't have a direct map since there is no BAT */
678 /* Make sure battable is zero, since we have no BAT */
679 for (i = 0; i < 16; i++) {
680 battable[i].batu = 0;
681 battable[i].batl = 0;
684 moea64_probe_large_page();
686 /* Use a direct map if we have large page support */
687 if (moea64_large_page_size > 0)
693 /* Get physical memory regions from firmware */
694 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
695 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
697 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
698 panic("moea64_bootstrap: phys_avail too small");
700 phys_avail_count = 0;
703 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
704 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
705 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
706 regions[i].mr_start + regions[i].mr_size,
709 (physsz + regions[i].mr_size) >= hwphyssz) {
710 if (physsz < hwphyssz) {
711 phys_avail[j] = regions[i].mr_start;
712 phys_avail[j + 1] = regions[i].mr_start +
719 phys_avail[j] = regions[i].mr_start;
720 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
722 physsz += regions[i].mr_size;
725 /* Check for overlap with the kernel and exception vectors */
726 for (j = 0; j < 2*phys_avail_count; j+=2) {
727 if (phys_avail[j] < EXC_LAST)
728 phys_avail[j] += EXC_LAST;
730 if (kernelstart >= phys_avail[j] &&
731 kernelstart < phys_avail[j+1]) {
732 if (kernelend < phys_avail[j+1]) {
733 phys_avail[2*phys_avail_count] =
734 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
735 phys_avail[2*phys_avail_count + 1] =
740 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
743 if (kernelend >= phys_avail[j] &&
744 kernelend < phys_avail[j+1]) {
745 if (kernelstart > phys_avail[j]) {
746 phys_avail[2*phys_avail_count] = phys_avail[j];
747 phys_avail[2*phys_avail_count + 1] =
748 kernelstart & ~PAGE_MASK;
752 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
756 physmem = btoc(physsz);
759 moea64_pteg_count = PTEGCOUNT;
761 moea64_pteg_count = 0x1000;
763 while (moea64_pteg_count < physmem)
764 moea64_pteg_count <<= 1;
766 moea64_pteg_count >>= 1;
767 #endif /* PTEGCOUNT */
771 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
780 moea64_pteg_mask = moea64_pteg_count - 1;
783 * Allocate pv/overflow lists.
785 size = sizeof(struct pvo_head) * moea64_pteg_count;
787 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
789 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
792 for (i = 0; i < moea64_pteg_count; i++)
793 LIST_INIT(&moea64_pvo_table[i]);
797 * Initialize the lock that synchronizes access to the pteg and pvo
800 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
801 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
804 * Initialise the unmanaged pvo pool.
806 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
807 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
808 moea64_bpvo_pool_index = 0;
811 * Make sure kernel vsid is allocated as well as VSID 0.
813 #ifndef __powerpc64__
814 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
815 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
816 moea64_vsid_bitmap[0] |= 1;
820 * Initialize the kernel pmap (which is statically allocated).
823 for (i = 0; i < 64; i++) {
824 pcpup->pc_slb[i].slbv = 0;
825 pcpup->pc_slb[i].slbe = 0;
828 for (i = 0; i < 16; i++)
829 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
832 kernel_pmap->pmap_phys = kernel_pmap;
833 CPU_FILL(&kernel_pmap->pm_active);
834 LIST_INIT(&kernel_pmap->pmap_pvo);
836 PMAP_LOCK_INIT(kernel_pmap);
839 * Now map in all the other buffers we allocated earlier
842 moea64_setup_direct_map(mmup, kernelstart, kernelend);
846 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
857 * Set up the Open Firmware pmap and add its mappings if not in real
861 chosen = OF_finddevice("/chosen");
862 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
863 mmu = OF_instance_to_package(mmui);
864 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
866 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
867 panic("moea64_bootstrap: too many ofw translations");
870 moea64_add_ofw_mappings(mmup, mmu, sz);
874 * Calculate the last available physical address.
876 for (i = 0; phys_avail[i + 2] != 0; i += 2)
878 Maxmem = powerpc_btop(phys_avail[i + 1]);
881 * Initialize MMU and remap early physical mappings
883 MMU_CPU_BOOTSTRAP(mmup,0);
884 mtmsr(mfmsr() | PSL_DR | PSL_IR);
886 bs_remap_earlyboot();
889 * Set the start and end of kva.
891 virtual_avail = VM_MIN_KERNEL_ADDRESS;
892 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
895 * Map the entire KVA range into the SLB. We must not fault there.
898 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
899 moea64_bootstrap_slb_prefault(va, 0);
903 * Figure out how far we can extend virtual_end into segment 16
904 * without running into existing mappings. Segment 16 is guaranteed
905 * to contain neither RAM nor devices (at least on Apple hardware),
906 * but will generally contain some OFW mappings we should not
910 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
911 PMAP_LOCK(kernel_pmap);
912 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
913 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
914 virtual_end += PAGE_SIZE;
915 PMAP_UNLOCK(kernel_pmap);
919 * Allocate a kernel stack with a guard page for thread0 and map it
920 * into the kernel page map.
922 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
923 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
924 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
925 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
926 thread0.td_kstack = va;
927 thread0.td_kstack_pages = KSTACK_PAGES;
928 for (i = 0; i < KSTACK_PAGES; i++) {
929 moea64_kenter(mmup, va, pa);
935 * Allocate virtual address space for the message buffer.
937 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
938 msgbufp = (struct msgbuf *)virtual_avail;
940 virtual_avail += round_page(msgbufsize);
941 while (va < virtual_avail) {
942 moea64_kenter(mmup, va, pa);
948 * Allocate virtual address space for the dynamic percpu area.
950 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
951 dpcpu = (void *)virtual_avail;
953 virtual_avail += DPCPU_SIZE;
954 while (va < virtual_avail) {
955 moea64_kenter(mmup, va, pa);
959 dpcpu_init(dpcpu, 0);
962 * Allocate some things for page zeroing. We put this directly
963 * in the page table, marked with LPTE_LOCKED, to avoid any
964 * of the PVO book-keeping or other parts of the VM system
965 * from even knowing that this hack exists.
968 if (!hw_direct_map) {
969 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
971 for (i = 0; i < 2; i++) {
972 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
973 virtual_end -= PAGE_SIZE;
975 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
977 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
978 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
980 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
981 mmup, moea64_scratchpage_pvo[i]);
982 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
984 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
985 &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
986 moea64_scratchpage_pvo[i]->pvo_vpn);
993 * Activate a user pmap. The pmap must be activated before its address
994 * space can be accessed in any way.
997 moea64_activate(mmu_t mmu, struct thread *td)
1001 pm = &td->td_proc->p_vmspace->vm_pmap;
1002 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1004 #ifdef __powerpc64__
1005 PCPU_SET(userslb, pm->pm_slb);
1007 PCPU_SET(curpmap, pm->pmap_phys);
1012 moea64_deactivate(mmu_t mmu, struct thread *td)
1016 pm = &td->td_proc->p_vmspace->vm_pmap;
1017 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1018 #ifdef __powerpc64__
1019 PCPU_SET(userslb, NULL);
1021 PCPU_SET(curpmap, NULL);
1026 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1028 struct pvo_entry *pvo;
1035 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1038 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1041 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1042 pm->pm_stats.wired_count++;
1043 pvo->pvo_vaddr |= PVO_WIRED;
1044 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1046 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1047 pm->pm_stats.wired_count--;
1048 pvo->pvo_vaddr &= ~PVO_WIRED;
1049 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1053 /* Update wiring flag in page table. */
1054 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1058 * If we are wiring the page, and it wasn't in the
1059 * page table before, add it.
1061 vsid = PVO_VSID(pvo);
1062 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1063 pvo->pvo_vaddr & PVO_LARGE);
1065 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1068 PVO_PTEGIDX_CLR(pvo);
1069 PVO_PTEGIDX_SET(pvo, i);
1079 * This goes through and sets the physical address of our
1080 * special scratch PTE to the PA we want to zero or copy. Because
1081 * of locking issues (this can get called in pvo_enter() by
1082 * the UMA allocator), we can't use most other utility functions here
1086 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1088 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1089 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1091 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1092 ~(LPTE_WIMG | LPTE_RPGN);
1093 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1094 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1095 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1096 &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1097 moea64_scratchpage_pvo[which]->pvo_vpn);
1102 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1107 dst = VM_PAGE_TO_PHYS(mdst);
1108 src = VM_PAGE_TO_PHYS(msrc);
1110 if (hw_direct_map) {
1111 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1113 mtx_lock(&moea64_scratchpage_mtx);
1115 moea64_set_scratchpage_pa(mmu, 0, src);
1116 moea64_set_scratchpage_pa(mmu, 1, dst);
1118 bcopy((void *)moea64_scratchpage_va[0],
1119 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1121 mtx_unlock(&moea64_scratchpage_mtx);
1126 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1127 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1130 vm_offset_t a_pg_offset, b_pg_offset;
1133 while (xfersize > 0) {
1134 a_pg_offset = a_offset & PAGE_MASK;
1135 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1136 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1138 b_pg_offset = b_offset & PAGE_MASK;
1139 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1140 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1142 bcopy(a_cp, b_cp, cnt);
1150 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1151 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1154 vm_offset_t a_pg_offset, b_pg_offset;
1157 mtx_lock(&moea64_scratchpage_mtx);
1158 while (xfersize > 0) {
1159 a_pg_offset = a_offset & PAGE_MASK;
1160 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1161 moea64_set_scratchpage_pa(mmu, 0,
1162 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1163 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1164 b_pg_offset = b_offset & PAGE_MASK;
1165 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1166 moea64_set_scratchpage_pa(mmu, 1,
1167 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1168 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1169 bcopy(a_cp, b_cp, cnt);
1174 mtx_unlock(&moea64_scratchpage_mtx);
1178 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1179 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1182 if (hw_direct_map) {
1183 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1186 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1192 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1194 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1196 if (size + off > PAGE_SIZE)
1197 panic("moea64_zero_page: size + off > PAGE_SIZE");
1199 if (hw_direct_map) {
1200 bzero((caddr_t)pa + off, size);
1202 mtx_lock(&moea64_scratchpage_mtx);
1203 moea64_set_scratchpage_pa(mmu, 0, pa);
1204 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1205 mtx_unlock(&moea64_scratchpage_mtx);
1210 * Zero a page of physical memory by temporarily mapping it
1213 moea64_zero_page(mmu_t mmu, vm_page_t m)
1215 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1216 vm_offset_t va, off;
1218 if (!hw_direct_map) {
1219 mtx_lock(&moea64_scratchpage_mtx);
1221 moea64_set_scratchpage_pa(mmu, 0, pa);
1222 va = moea64_scratchpage_va[0];
1227 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1228 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1231 mtx_unlock(&moea64_scratchpage_mtx);
1235 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1238 moea64_zero_page(mmu, m);
1242 * Map the given physical page at the specified virtual address in the
1243 * target pmap with the protection requested. If specified the page
1244 * will be wired down.
1248 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1249 vm_prot_t prot, boolean_t wired)
1251 struct pvo_head *pvo_head;
1258 if (!moea64_initialized) {
1259 pvo_head = &moea64_pvo_kunmanaged;
1261 zone = moea64_upvo_zone;
1264 pvo_head = vm_page_to_pvoh(m);
1266 zone = moea64_mpvo_zone;
1267 pvo_flags = PVO_MANAGED;
1270 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1271 VM_OBJECT_LOCKED(m->object),
1272 ("moea64_enter: page %p is not busy", m));
1274 /* XXX change the pvo head for fake pages */
1275 if ((m->oflags & VPO_UNMANAGED) != 0) {
1276 pvo_flags &= ~PVO_MANAGED;
1277 pvo_head = &moea64_pvo_kunmanaged;
1278 zone = moea64_upvo_zone;
1281 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1283 if (prot & VM_PROT_WRITE) {
1285 if (pmap_bootstrapped &&
1286 (m->oflags & VPO_UNMANAGED) == 0)
1287 vm_page_aflag_set(m, PGA_WRITEABLE);
1291 if ((prot & VM_PROT_EXECUTE) == 0)
1292 pte_lo |= LPTE_NOEXEC;
1295 pvo_flags |= PVO_WIRED;
1299 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1300 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1305 * Flush the page from the instruction cache if this page is
1306 * mapped executable and cacheable.
1308 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1309 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1310 vm_page_aflag_set(m, PGA_EXECUTABLE);
1311 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1316 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1321 * This is much trickier than on older systems because
1322 * we can't sync the icache on physical addresses directly
1323 * without a direct map. Instead we check a couple of cases
1324 * where the memory is already mapped in and, failing that,
1325 * use the same trick we use for page zeroing to create
1326 * a temporary mapping for this physical address.
1329 if (!pmap_bootstrapped) {
1331 * If PMAP is not bootstrapped, we are likely to be
1334 __syncicache((void *)pa, sz);
1335 } else if (pmap == kernel_pmap) {
1336 __syncicache((void *)va, sz);
1337 } else if (hw_direct_map) {
1338 __syncicache((void *)pa, sz);
1340 /* Use the scratch page to set up a temp mapping */
1342 mtx_lock(&moea64_scratchpage_mtx);
1344 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1345 __syncicache((void *)(moea64_scratchpage_va[1] +
1346 (va & ADDR_POFF)), sz);
1348 mtx_unlock(&moea64_scratchpage_mtx);
1353 * Maps a sequence of resident pages belonging to the same object.
1354 * The sequence begins with the given page m_start. This page is
1355 * mapped at the given virtual address start. Each subsequent page is
1356 * mapped at a virtual address that is offset from start by the same
1357 * amount as the page is offset from m_start within the object. The
1358 * last page in the sequence is the page with the largest offset from
1359 * m_start that can be mapped at a virtual address less than the given
1360 * virtual address end. Not every virtual page between start and end
1361 * is mapped; only those for which a resident page exists with the
1362 * corresponding offset from m_start are mapped.
1365 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1366 vm_page_t m_start, vm_prot_t prot)
1369 vm_pindex_t diff, psize;
1371 psize = atop(end - start);
1373 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1374 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1375 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1376 m = TAILQ_NEXT(m, listq);
1381 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1385 moea64_enter(mmu, pm, va, m,
1386 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1390 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1392 struct pvo_entry *pvo;
1397 pvo = moea64_pvo_find_va(pm, va);
1401 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1402 (va - PVO_VADDR(pvo));
1409 * Atomically extract and hold the physical page with the given
1410 * pmap and virtual address pair if that mapping permits the given
1414 extern int pa_tryrelock_restart;
1417 vm_page_pa_tryrelock_moea64(pmap_t pmap, vm_paddr_t pa, vm_paddr_t *locked)
1420 * This is a duplicate of vm_page_pa_tryrelock(), but with proper
1421 * handling of the table lock
1428 PA_LOCK_ASSERT(lockpa, MA_OWNED);
1429 if (PA_LOCKPTR(pa) == PA_LOCKPTR(lockpa))
1437 atomic_add_int(&pa_tryrelock_restart, 1);
1445 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1447 struct pvo_entry *pvo;
1456 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1457 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1458 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1459 (prot & VM_PROT_WRITE) == 0)) {
1460 if (vm_page_pa_tryrelock_moea64(pmap,
1461 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1463 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1472 static mmu_t installed_mmu;
1475 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1478 * This entire routine is a horrible hack to avoid bothering kmem
1479 * for new KVA addresses. Because this can get called from inside
1480 * kmem allocation routines, calling kmem for a new address here
1481 * can lead to multiply locking non-recursive mutexes.
1483 static vm_pindex_t color;
1487 int pflags, needed_lock;
1489 *flags = UMA_SLAB_PRIV;
1490 needed_lock = !PMAP_LOCKED(kernel_pmap);
1492 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT)
1493 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED;
1495 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED;
1497 pflags |= VM_ALLOC_ZERO;
1500 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ);
1502 if (wait & M_NOWAIT)
1509 va = VM_PAGE_TO_PHYS(m);
1513 PMAP_LOCK(kernel_pmap);
1515 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1516 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M,
1517 PVO_WIRED | PVO_BOOTSTRAP);
1520 PMAP_UNLOCK(kernel_pmap);
1523 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1524 bzero((void *)va, PAGE_SIZE);
1529 extern int elf32_nxstack;
1532 moea64_init(mmu_t mmu)
1535 CTR0(KTR_PMAP, "moea64_init");
1537 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1538 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1539 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1540 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1541 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1542 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1544 if (!hw_direct_map) {
1545 installed_mmu = mmu;
1546 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1547 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1550 #ifdef COMPAT_FREEBSD32
1554 moea64_initialized = TRUE;
1558 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1561 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1562 ("moea64_is_referenced: page %p is not managed", m));
1563 return (moea64_query_bit(mmu, m, PTE_REF));
1567 moea64_is_modified(mmu_t mmu, vm_page_t m)
1570 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1571 ("moea64_is_modified: page %p is not managed", m));
1574 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1575 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1576 * is clear, no PTEs can have LPTE_CHG set.
1578 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1579 if ((m->oflags & VPO_BUSY) == 0 &&
1580 (m->aflags & PGA_WRITEABLE) == 0)
1582 return (moea64_query_bit(mmu, m, LPTE_CHG));
1586 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1588 struct pvo_entry *pvo;
1593 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1594 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1601 moea64_clear_reference(mmu_t mmu, vm_page_t m)
1604 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1605 ("moea64_clear_reference: page %p is not managed", m));
1606 moea64_clear_bit(mmu, m, LPTE_REF);
1610 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1613 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1614 ("moea64_clear_modify: page %p is not managed", m));
1615 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1616 KASSERT((m->oflags & VPO_BUSY) == 0,
1617 ("moea64_clear_modify: page %p is busy", m));
1620 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1621 * set. If the object containing the page is locked and the page is
1622 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1624 if ((m->aflags & PGA_WRITEABLE) == 0)
1626 moea64_clear_bit(mmu, m, LPTE_CHG);
1630 * Clear the write and modified bits in each of the given page's mappings.
1633 moea64_remove_write(mmu_t mmu, vm_page_t m)
1635 struct pvo_entry *pvo;
1640 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1641 ("moea64_remove_write: page %p is not managed", m));
1644 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1645 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1646 * is clear, no page table entries need updating.
1648 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1649 if ((m->oflags & VPO_BUSY) == 0 &&
1650 (m->aflags & PGA_WRITEABLE) == 0)
1654 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1655 pmap = pvo->pvo_pmap;
1657 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1658 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1659 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1660 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1662 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1663 lo |= pvo->pvo_pte.lpte.pte_lo;
1664 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1665 MOEA64_PTE_CHANGE(mmu, pt,
1666 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1667 if (pvo->pvo_pmap == kernel_pmap)
1671 if ((lo & LPTE_CHG) != 0)
1676 vm_page_aflag_clear(m, PGA_WRITEABLE);
1680 * moea64_ts_referenced:
1682 * Return a count of reference bits for a page, clearing those bits.
1683 * It is not necessary for every reference bit to be cleared, but it
1684 * is necessary that 0 only be returned when there are truly no
1685 * reference bits set.
1687 * XXX: The exact number of bits to check and clear is a matter that
1688 * should be tested and standardized at some point in the future for
1689 * optimal aging of shared pages.
1692 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1695 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1696 ("moea64_ts_referenced: page %p is not managed", m));
1697 return (moea64_clear_bit(mmu, m, LPTE_REF));
1701 * Modify the WIMG settings of all mappings for a page.
1704 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1706 struct pvo_entry *pvo;
1707 struct pvo_head *pvo_head;
1712 if ((m->oflags & VPO_UNMANAGED) != 0) {
1713 m->md.mdpg_cache_attrs = ma;
1717 pvo_head = vm_page_to_pvoh(m);
1718 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1720 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1721 pmap = pvo->pvo_pmap;
1723 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1724 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1725 pvo->pvo_pte.lpte.pte_lo |= lo;
1727 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1729 if (pvo->pvo_pmap == kernel_pmap)
1735 m->md.mdpg_cache_attrs = ma;
1739 * Map a wired page into kernel virtual address space.
1742 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1747 pte_lo = moea64_calc_wimg(pa, ma);
1750 PMAP_LOCK(kernel_pmap);
1751 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1752 &moea64_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1753 PMAP_UNLOCK(kernel_pmap);
1756 if (error != 0 && error != ENOENT)
1757 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1762 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1765 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1769 * Extract the physical page address associated with the given kernel virtual
1773 moea64_kextract(mmu_t mmu, vm_offset_t va)
1775 struct pvo_entry *pvo;
1779 * Shortcut the direct-mapped case when applicable. We never put
1780 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1782 if (va < VM_MIN_KERNEL_ADDRESS)
1786 PMAP_LOCK(kernel_pmap);
1787 pvo = moea64_pvo_find_va(kernel_pmap, va);
1788 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1790 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1792 PMAP_UNLOCK(kernel_pmap);
1797 * Remove a wired page from kernel virtual address space.
1800 moea64_kremove(mmu_t mmu, vm_offset_t va)
1802 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1806 * Map a range of physical addresses into kernel virtual address space.
1808 * The value passed in *virt is a suggested virtual address for the mapping.
1809 * Architectures which can support a direct-mapped physical to virtual region
1810 * can return the appropriate address within that region, leaving '*virt'
1811 * unchanged. We cannot and therefore do not; *virt is updated with the
1812 * first usable address after the mapped region.
1815 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1816 vm_offset_t pa_end, int prot)
1818 vm_offset_t sva, va;
1822 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1823 moea64_kenter(mmu, va, pa_start);
1830 * Returns true if the pmap's pv is one of the first
1831 * 16 pvs linked to from this page. This count may
1832 * be changed upwards or downwards in the future; it
1833 * is only necessary that true be returned for a small
1834 * subset of pmaps for proper page aging.
1837 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1840 struct pvo_entry *pvo;
1843 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1844 ("moea64_page_exists_quick: page %p is not managed", m));
1848 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1849 if (pvo->pvo_pmap == pmap) {
1861 * Return the number of managed mappings to the given physical page
1865 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1867 struct pvo_entry *pvo;
1871 if ((m->oflags & VPO_UNMANAGED) != 0)
1874 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1875 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1881 static uintptr_t moea64_vsidcontext;
1884 moea64_get_unique_vsid(void) {
1891 __asm __volatile("mftb %0" : "=r"(entropy));
1893 mtx_lock(&moea64_slb_mutex);
1894 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1898 * Create a new value by mutiplying by a prime and adding in
1899 * entropy from the timebase register. This is to make the
1900 * VSID more random so that the PT hash function collides
1901 * less often. (Note that the prime casues gcc to do shifts
1902 * instead of a multiply.)
1904 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1905 hash = moea64_vsidcontext & (NVSIDS - 1);
1906 if (hash == 0) /* 0 is special, avoid it */
1909 mask = 1 << (hash & (VSID_NBPW - 1));
1910 hash = (moea64_vsidcontext & VSID_HASHMASK);
1911 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1912 /* anything free in this bucket? */
1913 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1914 entropy = (moea64_vsidcontext >> 20);
1917 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1919 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1922 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1923 ("Allocating in-use VSID %#zx\n", hash));
1924 moea64_vsid_bitmap[n] |= mask;
1925 mtx_unlock(&moea64_slb_mutex);
1929 mtx_unlock(&moea64_slb_mutex);
1930 panic("%s: out of segments",__func__);
1933 #ifdef __powerpc64__
1935 moea64_pinit(mmu_t mmu, pmap_t pmap)
1937 PMAP_LOCK_INIT(pmap);
1938 LIST_INIT(&pmap->pmap_pvo);
1940 pmap->pm_slb_tree_root = slb_alloc_tree();
1941 pmap->pm_slb = slb_alloc_user_cache();
1942 pmap->pm_slb_len = 0;
1946 moea64_pinit(mmu_t mmu, pmap_t pmap)
1951 PMAP_LOCK_INIT(pmap);
1952 LIST_INIT(&pmap->pmap_pvo);
1954 if (pmap_bootstrapped)
1955 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1958 pmap->pmap_phys = pmap;
1961 * Allocate some segment registers for this pmap.
1963 hash = moea64_get_unique_vsid();
1965 for (i = 0; i < 16; i++)
1966 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1968 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1973 * Initialize the pmap associated with process 0.
1976 moea64_pinit0(mmu_t mmu, pmap_t pm)
1978 moea64_pinit(mmu, pm);
1979 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1983 * Set the physical protection on the specified range of this map as requested.
1986 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1992 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1995 * Grab the PTE pointer before we diddle with the cached PTE
1998 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2001 * Change the protection of the page.
2003 oldlo = pvo->pvo_pte.lpte.pte_lo;
2004 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
2005 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
2006 if ((prot & VM_PROT_EXECUTE) == 0)
2007 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
2008 if (prot & VM_PROT_WRITE)
2009 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
2011 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
2013 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2016 * If the PVO is in the page table, update that pte as well.
2019 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
2021 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2022 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2023 if ((pg->oflags & VPO_UNMANAGED) == 0)
2024 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2025 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2026 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
2030 * Update vm about the REF/CHG bits if the page is managed and we have
2031 * removed write access.
2033 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
2034 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) {
2036 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2038 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2039 vm_page_aflag_set(pg, PGA_REFERENCED);
2045 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2048 struct pvo_entry *pvo, *tpvo;
2050 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2053 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2054 ("moea64_protect: non current pmap"));
2056 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2057 moea64_remove(mmu, pm, sva, eva);
2063 if ((eva - sva)/PAGE_SIZE < pm->pm_stats.resident_count) {
2065 #ifdef __powerpc64__
2066 if (pm != kernel_pmap &&
2067 user_va_to_slb_entry(pm, sva) == NULL) {
2068 sva = roundup2(sva + 1, SEGMENT_LENGTH);
2072 pvo = moea64_pvo_find_va(pm, sva);
2074 moea64_pvo_protect(mmu, pm, pvo, prot);
2078 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) {
2079 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva)
2081 moea64_pvo_protect(mmu, pm, pvo, prot);
2089 * Map a list of wired pages into kernel virtual address space. This is
2090 * intended for temporary mappings which do not need page modification or
2091 * references recorded. Existing mappings in the region are overwritten.
2094 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2096 while (count-- > 0) {
2097 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2104 * Remove page mappings from kernel virtual address space. Intended for
2105 * temporary mappings entered by moea64_qenter.
2108 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2110 while (count-- > 0) {
2111 moea64_kremove(mmu, va);
2117 moea64_release_vsid(uint64_t vsid)
2121 mtx_lock(&moea64_slb_mutex);
2122 idx = vsid & (NVSIDS-1);
2123 mask = 1 << (idx % VSID_NBPW);
2125 KASSERT(moea64_vsid_bitmap[idx] & mask,
2126 ("Freeing unallocated VSID %#jx", vsid));
2127 moea64_vsid_bitmap[idx] &= ~mask;
2128 mtx_unlock(&moea64_slb_mutex);
2133 moea64_release(mmu_t mmu, pmap_t pmap)
2137 * Free segment registers' VSIDs
2139 #ifdef __powerpc64__
2140 slb_free_tree(pmap);
2141 slb_free_user_cache(pmap->pm_slb);
2143 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2145 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2148 PMAP_LOCK_DESTROY(pmap);
2152 * Remove all pages mapped by the specified pmap
2155 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2157 struct pvo_entry *pvo, *tpvo;
2161 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) {
2162 if (!(pvo->pvo_vaddr & PVO_WIRED))
2163 moea64_pvo_remove(mmu, pvo);
2170 * Remove the given range of addresses from the specified map.
2173 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2175 struct pvo_entry *pvo, *tpvo;
2178 * Perform an unsynchronized read. This is, however, safe.
2180 if (pm->pm_stats.resident_count == 0)
2185 if ((eva - sva)/PAGE_SIZE < pm->pm_stats.resident_count) {
2187 #ifdef __powerpc64__
2188 if (pm != kernel_pmap &&
2189 user_va_to_slb_entry(pm, sva) == NULL) {
2190 sva = roundup2(sva + 1, SEGMENT_LENGTH);
2194 pvo = moea64_pvo_find_va(pm, sva);
2196 moea64_pvo_remove(mmu, pvo);
2200 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) {
2201 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva)
2203 moea64_pvo_remove(mmu, pvo);
2211 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2212 * will reflect changes in pte's back to the vm_page.
2215 moea64_remove_all(mmu_t mmu, vm_page_t m)
2217 struct pvo_entry *pvo, *next_pvo;
2221 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2222 pmap = pvo->pvo_pmap;
2224 moea64_pvo_remove(mmu, pvo);
2228 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2230 vm_page_aflag_clear(m, PGA_WRITEABLE);
2231 vm_page_aflag_clear(m, PGA_EXECUTABLE);
2235 * Allocate a physical page of memory directly from the phys_avail map.
2236 * Can only be called from moea64_bootstrap before avail start and end are
2240 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2245 size = round_page(size);
2246 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2248 s = (phys_avail[i] + align - 1) & ~(align - 1);
2253 if (s < phys_avail[i] || e > phys_avail[i + 1])
2256 if (s + size > platform_real_maxaddr())
2259 if (s == phys_avail[i]) {
2260 phys_avail[i] += size;
2261 } else if (e == phys_avail[i + 1]) {
2262 phys_avail[i + 1] -= size;
2264 for (j = phys_avail_count * 2; j > i; j -= 2) {
2265 phys_avail[j] = phys_avail[j - 2];
2266 phys_avail[j + 1] = phys_avail[j - 1];
2269 phys_avail[i + 3] = phys_avail[i + 1];
2270 phys_avail[i + 1] = s;
2271 phys_avail[i + 2] = e;
2277 panic("moea64_bootstrap_alloc: could not allocate memory");
2281 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2282 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2283 uint64_t pte_lo, int flags)
2285 struct pvo_entry *pvo;
2293 * One nasty thing that can happen here is that the UMA calls to
2294 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2295 * which calls UMA...
2297 * We break the loop by detecting recursion and allocating out of
2298 * the bootstrap pool.
2302 bootstrap = (flags & PVO_BOOTSTRAP);
2304 if (!moea64_initialized)
2307 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2308 rw_assert(&moea64_table_lock, RA_WLOCKED);
2311 * Compute the PTE Group index.
2314 vsid = va_to_vsid(pm, va);
2315 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2318 * Remove any existing mapping for this page. Reuse the pvo entry if
2319 * there is a mapping.
2321 moea64_pvo_enter_calls++;
2323 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2324 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2325 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2326 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2327 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2328 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2329 /* Re-insert if spilled */
2330 i = MOEA64_PTE_INSERT(mmu, ptegidx,
2331 &pvo->pvo_pte.lpte);
2333 PVO_PTEGIDX_SET(pvo, i);
2334 moea64_pte_overflow--;
2338 moea64_pvo_remove(mmu, pvo);
2344 * If we aren't overwriting a mapping, try to allocate.
2347 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2348 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2349 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2350 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2352 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2353 moea64_bpvo_pool_index++;
2357 * Note: drop the table lock around the UMA allocation in
2358 * case the UMA allocator needs to manipulate the page
2359 * table. The mapping we are working with is already
2360 * protected by the PMAP lock.
2362 pvo = uma_zalloc(zone, M_NOWAIT);
2368 moea64_pvo_entries++;
2369 pvo->pvo_vaddr = va;
2370 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2373 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2374 pvo->pvo_vaddr &= ~ADDR_POFF;
2376 if (flags & PVO_WIRED)
2377 pvo->pvo_vaddr |= PVO_WIRED;
2378 if (pvo_head != &moea64_pvo_kunmanaged)
2379 pvo->pvo_vaddr |= PVO_MANAGED;
2381 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2382 if (flags & PVO_LARGE)
2383 pvo->pvo_vaddr |= PVO_LARGE;
2385 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2386 (uint64_t)(pa) | pte_lo, flags);
2391 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink);
2394 * Remember if the list was empty and therefore will be the first
2397 if (LIST_FIRST(pvo_head) == NULL)
2399 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2401 if (pvo->pvo_vaddr & PVO_WIRED) {
2402 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2403 pm->pm_stats.wired_count++;
2405 pm->pm_stats.resident_count++;
2408 * We hope this succeeds but it isn't required.
2410 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2412 PVO_PTEGIDX_SET(pvo, i);
2414 panic("moea64_pvo_enter: overflow");
2415 moea64_pte_overflow++;
2418 if (pm == kernel_pmap)
2421 #ifdef __powerpc64__
2423 * Make sure all our bootstrap mappings are in the SLB as soon
2424 * as virtual memory is switched on.
2426 if (!pmap_bootstrapped)
2427 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2430 return (first ? ENOENT : 0);
2434 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2439 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2440 rw_assert(&moea64_table_lock, RA_WLOCKED);
2443 * If there is an active pte entry, we need to deactivate it (and
2444 * save the ref & cfg bits).
2446 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2448 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2449 PVO_PTEGIDX_CLR(pvo);
2451 moea64_pte_overflow--;
2455 * Update our statistics.
2457 pvo->pvo_pmap->pm_stats.resident_count--;
2458 if (pvo->pvo_vaddr & PVO_WIRED)
2459 pvo->pvo_pmap->pm_stats.wired_count--;
2462 * Remove this PVO from the PV and pmap lists.
2464 LIST_REMOVE(pvo, pvo_vlink);
2465 LIST_REMOVE(pvo, pvo_plink);
2468 * Remove this from the overflow list and return it to the pool
2469 * if we aren't going to reuse it.
2471 LIST_REMOVE(pvo, pvo_olink);
2474 * Update vm about the REF/CHG bits if the page is managed.
2476 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2478 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2479 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2480 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2482 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2483 vm_page_aflag_set(pg, PGA_REFERENCED);
2484 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2485 vm_page_aflag_clear(pg, PGA_WRITEABLE);
2487 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2488 vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2491 moea64_pvo_entries--;
2492 moea64_pvo_remove_calls++;
2494 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2495 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2496 moea64_upvo_zone, pvo);
2499 static struct pvo_entry *
2500 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2502 struct pvo_entry *pvo;
2505 #ifdef __powerpc64__
2508 if (pm == kernel_pmap) {
2509 slbv = kernel_va_to_slbv(va);
2512 slb = user_va_to_slb_entry(pm, va);
2513 /* The page is not mapped if the segment isn't */
2519 vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT;
2521 va &= ~moea64_large_page_mask;
2524 ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L);
2527 vsid = va_to_vsid(pm, va);
2528 ptegidx = va_to_pteg(vsid, va, 0);
2531 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2532 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va)
2540 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2542 struct pvo_entry *pvo;
2546 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2548 * See if we saved the bit off. If so, return success.
2550 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2557 * No luck, now go through the hard part of looking at the PTEs
2558 * themselves. Sync so that any pending REF/CHG bits are flushed to
2562 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2565 * See if this pvo has a valid PTE. if so, fetch the
2566 * REF/CHG bits from the valid PTE. If the appropriate
2567 * ptebit is set, return success.
2569 PMAP_LOCK(pvo->pvo_pmap);
2570 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2572 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2573 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2574 PMAP_UNLOCK(pvo->pvo_pmap);
2579 PMAP_UNLOCK(pvo->pvo_pmap);
2587 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2590 struct pvo_entry *pvo;
2594 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2595 * we can reset the right ones). note that since the pvo entries and
2596 * list heads are accessed via BAT0 and are never placed in the page
2597 * table, we don't have to worry about further accesses setting the
2603 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2604 * valid pte clear the ptebit from the valid pte.
2608 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2609 PMAP_LOCK(pvo->pvo_pmap);
2610 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2612 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2613 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2615 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2616 pvo->pvo_vpn, ptebit);
2619 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2620 PMAP_UNLOCK(pvo->pvo_pmap);
2628 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2630 struct pvo_entry *pvo;
2635 PMAP_LOCK(kernel_pmap);
2636 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) {
2637 pvo = moea64_pvo_find_va(kernel_pmap, ppa);
2639 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2645 PMAP_UNLOCK(kernel_pmap);
2651 * Map a set of physical memory pages into the kernel virtual
2652 * address space. Return a pointer to where it is mapped. This
2653 * routine is intended to be used for mapping device memory,
2657 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2659 vm_offset_t va, tmpva, ppa, offset;
2661 ppa = trunc_page(pa);
2662 offset = pa & PAGE_MASK;
2663 size = roundup2(offset + size, PAGE_SIZE);
2665 va = kmem_alloc_nofault(kernel_map, size);
2668 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2670 for (tmpva = va; size > 0;) {
2671 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2677 return ((void *)(va + offset));
2681 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2684 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2688 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2690 vm_offset_t base, offset;
2692 base = trunc_page(va);
2693 offset = va & PAGE_MASK;
2694 size = roundup2(offset + size, PAGE_SIZE);
2696 kmem_free(kernel_map, base, size);
2700 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2702 struct pvo_entry *pvo;
2710 lim = round_page(va);
2711 len = MIN(lim - va, sz);
2712 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2713 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2714 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2716 moea64_syncicache(mmu, pm, va, pa, len);